drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 149 {
 150         dep->trb_enqueue++;
 151         dep->trb_enqueue %= DWC3_TRB_NUM;
 152 }
 153
 154 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 155 {
 156         dep->trb_dequeue++;
 157         dep->trb_dequeue %= DWC3_TRB_NUM;
 158 }
 159
 160 static int dwc3_ep_is_last_trb(unsigned int index)
 161 {
 162         return index == DWC3_TRB_NUM - 1;
 163 }
 164
 165 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 166                 int status)
 167 {
 168         struct dwc3                     *dwc = dep->dwc;
 169         int                             i;
 170
 171         if (req->started) {
 172                 i = 0;
 173                 do {
 174                         dwc3_ep_inc_deq(dep);
 175                         /*
 176                          * Skip LINK TRB. We can't use req->trb and check for
 177                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 178                          * just completed (not the LINK TRB).
 179                          */
 180                         if (dwc3_ep_is_last_trb(dep->trb_dequeue) &&
 181                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 182                                 dwc3_ep_inc_deq(dep);
 183                 } while(++i < req->request.num_mapped_sgs);
 184                 req->started = false;
 185         }
 186         list_del(&req->list);
 187         req->trb = NULL;
 188
 189         if (req->request.status == -EINPROGRESS)
 190                 req->request.status = status;
 191
 192         if (dwc->ep0_bounced && dep->number == 0)
 193                 dwc->ep0_bounced = false;
 194         else
 195                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 196                                 req->direction);
 197
 198         trace_dwc3_gadget_giveback(req);
 199
 200         spin_unlock(&dwc->lock);
 201         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 202         spin_lock(&dwc->lock);
 203 }
 204
 205 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 206 {
 207         u32             timeout = 500;
 208         u32             reg;
 209
 210         trace_dwc3_gadget_generic_cmd(cmd, param);
 211
 212         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 213         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 214
 215         do {
 216                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 217                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 218                         dwc3_trace(trace_dwc3_gadget,
 219                                         "Command Complete --> %d",
 220                                         DWC3_DGCMD_STATUS(reg));
 221                         if (DWC3_DGCMD_STATUS(reg))
 222                                 return -EINVAL;
 223                         return 0;
 224                 }
 225
 226                 /*
 227                  * We can't sleep here, because it's also called from
 228                  * interrupt context.
 229                  */
 230                 timeout--;
 231                 if (!timeout) {
 232                         dwc3_trace(trace_dwc3_gadget,
 233                                         "Command Timed Out");
 234                         return -ETIMEDOUT;
 235                 }
 236                 udelay(1);
 237         } while (1);
 238 }
 239
 240 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 241
 242 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 243                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 244 {
 245         struct dwc3_ep          *dep = dwc->eps[ep];
 246         u32                     timeout = 500;
 247         u32                     reg;
 248
 249         int                     susphy = false;
 250         int                     ret = -EINVAL;
 251
 252         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 253
 254         /*
 255          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 256          * we're issuing an endpoint command, we must check if
 257          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 258          *
 259          * We will also set SUSPHY bit to what it was before returning as stated
 260          * by the same section on Synopsys databook.
 261          */
 262         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 263         if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 264                 susphy = true;
 265                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 266                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 267         }
 268
 269         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 270                 int             needs_wakeup;
 271
 272                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 273                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 274                                 dwc->link_state == DWC3_LINK_STATE_U3);
 275
 276                 if (unlikely(needs_wakeup)) {
 277                         ret = __dwc3_gadget_wakeup(dwc);
 278                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 279                                         ret);
 280                 }
 281         }
 282
 283         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 284         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 285         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 286
 287         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 288         do {
 289                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 290                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 291                         dwc3_trace(trace_dwc3_gadget,
 292                                         "Command Complete --> %d",
 293                                         DWC3_DEPCMD_STATUS(reg));
 294                         if (DWC3_DEPCMD_STATUS(reg))
 295                                 break;
 296                         ret = 0;
 297                         break;
 298                 }
 299
 300                 /*
 301                  * We can't sleep here, because it is also called from
 302                  * interrupt context.
 303                  */
 304                 timeout--;
 305                 if (!timeout) {
 306                         dwc3_trace(trace_dwc3_gadget,
 307                                         "Command Timed Out");
 308                         ret = -ETIMEDOUT;
 309                         break;
 310                 }
 311
 312                 udelay(1);
 313         } while (1);
 314
 315         if (unlikely(susphy)) {
 316                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 317                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 318                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 319         }
 320
 321         return ret;
 322 }
 323
 324 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 325                 struct dwc3_trb *trb)
 326 {
 327         u32             offset = (char *) trb - (char *) dep->trb_pool;
 328
 329         return dep->trb_pool_dma + offset;
 330 }
 331
 332 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 333 {
 334         struct dwc3             *dwc = dep->dwc;
 335
 336         if (dep->trb_pool)
 337                 return 0;
 338
 339         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 340                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 341                         &dep->trb_pool_dma, GFP_KERNEL);
 342         if (!dep->trb_pool) {
 343                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 344                                 dep->name);
 345                 return -ENOMEM;
 346         }
 347
 348         return 0;
 349 }
 350
 351 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 352 {
 353         struct dwc3             *dwc = dep->dwc;
 354
 355         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 356                         dep->trb_pool, dep->trb_pool_dma);
 357
 358         dep->trb_pool = NULL;
 359         dep->trb_pool_dma = 0;
 360 }
 361
 362 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 363
 364 /**
 365  * dwc3_gadget_start_config - Configure EP resources
 366  * @dwc: pointer to our controller context structure
 367  * @dep: endpoint that is being enabled
 368  *
 369  * The assignment of transfer resources cannot perfectly follow the
 370  * data book due to the fact that the controller driver does not have
 371  * all knowledge of the configuration in advance. It is given this
 372  * information piecemeal by the composite gadget framework after every
 373  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 374  * programming model in this scenario can cause errors. For two
 375  * reasons:
 376  *
 377  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 378  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 379  * multiple interfaces.
 380  *
 381  * 2) The databook does not mention doing more DEPXFERCFG for new
 382  * endpoint on alt setting (8.1.6).
 383  *
 384  * The following simplified method is used instead:
 385  *
 386  * All hardware endpoints can be assigned a transfer resource and this
 387  * setting will stay persistent until either a core reset or
 388  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 389  * do DEPXFERCFG for every hardware endpoint as well. We are
 390  * guaranteed that there are as many transfer resources as endpoints.
 391  *
 392  * This function is called for each endpoint when it is being enabled
 393  * but is triggered only when called for EP0-out, which always happens
 394  * first, and which should only happen in one of the above conditions.
 395  */
 396 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 397 {
 398         struct dwc3_gadget_ep_cmd_params params;
 399         u32                     cmd;
 400         int                     i;
 401         int                     ret;
 402
 403         if (dep->number)
 404                 return 0;
 405
 406         memset(&params, 0x00, sizeof(params));
 407         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 408
 409         ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 410         if (ret)
 411                 return ret;
 412
 413         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 414                 struct dwc3_ep *dep = dwc->eps[i];
 415
 416                 if (!dep)
 417                         continue;
 418
 419                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 420                 if (ret)
 421                         return ret;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 428                 const struct usb_endpoint_descriptor *desc,
 429                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 430                 bool ignore, bool restore)
 431 {
 432         struct dwc3_gadget_ep_cmd_params params;
 433
 434         memset(&params, 0x00, sizeof(params));
 435
 436         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 437                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 438
 439         /* Burst size is only needed in SuperSpeed mode */
 440         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 441                 u32 burst = dep->endpoint.maxburst - 1;
 442
 443                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 444         }
 445
 446         if (ignore)
 447                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 448
 449         if (restore) {
 450                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 451                 params.param2 |= dep->saved_state;
 452         }
 453
 454         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 455                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 456
 457         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 458                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 459                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 460                 dep->stream_capable = true;
 461         }
 462
 463         if (!usb_endpoint_xfer_control(desc))
 464                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 465
 466         /*
 467          * We are doing 1:1 mapping for endpoints, meaning
 468          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 469          * so on. We consider the direction bit as part of the physical
 470          * endpoint number. So USB endpoint 0x81 is 0x03.
 471          */
 472         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 473
 474         /*
 475          * We must use the lower 16 TX FIFOs even though
 476          * HW might have more
 477          */
 478         if (dep->direction)
 479                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 480
 481         if (desc->bInterval) {
 482                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 483                 dep->interval = 1 << (desc->bInterval - 1);
 484         }
 485
 486         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 487                         DWC3_DEPCMD_SETEPCONFIG, &params);
 488 }
 489
 490 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 491 {
 492         struct dwc3_gadget_ep_cmd_params params;
 493
 494         memset(&params, 0x00, sizeof(params));
 495
 496         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 497
 498         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 499                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 500 }
 501
 502 /**
 503  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 504  * @dep: endpoint to be initialized
 505  * @desc: USB Endpoint Descriptor
 506  *
 507  * Caller should take care of locking
 508  */
 509 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 510                 const struct usb_endpoint_descriptor *desc,
 511                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 512                 bool ignore, bool restore)
 513 {
 514         struct dwc3             *dwc = dep->dwc;
 515         u32                     reg;
 516         int                     ret;
 517
 518         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 519
 520         if (!(dep->flags & DWC3_EP_ENABLED)) {
 521                 ret = dwc3_gadget_start_config(dwc, dep);
 522                 if (ret)
 523                         return ret;
 524         }
 525
 526         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 527                         restore);
 528         if (ret)
 529                 return ret;
 530
 531         if (!(dep->flags & DWC3_EP_ENABLED)) {
 532                 struct dwc3_trb *trb_st_hw;
 533                 struct dwc3_trb *trb_link;
 534
 535                 dep->endpoint.desc = desc;
 536                 dep->comp_desc = comp_desc;
 537                 dep->type = usb_endpoint_type(desc);
 538                 dep->flags |= DWC3_EP_ENABLED;
 539
 540                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 541                 reg |= DWC3_DALEPENA_EP(dep->number);
 542                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 543
 544                 if (!usb_endpoint_xfer_isoc(desc))
 545                         goto out;
 546
 547                 /* Link TRB for ISOC. The HWO bit is never reset */
 548                 trb_st_hw = &dep->trb_pool[0];
 549
 550                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 551                 memset(trb_link, 0, sizeof(*trb_link));
 552
 553                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 554                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 555                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 556                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 557         }
 558
 559 out:
 560         switch (usb_endpoint_type(desc)) {
 561         case USB_ENDPOINT_XFER_CONTROL:
 562                 /* don't change name */
 563                 break;
 564         case USB_ENDPOINT_XFER_ISOC:
 565                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 566                 break;
 567         case USB_ENDPOINT_XFER_BULK:
 568                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 569                 break;
 570         case USB_ENDPOINT_XFER_INT:
 571                 strlcat(dep->name, "-int", sizeof(dep->name));
 572                 break;
 573         default:
 574                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 575         }
 576
 577         return 0;
 578 }
 579
 580 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 581 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 582 {
 583         struct dwc3_request             *req;
 584
 585         if (!list_empty(&dep->started_list)) {
 586                 dwc3_stop_active_transfer(dwc, dep->number, true);
 587
 588                 /* - giveback all requests to gadget driver */
 589                 while (!list_empty(&dep->started_list)) {
 590                         req = next_request(&dep->started_list);
 591
 592                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 593                 }
 594         }
 595
 596         while (!list_empty(&dep->pending_list)) {
 597                 req = next_request(&dep->pending_list);
 598
 599                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 600         }
 601 }
 602
 603 /**
 604  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 605  * @dep: the endpoint to disable
 606  *
 607  * This function also removes requests which are currently processed ny the
 608  * hardware and those which are not yet scheduled.
 609  * Caller should take care of locking.
 610  */
 611 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 612 {
 613         struct dwc3             *dwc = dep->dwc;
 614         u32                     reg;
 615
 616         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 617
 618         dwc3_remove_requests(dwc, dep);
 619
 620         /* make sure HW endpoint isn't stalled */
 621         if (dep->flags & DWC3_EP_STALL)
 622                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 623
 624         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 625         reg &= ~DWC3_DALEPENA_EP(dep->number);
 626         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 627
 628         dep->stream_capable = false;
 629         dep->endpoint.desc = NULL;
 630         dep->comp_desc = NULL;
 631         dep->type = 0;
 632         dep->flags = 0;
 633
 634         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 635                         dep->number >> 1,
 636                         (dep->number & 1) ? "in" : "out");
 637
 638         return 0;
 639 }
 640
 641 /* -------------------------------------------------------------------------- */
 642
 643 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 644                 const struct usb_endpoint_descriptor *desc)
 645 {
 646         return -EINVAL;
 647 }
 648
 649 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 650 {
 651         return -EINVAL;
 652 }
 653
 654 /* -------------------------------------------------------------------------- */
 655
 656 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 657                 const struct usb_endpoint_descriptor *desc)
 658 {
 659         struct dwc3_ep                  *dep;
 660         struct dwc3                     *dwc;
 661         unsigned long                   flags;
 662         int                             ret;
 663
 664         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 665                 pr_debug("dwc3: invalid parameters\n");
 666                 return -EINVAL;
 667         }
 668
 669         if (!desc->wMaxPacketSize) {
 670                 pr_debug("dwc3: missing wMaxPacketSize\n");
 671                 return -EINVAL;
 672         }
 673
 674         dep = to_dwc3_ep(ep);
 675         dwc = dep->dwc;
 676
 677         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 678                                         "%s is already enabled\n",
 679                                         dep->name))
 680                 return 0;
 681
 682         spin_lock_irqsave(&dwc->lock, flags);
 683         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 684         spin_unlock_irqrestore(&dwc->lock, flags);
 685
 686         return ret;
 687 }
 688
 689 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 690 {
 691         struct dwc3_ep                  *dep;
 692         struct dwc3                     *dwc;
 693         unsigned long                   flags;
 694         int                             ret;
 695
 696         if (!ep) {
 697                 pr_debug("dwc3: invalid parameters\n");
 698                 return -EINVAL;
 699         }
 700
 701         dep = to_dwc3_ep(ep);
 702         dwc = dep->dwc;
 703
 704         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 705                                         "%s is already disabled\n",
 706                                         dep->name))
 707                 return 0;
 708
 709         spin_lock_irqsave(&dwc->lock, flags);
 710         ret = __dwc3_gadget_ep_disable(dep);
 711         spin_unlock_irqrestore(&dwc->lock, flags);
 712
 713         return ret;
 714 }
 715
 716 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 717         gfp_t gfp_flags)
 718 {
 719         struct dwc3_request             *req;
 720         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 721
 722         req = kzalloc(sizeof(*req), gfp_flags);
 723         if (!req)
 724                 return NULL;
 725
 726         req->epnum      = dep->number;
 727         req->dep        = dep;
 728
 729         trace_dwc3_alloc_request(req);
 730
 731         return &req->request;
 732 }
 733
 734 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 735                 struct usb_request *request)
 736 {
 737         struct dwc3_request             *req = to_dwc3_request(request);
 738
 739         trace_dwc3_free_request(req);
 740         kfree(req);
 741 }
 742
 743 /**
 744  * dwc3_prepare_one_trb - setup one TRB from one request
 745  * @dep: endpoint for which this request is prepared
 746  * @req: dwc3_request pointer
 747  */
 748 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 749                 struct dwc3_request *req, dma_addr_t dma,
 750                 unsigned length, unsigned last, unsigned chain, unsigned node)
 751 {
 752         struct dwc3_trb         *trb;
 753
 754         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 755                         dep->name, req, (unsigned long long) dma,
 756                         length, last ? " last" : "",
 757                         chain ? " chain" : "");
 758
 759
 760         trb = &dep->trb_pool[dep->trb_enqueue];
 761
 762         if (!req->trb) {
 763                 dwc3_gadget_move_started_request(req);
 764                 req->trb = trb;
 765                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 766                 req->first_trb_index = dep->trb_enqueue;
 767         }
 768
 769         dwc3_ep_inc_enq(dep);
 770         /* Skip the LINK-TRB on ISOC */
 771         if (dwc3_ep_is_last_trb(dep->trb_enqueue) &&
 772                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 773                 dwc3_ep_inc_enq(dep);
 774
 775         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 776         trb->bpl = lower_32_bits(dma);
 777         trb->bph = upper_32_bits(dma);
 778
 779         switch (usb_endpoint_type(dep->endpoint.desc)) {
 780         case USB_ENDPOINT_XFER_CONTROL:
 781                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 782                 break;
 783
 784         case USB_ENDPOINT_XFER_ISOC:
 785                 if (!node)
 786                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 787                 else
 788                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 789
 790                 /* always enable Interrupt on Missed ISOC */
 791                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 792                 break;
 793
 794         case USB_ENDPOINT_XFER_BULK:
 795         case USB_ENDPOINT_XFER_INT:
 796                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 797                 break;
 798         default:
 799                 /*
 800                  * This is only possible with faulty memory because we
 801                  * checked it already :)
 802                  */
 803                 BUG();
 804         }
 805
 806         /* always enable Continue on Short Packet */
 807         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 808
 809         if (!req->request.no_interrupt)
 810                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 811
 812         if (last)
 813                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 814
 815         if (chain)
 816                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 817
 818         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 819                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 820
 821         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 822
 823         trace_dwc3_prepare_trb(dep, trb);
 824 }
 825
 826 /*
 827  * dwc3_prepare_trbs - setup TRBs from requests
 828  * @dep: endpoint for which requests are being prepared
 829  * @starting: true if the endpoint is idle and no requests are queued.
 830  *
 831  * The function goes through the requests list and sets up TRBs for the
 832  * transfers. The function returns once there are no more TRBs available or
 833  * it runs out of requests.
 834  */
 835 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 836 {
 837         struct dwc3_request     *req, *n;
 838         u32                     trbs_left;
 839         u32                     max;
 840         unsigned int            last_one = 0;
 841
 842         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 843
 844         /* the first request must not be queued */
 845         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
 846
 847         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 848         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 849                 max = DWC3_TRB_NUM - dep->trb_enqueue;
 850                 if (trbs_left > max)
 851                         trbs_left = max;
 852         }
 853
 854         /*
 855          * If busy & slot are equal than it is either full or empty. If we are
 856          * starting to process requests then we are empty. Otherwise we are
 857          * full and don't do anything
 858          */
 859         if (!trbs_left) {
 860                 if (!starting)
 861                         return;
 862                 trbs_left = DWC3_TRB_NUM;
 863                 /*
 864                  * In case we start from scratch, we queue the ISOC requests
 865                  * starting from slot 1. This is done because we use ring
 866                  * buffer and have no LST bit to stop us. Instead, we place
 867                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 868                  * after the first request so we start at slot 1 and have
 869                  * 7 requests proceed before we hit the first IOC.
 870                  * Other transfer types don't use the ring buffer and are
 871                  * processed from the first TRB until the last one. Since we
 872                  * don't wrap around we have to start at the beginning.
 873                  */
 874                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 875                         dep->trb_dequeue = 1;
 876                         dep->trb_enqueue = 1;
 877                 } else {
 878                         dep->trb_dequeue = 0;
 879                         dep->trb_enqueue = 0;
 880                 }
 881         }
 882
 883         /* The last TRB is a link TRB, not used for xfer */
 884         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 885                 return;
 886
 887         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 888                 unsigned        length;
 889                 dma_addr_t      dma;
 890                 last_one = false;
 891
 892                 if (req->request.num_mapped_sgs > 0) {
 893                         struct usb_request *request = &req->request;
 894                         struct scatterlist *sg = request->sg;
 895                         struct scatterlist *s;
 896                         int             i;
 897
 898                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 899                                 unsigned chain = true;
 900
 901                                 length = sg_dma_len(s);
 902                                 dma = sg_dma_address(s);
 903
 904                                 if (i == (request->num_mapped_sgs - 1) ||
 905                                                 sg_is_last(s)) {
 906                                         if (list_empty(&dep->pending_list))
 907                                                 last_one = true;
 908                                         chain = false;
 909                                 }
 910
 911                                 trbs_left--;
 912                                 if (!trbs_left)
 913                                         last_one = true;
 914
 915                                 if (last_one)
 916                                         chain = false;
 917
 918                                 dwc3_prepare_one_trb(dep, req, dma, length,
 919                                                 last_one, chain, i);
 920
 921                                 if (last_one)
 922                                         break;
 923                         }
 924
 925                         if (last_one)
 926                                 break;
 927                 } else {
 928                         dma = req->request.dma;
 929                         length = req->request.length;
 930                         trbs_left--;
 931
 932                         if (!trbs_left)
 933                                 last_one = 1;
 934
 935                         /* Is this the last request? */
 936                         if (list_is_last(&req->list, &dep->pending_list))
 937                                 last_one = 1;
 938
 939                         dwc3_prepare_one_trb(dep, req, dma, length,
 940                                         last_one, false, 0);
 941
 942                         if (last_one)
 943                                 break;
 944                 }
 945         }
 946 }
 947
 948 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 949                 int start_new)
 950 {
 951         struct dwc3_gadget_ep_cmd_params params;
 952         struct dwc3_request             *req;
 953         struct dwc3                     *dwc = dep->dwc;
 954         int                             ret;
 955         u32                             cmd;
 956
 957         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 958                 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
 959                 return -EBUSY;
 960         }
 961
 962         /*
 963          * If we are getting here after a short-out-packet we don't enqueue any
 964          * new requests as we try to set the IOC bit only on the last request.
 965          */
 966         if (start_new) {
 967                 if (list_empty(&dep->started_list))
 968                         dwc3_prepare_trbs(dep, start_new);
 969
 970                 /* req points to the first request which will be sent */
 971                 req = next_request(&dep->started_list);
 972         } else {
 973                 dwc3_prepare_trbs(dep, start_new);
 974
 975                 /*
 976                  * req points to the first request where HWO changed from 0 to 1
 977                  */
 978                 req = next_request(&dep->started_list);
 979         }
 980         if (!req) {
 981                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 982                 return 0;
 983         }
 984
 985         memset(&params, 0, sizeof(params));
 986
 987         if (start_new) {
 988                 params.param0 = upper_32_bits(req->trb_dma);
 989                 params.param1 = lower_32_bits(req->trb_dma);
 990                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 991         } else {
 992                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 993         }
 994
 995         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 996         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 997         if (ret < 0) {
 998                 /*
 999                  * FIXME we need to iterate over the list of requests
1000                  * here and stop, unmap, free and del each of the linked
1001                  * requests instead of what we do now.
1002                  */
1003                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1004                                 req->direction);
1005                 list_del(&req->list);
1006                 return ret;
1007         }
1008
1009         dep->flags |= DWC3_EP_BUSY;
1010
1011         if (start_new) {
1012                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1013                                 dep->number);
1014                 WARN_ON_ONCE(!dep->resource_index);
1015         }
1016
1017         return 0;
1018 }
1019
1020 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1021                 struct dwc3_ep *dep, u32 cur_uf)
1022 {
1023         u32 uf;
1024
1025         if (list_empty(&dep->pending_list)) {
1026                 dwc3_trace(trace_dwc3_gadget,
1027                                 "ISOC ep %s run out for requests",
1028                                 dep->name);
1029                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1030                 return;
1031         }
1032
1033         /* 4 micro frames in the future */
1034         uf = cur_uf + dep->interval * 4;
1035
1036         __dwc3_gadget_kick_transfer(dep, uf, 1);
1037 }
1038
1039 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1040                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1041 {
1042         u32 cur_uf, mask;
1043
1044         mask = ~(dep->interval - 1);
1045         cur_uf = event->parameters & mask;
1046
1047         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1048 }
1049
1050 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1051 {
1052         struct dwc3             *dwc = dep->dwc;
1053         int                     ret;
1054
1055         if (!dep->endpoint.desc) {
1056                 dwc3_trace(trace_dwc3_gadget,
1057                                 "trying to queue request %p to disabled %s\n",
1058                                 &req->request, dep->endpoint.name);
1059                 return -ESHUTDOWN;
1060         }
1061
1062         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1063                                 &req->request, req->dep->name)) {
1064                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1065                                 &req->request, req->dep->name);
1066                 return -EINVAL;
1067         }
1068
1069         req->request.actual     = 0;
1070         req->request.status     = -EINPROGRESS;
1071         req->direction          = dep->direction;
1072         req->epnum              = dep->number;
1073
1074         trace_dwc3_ep_queue(req);
1075
1076         /*
1077          * We only add to our list of requests now and
1078          * start consuming the list once we get XferNotReady
1079          * IRQ.
1080          *
1081          * That way, we avoid doing anything that we don't need
1082          * to do now and defer it until the point we receive a
1083          * particular token from the Host side.
1084          *
1085          * This will also avoid Host cancelling URBs due to too
1086          * many NAKs.
1087          */
1088         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1089                         dep->direction);
1090         if (ret)
1091                 return ret;
1092
1093         list_add_tail(&req->list, &dep->pending_list);
1094
1095         /*
1096          * If there are no pending requests and the endpoint isn't already
1097          * busy, we will just start the request straight away.
1098          *
1099          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1100          * little bit faster.
1101          */
1102         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1103                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1104                         !(dep->flags & DWC3_EP_BUSY)) {
1105                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1106                 goto out;
1107         }
1108
1109         /*
1110          * There are a few special cases:
1111          *
1112          * 1. XferNotReady with empty list of requests. We need to kick the
1113          *    transfer here in that situation, otherwise we will be NAKing
1114          *    forever. If we get XferNotReady before gadget driver has a
1115          *    chance to queue a request, we will ACK the IRQ but won't be
1116          *    able to receive the data until the next request is queued.
1117          *    The following code is handling exactly that.
1118          *
1119          */
1120         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1121                 /*
1122                  * If xfernotready is already elapsed and it is a case
1123                  * of isoc transfer, then issue END TRANSFER, so that
1124                  * you can receive xfernotready again and can have
1125                  * notion of current microframe.
1126                  */
1127                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1128                         if (list_empty(&dep->started_list)) {
1129                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1130                                 dep->flags = DWC3_EP_ENABLED;
1131                         }
1132                         return 0;
1133                 }
1134
1135                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1136                 if (!ret)
1137                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1138
1139                 goto out;
1140         }
1141
1142         /*
1143          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1144          *    kick the transfer here after queuing a request, otherwise the
1145          *    core may not see the modified TRB(s).
1146          */
1147         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1148                         (dep->flags & DWC3_EP_BUSY) &&
1149                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1150                 WARN_ON_ONCE(!dep->resource_index);
1151                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1152                                 false);
1153                 goto out;
1154         }
1155
1156         /*
1157          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1158          * right away, otherwise host will not know we have streams to be
1159          * handled.
1160          */
1161         if (dep->stream_capable)
1162                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1163
1164 out:
1165         if (ret && ret != -EBUSY)
1166                 dwc3_trace(trace_dwc3_gadget,
1167                                 "%s: failed to kick transfers\n",
1168                                 dep->name);
1169         if (ret == -EBUSY)
1170                 ret = 0;
1171
1172         return ret;
1173 }
1174
1175 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1176                 struct usb_request *request)
1177 {
1178         dwc3_gadget_ep_free_request(ep, request);
1179 }
1180
1181 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1182 {
1183         struct dwc3_request             *req;
1184         struct usb_request              *request;
1185         struct usb_ep                   *ep = &dep->endpoint;
1186
1187         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1188         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1189         if (!request)
1190                 return -ENOMEM;
1191
1192         request->length = 0;
1193         request->buf = dwc->zlp_buf;
1194         request->complete = __dwc3_gadget_ep_zlp_complete;
1195
1196         req = to_dwc3_request(request);
1197
1198         return __dwc3_gadget_ep_queue(dep, req);
1199 }
1200
1201 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1202         gfp_t gfp_flags)
1203 {
1204         struct dwc3_request             *req = to_dwc3_request(request);
1205         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1206         struct dwc3                     *dwc = dep->dwc;
1207
1208         unsigned long                   flags;
1209
1210         int                             ret;
1211
1212         spin_lock_irqsave(&dwc->lock, flags);
1213         ret = __dwc3_gadget_ep_queue(dep, req);
1214
1215         /*
1216          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1217          * setting request->zero, instead of doing magic, we will just queue an
1218          * extra usb_request ourselves so that it gets handled the same way as
1219          * any other request.
1220          */
1221         if (ret == 0 && request->zero && request->length &&
1222             (request->length % ep->maxpacket == 0))
1223                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1224
1225         spin_unlock_irqrestore(&dwc->lock, flags);
1226
1227         return ret;
1228 }
1229
1230 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1231                 struct usb_request *request)
1232 {
1233         struct dwc3_request             *req = to_dwc3_request(request);
1234         struct dwc3_request             *r = NULL;
1235
1236         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1237         struct dwc3                     *dwc = dep->dwc;
1238
1239         unsigned long                   flags;
1240         int                             ret = 0;
1241
1242         trace_dwc3_ep_dequeue(req);
1243
1244         spin_lock_irqsave(&dwc->lock, flags);
1245
1246         list_for_each_entry(r, &dep->pending_list, list) {
1247                 if (r == req)
1248                         break;
1249         }
1250
1251         if (r != req) {
1252                 list_for_each_entry(r, &dep->started_list, list) {
1253                         if (r == req)
1254                                 break;
1255                 }
1256                 if (r == req) {
1257                         /* wait until it is processed */
1258                         dwc3_stop_active_transfer(dwc, dep->number, true);
1259                         goto out1;
1260                 }
1261                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1262                                 request, ep->name);
1263                 ret = -EINVAL;
1264                 goto out0;
1265         }
1266
1267 out1:
1268         /* giveback the request */
1269         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1270
1271 out0:
1272         spin_unlock_irqrestore(&dwc->lock, flags);
1273
1274         return ret;
1275 }
1276
1277 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1278 {
1279         struct dwc3_gadget_ep_cmd_params        params;
1280         struct dwc3                             *dwc = dep->dwc;
1281         int                                     ret;
1282
1283         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1284                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1285                 return -EINVAL;
1286         }
1287
1288         memset(&params, 0x00, sizeof(params));
1289
1290         if (value) {
1291                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1292                                 (!list_empty(&dep->started_list) ||
1293                                  !list_empty(&dep->pending_list)))) {
1294                         dwc3_trace(trace_dwc3_gadget,
1295                                         "%s: pending request, cannot halt\n",
1296                                         dep->name);
1297                         return -EAGAIN;
1298                 }
1299
1300                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1301                         DWC3_DEPCMD_SETSTALL, &params);
1302                 if (ret)
1303                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1304                                         dep->name);
1305                 else
1306                         dep->flags |= DWC3_EP_STALL;
1307         } else {
1308                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1309                         DWC3_DEPCMD_CLEARSTALL, &params);
1310                 if (ret)
1311                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1312                                         dep->name);
1313                 else
1314                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1315         }
1316
1317         return ret;
1318 }
1319
1320 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1321 {
1322         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1323         struct dwc3                     *dwc = dep->dwc;
1324
1325         unsigned long                   flags;
1326
1327         int                             ret;
1328
1329         spin_lock_irqsave(&dwc->lock, flags);
1330         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1331         spin_unlock_irqrestore(&dwc->lock, flags);
1332
1333         return ret;
1334 }
1335
1336 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1337 {
1338         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1339         struct dwc3                     *dwc = dep->dwc;
1340         unsigned long                   flags;
1341         int                             ret;
1342
1343         spin_lock_irqsave(&dwc->lock, flags);
1344         dep->flags |= DWC3_EP_WEDGE;
1345
1346         if (dep->number == 0 || dep->number == 1)
1347                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1348         else
1349                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1350         spin_unlock_irqrestore(&dwc->lock, flags);
1351
1352         return ret;
1353 }
1354
1355 /* -------------------------------------------------------------------------- */
1356
1357 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1358         .bLength        = USB_DT_ENDPOINT_SIZE,
1359         .bDescriptorType = USB_DT_ENDPOINT,
1360         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1361 };
1362
1363 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1364         .enable         = dwc3_gadget_ep0_enable,
1365         .disable        = dwc3_gadget_ep0_disable,
1366         .alloc_request  = dwc3_gadget_ep_alloc_request,
1367         .free_request   = dwc3_gadget_ep_free_request,
1368         .queue          = dwc3_gadget_ep0_queue,
1369         .dequeue        = dwc3_gadget_ep_dequeue,
1370         .set_halt       = dwc3_gadget_ep0_set_halt,
1371         .set_wedge      = dwc3_gadget_ep_set_wedge,
1372 };
1373
1374 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1375         .enable         = dwc3_gadget_ep_enable,
1376         .disable        = dwc3_gadget_ep_disable,
1377         .alloc_request  = dwc3_gadget_ep_alloc_request,
1378         .free_request   = dwc3_gadget_ep_free_request,
1379         .queue          = dwc3_gadget_ep_queue,
1380         .dequeue        = dwc3_gadget_ep_dequeue,
1381         .set_halt       = dwc3_gadget_ep_set_halt,
1382         .set_wedge      = dwc3_gadget_ep_set_wedge,
1383 };
1384
1385 /* -------------------------------------------------------------------------- */
1386
1387 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1388 {
1389         struct dwc3             *dwc = gadget_to_dwc(g);
1390         u32                     reg;
1391
1392         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1393         return DWC3_DSTS_SOFFN(reg);
1394 }
1395
1396 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1397 {
1398         unsigned long           timeout;
1399
1400         int                     ret;
1401         u32                     reg;
1402
1403         u8                      link_state;
1404         u8                      speed;
1405
1406         /*
1407          * According to the Databook Remote wakeup request should
1408          * be issued only when the device is in early suspend state.
1409          *
1410          * We can check that via USB Link State bits in DSTS register.
1411          */
1412         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1413
1414         speed = reg & DWC3_DSTS_CONNECTSPD;
1415         if ((speed == DWC3_DSTS_SUPERSPEED) ||
1416             (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1417                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1418                 return -EINVAL;
1419         }
1420
1421         link_state = DWC3_DSTS_USBLNKST(reg);
1422
1423         switch (link_state) {
1424         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1425         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1426                 break;
1427         default:
1428                 dwc3_trace(trace_dwc3_gadget,
1429                                 "can't wakeup from '%s'\n",
1430                                 dwc3_gadget_link_string(link_state));
1431                 return -EINVAL;
1432         }
1433
1434         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1435         if (ret < 0) {
1436                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1437                 return ret;
1438         }
1439
1440         /* Recent versions do this automatically */
1441         if (dwc->revision < DWC3_REVISION_194A) {
1442                 /* write zeroes to Link Change Request */
1443                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1444                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1445                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1446         }
1447
1448         /* poll until Link State changes to ON */
1449         timeout = jiffies + msecs_to_jiffies(100);
1450
1451         while (!time_after(jiffies, timeout)) {
1452                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1453
1454                 /* in HS, means ON */
1455                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1456                         break;
1457         }
1458
1459         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1460                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1461                 return -EINVAL;
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1468 {
1469         struct dwc3             *dwc = gadget_to_dwc(g);
1470         unsigned long           flags;
1471         int                     ret;
1472
1473         spin_lock_irqsave(&dwc->lock, flags);
1474         ret = __dwc3_gadget_wakeup(dwc);
1475         spin_unlock_irqrestore(&dwc->lock, flags);
1476
1477         return ret;
1478 }
1479
1480 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1481                 int is_selfpowered)
1482 {
1483         struct dwc3             *dwc = gadget_to_dwc(g);
1484         unsigned long           flags;
1485
1486         spin_lock_irqsave(&dwc->lock, flags);
1487         g->is_selfpowered = !!is_selfpowered;
1488         spin_unlock_irqrestore(&dwc->lock, flags);
1489
1490         return 0;
1491 }
1492
1493 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1494 {
1495         u32                     reg;
1496         u32                     timeout = 500;
1497
1498         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1499         if (is_on) {
1500                 if (dwc->revision <= DWC3_REVISION_187A) {
1501                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1502                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1503                 }
1504
1505                 if (dwc->revision >= DWC3_REVISION_194A)
1506                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1507                 reg |= DWC3_DCTL_RUN_STOP;
1508
1509                 if (dwc->has_hibernation)
1510                         reg |= DWC3_DCTL_KEEP_CONNECT;
1511
1512                 dwc->pullups_connected = true;
1513         } else {
1514                 reg &= ~DWC3_DCTL_RUN_STOP;
1515
1516                 if (dwc->has_hibernation && !suspend)
1517                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1518
1519                 dwc->pullups_connected = false;
1520         }
1521
1522         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1523
1524         do {
1525                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1526                 if (is_on) {
1527                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1528                                 break;
1529                 } else {
1530                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1531                                 break;
1532                 }
1533                 timeout--;
1534                 if (!timeout)
1535                         return -ETIMEDOUT;
1536                 udelay(1);
1537         } while (1);
1538
1539         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1540                         dwc->gadget_driver
1541                         ? dwc->gadget_driver->function : "no-function",
1542                         is_on ? "connect" : "disconnect");
1543
1544         return 0;
1545 }
1546
1547 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1548 {
1549         struct dwc3             *dwc = gadget_to_dwc(g);
1550         unsigned long           flags;
1551         int                     ret;
1552
1553         is_on = !!is_on;
1554
1555         spin_lock_irqsave(&dwc->lock, flags);
1556         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1557         spin_unlock_irqrestore(&dwc->lock, flags);
1558
1559         return ret;
1560 }
1561
1562 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1563 {
1564         u32                     reg;
1565
1566         /* Enable all but Start and End of Frame IRQs */
1567         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1568                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1569                         DWC3_DEVTEN_CMDCMPLTEN |
1570                         DWC3_DEVTEN_ERRTICERREN |
1571                         DWC3_DEVTEN_WKUPEVTEN |
1572                         DWC3_DEVTEN_ULSTCNGEN |
1573                         DWC3_DEVTEN_CONNECTDONEEN |
1574                         DWC3_DEVTEN_USBRSTEN |
1575                         DWC3_DEVTEN_DISCONNEVTEN);
1576
1577         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1578 }
1579
1580 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1581 {
1582         /* mask all interrupts */
1583         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1584 }
1585
1586 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1587 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1588
1589 static int dwc3_gadget_start(struct usb_gadget *g,
1590                 struct usb_gadget_driver *driver)
1591 {
1592         struct dwc3             *dwc = gadget_to_dwc(g);
1593         struct dwc3_ep          *dep;
1594         unsigned long           flags;
1595         int                     ret = 0;
1596         int                     irq;
1597         u32                     reg;
1598
1599         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1600         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1601                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1602         if (ret) {
1603                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1604                                 irq, ret);
1605                 goto err0;
1606         }
1607
1608         spin_lock_irqsave(&dwc->lock, flags);
1609
1610         if (dwc->gadget_driver) {
1611                 dev_err(dwc->dev, "%s is already bound to %s\n",
1612                                 dwc->gadget.name,
1613                                 dwc->gadget_driver->driver.name);
1614                 ret = -EBUSY;
1615                 goto err1;
1616         }
1617
1618         dwc->gadget_driver      = driver;
1619
1620         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1621         reg &= ~(DWC3_DCFG_SPEED_MASK);
1622
1623         /**
1624          * WORKAROUND: DWC3 revision < 2.20a have an issue
1625          * which would cause metastability state on Run/Stop
1626          * bit if we try to force the IP to USB2-only mode.
1627          *
1628          * Because of that, we cannot configure the IP to any
1629          * speed other than the SuperSpeed
1630          *
1631          * Refers to:
1632          *
1633          * STAR#9000525659: Clock Domain Crossing on DCTL in
1634          * USB 2.0 Mode
1635          */
1636         if (dwc->revision < DWC3_REVISION_220A) {
1637                 reg |= DWC3_DCFG_SUPERSPEED;
1638         } else {
1639                 switch (dwc->maximum_speed) {
1640                 case USB_SPEED_LOW:
1641                         reg |= DWC3_DSTS_LOWSPEED;
1642                         break;
1643                 case USB_SPEED_FULL:
1644                         reg |= DWC3_DSTS_FULLSPEED1;
1645                         break;
1646                 case USB_SPEED_HIGH:
1647                         reg |= DWC3_DSTS_HIGHSPEED;
1648                         break;
1649                 case USB_SPEED_SUPER_PLUS:
1650                         reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1651                         break;
1652                 default:
1653                         dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1654                                 dwc->maximum_speed);
1655                         /* fall through */
1656                 case USB_SPEED_SUPER:
1657                         reg |= DWC3_DCFG_SUPERSPEED;
1658                         break;
1659                 }
1660         }
1661         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1662
1663         /* Start with SuperSpeed Default */
1664         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1665
1666         dep = dwc->eps[0];
1667         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1668                         false);
1669         if (ret) {
1670                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1671                 goto err2;
1672         }
1673
1674         dep = dwc->eps[1];
1675         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1676                         false);
1677         if (ret) {
1678                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1679                 goto err3;
1680         }
1681
1682         /* begin to receive SETUP packets */
1683         dwc->ep0state = EP0_SETUP_PHASE;
1684         dwc3_ep0_out_start(dwc);
1685
1686         dwc3_gadget_enable_irq(dwc);
1687
1688         spin_unlock_irqrestore(&dwc->lock, flags);
1689
1690         return 0;
1691
1692 err3:
1693         __dwc3_gadget_ep_disable(dwc->eps[0]);
1694
1695 err2:
1696         dwc->gadget_driver = NULL;
1697
1698 err1:
1699         spin_unlock_irqrestore(&dwc->lock, flags);
1700
1701         free_irq(irq, dwc->ev_buf);
1702
1703 err0:
1704         return ret;
1705 }
1706
1707 static int dwc3_gadget_stop(struct usb_gadget *g)
1708 {
1709         struct dwc3             *dwc = gadget_to_dwc(g);
1710         unsigned long           flags;
1711         int                     irq;
1712
1713         spin_lock_irqsave(&dwc->lock, flags);
1714
1715         dwc3_gadget_disable_irq(dwc);
1716         __dwc3_gadget_ep_disable(dwc->eps[0]);
1717         __dwc3_gadget_ep_disable(dwc->eps[1]);
1718
1719         dwc->gadget_driver      = NULL;
1720
1721         spin_unlock_irqrestore(&dwc->lock, flags);
1722
1723         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1724         free_irq(irq, dwc->ev_buf);
1725
1726         return 0;
1727 }
1728
1729 static const struct usb_gadget_ops dwc3_gadget_ops = {
1730         .get_frame              = dwc3_gadget_get_frame,
1731         .wakeup                 = dwc3_gadget_wakeup,
1732         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1733         .pullup                 = dwc3_gadget_pullup,
1734         .udc_start              = dwc3_gadget_start,
1735         .udc_stop               = dwc3_gadget_stop,
1736 };
1737
1738 /* -------------------------------------------------------------------------- */
1739
1740 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1741                 u8 num, u32 direction)
1742 {
1743         struct dwc3_ep                  *dep;
1744         u8                              i;
1745
1746         for (i = 0; i < num; i++) {
1747                 u8 epnum = (i << 1) | (!!direction);
1748
1749                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1750                 if (!dep)
1751                         return -ENOMEM;
1752
1753                 dep->dwc = dwc;
1754                 dep->number = epnum;
1755                 dep->direction = !!direction;
1756                 dwc->eps[epnum] = dep;
1757
1758                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1759                                 (epnum & 1) ? "in" : "out");
1760
1761                 dep->endpoint.name = dep->name;
1762
1763                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1764
1765                 if (epnum == 0 || epnum == 1) {
1766                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1767                         dep->endpoint.maxburst = 1;
1768                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1769                         if (!epnum)
1770                                 dwc->gadget.ep0 = &dep->endpoint;
1771                 } else {
1772                         int             ret;
1773
1774                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1775                         dep->endpoint.max_streams = 15;
1776                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1777                         list_add_tail(&dep->endpoint.ep_list,
1778                                         &dwc->gadget.ep_list);
1779
1780                         ret = dwc3_alloc_trb_pool(dep);
1781                         if (ret)
1782                                 return ret;
1783                 }
1784
1785                 if (epnum == 0 || epnum == 1) {
1786                         dep->endpoint.caps.type_control = true;
1787                 } else {
1788                         dep->endpoint.caps.type_iso = true;
1789                         dep->endpoint.caps.type_bulk = true;
1790                         dep->endpoint.caps.type_int = true;
1791                 }
1792
1793                 dep->endpoint.caps.dir_in = !!direction;
1794                 dep->endpoint.caps.dir_out = !direction;
1795
1796                 INIT_LIST_HEAD(&dep->pending_list);
1797                 INIT_LIST_HEAD(&dep->started_list);
1798         }
1799
1800         return 0;
1801 }
1802
1803 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1804 {
1805         int                             ret;
1806
1807         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1808
1809         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1810         if (ret < 0) {
1811                 dwc3_trace(trace_dwc3_gadget,
1812                                 "failed to allocate OUT endpoints");
1813                 return ret;
1814         }
1815
1816         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1817         if (ret < 0) {
1818                 dwc3_trace(trace_dwc3_gadget,
1819                                 "failed to allocate IN endpoints");
1820                 return ret;
1821         }
1822
1823         return 0;
1824 }
1825
1826 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1827 {
1828         struct dwc3_ep                  *dep;
1829         u8                              epnum;
1830
1831         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1832                 dep = dwc->eps[epnum];
1833                 if (!dep)
1834                         continue;
1835                 /*
1836                  * Physical endpoints 0 and 1 are special; they form the
1837                  * bi-directional USB endpoint 0.
1838                  *
1839                  * For those two physical endpoints, we don't allocate a TRB
1840                  * pool nor do we add them the endpoints list. Due to that, we
1841                  * shouldn't do these two operations otherwise we would end up
1842                  * with all sorts of bugs when removing dwc3.ko.
1843                  */
1844                 if (epnum != 0 && epnum != 1) {
1845                         dwc3_free_trb_pool(dep);
1846                         list_del(&dep->endpoint.ep_list);
1847                 }
1848
1849                 kfree(dep);
1850         }
1851 }
1852
1853 /* -------------------------------------------------------------------------- */
1854
1855 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1856                 struct dwc3_request *req, struct dwc3_trb *trb,
1857                 const struct dwc3_event_depevt *event, int status)
1858 {
1859         unsigned int            count;
1860         unsigned int            s_pkt = 0;
1861         unsigned int            trb_status;
1862
1863         trace_dwc3_complete_trb(dep, trb);
1864
1865         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1866                 /*
1867                  * We continue despite the error. There is not much we
1868                  * can do. If we don't clean it up we loop forever. If
1869                  * we skip the TRB then it gets overwritten after a
1870                  * while since we use them in a ring buffer. A BUG()
1871                  * would help. Lets hope that if this occurs, someone
1872                  * fixes the root cause instead of looking away :)
1873                  */
1874                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1875                                 dep->name, trb);
1876         count = trb->size & DWC3_TRB_SIZE_MASK;
1877
1878         if (dep->direction) {
1879                 if (count) {
1880                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1881                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1882                                 dwc3_trace(trace_dwc3_gadget,
1883                                                 "%s: incomplete IN transfer\n",
1884                                                 dep->name);
1885                                 /*
1886                                  * If missed isoc occurred and there is
1887                                  * no request queued then issue END
1888                                  * TRANSFER, so that core generates
1889                                  * next xfernotready and we will issue
1890                                  * a fresh START TRANSFER.
1891                                  * If there are still queued request
1892                                  * then wait, do not issue either END
1893                                  * or UPDATE TRANSFER, just attach next
1894                                  * request in pending_list during
1895                                  * giveback.If any future queued request
1896                                  * is successfully transferred then we
1897                                  * will issue UPDATE TRANSFER for all
1898                                  * request in the pending_list.
1899                                  */
1900                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1901                         } else {
1902                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1903                                                 dep->name);
1904                                 status = -ECONNRESET;
1905                         }
1906                 } else {
1907                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1908                 }
1909         } else {
1910                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1911                         s_pkt = 1;
1912         }
1913
1914         /*
1915          * We assume here we will always receive the entire data block
1916          * which we should receive. Meaning, if we program RX to
1917          * receive 4K but we receive only 2K, we assume that's all we
1918          * should receive and we simply bounce the request back to the
1919          * gadget driver for further processing.
1920          */
1921         req->request.actual += req->request.length - count;
1922         if (s_pkt)
1923                 return 1;
1924         if ((event->status & DEPEVT_STATUS_LST) &&
1925                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1926                                 DWC3_TRB_CTRL_HWO)))
1927                 return 1;
1928         if ((event->status & DEPEVT_STATUS_IOC) &&
1929                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1930                 return 1;
1931         return 0;
1932 }
1933
1934 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1935                 const struct dwc3_event_depevt *event, int status)
1936 {
1937         struct dwc3_request     *req;
1938         struct dwc3_trb         *trb;
1939         unsigned int            slot;
1940         unsigned int            i;
1941         int                     ret;
1942
1943         do {
1944                 req = next_request(&dep->started_list);
1945                 if (WARN_ON_ONCE(!req))
1946                         return 1;
1947
1948                 i = 0;
1949                 do {
1950                         slot = req->first_trb_index + i;
1951                         if ((slot == DWC3_TRB_NUM - 1) &&
1952                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1953                                 slot++;
1954                         slot %= DWC3_TRB_NUM;
1955                         trb = &dep->trb_pool[slot];
1956
1957                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1958                                         event, status);
1959                         if (ret)
1960                                 break;
1961                 } while (++i < req->request.num_mapped_sgs);
1962
1963                 dwc3_gadget_giveback(dep, req, status);
1964
1965                 if (ret)
1966                         break;
1967         } while (1);
1968
1969         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1970                         list_empty(&dep->started_list)) {
1971                 if (list_empty(&dep->pending_list)) {
1972                         /*
1973                          * If there is no entry in request list then do
1974                          * not issue END TRANSFER now. Just set PENDING
1975                          * flag, so that END TRANSFER is issued when an
1976                          * entry is added into request list.
1977                          */
1978                         dep->flags = DWC3_EP_PENDING_REQUEST;
1979                 } else {
1980                         dwc3_stop_active_transfer(dwc, dep->number, true);
1981                         dep->flags = DWC3_EP_ENABLED;
1982                 }
1983                 return 1;
1984         }
1985
1986         return 1;
1987 }
1988
1989 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1990                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1991 {
1992         unsigned                status = 0;
1993         int                     clean_busy;
1994         u32                     is_xfer_complete;
1995
1996         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
1997
1998         if (event->status & DEPEVT_STATUS_BUSERR)
1999                 status = -ECONNRESET;
2000
2001         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2002         if (clean_busy && (is_xfer_complete ||
2003                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2004                 dep->flags &= ~DWC3_EP_BUSY;
2005
2006         /*
2007          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2008          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2009          */
2010         if (dwc->revision < DWC3_REVISION_183A) {
2011                 u32             reg;
2012                 int             i;
2013
2014                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2015                         dep = dwc->eps[i];
2016
2017                         if (!(dep->flags & DWC3_EP_ENABLED))
2018                                 continue;
2019
2020                         if (!list_empty(&dep->started_list))
2021                                 return;
2022                 }
2023
2024                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2025                 reg |= dwc->u1u2;
2026                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2027
2028                 dwc->u1u2 = 0;
2029         }
2030
2031         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2032                 int ret;
2033
2034                 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2035                 if (!ret || ret == -EBUSY)
2036                         return;
2037         }
2038 }
2039
2040 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2041                 const struct dwc3_event_depevt *event)
2042 {
2043         struct dwc3_ep          *dep;
2044         u8                      epnum = event->endpoint_number;
2045
2046         dep = dwc->eps[epnum];
2047
2048         if (!(dep->flags & DWC3_EP_ENABLED))
2049                 return;
2050
2051         if (epnum == 0 || epnum == 1) {
2052                 dwc3_ep0_interrupt(dwc, event);
2053                 return;
2054         }
2055
2056         switch (event->endpoint_event) {
2057         case DWC3_DEPEVT_XFERCOMPLETE:
2058                 dep->resource_index = 0;
2059
2060                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2061                         dwc3_trace(trace_dwc3_gadget,
2062                                         "%s is an Isochronous endpoint\n",
2063                                         dep->name);
2064                         return;
2065                 }
2066
2067                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2068                 break;
2069         case DWC3_DEPEVT_XFERINPROGRESS:
2070                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2071                 break;
2072         case DWC3_DEPEVT_XFERNOTREADY:
2073                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2074                         dwc3_gadget_start_isoc(dwc, dep, event);
2075                 } else {
2076                         int active;
2077                         int ret;
2078
2079                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2080
2081                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2082                                         dep->name, active ? "Transfer Active"
2083                                         : "Transfer Not Active");
2084
2085                         ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2086                         if (!ret || ret == -EBUSY)
2087                                 return;
2088
2089                         dwc3_trace(trace_dwc3_gadget,
2090                                         "%s: failed to kick transfers\n",
2091                                         dep->name);
2092                 }
2093
2094                 break;
2095         case DWC3_DEPEVT_STREAMEVT:
2096                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2097                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2098                                         dep->name);
2099                         return;
2100                 }
2101
2102                 switch (event->status) {
2103                 case DEPEVT_STREAMEVT_FOUND:
2104                         dwc3_trace(trace_dwc3_gadget,
2105                                         "Stream %d found and started",
2106                                         event->parameters);
2107
2108                         break;
2109                 case DEPEVT_STREAMEVT_NOTFOUND:
2110                         /* FALLTHROUGH */
2111                 default:
2112                         dwc3_trace(trace_dwc3_gadget,
2113                                         "unable to find suitable stream\n");
2114                 }
2115                 break;
2116         case DWC3_DEPEVT_RXTXFIFOEVT:
2117                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2118                 break;
2119         case DWC3_DEPEVT_EPCMDCMPLT:
2120                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2121                 break;
2122         }
2123 }
2124
2125 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2126 {
2127         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2128                 spin_unlock(&dwc->lock);
2129                 dwc->gadget_driver->disconnect(&dwc->gadget);
2130                 spin_lock(&dwc->lock);
2131         }
2132 }
2133
2134 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2135 {
2136         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2137                 spin_unlock(&dwc->lock);
2138                 dwc->gadget_driver->suspend(&dwc->gadget);
2139                 spin_lock(&dwc->lock);
2140         }
2141 }
2142
2143 static void dwc3_resume_gadget(struct dwc3 *dwc)
2144 {
2145         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2146                 spin_unlock(&dwc->lock);
2147                 dwc->gadget_driver->resume(&dwc->gadget);
2148                 spin_lock(&dwc->lock);
2149         }
2150 }
2151
2152 static void dwc3_reset_gadget(struct dwc3 *dwc)
2153 {
2154         if (!dwc->gadget_driver)
2155                 return;
2156
2157         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2158                 spin_unlock(&dwc->lock);
2159                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2160                 spin_lock(&dwc->lock);
2161         }
2162 }
2163
2164 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2165 {
2166         struct dwc3_ep *dep;
2167         struct dwc3_gadget_ep_cmd_params params;
2168         u32 cmd;
2169         int ret;
2170
2171         dep = dwc->eps[epnum];
2172
2173         if (!dep->resource_index)
2174                 return;
2175
2176         /*
2177          * NOTICE: We are violating what the Databook says about the
2178          * EndTransfer command. Ideally we would _always_ wait for the
2179          * EndTransfer Command Completion IRQ, but that's causing too
2180          * much trouble synchronizing between us and gadget driver.
2181          *
2182          * We have discussed this with the IP Provider and it was
2183          * suggested to giveback all requests here, but give HW some
2184          * extra time to synchronize with the interconnect. We're using
2185          * an arbitrary 100us delay for that.
2186          *
2187          * Note also that a similar handling was tested by Synopsys
2188          * (thanks a lot Paul) and nothing bad has come out of it.
2189          * In short, what we're doing is:
2190          *
2191          * - Issue EndTransfer WITH CMDIOC bit set
2192          * - Wait 100us
2193          */
2194
2195         cmd = DWC3_DEPCMD_ENDTRANSFER;
2196         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2197         cmd |= DWC3_DEPCMD_CMDIOC;
2198         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2199         memset(&params, 0, sizeof(params));
2200         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2201         WARN_ON_ONCE(ret);
2202         dep->resource_index = 0;
2203         dep->flags &= ~DWC3_EP_BUSY;
2204         udelay(100);
2205 }
2206
2207 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2208 {
2209         u32 epnum;
2210
2211         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2212                 struct dwc3_ep *dep;
2213
2214                 dep = dwc->eps[epnum];
2215                 if (!dep)
2216                         continue;
2217
2218                 if (!(dep->flags & DWC3_EP_ENABLED))
2219                         continue;
2220
2221                 dwc3_remove_requests(dwc, dep);
2222         }
2223 }
2224
2225 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2226 {
2227         u32 epnum;
2228
2229         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2230                 struct dwc3_ep *dep;
2231                 struct dwc3_gadget_ep_cmd_params params;
2232                 int ret;
2233
2234                 dep = dwc->eps[epnum];
2235                 if (!dep)
2236                         continue;
2237
2238                 if (!(dep->flags & DWC3_EP_STALL))
2239                         continue;
2240
2241                 dep->flags &= ~DWC3_EP_STALL;
2242
2243                 memset(&params, 0, sizeof(params));
2244                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2245                                 DWC3_DEPCMD_CLEARSTALL, &params);
2246                 WARN_ON_ONCE(ret);
2247         }
2248 }
2249
2250 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2251 {
2252         int                     reg;
2253
2254         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2255         reg &= ~DWC3_DCTL_INITU1ENA;
2256         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2257
2258         reg &= ~DWC3_DCTL_INITU2ENA;
2259         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2260
2261         dwc3_disconnect_gadget(dwc);
2262
2263         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2264         dwc->setup_packet_pending = false;
2265         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2266 }
2267
2268 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2269 {
2270         u32                     reg;
2271
2272         /*
2273          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2274          * would cause a missing Disconnect Event if there's a
2275          * pending Setup Packet in the FIFO.
2276          *
2277          * There's no suggested workaround on the official Bug
2278          * report, which states that "unless the driver/application
2279          * is doing any special handling of a disconnect event,
2280          * there is no functional issue".
2281          *
2282          * Unfortunately, it turns out that we _do_ some special
2283          * handling of a disconnect event, namely complete all
2284          * pending transfers, notify gadget driver of the
2285          * disconnection, and so on.
2286          *
2287          * Our suggested workaround is to follow the Disconnect
2288          * Event steps here, instead, based on a setup_packet_pending
2289          * flag. Such flag gets set whenever we have a SETUP_PENDING
2290          * status for EP0 TRBs and gets cleared on XferComplete for the
2291          * same endpoint.
2292          *
2293          * Refers to:
2294          *
2295          * STAR#9000466709: RTL: Device : Disconnect event not
2296          * generated if setup packet pending in FIFO
2297          */
2298         if (dwc->revision < DWC3_REVISION_188A) {
2299                 if (dwc->setup_packet_pending)
2300                         dwc3_gadget_disconnect_interrupt(dwc);
2301         }
2302
2303         dwc3_reset_gadget(dwc);
2304
2305         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2306         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2307         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2308         dwc->test_mode = false;
2309
2310         dwc3_stop_active_transfers(dwc);
2311         dwc3_clear_stall_all_ep(dwc);
2312
2313         /* Reset device address to zero */
2314         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2315         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2316         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2317 }
2318
2319 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2320 {
2321         u32 reg;
2322         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2323
2324         /*
2325          * We change the clock only at SS but I dunno why I would want to do
2326          * this. Maybe it becomes part of the power saving plan.
2327          */
2328
2329         if ((speed != DWC3_DSTS_SUPERSPEED) &&
2330             (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2331                 return;
2332
2333         /*
2334          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2335          * each time on Connect Done.
2336          */
2337         if (!usb30_clock)
2338                 return;
2339
2340         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2341         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2342         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2343 }
2344
2345 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2346 {
2347         struct dwc3_ep          *dep;
2348         int                     ret;
2349         u32                     reg;
2350         u8                      speed;
2351
2352         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2353         speed = reg & DWC3_DSTS_CONNECTSPD;
2354         dwc->speed = speed;
2355
2356         dwc3_update_ram_clk_sel(dwc, speed);
2357
2358         switch (speed) {
2359         case DWC3_DCFG_SUPERSPEED_PLUS:
2360                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2361                 dwc->gadget.ep0->maxpacket = 512;
2362                 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2363                 break;
2364         case DWC3_DCFG_SUPERSPEED:
2365                 /*
2366                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2367                  * would cause a missing USB3 Reset event.
2368                  *
2369                  * In such situations, we should force a USB3 Reset
2370                  * event by calling our dwc3_gadget_reset_interrupt()
2371                  * routine.
2372                  *
2373                  * Refers to:
2374                  *
2375                  * STAR#9000483510: RTL: SS : USB3 reset event may
2376                  * not be generated always when the link enters poll
2377                  */
2378                 if (dwc->revision < DWC3_REVISION_190A)
2379                         dwc3_gadget_reset_interrupt(dwc);
2380
2381                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2382                 dwc->gadget.ep0->maxpacket = 512;
2383                 dwc->gadget.speed = USB_SPEED_SUPER;
2384                 break;
2385         case DWC3_DCFG_HIGHSPEED:
2386                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2387                 dwc->gadget.ep0->maxpacket = 64;
2388                 dwc->gadget.speed = USB_SPEED_HIGH;
2389                 break;
2390         case DWC3_DCFG_FULLSPEED2:
2391         case DWC3_DCFG_FULLSPEED1:
2392                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2393                 dwc->gadget.ep0->maxpacket = 64;
2394                 dwc->gadget.speed = USB_SPEED_FULL;
2395                 break;
2396         case DWC3_DCFG_LOWSPEED:
2397                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2398                 dwc->gadget.ep0->maxpacket = 8;
2399                 dwc->gadget.speed = USB_SPEED_LOW;
2400                 break;
2401         }
2402
2403         /* Enable USB2 LPM Capability */
2404
2405         if ((dwc->revision > DWC3_REVISION_194A) &&
2406             (speed != DWC3_DCFG_SUPERSPEED) &&
2407             (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2408                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2409                 reg |= DWC3_DCFG_LPM_CAP;
2410                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2411
2412                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2413                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2414
2415                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2416
2417                 /*
2418                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2419                  * DCFG.LPMCap is set, core responses with an ACK and the
2420                  * BESL value in the LPM token is less than or equal to LPM
2421                  * NYET threshold.
2422                  */
2423                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2424                                 && dwc->has_lpm_erratum,
2425                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2426
2427                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2428                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2429
2430                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2431         } else {
2432                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2433                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2434                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2435         }
2436
2437         dep = dwc->eps[0];
2438         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2439                         false);
2440         if (ret) {
2441                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2442                 return;
2443         }
2444
2445         dep = dwc->eps[1];
2446         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2447                         false);
2448         if (ret) {
2449                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2450                 return;
2451         }
2452
2453         /*
2454          * Configure PHY via GUSB3PIPECTLn if required.
2455          *
2456          * Update GTXFIFOSIZn
2457          *
2458          * In both cases reset values should be sufficient.
2459          */
2460 }
2461
2462 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2463 {
2464         /*
2465          * TODO take core out of low power mode when that's
2466          * implemented.
2467          */
2468
2469         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2470                 spin_unlock(&dwc->lock);
2471                 dwc->gadget_driver->resume(&dwc->gadget);
2472                 spin_lock(&dwc->lock);
2473         }
2474 }
2475
2476 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2477                 unsigned int evtinfo)
2478 {
2479         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2480         unsigned int            pwropt;
2481
2482         /*
2483          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2484          * Hibernation mode enabled which would show up when device detects
2485          * host-initiated U3 exit.
2486          *
2487          * In that case, device will generate a Link State Change Interrupt
2488          * from U3 to RESUME which is only necessary if Hibernation is
2489          * configured in.
2490          *
2491          * There are no functional changes due to such spurious event and we
2492          * just need to ignore it.
2493          *
2494          * Refers to:
2495          *
2496          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2497          * operational mode
2498          */
2499         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2500         if ((dwc->revision < DWC3_REVISION_250A) &&
2501                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2502                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2503                                 (next == DWC3_LINK_STATE_RESUME)) {
2504                         dwc3_trace(trace_dwc3_gadget,
2505                                         "ignoring transition U3 -> Resume");
2506                         return;
2507                 }
2508         }
2509
2510         /*
2511          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2512          * on the link partner, the USB session might do multiple entry/exit
2513          * of low power states before a transfer takes place.
2514          *
2515          * Due to this problem, we might experience lower throughput. The
2516          * suggested workaround is to disable DCTL[12:9] bits if we're
2517          * transitioning from U1/U2 to U0 and enable those bits again
2518          * after a transfer completes and there are no pending transfers
2519          * on any of the enabled endpoints.
2520          *
2521          * This is the first half of that workaround.
2522          *
2523          * Refers to:
2524          *
2525          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2526          * core send LGO_Ux entering U0
2527          */
2528         if (dwc->revision < DWC3_REVISION_183A) {
2529                 if (next == DWC3_LINK_STATE_U0) {
2530                         u32     u1u2;
2531                         u32     reg;
2532
2533                         switch (dwc->link_state) {
2534                         case DWC3_LINK_STATE_U1:
2535                         case DWC3_LINK_STATE_U2:
2536                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2537                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2538                                                 | DWC3_DCTL_ACCEPTU2ENA
2539                                                 | DWC3_DCTL_INITU1ENA
2540                                                 | DWC3_DCTL_ACCEPTU1ENA);
2541
2542                                 if (!dwc->u1u2)
2543                                         dwc->u1u2 = reg & u1u2;
2544
2545                                 reg &= ~u1u2;
2546
2547                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2548                                 break;
2549                         default:
2550                                 /* do nothing */
2551                                 break;
2552                         }
2553                 }
2554         }
2555
2556         switch (next) {
2557         case DWC3_LINK_STATE_U1:
2558                 if (dwc->speed == USB_SPEED_SUPER)
2559                         dwc3_suspend_gadget(dwc);
2560                 break;
2561         case DWC3_LINK_STATE_U2:
2562         case DWC3_LINK_STATE_U3:
2563                 dwc3_suspend_gadget(dwc);
2564                 break;
2565         case DWC3_LINK_STATE_RESUME:
2566                 dwc3_resume_gadget(dwc);
2567                 break;
2568         default:
2569                 /* do nothing */
2570                 break;
2571         }
2572
2573         dwc->link_state = next;
2574 }
2575
2576 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2577                 unsigned int evtinfo)
2578 {
2579         unsigned int is_ss = evtinfo & BIT(4);
2580
2581         /**
2582          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2583          * have a known issue which can cause USB CV TD.9.23 to fail
2584          * randomly.
2585          *
2586          * Because of this issue, core could generate bogus hibernation
2587          * events which SW needs to ignore.
2588          *
2589          * Refers to:
2590          *
2591          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2592          * Device Fallback from SuperSpeed
2593          */
2594         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2595                 return;
2596
2597         /* enter hibernation here */
2598 }
2599
2600 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2601                 const struct dwc3_event_devt *event)
2602 {
2603         switch (event->type) {
2604         case DWC3_DEVICE_EVENT_DISCONNECT:
2605                 dwc3_gadget_disconnect_interrupt(dwc);
2606                 break;
2607         case DWC3_DEVICE_EVENT_RESET:
2608                 dwc3_gadget_reset_interrupt(dwc);
2609                 break;
2610         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2611                 dwc3_gadget_conndone_interrupt(dwc);
2612                 break;
2613         case DWC3_DEVICE_EVENT_WAKEUP:
2614                 dwc3_gadget_wakeup_interrupt(dwc);
2615                 break;
2616         case DWC3_DEVICE_EVENT_HIBER_REQ:
2617                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2618                                         "unexpected hibernation event\n"))
2619                         break;
2620
2621                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2622                 break;
2623         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2624                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2625                 break;
2626         case DWC3_DEVICE_EVENT_EOPF:
2627                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2628                 break;
2629         case DWC3_DEVICE_EVENT_SOF:
2630                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2631                 break;
2632         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2633                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2634                 break;
2635         case DWC3_DEVICE_EVENT_CMD_CMPL:
2636                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2637                 break;
2638         case DWC3_DEVICE_EVENT_OVERFLOW:
2639                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2640                 break;
2641         default:
2642                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2643         }
2644 }
2645
2646 static void dwc3_process_event_entry(struct dwc3 *dwc,
2647                 const union dwc3_event *event)
2648 {
2649         trace_dwc3_event(event->raw);
2650
2651         /* Endpoint IRQ, handle it and return early */
2652         if (event->type.is_devspec == 0) {
2653                 /* depevt */
2654                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2655         }
2656
2657         switch (event->type.type) {
2658         case DWC3_EVENT_TYPE_DEV:
2659                 dwc3_gadget_interrupt(dwc, &event->devt);
2660                 break;
2661         /* REVISIT what to do with Carkit and I2C events ? */
2662         default:
2663                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2664         }
2665 }
2666
2667 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2668 {
2669         struct dwc3 *dwc = evt->dwc;
2670         irqreturn_t ret = IRQ_NONE;
2671         int left;
2672         u32 reg;
2673
2674         left = evt->count;
2675
2676         if (!(evt->flags & DWC3_EVENT_PENDING))
2677                 return IRQ_NONE;
2678
2679         while (left > 0) {
2680                 union dwc3_event event;
2681
2682                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2683
2684                 dwc3_process_event_entry(dwc, &event);
2685
2686                 /*
2687                  * FIXME we wrap around correctly to the next entry as
2688                  * almost all entries are 4 bytes in size. There is one
2689                  * entry which has 12 bytes which is a regular entry
2690                  * followed by 8 bytes data. ATM I don't know how
2691                  * things are organized if we get next to the a
2692                  * boundary so I worry about that once we try to handle
2693                  * that.
2694                  */
2695                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2696                 left -= 4;
2697
2698                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2699         }
2700
2701         evt->count = 0;
2702         evt->flags &= ~DWC3_EVENT_PENDING;
2703         ret = IRQ_HANDLED;
2704
2705         /* Unmask interrupt */
2706         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2707         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2708         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2709
2710         return ret;
2711 }
2712
2713 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2714 {
2715         struct dwc3_event_buffer *evt = _evt;
2716         struct dwc3 *dwc = evt->dwc;
2717         unsigned long flags;
2718         irqreturn_t ret = IRQ_NONE;
2719
2720         spin_lock_irqsave(&dwc->lock, flags);
2721         ret = dwc3_process_event_buf(evt);
2722         spin_unlock_irqrestore(&dwc->lock, flags);
2723
2724         return ret;
2725 }
2726
2727 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2728 {
2729         struct dwc3 *dwc = evt->dwc;
2730         u32 count;
2731         u32 reg;
2732
2733         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2734         count &= DWC3_GEVNTCOUNT_MASK;
2735         if (!count)
2736                 return IRQ_NONE;
2737
2738         evt->count = count;
2739         evt->flags |= DWC3_EVENT_PENDING;
2740
2741         /* Mask interrupt */
2742         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2743         reg |= DWC3_GEVNTSIZ_INTMASK;
2744         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2745
2746         return IRQ_WAKE_THREAD;
2747 }
2748
2749 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2750 {
2751         struct dwc3_event_buffer        *evt = _evt;
2752
2753         return dwc3_check_event_buf(evt);
2754 }
2755
2756 /**
2757  * dwc3_gadget_init - Initializes gadget related registers
2758  * @dwc: pointer to our controller context structure
2759  *
2760  * Returns 0 on success otherwise negative errno.
2761  */
2762 int dwc3_gadget_init(struct dwc3 *dwc)
2763 {
2764         int                                     ret;
2765
2766         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2767                         &dwc->ctrl_req_addr, GFP_KERNEL);
2768         if (!dwc->ctrl_req) {
2769                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2770                 ret = -ENOMEM;
2771                 goto err0;
2772         }
2773
2774         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2775                         &dwc->ep0_trb_addr, GFP_KERNEL);
2776         if (!dwc->ep0_trb) {
2777                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2778                 ret = -ENOMEM;
2779                 goto err1;
2780         }
2781
2782         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2783         if (!dwc->setup_buf) {
2784                 ret = -ENOMEM;
2785                 goto err2;
2786         }
2787
2788         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2789                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2790                         GFP_KERNEL);
2791         if (!dwc->ep0_bounce) {
2792                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2793                 ret = -ENOMEM;
2794                 goto err3;
2795         }
2796
2797         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2798         if (!dwc->zlp_buf) {
2799                 ret = -ENOMEM;
2800                 goto err4;
2801         }
2802
2803         dwc->gadget.ops                 = &dwc3_gadget_ops;
2804         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2805         dwc->gadget.sg_supported        = true;
2806         dwc->gadget.name                = "dwc3-gadget";
2807         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2808
2809         /*
2810          * FIXME We might be setting max_speed to <SUPER, however versions
2811          * <2.20a of dwc3 have an issue with metastability (documented
2812          * elsewhere in this driver) which tells us we can't set max speed to
2813          * anything lower than SUPER.
2814          *
2815          * Because gadget.max_speed is only used by composite.c and function
2816          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2817          * to happen so we avoid sending SuperSpeed Capability descriptor
2818          * together with our BOS descriptor as that could confuse host into
2819          * thinking we can handle super speed.
2820          *
2821          * Note that, in fact, we won't even support GetBOS requests when speed
2822          * is less than super speed because we don't have means, yet, to tell
2823          * composite.c that we are USB 2.0 + LPM ECN.
2824          */
2825         if (dwc->revision < DWC3_REVISION_220A)
2826                 dwc3_trace(trace_dwc3_gadget,
2827                                 "Changing max_speed on rev %08x\n",
2828                                 dwc->revision);
2829
2830         dwc->gadget.max_speed           = dwc->maximum_speed;
2831
2832         /*
2833          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2834          * on ep out.
2835          */
2836         dwc->gadget.quirk_ep_out_aligned_size = true;
2837
2838         /*
2839          * REVISIT: Here we should clear all pending IRQs to be
2840          * sure we're starting from a well known location.
2841          */
2842
2843         ret = dwc3_gadget_init_endpoints(dwc);
2844         if (ret)
2845                 goto err5;
2846
2847         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2848         if (ret) {
2849                 dev_err(dwc->dev, "failed to register udc\n");
2850                 goto err5;
2851         }
2852
2853         return 0;
2854
2855 err5:
2856         kfree(dwc->zlp_buf);
2857
2858 err4:
2859         dwc3_gadget_free_endpoints(dwc);
2860         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2861                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2862
2863 err3:
2864         kfree(dwc->setup_buf);
2865
2866 err2:
2867         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2868                         dwc->ep0_trb, dwc->ep0_trb_addr);
2869
2870 err1:
2871         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2872                         dwc->ctrl_req, dwc->ctrl_req_addr);
2873
2874 err0:
2875         return ret;
2876 }
2877
2878 /* -------------------------------------------------------------------------- */
2879
2880 void dwc3_gadget_exit(struct dwc3 *dwc)
2881 {
2882         usb_del_gadget_udc(&dwc->gadget);
2883
2884         dwc3_gadget_free_endpoints(dwc);
2885
2886         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2887                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2888
2889         kfree(dwc->setup_buf);
2890         kfree(dwc->zlp_buf);
2891
2892         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2893                         dwc->ep0_trb, dwc->ep0_trb_addr);
2894
2895         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2896                         dwc->ctrl_req, dwc->ctrl_req_addr);
2897 }
2898
2899 int dwc3_gadget_suspend(struct dwc3 *dwc)
2900 {
2901         if (dwc->pullups_connected) {
2902                 dwc3_gadget_disable_irq(dwc);
2903                 dwc3_gadget_run_stop(dwc, true, true);
2904         }
2905
2906         __dwc3_gadget_ep_disable(dwc->eps[0]);
2907         __dwc3_gadget_ep_disable(dwc->eps[1]);
2908
2909         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2910
2911         return 0;
2912 }
2913
2914 int dwc3_gadget_resume(struct dwc3 *dwc)
2915 {
2916         struct dwc3_ep          *dep;
2917         int                     ret;
2918
2919         /* Start with SuperSpeed Default */
2920         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2921
2922         dep = dwc->eps[0];
2923         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2924                         false);
2925         if (ret)
2926                 goto err0;
2927
2928         dep = dwc->eps[1];
2929         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2930                         false);
2931         if (ret)
2932                 goto err1;
2933
2934         /* begin to receive SETUP packets */
2935         dwc->ep0state = EP0_SETUP_PHASE;
2936         dwc3_ep0_out_start(dwc);
2937
2938         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2939
2940         if (dwc->pullups_connected) {
2941                 dwc3_gadget_enable_irq(dwc);
2942                 dwc3_gadget_run_stop(dwc, true, false);
2943         }
2944
2945         return 0;
2946
2947 err1:
2948         __dwc3_gadget_ep_disable(dwc->eps[0]);
2949
2950 err0:
2951         return ret;
2952 }