drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 /**
 149  * dwc3_ep_inc_trb() - Increment a TRB index.
 150  * @index - Pointer to the TRB index to increment.
 151  *
 152  * The index should never point to the link TRB. After incrementing,
 153  * if it is point to the link TRB, wrap around to the beginning. The
 154  * link TRB is always at the last TRB entry.
 155  */
 156 static void dwc3_ep_inc_trb(u8 *index)
 157 {
 158         (*index)++;
 159         if (*index == (DWC3_TRB_NUM - 1))
 160                 *index = 0;
 161 }
 162
 163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 164 {
 165         dwc3_ep_inc_trb(&dep->trb_enqueue);
 166 }
 167
 168 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 169 {
 170         dwc3_ep_inc_trb(&dep->trb_dequeue);
 171 }
 172
 173 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 174                 int status)
 175 {
 176         struct dwc3                     *dwc = dep->dwc;
 177         int                             i;
 178
 179         if (req->started) {
 180                 i = 0;
 181                 do {
 182                         dwc3_ep_inc_deq(dep);
 183                 } while(++i < req->request.num_mapped_sgs);
 184                 req->started = false;
 185         }
 186         list_del(&req->list);
 187         req->trb = NULL;
 188
 189         if (req->request.status == -EINPROGRESS)
 190                 req->request.status = status;
 191
 192         if (dwc->ep0_bounced && dep->number == 0)
 193                 dwc->ep0_bounced = false;
 194         else
 195                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 196                                 req->direction);
 197
 198         trace_dwc3_gadget_giveback(req);
 199
 200         spin_unlock(&dwc->lock);
 201         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 202         spin_lock(&dwc->lock);
 203
 204         if (dep->number > 1)
 205                 pm_runtime_put(dwc->dev);
 206 }
 207
 208 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 209 {
 210         u32             timeout = 500;
 211         int             status = 0;
 212         int             ret = 0;
 213         u32             reg;
 214
 215         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 216         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 217
 218         do {
 219                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 220                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 221                         status = DWC3_DGCMD_STATUS(reg);
 222                         if (status)
 223                                 ret = -EINVAL;
 224                         break;
 225                 }
 226         } while (timeout--);
 227
 228         if (!timeout) {
 229                 ret = -ETIMEDOUT;
 230                 status = -ETIMEDOUT;
 231         }
 232
 233         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 234
 235         return ret;
 236 }
 237
 238 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 239
 240 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
 241                 struct dwc3_gadget_ep_cmd_params *params)
 242 {
 243         struct dwc3             *dwc = dep->dwc;
 244         u32                     timeout = 500;
 245         u32                     reg;
 246
 247         int                     cmd_status = 0;
 248         int                     susphy = false;
 249         int                     ret = -EINVAL;
 250
 251         /*
 252          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 253          * we're issuing an endpoint command, we must check if
 254          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 255          *
 256          * We will also set SUSPHY bit to what it was before returning as stated
 257          * by the same section on Synopsys databook.
 258          */
 259         if (dwc->gadget.speed <= USB_SPEED_HIGH) {
 260                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 261                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 262                         susphy = true;
 263                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 264                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 265                 }
 266         }
 267
 268         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 269                 int             needs_wakeup;
 270
 271                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 272                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 273                                 dwc->link_state == DWC3_LINK_STATE_U3);
 274
 275                 if (unlikely(needs_wakeup)) {
 276                         ret = __dwc3_gadget_wakeup(dwc);
 277                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 278                                         ret);
 279                 }
 280         }
 281
 282         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 283         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 284         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 285
 286         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
 287         do {
 288                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 289                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 290                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 291
 292                         switch (cmd_status) {
 293                         case 0:
 294                                 ret = 0;
 295                                 break;
 296                         case DEPEVT_TRANSFER_NO_RESOURCE:
 297                                 ret = -EINVAL;
 298                                 break;
 299                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 300                                 /*
 301                                  * SW issues START TRANSFER command to
 302                                  * isochronous ep with future frame interval. If
 303                                  * future interval time has already passed when
 304                                  * core receives the command, it will respond
 305                                  * with an error status of 'Bus Expiry'.
 306                                  *
 307                                  * Instead of always returning -EINVAL, let's
 308                                  * give a hint to the gadget driver that this is
 309                                  * the case by returning -EAGAIN.
 310                                  */
 311                                 ret = -EAGAIN;
 312                                 break;
 313                         default:
 314                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 315                         }
 316
 317                         break;
 318                 }
 319         } while (--timeout);
 320
 321         if (timeout == 0) {
 322                 ret = -ETIMEDOUT;
 323                 cmd_status = -ETIMEDOUT;
 324         }
 325
 326         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 327
 328         if (unlikely(susphy)) {
 329                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 330                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 331                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 332         }
 333
 334         return ret;
 335 }
 336
 337 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 338 {
 339         struct dwc3 *dwc = dep->dwc;
 340         struct dwc3_gadget_ep_cmd_params params;
 341         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 342
 343         /*
 344          * As of core revision 2.60a the recommended programming model
 345          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 346          * command for IN endpoints. This is to prevent an issue where
 347          * some (non-compliant) hosts may not send ACK TPs for pending
 348          * IN transfers due to a mishandled error condition. Synopsys
 349          * STAR 9000614252.
 350          */
 351         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
 352                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 353
 354         memset(&params, 0, sizeof(params));
 355
 356         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 357 }
 358
 359 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 360                 struct dwc3_trb *trb)
 361 {
 362         u32             offset = (char *) trb - (char *) dep->trb_pool;
 363
 364         return dep->trb_pool_dma + offset;
 365 }
 366
 367 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 368 {
 369         struct dwc3             *dwc = dep->dwc;
 370
 371         if (dep->trb_pool)
 372                 return 0;
 373
 374         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 375                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 376                         &dep->trb_pool_dma, GFP_KERNEL);
 377         if (!dep->trb_pool) {
 378                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 379                                 dep->name);
 380                 return -ENOMEM;
 381         }
 382
 383         return 0;
 384 }
 385
 386 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 387 {
 388         struct dwc3             *dwc = dep->dwc;
 389
 390         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 391                         dep->trb_pool, dep->trb_pool_dma);
 392
 393         dep->trb_pool = NULL;
 394         dep->trb_pool_dma = 0;
 395 }
 396
 397 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 398
 399 /**
 400  * dwc3_gadget_start_config - Configure EP resources
 401  * @dwc: pointer to our controller context structure
 402  * @dep: endpoint that is being enabled
 403  *
 404  * The assignment of transfer resources cannot perfectly follow the
 405  * data book due to the fact that the controller driver does not have
 406  * all knowledge of the configuration in advance. It is given this
 407  * information piecemeal by the composite gadget framework after every
 408  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 409  * programming model in this scenario can cause errors. For two
 410  * reasons:
 411  *
 412  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 413  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 414  * multiple interfaces.
 415  *
 416  * 2) The databook does not mention doing more DEPXFERCFG for new
 417  * endpoint on alt setting (8.1.6).
 418  *
 419  * The following simplified method is used instead:
 420  *
 421  * All hardware endpoints can be assigned a transfer resource and this
 422  * setting will stay persistent until either a core reset or
 423  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 424  * do DEPXFERCFG for every hardware endpoint as well. We are
 425  * guaranteed that there are as many transfer resources as endpoints.
 426  *
 427  * This function is called for each endpoint when it is being enabled
 428  * but is triggered only when called for EP0-out, which always happens
 429  * first, and which should only happen in one of the above conditions.
 430  */
 431 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 432 {
 433         struct dwc3_gadget_ep_cmd_params params;
 434         u32                     cmd;
 435         int                     i;
 436         int                     ret;
 437
 438         if (dep->number)
 439                 return 0;
 440
 441         memset(&params, 0x00, sizeof(params));
 442         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 443
 444         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 445         if (ret)
 446                 return ret;
 447
 448         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 449                 struct dwc3_ep *dep = dwc->eps[i];
 450
 451                 if (!dep)
 452                         continue;
 453
 454                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 455                 if (ret)
 456                         return ret;
 457         }
 458
 459         return 0;
 460 }
 461
 462 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 463                 const struct usb_endpoint_descriptor *desc,
 464                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 465                 bool ignore, bool restore)
 466 {
 467         struct dwc3_gadget_ep_cmd_params params;
 468
 469         memset(&params, 0x00, sizeof(params));
 470
 471         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 472                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 473
 474         /* Burst size is only needed in SuperSpeed mode */
 475         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 476                 u32 burst = dep->endpoint.maxburst;
 477                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 478         }
 479
 480         if (ignore)
 481                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 482
 483         if (restore) {
 484                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 485                 params.param2 |= dep->saved_state;
 486         }
 487
 488         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 489
 490         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 491                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 492
 493         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 494                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 495                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 496                 dep->stream_capable = true;
 497         }
 498
 499         if (!usb_endpoint_xfer_control(desc))
 500                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 501
 502         /*
 503          * We are doing 1:1 mapping for endpoints, meaning
 504          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 505          * so on. We consider the direction bit as part of the physical
 506          * endpoint number. So USB endpoint 0x81 is 0x03.
 507          */
 508         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 509
 510         /*
 511          * We must use the lower 16 TX FIFOs even though
 512          * HW might have more
 513          */
 514         if (dep->direction)
 515                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 516
 517         if (desc->bInterval) {
 518                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 519                 dep->interval = 1 << (desc->bInterval - 1);
 520         }
 521
 522         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 523 }
 524
 525 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 526 {
 527         struct dwc3_gadget_ep_cmd_params params;
 528
 529         memset(&params, 0x00, sizeof(params));
 530
 531         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 532
 533         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 534                         &params);
 535 }
 536
 537 /**
 538  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 539  * @dep: endpoint to be initialized
 540  * @desc: USB Endpoint Descriptor
 541  *
 542  * Caller should take care of locking
 543  */
 544 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 545                 const struct usb_endpoint_descriptor *desc,
 546                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 547                 bool ignore, bool restore)
 548 {
 549         struct dwc3             *dwc = dep->dwc;
 550         u32                     reg;
 551         int                     ret;
 552
 553         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 554
 555         if (!(dep->flags & DWC3_EP_ENABLED)) {
 556                 ret = dwc3_gadget_start_config(dwc, dep);
 557                 if (ret)
 558                         return ret;
 559         }
 560
 561         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 562                         restore);
 563         if (ret)
 564                 return ret;
 565
 566         if (!(dep->flags & DWC3_EP_ENABLED)) {
 567                 struct dwc3_trb *trb_st_hw;
 568                 struct dwc3_trb *trb_link;
 569
 570                 dep->endpoint.desc = desc;
 571                 dep->comp_desc = comp_desc;
 572                 dep->type = usb_endpoint_type(desc);
 573                 dep->flags |= DWC3_EP_ENABLED;
 574
 575                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 576                 reg |= DWC3_DALEPENA_EP(dep->number);
 577                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 578
 579                 if (usb_endpoint_xfer_control(desc))
 580                         return 0;
 581
 582                 /* Initialize the TRB ring */
 583                 dep->trb_dequeue = 0;
 584                 dep->trb_enqueue = 0;
 585                 memset(dep->trb_pool, 0,
 586                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 587
 588                 /* Link TRB. The HWO bit is never reset */
 589                 trb_st_hw = &dep->trb_pool[0];
 590
 591                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 592                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 593                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 594                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 595                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 602 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 603 {
 604         struct dwc3_request             *req;
 605         struct dwc3_trb                 *current_trb;
 606         unsigned                        transfer_in_flight;
 607
 608         if (dep->number > 1)
 609                 current_trb = &dep->trb_pool[dep->trb_enqueue];
 610         else
 611                 current_trb = &dwc->ep0_trb[dep->trb_enqueue];
 612         transfer_in_flight = current_trb->ctrl & DWC3_TRB_CTRL_HWO;
 613
 614         if (transfer_in_flight && !list_empty(&dep->started_list)) {
 615                 dwc3_stop_active_transfer(dwc, dep->number, true);
 616
 617                 /* - giveback all requests to gadget driver */
 618                 while (!list_empty(&dep->started_list)) {
 619                         req = next_request(&dep->started_list);
 620
 621                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 622                 }
 623         }
 624
 625         while (!list_empty(&dep->pending_list)) {
 626                 req = next_request(&dep->pending_list);
 627
 628                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 629         }
 630 }
 631
 632 /**
 633  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 634  * @dep: the endpoint to disable
 635  *
 636  * This function also removes requests which are currently processed ny the
 637  * hardware and those which are not yet scheduled.
 638  * Caller should take care of locking.
 639  */
 640 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 641 {
 642         struct dwc3             *dwc = dep->dwc;
 643         u32                     reg;
 644
 645         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 646
 647         dwc3_remove_requests(dwc, dep);
 648
 649         /* make sure HW endpoint isn't stalled */
 650         if (dep->flags & DWC3_EP_STALL)
 651                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 652
 653         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 654         reg &= ~DWC3_DALEPENA_EP(dep->number);
 655         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 656
 657         dep->stream_capable = false;
 658         dep->endpoint.desc = NULL;
 659         dep->comp_desc = NULL;
 660         dep->type = 0;
 661         dep->flags = 0;
 662
 663         return 0;
 664 }
 665
 666 /* -------------------------------------------------------------------------- */
 667
 668 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 669                 const struct usb_endpoint_descriptor *desc)
 670 {
 671         return -EINVAL;
 672 }
 673
 674 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 675 {
 676         return -EINVAL;
 677 }
 678
 679 /* -------------------------------------------------------------------------- */
 680
 681 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 682                 const struct usb_endpoint_descriptor *desc)
 683 {
 684         struct dwc3_ep                  *dep;
 685         struct dwc3                     *dwc;
 686         unsigned long                   flags;
 687         int                             ret;
 688
 689         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 690                 pr_debug("dwc3: invalid parameters\n");
 691                 return -EINVAL;
 692         }
 693
 694         if (!desc->wMaxPacketSize) {
 695                 pr_debug("dwc3: missing wMaxPacketSize\n");
 696                 return -EINVAL;
 697         }
 698
 699         dep = to_dwc3_ep(ep);
 700         dwc = dep->dwc;
 701
 702         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 703                                         "%s is already enabled\n",
 704                                         dep->name))
 705                 return 0;
 706
 707         spin_lock_irqsave(&dwc->lock, flags);
 708         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 709         spin_unlock_irqrestore(&dwc->lock, flags);
 710
 711         return ret;
 712 }
 713
 714 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 715 {
 716         struct dwc3_ep                  *dep;
 717         struct dwc3                     *dwc;
 718         unsigned long                   flags;
 719         int                             ret;
 720
 721         if (!ep) {
 722                 pr_debug("dwc3: invalid parameters\n");
 723                 return -EINVAL;
 724         }
 725
 726         dep = to_dwc3_ep(ep);
 727         dwc = dep->dwc;
 728
 729         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 730                                         "%s is already disabled\n",
 731                                         dep->name))
 732                 return 0;
 733
 734         spin_lock_irqsave(&dwc->lock, flags);
 735         ret = __dwc3_gadget_ep_disable(dep);
 736         spin_unlock_irqrestore(&dwc->lock, flags);
 737
 738         return ret;
 739 }
 740
 741 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 742         gfp_t gfp_flags)
 743 {
 744         struct dwc3_request             *req;
 745         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 746
 747         req = kzalloc(sizeof(*req), gfp_flags);
 748         if (!req)
 749                 return NULL;
 750
 751         req->epnum      = dep->number;
 752         req->dep        = dep;
 753
 754         dep->allocated_requests++;
 755
 756         trace_dwc3_alloc_request(req);
 757
 758         return &req->request;
 759 }
 760
 761 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 762                 struct usb_request *request)
 763 {
 764         struct dwc3_request             *req = to_dwc3_request(request);
 765         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 766
 767         dep->allocated_requests--;
 768         trace_dwc3_free_request(req);
 769         kfree(req);
 770 }
 771
 772 /**
 773  * dwc3_prepare_one_trb - setup one TRB from one request
 774  * @dep: endpoint for which this request is prepared
 775  * @req: dwc3_request pointer
 776  */
 777 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 778                 struct dwc3_request *req, dma_addr_t dma,
 779                 unsigned length, unsigned last, unsigned chain, unsigned node)
 780 {
 781         struct dwc3_trb         *trb;
 782
 783         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 784                         dep->name, req, (unsigned long long) dma,
 785                         length, last ? " last" : "",
 786                         chain ? " chain" : "");
 787
 788
 789         trb = &dep->trb_pool[dep->trb_enqueue];
 790
 791         if (!req->trb) {
 792                 dwc3_gadget_move_started_request(req);
 793                 req->trb = trb;
 794                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 795                 req->first_trb_index = dep->trb_enqueue;
 796         }
 797
 798         dwc3_ep_inc_enq(dep);
 799
 800         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 801         trb->bpl = lower_32_bits(dma);
 802         trb->bph = upper_32_bits(dma);
 803
 804         switch (usb_endpoint_type(dep->endpoint.desc)) {
 805         case USB_ENDPOINT_XFER_CONTROL:
 806                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 807                 break;
 808
 809         case USB_ENDPOINT_XFER_ISOC:
 810                 if (!node)
 811                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 812                 else
 813                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 814
 815                 /* always enable Interrupt on Missed ISOC */
 816                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 817                 break;
 818
 819         case USB_ENDPOINT_XFER_BULK:
 820         case USB_ENDPOINT_XFER_INT:
 821                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 822                 break;
 823         default:
 824                 /*
 825                  * This is only possible with faulty memory because we
 826                  * checked it already :)
 827                  */
 828                 BUG();
 829         }
 830
 831         /* always enable Continue on Short Packet */
 832         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 833
 834         if (!req->request.no_interrupt && !chain)
 835                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 836
 837         if (last)
 838                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 839
 840         if (chain)
 841                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 842
 843         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 844                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 845
 846         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 847
 848         dep->queued_requests++;
 849
 850         trace_dwc3_prepare_trb(dep, trb);
 851 }
 852
 853 /**
 854  * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
 855  * @dep: The endpoint with the TRB ring
 856  * @index: The index of the current TRB in the ring
 857  *
 858  * Returns the TRB prior to the one pointed to by the index. If the
 859  * index is 0, we will wrap backwards, skip the link TRB, and return
 860  * the one just before that.
 861  */
 862 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
 863 {
 864         if (!index)
 865                 index = DWC3_TRB_NUM - 2;
 866         else
 867                 index = dep->trb_enqueue - 1;
 868
 869         return &dep->trb_pool[index];
 870 }
 871
 872 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 873 {
 874         struct dwc3_trb         *tmp;
 875         u8                      trbs_left;
 876
 877         /*
 878          * If enqueue & dequeue are equal than it is either full or empty.
 879          *
 880          * One way to know for sure is if the TRB right before us has HWO bit
 881          * set or not. If it has, then we're definitely full and can't fit any
 882          * more transfers in our ring.
 883          */
 884         if (dep->trb_enqueue == dep->trb_dequeue) {
 885                 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
 886                 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
 887                         return 0;
 888
 889                 return DWC3_TRB_NUM - 1;
 890         }
 891
 892         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
 893         trbs_left &= (DWC3_TRB_NUM - 1);
 894
 895         if (dep->trb_dequeue < dep->trb_enqueue)
 896                 trbs_left--;
 897
 898         return trbs_left;
 899 }
 900
 901 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
 902                 struct dwc3_request *req, unsigned int trbs_left,
 903                 unsigned int more_coming)
 904 {
 905         struct usb_request *request = &req->request;
 906         struct scatterlist *sg = request->sg;
 907         struct scatterlist *s;
 908         unsigned int    last = false;
 909         unsigned int    length;
 910         dma_addr_t      dma;
 911         int             i;
 912
 913         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 914                 unsigned chain = true;
 915
 916                 length = sg_dma_len(s);
 917                 dma = sg_dma_address(s);
 918
 919                 if (sg_is_last(s)) {
 920                         if (usb_endpoint_xfer_int(dep->endpoint.desc) ||
 921                                 !more_coming)
 922                                 last = true;
 923
 924                         chain = false;
 925                 }
 926
 927                 if (!trbs_left--)
 928                         last = true;
 929
 930                 if (last)
 931                         chain = false;
 932
 933                 dwc3_prepare_one_trb(dep, req, dma, length,
 934                                 last, chain, i);
 935
 936                 if (last)
 937                         break;
 938         }
 939 }
 940
 941 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
 942                 struct dwc3_request *req, unsigned int trbs_left,
 943                 unsigned int more_coming)
 944 {
 945         unsigned int    last = false;
 946         unsigned int    length;
 947         dma_addr_t      dma;
 948
 949         dma = req->request.dma;
 950         length = req->request.length;
 951
 952         if (!trbs_left)
 953                 last = true;
 954
 955         /* Is this the last request? */
 956         if (usb_endpoint_xfer_int(dep->endpoint.desc) || !more_coming)
 957                 last = true;
 958
 959         dwc3_prepare_one_trb(dep, req, dma, length,
 960                         last, false, 0);
 961 }
 962
 963 /*
 964  * dwc3_prepare_trbs - setup TRBs from requests
 965  * @dep: endpoint for which requests are being prepared
 966  *
 967  * The function goes through the requests list and sets up TRBs for the
 968  * transfers. The function returns once there are no more TRBs available or
 969  * it runs out of requests.
 970  */
 971 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
 972 {
 973         struct dwc3_request     *req, *n;
 974         unsigned int            more_coming;
 975         u32                     trbs_left;
 976
 977         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 978
 979         trbs_left = dwc3_calc_trbs_left(dep);
 980         if (!trbs_left)
 981                 return;
 982
 983         more_coming = dep->allocated_requests - dep->queued_requests;
 984
 985         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 986                 if (req->request.num_mapped_sgs > 0)
 987                         dwc3_prepare_one_trb_sg(dep, req, trbs_left--,
 988                                         more_coming);
 989                 else
 990                         dwc3_prepare_one_trb_linear(dep, req, trbs_left--,
 991                                         more_coming);
 992
 993                 if (!trbs_left)
 994                         return;
 995         }
 996 }
 997
 998 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
 999 {
1000         struct dwc3_gadget_ep_cmd_params params;
1001         struct dwc3_request             *req;
1002         struct dwc3                     *dwc = dep->dwc;
1003         int                             starting;
1004         int                             ret;
1005         u32                             cmd;
1006
1007         starting = !(dep->flags & DWC3_EP_BUSY);
1008
1009         dwc3_prepare_trbs(dep);
1010         req = next_request(&dep->started_list);
1011         if (!req) {
1012                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1013                 return 0;
1014         }
1015
1016         memset(&params, 0, sizeof(params));
1017
1018         if (starting) {
1019                 params.param0 = upper_32_bits(req->trb_dma);
1020                 params.param1 = lower_32_bits(req->trb_dma);
1021                 cmd = DWC3_DEPCMD_STARTTRANSFER |
1022                         DWC3_DEPCMD_PARAM(cmd_param);
1023         } else {
1024                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1025                         DWC3_DEPCMD_PARAM(dep->resource_index);
1026         }
1027
1028         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1029         if (ret < 0) {
1030                 /*
1031                  * FIXME we need to iterate over the list of requests
1032                  * here and stop, unmap, free and del each of the linked
1033                  * requests instead of what we do now.
1034                  */
1035                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1036                                 req->direction);
1037                 list_del(&req->list);
1038                 return ret;
1039         }
1040
1041         dep->flags |= DWC3_EP_BUSY;
1042
1043         if (starting) {
1044                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1045                 WARN_ON_ONCE(!dep->resource_index);
1046         }
1047
1048         return 0;
1049 }
1050
1051 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1052                 struct dwc3_ep *dep, u32 cur_uf)
1053 {
1054         u32 uf;
1055
1056         if (list_empty(&dep->pending_list)) {
1057                 dwc3_trace(trace_dwc3_gadget,
1058                                 "ISOC ep %s run out for requests",
1059                                 dep->name);
1060                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1061                 return;
1062         }
1063
1064         /* 4 micro frames in the future */
1065         uf = cur_uf + dep->interval * 4;
1066
1067         __dwc3_gadget_kick_transfer(dep, uf);
1068 }
1069
1070 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1071                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1072 {
1073         u32 cur_uf, mask;
1074
1075         mask = ~(dep->interval - 1);
1076         cur_uf = event->parameters & mask;
1077
1078         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1079 }
1080
1081 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1082 {
1083         struct dwc3             *dwc = dep->dwc;
1084         int                     ret;
1085
1086         if (!dep->endpoint.desc) {
1087                 dwc3_trace(trace_dwc3_gadget,
1088                                 "trying to queue request %p to disabled %s",
1089                                 &req->request, dep->endpoint.name);
1090                 return -ESHUTDOWN;
1091         }
1092
1093         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1094                                 &req->request, req->dep->name)) {
1095                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'",
1096                                 &req->request, req->dep->name);
1097                 return -EINVAL;
1098         }
1099
1100         pm_runtime_get(dwc->dev);
1101
1102         req->request.actual     = 0;
1103         req->request.status     = -EINPROGRESS;
1104         req->direction          = dep->direction;
1105         req->epnum              = dep->number;
1106
1107         trace_dwc3_ep_queue(req);
1108
1109         /*
1110          * We only add to our list of requests now and
1111          * start consuming the list once we get XferNotReady
1112          * IRQ.
1113          *
1114          * That way, we avoid doing anything that we don't need
1115          * to do now and defer it until the point we receive a
1116          * particular token from the Host side.
1117          *
1118          * This will also avoid Host cancelling URBs due to too
1119          * many NAKs.
1120          */
1121         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1122                         dep->direction);
1123         if (ret)
1124                 return ret;
1125
1126         list_add_tail(&req->list, &dep->pending_list);
1127
1128         /*
1129          * If there are no pending requests and the endpoint isn't already
1130          * busy, we will just start the request straight away.
1131          *
1132          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1133          * little bit faster.
1134          */
1135         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1136                         !usb_endpoint_xfer_int(dep->endpoint.desc)) {
1137                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1138                 goto out;
1139         }
1140
1141         /*
1142          * There are a few special cases:
1143          *
1144          * 1. XferNotReady with empty list of requests. We need to kick the
1145          *    transfer here in that situation, otherwise we will be NAKing
1146          *    forever. If we get XferNotReady before gadget driver has a
1147          *    chance to queue a request, we will ACK the IRQ but won't be
1148          *    able to receive the data until the next request is queued.
1149          *    The following code is handling exactly that.
1150          *
1151          */
1152         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1153                 /*
1154                  * If xfernotready is already elapsed and it is a case
1155                  * of isoc transfer, then issue END TRANSFER, so that
1156                  * you can receive xfernotready again and can have
1157                  * notion of current microframe.
1158                  */
1159                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1160                         if (list_empty(&dep->started_list)) {
1161                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1162                                 dep->flags = DWC3_EP_ENABLED;
1163                         }
1164                         return 0;
1165                 }
1166
1167                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1168                 if (!ret)
1169                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1170
1171                 goto out;
1172         }
1173
1174         /*
1175          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1176          *    kick the transfer here after queuing a request, otherwise the
1177          *    core may not see the modified TRB(s).
1178          */
1179         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1180                         (dep->flags & DWC3_EP_BUSY) &&
1181                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1182                 WARN_ON_ONCE(!dep->resource_index);
1183                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1184                 goto out;
1185         }
1186
1187         /*
1188          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1189          * right away, otherwise host will not know we have streams to be
1190          * handled.
1191          */
1192         if (dep->stream_capable)
1193                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1194
1195 out:
1196         if (ret && ret != -EBUSY)
1197                 dwc3_trace(trace_dwc3_gadget,
1198                                 "%s: failed to kick transfers",
1199                                 dep->name);
1200         if (ret == -EBUSY)
1201                 ret = 0;
1202
1203         return ret;
1204 }
1205
1206 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1207                 struct usb_request *request)
1208 {
1209         dwc3_gadget_ep_free_request(ep, request);
1210 }
1211
1212 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1213 {
1214         struct dwc3_request             *req;
1215         struct usb_request              *request;
1216         struct usb_ep                   *ep = &dep->endpoint;
1217
1218         dwc3_trace(trace_dwc3_gadget, "queueing ZLP");
1219         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1220         if (!request)
1221                 return -ENOMEM;
1222
1223         request->length = 0;
1224         request->buf = dwc->zlp_buf;
1225         request->complete = __dwc3_gadget_ep_zlp_complete;
1226
1227         req = to_dwc3_request(request);
1228
1229         return __dwc3_gadget_ep_queue(dep, req);
1230 }
1231
1232 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1233         gfp_t gfp_flags)
1234 {
1235         struct dwc3_request             *req = to_dwc3_request(request);
1236         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1237         struct dwc3                     *dwc = dep->dwc;
1238
1239         unsigned long                   flags;
1240
1241         int                             ret;
1242
1243         spin_lock_irqsave(&dwc->lock, flags);
1244         ret = __dwc3_gadget_ep_queue(dep, req);
1245
1246         /*
1247          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1248          * setting request->zero, instead of doing magic, we will just queue an
1249          * extra usb_request ourselves so that it gets handled the same way as
1250          * any other request.
1251          */
1252         if (ret == 0 && request->zero && request->length &&
1253             (request->length % ep->maxpacket == 0))
1254                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1255
1256         spin_unlock_irqrestore(&dwc->lock, flags);
1257
1258         return ret;
1259 }
1260
1261 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1262                 struct usb_request *request)
1263 {
1264         struct dwc3_request             *req = to_dwc3_request(request);
1265         struct dwc3_request             *r = NULL;
1266
1267         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1268         struct dwc3                     *dwc = dep->dwc;
1269
1270         unsigned long                   flags;
1271         int                             ret = 0;
1272
1273         trace_dwc3_ep_dequeue(req);
1274
1275         spin_lock_irqsave(&dwc->lock, flags);
1276
1277         list_for_each_entry(r, &dep->pending_list, list) {
1278                 if (r == req)
1279                         break;
1280         }
1281
1282         if (r != req) {
1283                 list_for_each_entry(r, &dep->started_list, list) {
1284                         if (r == req)
1285                                 break;
1286                 }
1287                 if (r == req) {
1288                         /* wait until it is processed */
1289                         dwc3_stop_active_transfer(dwc, dep->number, true);
1290                         goto out1;
1291                 }
1292                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1293                                 request, ep->name);
1294                 ret = -EINVAL;
1295                 goto out0;
1296         }
1297
1298 out1:
1299         /* giveback the request */
1300         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1301
1302 out0:
1303         spin_unlock_irqrestore(&dwc->lock, flags);
1304
1305         return ret;
1306 }
1307
1308 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1309 {
1310         struct dwc3_gadget_ep_cmd_params        params;
1311         struct dwc3                             *dwc = dep->dwc;
1312         int                                     ret;
1313
1314         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1315                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1316                 return -EINVAL;
1317         }
1318
1319         memset(&params, 0x00, sizeof(params));
1320
1321         if (value) {
1322                 struct dwc3_trb *trb;
1323
1324                 unsigned transfer_in_flight;
1325                 unsigned started;
1326
1327                 if (dep->number > 1)
1328                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1329                 else
1330                         trb = &dwc->ep0_trb[dep->trb_enqueue];
1331
1332                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1333                 started = !list_empty(&dep->started_list);
1334
1335                 if (!protocol && ((dep->direction && transfer_in_flight) ||
1336                                 (!dep->direction && started))) {
1337                         dwc3_trace(trace_dwc3_gadget,
1338                                         "%s: pending request, cannot halt",
1339                                         dep->name);
1340                         return -EAGAIN;
1341                 }
1342
1343                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1344                                 &params);
1345                 if (ret)
1346                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1347                                         dep->name);
1348                 else
1349                         dep->flags |= DWC3_EP_STALL;
1350         } else {
1351
1352                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1353                 if (ret)
1354                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1355                                         dep->name);
1356                 else
1357                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1358         }
1359
1360         return ret;
1361 }
1362
1363 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1364 {
1365         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1366         struct dwc3                     *dwc = dep->dwc;
1367
1368         unsigned long                   flags;
1369
1370         int                             ret;
1371
1372         spin_lock_irqsave(&dwc->lock, flags);
1373         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1374         spin_unlock_irqrestore(&dwc->lock, flags);
1375
1376         return ret;
1377 }
1378
1379 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1380 {
1381         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1382         struct dwc3                     *dwc = dep->dwc;
1383         unsigned long                   flags;
1384         int                             ret;
1385
1386         spin_lock_irqsave(&dwc->lock, flags);
1387         dep->flags |= DWC3_EP_WEDGE;
1388
1389         if (dep->number == 0 || dep->number == 1)
1390                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1391         else
1392                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1393         spin_unlock_irqrestore(&dwc->lock, flags);
1394
1395         return ret;
1396 }
1397
1398 /* -------------------------------------------------------------------------- */
1399
1400 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1401         .bLength        = USB_DT_ENDPOINT_SIZE,
1402         .bDescriptorType = USB_DT_ENDPOINT,
1403         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1404 };
1405
1406 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1407         .enable         = dwc3_gadget_ep0_enable,
1408         .disable        = dwc3_gadget_ep0_disable,
1409         .alloc_request  = dwc3_gadget_ep_alloc_request,
1410         .free_request   = dwc3_gadget_ep_free_request,
1411         .queue          = dwc3_gadget_ep0_queue,
1412         .dequeue        = dwc3_gadget_ep_dequeue,
1413         .set_halt       = dwc3_gadget_ep0_set_halt,
1414         .set_wedge      = dwc3_gadget_ep_set_wedge,
1415 };
1416
1417 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1418         .enable         = dwc3_gadget_ep_enable,
1419         .disable        = dwc3_gadget_ep_disable,
1420         .alloc_request  = dwc3_gadget_ep_alloc_request,
1421         .free_request   = dwc3_gadget_ep_free_request,
1422         .queue          = dwc3_gadget_ep_queue,
1423         .dequeue        = dwc3_gadget_ep_dequeue,
1424         .set_halt       = dwc3_gadget_ep_set_halt,
1425         .set_wedge      = dwc3_gadget_ep_set_wedge,
1426 };
1427
1428 /* -------------------------------------------------------------------------- */
1429
1430 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1431 {
1432         struct dwc3             *dwc = gadget_to_dwc(g);
1433         u32                     reg;
1434
1435         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1436         return DWC3_DSTS_SOFFN(reg);
1437 }
1438
1439 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1440 {
1441         unsigned long           timeout;
1442
1443         int                     ret;
1444         u32                     reg;
1445
1446         u8                      link_state;
1447         u8                      speed;
1448
1449         /*
1450          * According to the Databook Remote wakeup request should
1451          * be issued only when the device is in early suspend state.
1452          *
1453          * We can check that via USB Link State bits in DSTS register.
1454          */
1455         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1456
1457         speed = reg & DWC3_DSTS_CONNECTSPD;
1458         if ((speed == DWC3_DSTS_SUPERSPEED) ||
1459             (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1460                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed");
1461                 return 0;
1462         }
1463
1464         link_state = DWC3_DSTS_USBLNKST(reg);
1465
1466         switch (link_state) {
1467         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1468         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1469                 break;
1470         default:
1471                 dwc3_trace(trace_dwc3_gadget,
1472                                 "can't wakeup from '%s'",
1473                                 dwc3_gadget_link_string(link_state));
1474                 return -EINVAL;
1475         }
1476
1477         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1478         if (ret < 0) {
1479                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1480                 return ret;
1481         }
1482
1483         /* Recent versions do this automatically */
1484         if (dwc->revision < DWC3_REVISION_194A) {
1485                 /* write zeroes to Link Change Request */
1486                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1487                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1488                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1489         }
1490
1491         /* poll until Link State changes to ON */
1492         timeout = jiffies + msecs_to_jiffies(100);
1493
1494         while (!time_after(jiffies, timeout)) {
1495                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1496
1497                 /* in HS, means ON */
1498                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1499                         break;
1500         }
1501
1502         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1503                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1504                 return -EINVAL;
1505         }
1506
1507         return 0;
1508 }
1509
1510 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1511 {
1512         struct dwc3             *dwc = gadget_to_dwc(g);
1513         unsigned long           flags;
1514         int                     ret;
1515
1516         spin_lock_irqsave(&dwc->lock, flags);
1517         ret = __dwc3_gadget_wakeup(dwc);
1518         spin_unlock_irqrestore(&dwc->lock, flags);
1519
1520         return ret;
1521 }
1522
1523 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1524                 int is_selfpowered)
1525 {
1526         struct dwc3             *dwc = gadget_to_dwc(g);
1527         unsigned long           flags;
1528
1529         spin_lock_irqsave(&dwc->lock, flags);
1530         g->is_selfpowered = !!is_selfpowered;
1531         spin_unlock_irqrestore(&dwc->lock, flags);
1532
1533         return 0;
1534 }
1535
1536 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1537 {
1538         u32                     reg;
1539         u32                     timeout = 500;
1540
1541         if (pm_runtime_suspended(dwc->dev))
1542                 return 0;
1543
1544         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1545         if (is_on) {
1546                 if (dwc->revision <= DWC3_REVISION_187A) {
1547                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1548                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1549                 }
1550
1551                 if (dwc->revision >= DWC3_REVISION_194A)
1552                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1553                 reg |= DWC3_DCTL_RUN_STOP;
1554
1555                 if (dwc->has_hibernation)
1556                         reg |= DWC3_DCTL_KEEP_CONNECT;
1557
1558                 dwc->pullups_connected = true;
1559         } else {
1560                 reg &= ~DWC3_DCTL_RUN_STOP;
1561
1562                 if (dwc->has_hibernation && !suspend)
1563                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1564
1565                 dwc->pullups_connected = false;
1566         }
1567
1568         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1569
1570         do {
1571                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1572                 if (is_on) {
1573                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1574                                 break;
1575                 } else {
1576                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1577                                 break;
1578                 }
1579                 timeout--;
1580                 if (!timeout)
1581                         return -ETIMEDOUT;
1582                 udelay(1);
1583         } while (1);
1584
1585         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1586                         dwc->gadget_driver
1587                         ? dwc->gadget_driver->function : "no-function",
1588                         is_on ? "connect" : "disconnect");
1589
1590         return 0;
1591 }
1592
1593 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1594 {
1595         struct dwc3             *dwc = gadget_to_dwc(g);
1596         unsigned long           flags;
1597         int                     ret;
1598
1599         is_on = !!is_on;
1600
1601         spin_lock_irqsave(&dwc->lock, flags);
1602         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1603         spin_unlock_irqrestore(&dwc->lock, flags);
1604
1605         return ret;
1606 }
1607
1608 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1609 {
1610         u32                     reg;
1611
1612         /* Enable all but Start and End of Frame IRQs */
1613         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1614                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1615                         DWC3_DEVTEN_CMDCMPLTEN |
1616                         DWC3_DEVTEN_ERRTICERREN |
1617                         DWC3_DEVTEN_WKUPEVTEN |
1618                         DWC3_DEVTEN_ULSTCNGEN |
1619                         DWC3_DEVTEN_CONNECTDONEEN |
1620                         DWC3_DEVTEN_USBRSTEN |
1621                         DWC3_DEVTEN_DISCONNEVTEN);
1622
1623         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1624 }
1625
1626 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1627 {
1628         /* mask all interrupts */
1629         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1630 }
1631
1632 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1633 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1634
1635 /**
1636  * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1637  * dwc: pointer to our context structure
1638  *
1639  * The following looks like complex but it's actually very simple. In order to
1640  * calculate the number of packets we can burst at once on OUT transfers, we're
1641  * gonna use RxFIFO size.
1642  *
1643  * To calculate RxFIFO size we need two numbers:
1644  * MDWIDTH = size, in bits, of the internal memory bus
1645  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1646  *
1647  * Given these two numbers, the formula is simple:
1648  *
1649  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1650  *
1651  * 24 bytes is for 3x SETUP packets
1652  * 16 bytes is a clock domain crossing tolerance
1653  *
1654  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1655  */
1656 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1657 {
1658         u32 ram2_depth;
1659         u32 mdwidth;
1660         u32 nump;
1661         u32 reg;
1662
1663         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1664         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1665
1666         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1667         nump = min_t(u32, nump, 16);
1668
1669         /* update NumP */
1670         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1671         reg &= ~DWC3_DCFG_NUMP_MASK;
1672         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1673         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1674 }
1675
1676 static int __dwc3_gadget_start(struct dwc3 *dwc)
1677 {
1678         struct dwc3_ep          *dep;
1679         int                     ret = 0;
1680         u32                     reg;
1681
1682         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1683         reg &= ~(DWC3_DCFG_SPEED_MASK);
1684
1685         /**
1686          * WORKAROUND: DWC3 revision < 2.20a have an issue
1687          * which would cause metastability state on Run/Stop
1688          * bit if we try to force the IP to USB2-only mode.
1689          *
1690          * Because of that, we cannot configure the IP to any
1691          * speed other than the SuperSpeed
1692          *
1693          * Refers to:
1694          *
1695          * STAR#9000525659: Clock Domain Crossing on DCTL in
1696          * USB 2.0 Mode
1697          */
1698         if (dwc->revision < DWC3_REVISION_220A) {
1699                 reg |= DWC3_DCFG_SUPERSPEED;
1700         } else {
1701                 switch (dwc->maximum_speed) {
1702                 case USB_SPEED_LOW:
1703                         reg |= DWC3_DCFG_LOWSPEED;
1704                         break;
1705                 case USB_SPEED_FULL:
1706                         reg |= DWC3_DCFG_FULLSPEED1;
1707                         break;
1708                 case USB_SPEED_HIGH:
1709                         reg |= DWC3_DCFG_HIGHSPEED;
1710                         break;
1711                 case USB_SPEED_SUPER_PLUS:
1712                         reg |= DWC3_DCFG_SUPERSPEED_PLUS;
1713                         break;
1714                 default:
1715                         dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1716                                 dwc->maximum_speed);
1717                         /* fall through */
1718                 case USB_SPEED_SUPER:
1719                         reg |= DWC3_DCFG_SUPERSPEED;
1720                         break;
1721                 }
1722         }
1723         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1724
1725         /*
1726          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1727          * field instead of letting dwc3 itself calculate that automatically.
1728          *
1729          * This way, we maximize the chances that we'll be able to get several
1730          * bursts of data without going through any sort of endpoint throttling.
1731          */
1732         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1733         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1734         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1735
1736         dwc3_gadget_setup_nump(dwc);
1737
1738         /* Start with SuperSpeed Default */
1739         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1740
1741         dep = dwc->eps[0];
1742         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1743                         false);
1744         if (ret) {
1745                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1746                 goto err0;
1747         }
1748
1749         dep = dwc->eps[1];
1750         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1751                         false);
1752         if (ret) {
1753                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1754                 goto err1;
1755         }
1756
1757         /* begin to receive SETUP packets */
1758         dwc->ep0state = EP0_SETUP_PHASE;
1759         dwc3_ep0_out_start(dwc);
1760
1761         dwc3_gadget_enable_irq(dwc);
1762
1763         return 0;
1764
1765 err1:
1766         __dwc3_gadget_ep_disable(dwc->eps[0]);
1767
1768 err0:
1769         return ret;
1770 }
1771
1772 static int dwc3_gadget_start(struct usb_gadget *g,
1773                 struct usb_gadget_driver *driver)
1774 {
1775         struct dwc3             *dwc = gadget_to_dwc(g);
1776         unsigned long           flags;
1777         int                     ret = 0;
1778         int                     irq;
1779
1780         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1781         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1782                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1783         if (ret) {
1784                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1785                                 irq, ret);
1786                 goto err0;
1787         }
1788         dwc->irq_gadget = irq;
1789
1790         spin_lock_irqsave(&dwc->lock, flags);
1791         if (dwc->gadget_driver) {
1792                 dev_err(dwc->dev, "%s is already bound to %s\n",
1793                                 dwc->gadget.name,
1794                                 dwc->gadget_driver->driver.name);
1795                 ret = -EBUSY;
1796                 goto err1;
1797         }
1798
1799         dwc->gadget_driver      = driver;
1800
1801         if (pm_runtime_active(dwc->dev))
1802                 __dwc3_gadget_start(dwc);
1803
1804         spin_unlock_irqrestore(&dwc->lock, flags);
1805
1806         return 0;
1807
1808 err1:
1809         spin_unlock_irqrestore(&dwc->lock, flags);
1810         free_irq(irq, dwc);
1811
1812 err0:
1813         return ret;
1814 }
1815
1816 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1817 {
1818         dwc3_gadget_disable_irq(dwc);
1819         __dwc3_gadget_ep_disable(dwc->eps[0]);
1820         __dwc3_gadget_ep_disable(dwc->eps[1]);
1821 }
1822
1823 static int dwc3_gadget_stop(struct usb_gadget *g)
1824 {
1825         struct dwc3             *dwc = gadget_to_dwc(g);
1826         unsigned long           flags;
1827
1828         spin_lock_irqsave(&dwc->lock, flags);
1829         __dwc3_gadget_stop(dwc);
1830         dwc->gadget_driver      = NULL;
1831         spin_unlock_irqrestore(&dwc->lock, flags);
1832
1833         free_irq(dwc->irq_gadget, dwc->ev_buf);
1834
1835         return 0;
1836 }
1837
1838 static const struct usb_gadget_ops dwc3_gadget_ops = {
1839         .get_frame              = dwc3_gadget_get_frame,
1840         .wakeup                 = dwc3_gadget_wakeup,
1841         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1842         .pullup                 = dwc3_gadget_pullup,
1843         .udc_start              = dwc3_gadget_start,
1844         .udc_stop               = dwc3_gadget_stop,
1845 };
1846
1847 /* -------------------------------------------------------------------------- */
1848
1849 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1850                 u8 num, u32 direction)
1851 {
1852         struct dwc3_ep                  *dep;
1853         u8                              i;
1854
1855         for (i = 0; i < num; i++) {
1856                 u8 epnum = (i << 1) | (direction ? 1 : 0);
1857
1858                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1859                 if (!dep)
1860                         return -ENOMEM;
1861
1862                 dep->dwc = dwc;
1863                 dep->number = epnum;
1864                 dep->direction = !!direction;
1865                 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1866                 dwc->eps[epnum] = dep;
1867
1868                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1869                                 (epnum & 1) ? "in" : "out");
1870
1871                 dep->endpoint.name = dep->name;
1872                 spin_lock_init(&dep->lock);
1873
1874                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1875
1876                 if (epnum == 0 || epnum == 1) {
1877                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1878                         dep->endpoint.maxburst = 1;
1879                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1880                         if (!epnum)
1881                                 dwc->gadget.ep0 = &dep->endpoint;
1882                 } else {
1883                         int             ret;
1884
1885                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1886                         dep->endpoint.max_streams = 15;
1887                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1888                         list_add_tail(&dep->endpoint.ep_list,
1889                                         &dwc->gadget.ep_list);
1890
1891                         ret = dwc3_alloc_trb_pool(dep);
1892                         if (ret)
1893                                 return ret;
1894                 }
1895
1896                 if (epnum == 0 || epnum == 1) {
1897                         dep->endpoint.caps.type_control = true;
1898                 } else {
1899                         dep->endpoint.caps.type_iso = true;
1900                         dep->endpoint.caps.type_bulk = true;
1901                         dep->endpoint.caps.type_int = true;
1902                 }
1903
1904                 dep->endpoint.caps.dir_in = !!direction;
1905                 dep->endpoint.caps.dir_out = !direction;
1906
1907                 INIT_LIST_HEAD(&dep->pending_list);
1908                 INIT_LIST_HEAD(&dep->started_list);
1909         }
1910
1911         return 0;
1912 }
1913
1914 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1915 {
1916         int                             ret;
1917
1918         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1919
1920         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1921         if (ret < 0) {
1922                 dwc3_trace(trace_dwc3_gadget,
1923                                 "failed to allocate OUT endpoints");
1924                 return ret;
1925         }
1926
1927         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1928         if (ret < 0) {
1929                 dwc3_trace(trace_dwc3_gadget,
1930                                 "failed to allocate IN endpoints");
1931                 return ret;
1932         }
1933
1934         return 0;
1935 }
1936
1937 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1938 {
1939         struct dwc3_ep                  *dep;
1940         u8                              epnum;
1941
1942         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1943                 dep = dwc->eps[epnum];
1944                 if (!dep)
1945                         continue;
1946                 /*
1947                  * Physical endpoints 0 and 1 are special; they form the
1948                  * bi-directional USB endpoint 0.
1949                  *
1950                  * For those two physical endpoints, we don't allocate a TRB
1951                  * pool nor do we add them the endpoints list. Due to that, we
1952                  * shouldn't do these two operations otherwise we would end up
1953                  * with all sorts of bugs when removing dwc3.ko.
1954                  */
1955                 if (epnum != 0 && epnum != 1) {
1956                         dwc3_free_trb_pool(dep);
1957                         list_del(&dep->endpoint.ep_list);
1958                 }
1959
1960                 kfree(dep);
1961         }
1962 }
1963
1964 /* -------------------------------------------------------------------------- */
1965
1966 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1967                 struct dwc3_request *req, struct dwc3_trb *trb,
1968                 const struct dwc3_event_depevt *event, int status)
1969 {
1970         unsigned int            count;
1971         unsigned int            s_pkt = 0;
1972         unsigned int            trb_status;
1973
1974         dep->queued_requests--;
1975         trace_dwc3_complete_trb(dep, trb);
1976
1977         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1978                 /*
1979                  * We continue despite the error. There is not much we
1980                  * can do. If we don't clean it up we loop forever. If
1981                  * we skip the TRB then it gets overwritten after a
1982                  * while since we use them in a ring buffer. A BUG()
1983                  * would help. Lets hope that if this occurs, someone
1984                  * fixes the root cause instead of looking away :)
1985                  */
1986                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1987                                 dep->name, trb);
1988         count = trb->size & DWC3_TRB_SIZE_MASK;
1989
1990         if (dep->direction) {
1991                 if (count) {
1992                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1993                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1994                                 dwc3_trace(trace_dwc3_gadget,
1995                                                 "%s: incomplete IN transfer",
1996                                                 dep->name);
1997                                 /*
1998                                  * If missed isoc occurred and there is
1999                                  * no request queued then issue END
2000                                  * TRANSFER, so that core generates
2001                                  * next xfernotready and we will issue
2002                                  * a fresh START TRANSFER.
2003                                  * If there are still queued request
2004                                  * then wait, do not issue either END
2005                                  * or UPDATE TRANSFER, just attach next
2006                                  * request in pending_list during
2007                                  * giveback.If any future queued request
2008                                  * is successfully transferred then we
2009                                  * will issue UPDATE TRANSFER for all
2010                                  * request in the pending_list.
2011                                  */
2012                                 dep->flags |= DWC3_EP_MISSED_ISOC;
2013                         } else {
2014                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2015                                                 dep->name);
2016                                 status = -ECONNRESET;
2017                         }
2018                 } else {
2019                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
2020                 }
2021         } else {
2022                 if (count && (event->status & DEPEVT_STATUS_SHORT))
2023                         s_pkt = 1;
2024         }
2025
2026         /*
2027          * We assume here we will always receive the entire data block
2028          * which we should receive. Meaning, if we program RX to
2029          * receive 4K but we receive only 2K, we assume that's all we
2030          * should receive and we simply bounce the request back to the
2031          * gadget driver for further processing.
2032          */
2033         req->request.actual += req->request.length - count;
2034         if (s_pkt)
2035                 return 1;
2036         if ((event->status & DEPEVT_STATUS_LST) &&
2037                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
2038                                 DWC3_TRB_CTRL_HWO)))
2039                 return 1;
2040         if ((event->status & DEPEVT_STATUS_IOC) &&
2041                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
2042                 return 1;
2043         return 0;
2044 }
2045
2046 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2047                 const struct dwc3_event_depevt *event, int status)
2048 {
2049         struct dwc3_request     *req;
2050         struct dwc3_trb         *trb;
2051         unsigned int            slot;
2052         unsigned int            i;
2053         int                     ret;
2054
2055         do {
2056                 req = next_request(&dep->started_list);
2057                 if (WARN_ON_ONCE(!req))
2058                         return 1;
2059
2060                 i = 0;
2061                 do {
2062                         slot = req->first_trb_index + i;
2063                         if (slot == DWC3_TRB_NUM - 1)
2064                                 slot++;
2065                         slot %= DWC3_TRB_NUM;
2066                         trb = &dep->trb_pool[slot];
2067
2068                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2069                                         event, status);
2070                         if (ret)
2071                                 break;
2072                 } while (++i < req->request.num_mapped_sgs);
2073
2074                 dwc3_gadget_giveback(dep, req, status);
2075
2076                 if (ret)
2077                         break;
2078         } while (1);
2079
2080         /*
2081          * Our endpoint might get disabled by another thread during
2082          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2083          * early on so DWC3_EP_BUSY flag gets cleared
2084          */
2085         if (!dep->endpoint.desc)
2086                 return 1;
2087
2088         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2089                         list_empty(&dep->started_list)) {
2090                 if (list_empty(&dep->pending_list)) {
2091                         /*
2092                          * If there is no entry in request list then do
2093                          * not issue END TRANSFER now. Just set PENDING
2094                          * flag, so that END TRANSFER is issued when an
2095                          * entry is added into request list.
2096                          */
2097                         dep->flags = DWC3_EP_PENDING_REQUEST;
2098                 } else {
2099                         dwc3_stop_active_transfer(dwc, dep->number, true);
2100                         dep->flags = DWC3_EP_ENABLED;
2101                 }
2102                 return 1;
2103         }
2104
2105         if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2106                 if ((event->status & DEPEVT_STATUS_IOC) &&
2107                                 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2108                         return 0;
2109         return 1;
2110 }
2111
2112 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2113                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2114 {
2115         unsigned                status = 0;
2116         int                     clean_busy;
2117         u32                     is_xfer_complete;
2118
2119         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2120
2121         if (event->status & DEPEVT_STATUS_BUSERR)
2122                 status = -ECONNRESET;
2123
2124         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2125         if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2126                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2127                 dep->flags &= ~DWC3_EP_BUSY;
2128
2129         /*
2130          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2131          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2132          */
2133         if (dwc->revision < DWC3_REVISION_183A) {
2134                 u32             reg;
2135                 int             i;
2136
2137                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2138                         dep = dwc->eps[i];
2139
2140                         if (!(dep->flags & DWC3_EP_ENABLED))
2141                                 continue;
2142
2143                         if (!list_empty(&dep->started_list))
2144                                 return;
2145                 }
2146
2147                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2148                 reg |= dwc->u1u2;
2149                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2150
2151                 dwc->u1u2 = 0;
2152         }
2153
2154         /*
2155          * Our endpoint might get disabled by another thread during
2156          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2157          * early on so DWC3_EP_BUSY flag gets cleared
2158          */
2159         if (!dep->endpoint.desc)
2160                 return;
2161
2162         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2163                 int ret;
2164
2165                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2166                 if (!ret || ret == -EBUSY)
2167                         return;
2168         }
2169 }
2170
2171 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2172                 const struct dwc3_event_depevt *event)
2173 {
2174         struct dwc3_ep          *dep;
2175         u8                      epnum = event->endpoint_number;
2176
2177         dep = dwc->eps[epnum];
2178
2179         if (!(dep->flags & DWC3_EP_ENABLED))
2180                 return;
2181
2182         if (epnum == 0 || epnum == 1) {
2183                 dwc3_ep0_interrupt(dwc, event);
2184                 return;
2185         }
2186
2187         switch (event->endpoint_event) {
2188         case DWC3_DEPEVT_XFERCOMPLETE:
2189                 dep->resource_index = 0;
2190
2191                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2192                         dwc3_trace(trace_dwc3_gadget,
2193                                         "%s is an Isochronous endpoint",
2194                                         dep->name);
2195                         return;
2196                 }
2197
2198                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2199                 break;
2200         case DWC3_DEPEVT_XFERINPROGRESS:
2201                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2202                 break;
2203         case DWC3_DEPEVT_XFERNOTREADY:
2204                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2205                         dwc3_gadget_start_isoc(dwc, dep, event);
2206                 } else {
2207                         int active;
2208                         int ret;
2209
2210                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2211
2212                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2213                                         dep->name, active ? "Transfer Active"
2214                                         : "Transfer Not Active");
2215
2216                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2217                         if (!ret || ret == -EBUSY)
2218                                 return;
2219
2220                         dwc3_trace(trace_dwc3_gadget,
2221                                         "%s: failed to kick transfers",
2222                                         dep->name);
2223                 }
2224
2225                 break;
2226         case DWC3_DEPEVT_STREAMEVT:
2227                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2228                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2229                                         dep->name);
2230                         return;
2231                 }
2232
2233                 switch (event->status) {
2234                 case DEPEVT_STREAMEVT_FOUND:
2235                         dwc3_trace(trace_dwc3_gadget,
2236                                         "Stream %d found and started",
2237                                         event->parameters);
2238
2239                         break;
2240                 case DEPEVT_STREAMEVT_NOTFOUND:
2241                         /* FALLTHROUGH */
2242                 default:
2243                         dwc3_trace(trace_dwc3_gadget,
2244                                         "unable to find suitable stream");
2245                 }
2246                 break;
2247         case DWC3_DEPEVT_RXTXFIFOEVT:
2248                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun", dep->name);
2249                 break;
2250         case DWC3_DEPEVT_EPCMDCMPLT:
2251                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2252                 break;
2253         }
2254 }
2255
2256 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2257 {
2258         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2259                 spin_unlock(&dwc->lock);
2260                 dwc->gadget_driver->disconnect(&dwc->gadget);
2261                 spin_lock(&dwc->lock);
2262         }
2263 }
2264
2265 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2266 {
2267         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2268                 spin_unlock(&dwc->lock);
2269                 dwc->gadget_driver->suspend(&dwc->gadget);
2270                 spin_lock(&dwc->lock);
2271         }
2272 }
2273
2274 static void dwc3_resume_gadget(struct dwc3 *dwc)
2275 {
2276         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2277                 spin_unlock(&dwc->lock);
2278                 dwc->gadget_driver->resume(&dwc->gadget);
2279                 spin_lock(&dwc->lock);
2280         }
2281 }
2282
2283 static void dwc3_reset_gadget(struct dwc3 *dwc)
2284 {
2285         if (!dwc->gadget_driver)
2286                 return;
2287
2288         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2289                 spin_unlock(&dwc->lock);
2290                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2291                 spin_lock(&dwc->lock);
2292         }
2293 }
2294
2295 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2296 {
2297         struct dwc3_ep *dep;
2298         struct dwc3_gadget_ep_cmd_params params;
2299         u32 cmd;
2300         int ret;
2301
2302         dep = dwc->eps[epnum];
2303
2304         if (!dep->resource_index)
2305                 return;
2306
2307         /*
2308          * NOTICE: We are violating what the Databook says about the
2309          * EndTransfer command. Ideally we would _always_ wait for the
2310          * EndTransfer Command Completion IRQ, but that's causing too
2311          * much trouble synchronizing between us and gadget driver.
2312          *
2313          * We have discussed this with the IP Provider and it was
2314          * suggested to giveback all requests here, but give HW some
2315          * extra time to synchronize with the interconnect. We're using
2316          * an arbitrary 100us delay for that.
2317          *
2318          * Note also that a similar handling was tested by Synopsys
2319          * (thanks a lot Paul) and nothing bad has come out of it.
2320          * In short, what we're doing is:
2321          *
2322          * - Issue EndTransfer WITH CMDIOC bit set
2323          * - Wait 100us
2324          */
2325
2326         cmd = DWC3_DEPCMD_ENDTRANSFER;
2327         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2328         cmd |= DWC3_DEPCMD_CMDIOC;
2329         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2330         memset(&params, 0, sizeof(params));
2331         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2332         WARN_ON_ONCE(ret);
2333         dep->resource_index = 0;
2334         dep->flags &= ~DWC3_EP_BUSY;
2335         udelay(100);
2336 }
2337
2338 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2339 {
2340         u32 epnum;
2341
2342         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2343                 struct dwc3_ep *dep;
2344
2345                 dep = dwc->eps[epnum];
2346                 if (!dep)
2347                         continue;
2348
2349                 if (!(dep->flags & DWC3_EP_ENABLED))
2350                         continue;
2351
2352                 dwc3_remove_requests(dwc, dep);
2353         }
2354 }
2355
2356 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2357 {
2358         u32 epnum;
2359
2360         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2361                 struct dwc3_ep *dep;
2362                 int ret;
2363
2364                 dep = dwc->eps[epnum];
2365                 if (!dep)
2366                         continue;
2367
2368                 if (!(dep->flags & DWC3_EP_STALL))
2369                         continue;
2370
2371                 dep->flags &= ~DWC3_EP_STALL;
2372
2373                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2374                 WARN_ON_ONCE(ret);
2375         }
2376 }
2377
2378 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2379 {
2380         int                     reg;
2381
2382         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2383         reg &= ~DWC3_DCTL_INITU1ENA;
2384         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2385
2386         reg &= ~DWC3_DCTL_INITU2ENA;
2387         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2388
2389         dwc3_disconnect_gadget(dwc);
2390
2391         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2392         dwc->setup_packet_pending = false;
2393         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2394
2395         dwc->connected = false;
2396 }
2397
2398 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2399 {
2400         u32                     reg;
2401
2402         dwc->connected = true;
2403
2404         /*
2405          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2406          * would cause a missing Disconnect Event if there's a
2407          * pending Setup Packet in the FIFO.
2408          *
2409          * There's no suggested workaround on the official Bug
2410          * report, which states that "unless the driver/application
2411          * is doing any special handling of a disconnect event,
2412          * there is no functional issue".
2413          *
2414          * Unfortunately, it turns out that we _do_ some special
2415          * handling of a disconnect event, namely complete all
2416          * pending transfers, notify gadget driver of the
2417          * disconnection, and so on.
2418          *
2419          * Our suggested workaround is to follow the Disconnect
2420          * Event steps here, instead, based on a setup_packet_pending
2421          * flag. Such flag gets set whenever we have a SETUP_PENDING
2422          * status for EP0 TRBs and gets cleared on XferComplete for the
2423          * same endpoint.
2424          *
2425          * Refers to:
2426          *
2427          * STAR#9000466709: RTL: Device : Disconnect event not
2428          * generated if setup packet pending in FIFO
2429          */
2430         if (dwc->revision < DWC3_REVISION_188A) {
2431                 if (dwc->setup_packet_pending)
2432                         dwc3_gadget_disconnect_interrupt(dwc);
2433         }
2434
2435         dwc3_reset_gadget(dwc);
2436
2437         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2438         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2439         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2440         dwc->test_mode = false;
2441
2442         dwc3_stop_active_transfers(dwc);
2443         dwc3_clear_stall_all_ep(dwc);
2444
2445         /* Reset device address to zero */
2446         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2447         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2448         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2449 }
2450
2451 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2452 {
2453         u32 reg;
2454         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2455
2456         /*
2457          * We change the clock only at SS but I dunno why I would want to do
2458          * this. Maybe it becomes part of the power saving plan.
2459          */
2460
2461         if ((speed != DWC3_DSTS_SUPERSPEED) &&
2462             (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2463                 return;
2464
2465         /*
2466          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2467          * each time on Connect Done.
2468          */
2469         if (!usb30_clock)
2470                 return;
2471
2472         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2473         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2474         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2475 }
2476
2477 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2478 {
2479         struct dwc3_ep          *dep;
2480         int                     ret;
2481         u32                     reg;
2482         u8                      speed;
2483
2484         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2485         speed = reg & DWC3_DSTS_CONNECTSPD;
2486         dwc->speed = speed;
2487
2488         dwc3_update_ram_clk_sel(dwc, speed);
2489
2490         switch (speed) {
2491         case DWC3_DSTS_SUPERSPEED_PLUS:
2492                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2493                 dwc->gadget.ep0->maxpacket = 512;
2494                 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2495                 break;
2496         case DWC3_DSTS_SUPERSPEED:
2497                 /*
2498                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2499                  * would cause a missing USB3 Reset event.
2500                  *
2501                  * In such situations, we should force a USB3 Reset
2502                  * event by calling our dwc3_gadget_reset_interrupt()
2503                  * routine.
2504                  *
2505                  * Refers to:
2506                  *
2507                  * STAR#9000483510: RTL: SS : USB3 reset event may
2508                  * not be generated always when the link enters poll
2509                  */
2510                 if (dwc->revision < DWC3_REVISION_190A)
2511                         dwc3_gadget_reset_interrupt(dwc);
2512
2513                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2514                 dwc->gadget.ep0->maxpacket = 512;
2515                 dwc->gadget.speed = USB_SPEED_SUPER;
2516                 break;
2517         case DWC3_DSTS_HIGHSPEED:
2518                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2519                 dwc->gadget.ep0->maxpacket = 64;
2520                 dwc->gadget.speed = USB_SPEED_HIGH;
2521                 break;
2522         case DWC3_DSTS_FULLSPEED2:
2523         case DWC3_DSTS_FULLSPEED1:
2524                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2525                 dwc->gadget.ep0->maxpacket = 64;
2526                 dwc->gadget.speed = USB_SPEED_FULL;
2527                 break;
2528         case DWC3_DSTS_LOWSPEED:
2529                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2530                 dwc->gadget.ep0->maxpacket = 8;
2531                 dwc->gadget.speed = USB_SPEED_LOW;
2532                 break;
2533         }
2534
2535         /* Enable USB2 LPM Capability */
2536
2537         if ((dwc->revision > DWC3_REVISION_194A) &&
2538             (speed != DWC3_DSTS_SUPERSPEED) &&
2539             (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2540                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2541                 reg |= DWC3_DCFG_LPM_CAP;
2542                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2543
2544                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2545                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2546
2547                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2548
2549                 /*
2550                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2551                  * DCFG.LPMCap is set, core responses with an ACK and the
2552                  * BESL value in the LPM token is less than or equal to LPM
2553                  * NYET threshold.
2554                  */
2555                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2556                                 && dwc->has_lpm_erratum,
2557                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2558
2559                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2560                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2561
2562                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2563         } else {
2564                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2565                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2566                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2567         }
2568
2569         dep = dwc->eps[0];
2570         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2571                         false);
2572         if (ret) {
2573                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2574                 return;
2575         }
2576
2577         dep = dwc->eps[1];
2578         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2579                         false);
2580         if (ret) {
2581                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2582                 return;
2583         }
2584
2585         /*
2586          * Configure PHY via GUSB3PIPECTLn if required.
2587          *
2588          * Update GTXFIFOSIZn
2589          *
2590          * In both cases reset values should be sufficient.
2591          */
2592 }
2593
2594 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2595 {
2596         /*
2597          * TODO take core out of low power mode when that's
2598          * implemented.
2599          */
2600
2601         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2602                 spin_unlock(&dwc->lock);
2603                 dwc->gadget_driver->resume(&dwc->gadget);
2604                 spin_lock(&dwc->lock);
2605         }
2606 }
2607
2608 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2609                 unsigned int evtinfo)
2610 {
2611         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2612         unsigned int            pwropt;
2613
2614         /*
2615          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2616          * Hibernation mode enabled which would show up when device detects
2617          * host-initiated U3 exit.
2618          *
2619          * In that case, device will generate a Link State Change Interrupt
2620          * from U3 to RESUME which is only necessary if Hibernation is
2621          * configured in.
2622          *
2623          * There are no functional changes due to such spurious event and we
2624          * just need to ignore it.
2625          *
2626          * Refers to:
2627          *
2628          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2629          * operational mode
2630          */
2631         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2632         if ((dwc->revision < DWC3_REVISION_250A) &&
2633                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2634                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2635                                 (next == DWC3_LINK_STATE_RESUME)) {
2636                         dwc3_trace(trace_dwc3_gadget,
2637                                         "ignoring transition U3 -> Resume");
2638                         return;
2639                 }
2640         }
2641
2642         /*
2643          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2644          * on the link partner, the USB session might do multiple entry/exit
2645          * of low power states before a transfer takes place.
2646          *
2647          * Due to this problem, we might experience lower throughput. The
2648          * suggested workaround is to disable DCTL[12:9] bits if we're
2649          * transitioning from U1/U2 to U0 and enable those bits again
2650          * after a transfer completes and there are no pending transfers
2651          * on any of the enabled endpoints.
2652          *
2653          * This is the first half of that workaround.
2654          *
2655          * Refers to:
2656          *
2657          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2658          * core send LGO_Ux entering U0
2659          */
2660         if (dwc->revision < DWC3_REVISION_183A) {
2661                 if (next == DWC3_LINK_STATE_U0) {
2662                         u32     u1u2;
2663                         u32     reg;
2664
2665                         switch (dwc->link_state) {
2666                         case DWC3_LINK_STATE_U1:
2667                         case DWC3_LINK_STATE_U2:
2668                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2669                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2670                                                 | DWC3_DCTL_ACCEPTU2ENA
2671                                                 | DWC3_DCTL_INITU1ENA
2672                                                 | DWC3_DCTL_ACCEPTU1ENA);
2673
2674                                 if (!dwc->u1u2)
2675                                         dwc->u1u2 = reg & u1u2;
2676
2677                                 reg &= ~u1u2;
2678
2679                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2680                                 break;
2681                         default:
2682                                 /* do nothing */
2683                                 break;
2684                         }
2685                 }
2686         }
2687
2688         switch (next) {
2689         case DWC3_LINK_STATE_U1:
2690                 if (dwc->speed == USB_SPEED_SUPER)
2691                         dwc3_suspend_gadget(dwc);
2692                 break;
2693         case DWC3_LINK_STATE_U2:
2694         case DWC3_LINK_STATE_U3:
2695                 dwc3_suspend_gadget(dwc);
2696                 break;
2697         case DWC3_LINK_STATE_RESUME:
2698                 dwc3_resume_gadget(dwc);
2699                 break;
2700         default:
2701                 /* do nothing */
2702                 break;
2703         }
2704
2705         dwc->link_state = next;
2706 }
2707
2708 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2709                 unsigned int evtinfo)
2710 {
2711         unsigned int is_ss = evtinfo & BIT(4);
2712
2713         /**
2714          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2715          * have a known issue which can cause USB CV TD.9.23 to fail
2716          * randomly.
2717          *
2718          * Because of this issue, core could generate bogus hibernation
2719          * events which SW needs to ignore.
2720          *
2721          * Refers to:
2722          *
2723          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2724          * Device Fallback from SuperSpeed
2725          */
2726         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2727                 return;
2728
2729         /* enter hibernation here */
2730 }
2731
2732 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2733                 const struct dwc3_event_devt *event)
2734 {
2735         switch (event->type) {
2736         case DWC3_DEVICE_EVENT_DISCONNECT:
2737                 dwc3_gadget_disconnect_interrupt(dwc);
2738                 break;
2739         case DWC3_DEVICE_EVENT_RESET:
2740                 dwc3_gadget_reset_interrupt(dwc);
2741                 break;
2742         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2743                 dwc3_gadget_conndone_interrupt(dwc);
2744                 break;
2745         case DWC3_DEVICE_EVENT_WAKEUP:
2746                 dwc3_gadget_wakeup_interrupt(dwc);
2747                 break;
2748         case DWC3_DEVICE_EVENT_HIBER_REQ:
2749                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2750                                         "unexpected hibernation event\n"))
2751                         break;
2752
2753                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2754                 break;
2755         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2756                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2757                 break;
2758         case DWC3_DEVICE_EVENT_EOPF:
2759                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2760                 break;
2761         case DWC3_DEVICE_EVENT_SOF:
2762                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2763                 break;
2764         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2765                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2766                 break;
2767         case DWC3_DEVICE_EVENT_CMD_CMPL:
2768                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2769                 break;
2770         case DWC3_DEVICE_EVENT_OVERFLOW:
2771                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2772                 break;
2773         default:
2774                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2775         }
2776 }
2777
2778 static void dwc3_process_event_entry(struct dwc3 *dwc,
2779                 const union dwc3_event *event)
2780 {
2781         trace_dwc3_event(event->raw);
2782
2783         /* Endpoint IRQ, handle it and return early */
2784         if (event->type.is_devspec == 0) {
2785                 /* depevt */
2786                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2787         }
2788
2789         switch (event->type.type) {
2790         case DWC3_EVENT_TYPE_DEV:
2791                 dwc3_gadget_interrupt(dwc, &event->devt);
2792                 break;
2793         /* REVISIT what to do with Carkit and I2C events ? */
2794         default:
2795                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2796         }
2797 }
2798
2799 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2800 {
2801         struct dwc3 *dwc = evt->dwc;
2802         irqreturn_t ret = IRQ_NONE;
2803         int left;
2804         u32 reg;
2805
2806         left = evt->count;
2807
2808         if (!(evt->flags & DWC3_EVENT_PENDING))
2809                 return IRQ_NONE;
2810
2811         while (left > 0) {
2812                 union dwc3_event event;
2813
2814                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2815
2816                 dwc3_process_event_entry(dwc, &event);
2817
2818                 /*
2819                  * FIXME we wrap around correctly to the next entry as
2820                  * almost all entries are 4 bytes in size. There is one
2821                  * entry which has 12 bytes which is a regular entry
2822                  * followed by 8 bytes data. ATM I don't know how
2823                  * things are organized if we get next to the a
2824                  * boundary so I worry about that once we try to handle
2825                  * that.
2826                  */
2827                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2828                 left -= 4;
2829
2830                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2831         }
2832
2833         evt->count = 0;
2834         evt->flags &= ~DWC3_EVENT_PENDING;
2835         ret = IRQ_HANDLED;
2836
2837         /* Unmask interrupt */
2838         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2839         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2840         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2841
2842         return ret;
2843 }
2844
2845 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2846 {
2847         struct dwc3_event_buffer *evt = _evt;
2848         struct dwc3 *dwc = evt->dwc;
2849         unsigned long flags;
2850         irqreturn_t ret = IRQ_NONE;
2851
2852         spin_lock_irqsave(&dwc->lock, flags);
2853         ret = dwc3_process_event_buf(evt);
2854         spin_unlock_irqrestore(&dwc->lock, flags);
2855
2856         return ret;
2857 }
2858
2859 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2860 {
2861         struct dwc3 *dwc = evt->dwc;
2862         u32 count;
2863         u32 reg;
2864
2865         if (pm_runtime_suspended(dwc->dev)) {
2866                 pm_runtime_get(dwc->dev);
2867                 disable_irq_nosync(dwc->irq_gadget);
2868                 dwc->pending_events = true;
2869                 return IRQ_HANDLED;
2870         }
2871
2872         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2873         count &= DWC3_GEVNTCOUNT_MASK;
2874         if (!count)
2875                 return IRQ_NONE;
2876
2877         evt->count = count;
2878         evt->flags |= DWC3_EVENT_PENDING;
2879
2880         /* Mask interrupt */
2881         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2882         reg |= DWC3_GEVNTSIZ_INTMASK;
2883         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2884
2885         return IRQ_WAKE_THREAD;
2886 }
2887
2888 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2889 {
2890         struct dwc3_event_buffer        *evt = _evt;
2891
2892         return dwc3_check_event_buf(evt);
2893 }
2894
2895 /**
2896  * dwc3_gadget_init - Initializes gadget related registers
2897  * @dwc: pointer to our controller context structure
2898  *
2899  * Returns 0 on success otherwise negative errno.
2900  */
2901 int dwc3_gadget_init(struct dwc3 *dwc)
2902 {
2903         int                                     ret;
2904
2905         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2906                         &dwc->ctrl_req_addr, GFP_KERNEL);
2907         if (!dwc->ctrl_req) {
2908                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2909                 ret = -ENOMEM;
2910                 goto err0;
2911         }
2912
2913         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2914                         &dwc->ep0_trb_addr, GFP_KERNEL);
2915         if (!dwc->ep0_trb) {
2916                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2917                 ret = -ENOMEM;
2918                 goto err1;
2919         }
2920
2921         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2922         if (!dwc->setup_buf) {
2923                 ret = -ENOMEM;
2924                 goto err2;
2925         }
2926
2927         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2928                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2929                         GFP_KERNEL);
2930         if (!dwc->ep0_bounce) {
2931                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2932                 ret = -ENOMEM;
2933                 goto err3;
2934         }
2935
2936         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2937         if (!dwc->zlp_buf) {
2938                 ret = -ENOMEM;
2939                 goto err4;
2940         }
2941
2942         dwc->gadget.ops                 = &dwc3_gadget_ops;
2943         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2944         dwc->gadget.sg_supported        = true;
2945         dwc->gadget.name                = "dwc3-gadget";
2946         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2947
2948         /*
2949          * FIXME We might be setting max_speed to <SUPER, however versions
2950          * <2.20a of dwc3 have an issue with metastability (documented
2951          * elsewhere in this driver) which tells us we can't set max speed to
2952          * anything lower than SUPER.
2953          *
2954          * Because gadget.max_speed is only used by composite.c and function
2955          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2956          * to happen so we avoid sending SuperSpeed Capability descriptor
2957          * together with our BOS descriptor as that could confuse host into
2958          * thinking we can handle super speed.
2959          *
2960          * Note that, in fact, we won't even support GetBOS requests when speed
2961          * is less than super speed because we don't have means, yet, to tell
2962          * composite.c that we are USB 2.0 + LPM ECN.
2963          */
2964         if (dwc->revision < DWC3_REVISION_220A)
2965                 dwc3_trace(trace_dwc3_gadget,
2966                                 "Changing max_speed on rev %08x",
2967                                 dwc->revision);
2968
2969         dwc->gadget.max_speed           = dwc->maximum_speed;
2970
2971         /*
2972          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2973          * on ep out.
2974          */
2975         dwc->gadget.quirk_ep_out_aligned_size = true;
2976
2977         /*
2978          * REVISIT: Here we should clear all pending IRQs to be
2979          * sure we're starting from a well known location.
2980          */
2981
2982         ret = dwc3_gadget_init_endpoints(dwc);
2983         if (ret)
2984                 goto err5;
2985
2986         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2987         if (ret) {
2988                 dev_err(dwc->dev, "failed to register udc\n");
2989                 goto err5;
2990         }
2991
2992         return 0;
2993
2994 err5:
2995         kfree(dwc->zlp_buf);
2996
2997 err4:
2998         dwc3_gadget_free_endpoints(dwc);
2999         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3000                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
3001
3002 err3:
3003         kfree(dwc->setup_buf);
3004
3005 err2:
3006         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3007                         dwc->ep0_trb, dwc->ep0_trb_addr);
3008
3009 err1:
3010         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3011                         dwc->ctrl_req, dwc->ctrl_req_addr);
3012
3013 err0:
3014         return ret;
3015 }
3016
3017 /* -------------------------------------------------------------------------- */
3018
3019 void dwc3_gadget_exit(struct dwc3 *dwc)
3020 {
3021         usb_del_gadget_udc(&dwc->gadget);
3022
3023         dwc3_gadget_free_endpoints(dwc);
3024
3025         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3026                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
3027
3028         kfree(dwc->setup_buf);
3029         kfree(dwc->zlp_buf);
3030
3031         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3032                         dwc->ep0_trb, dwc->ep0_trb_addr);
3033
3034         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3035                         dwc->ctrl_req, dwc->ctrl_req_addr);
3036 }
3037
3038 int dwc3_gadget_suspend(struct dwc3 *dwc)
3039 {
3040         int ret;
3041
3042         if (!dwc->gadget_driver)
3043                 return 0;
3044
3045         ret = dwc3_gadget_run_stop(dwc, false, false);
3046         if (ret < 0)
3047                 return ret;
3048
3049         dwc3_disconnect_gadget(dwc);
3050         __dwc3_gadget_stop(dwc);
3051
3052         return 0;
3053 }
3054
3055 int dwc3_gadget_resume(struct dwc3 *dwc)
3056 {
3057         int                     ret;
3058
3059         if (!dwc->gadget_driver)
3060                 return 0;
3061
3062         ret = __dwc3_gadget_start(dwc);
3063         if (ret < 0)
3064                 goto err0;
3065
3066         ret = dwc3_gadget_run_stop(dwc, true, false);
3067         if (ret < 0)
3068                 goto err1;
3069
3070         return 0;
3071
3072 err1:
3073         __dwc3_gadget_stop(dwc);
3074
3075 err0:
3076         return ret;
3077 }
3078
3079 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3080 {
3081         if (dwc->pending_events) {
3082                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3083                 dwc->pending_events = false;
3084                 enable_irq(dwc->irq_gadget);
3085         }
3086 }