drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 149                 int status)
 150 {
 151         struct dwc3                     *dwc = dep->dwc;
 152         int                             i;
 153
 154         if (req->started) {
 155                 i = 0;
 156                 do {
 157                         dep->busy_slot++;
 158                         /*
 159                          * Skip LINK TRB. We can't use req->trb and check for
 160                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 161                          * just completed (not the LINK TRB).
 162                          */
 163                         if (((dep->busy_slot & DWC3_TRB_MASK) ==
 164                                 DWC3_TRB_NUM- 1) &&
 165                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 166                                 dep->busy_slot++;
 167                 } while(++i < req->request.num_mapped_sgs);
 168                 req->started = false;
 169         }
 170         list_del(&req->list);
 171         req->trb = NULL;
 172
 173         if (req->request.status == -EINPROGRESS)
 174                 req->request.status = status;
 175
 176         if (dwc->ep0_bounced && dep->number == 0)
 177                 dwc->ep0_bounced = false;
 178         else
 179                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 180                                 req->direction);
 181
 182         trace_dwc3_gadget_giveback(req);
 183
 184         spin_unlock(&dwc->lock);
 185         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 186         spin_lock(&dwc->lock);
 187 }
 188
 189 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 190 {
 191         u32             timeout = 500;
 192         u32             reg;
 193
 194         trace_dwc3_gadget_generic_cmd(cmd, param);
 195
 196         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 197         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 198
 199         do {
 200                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 201                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 202                         dwc3_trace(trace_dwc3_gadget,
 203                                         "Command Complete --> %d",
 204                                         DWC3_DGCMD_STATUS(reg));
 205                         if (DWC3_DGCMD_STATUS(reg))
 206                                 return -EINVAL;
 207                         return 0;
 208                 }
 209
 210                 /*
 211                  * We can't sleep here, because it's also called from
 212                  * interrupt context.
 213                  */
 214                 timeout--;
 215                 if (!timeout) {
 216                         dwc3_trace(trace_dwc3_gadget,
 217                                         "Command Timed Out");
 218                         return -ETIMEDOUT;
 219                 }
 220                 udelay(1);
 221         } while (1);
 222 }
 223
 224 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 225                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 226 {
 227         struct dwc3_ep          *dep = dwc->eps[ep];
 228         u32                     timeout = 500;
 229         u32                     reg;
 230         int                     ret = -EINVAL;
 231
 232         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 233
 234         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 235         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 236         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 237
 238         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 239         do {
 240                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 241                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 242                         dwc3_trace(trace_dwc3_gadget,
 243                                         "Command Complete --> %d",
 244                                         DWC3_DEPCMD_STATUS(reg));
 245                         if (DWC3_DEPCMD_STATUS(reg))
 246                                 break;
 247                         ret = 0;
 248                         break;
 249                 }
 250
 251                 /*
 252                  * We can't sleep here, because it is also called from
 253                  * interrupt context.
 254                  */
 255                 timeout--;
 256                 if (!timeout) {
 257                         dwc3_trace(trace_dwc3_gadget,
 258                                         "Command Timed Out");
 259                         ret = -ETIMEDOUT;
 260                         break;
 261                 }
 262
 263                 udelay(1);
 264         } while (1);
 265
 266         return ret;
 267 }
 268
 269 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 270                 struct dwc3_trb *trb)
 271 {
 272         u32             offset = (char *) trb - (char *) dep->trb_pool;
 273
 274         return dep->trb_pool_dma + offset;
 275 }
 276
 277 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 278 {
 279         struct dwc3             *dwc = dep->dwc;
 280
 281         if (dep->trb_pool)
 282                 return 0;
 283
 284         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 285                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 286                         &dep->trb_pool_dma, GFP_KERNEL);
 287         if (!dep->trb_pool) {
 288                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 289                                 dep->name);
 290                 return -ENOMEM;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 297 {
 298         struct dwc3             *dwc = dep->dwc;
 299
 300         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 301                         dep->trb_pool, dep->trb_pool_dma);
 302
 303         dep->trb_pool = NULL;
 304         dep->trb_pool_dma = 0;
 305 }
 306
 307 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 308
 309 /**
 310  * dwc3_gadget_start_config - Configure EP resources
 311  * @dwc: pointer to our controller context structure
 312  * @dep: endpoint that is being enabled
 313  *
 314  * The assignment of transfer resources cannot perfectly follow the
 315  * data book due to the fact that the controller driver does not have
 316  * all knowledge of the configuration in advance. It is given this
 317  * information piecemeal by the composite gadget framework after every
 318  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 319  * programming model in this scenario can cause errors. For two
 320  * reasons:
 321  *
 322  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 323  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 324  * multiple interfaces.
 325  *
 326  * 2) The databook does not mention doing more DEPXFERCFG for new
 327  * endpoint on alt setting (8.1.6).
 328  *
 329  * The following simplified method is used instead:
 330  *
 331  * All hardware endpoints can be assigned a transfer resource and this
 332  * setting will stay persistent until either a core reset or
 333  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 334  * do DEPXFERCFG for every hardware endpoint as well. We are
 335  * guaranteed that there are as many transfer resources as endpoints.
 336  *
 337  * This function is called for each endpoint when it is being enabled
 338  * but is triggered only when called for EP0-out, which always happens
 339  * first, and which should only happen in one of the above conditions.
 340  */
 341 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 342 {
 343         struct dwc3_gadget_ep_cmd_params params;
 344         u32                     cmd;
 345         int                     i;
 346         int                     ret;
 347
 348         if (dep->number)
 349                 return 0;
 350
 351         memset(&params, 0x00, sizeof(params));
 352         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 353
 354         ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 355         if (ret)
 356                 return ret;
 357
 358         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 359                 struct dwc3_ep *dep = dwc->eps[i];
 360
 361                 if (!dep)
 362                         continue;
 363
 364                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 365                 if (ret)
 366                         return ret;
 367         }
 368
 369         return 0;
 370 }
 371
 372 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 373                 const struct usb_endpoint_descriptor *desc,
 374                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 375                 bool ignore, bool restore)
 376 {
 377         struct dwc3_gadget_ep_cmd_params params;
 378
 379         memset(&params, 0x00, sizeof(params));
 380
 381         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 382                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 383
 384         /* Burst size is only needed in SuperSpeed mode */
 385         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 386                 u32 burst = dep->endpoint.maxburst - 1;
 387
 388                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 389         }
 390
 391         if (ignore)
 392                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 393
 394         if (restore) {
 395                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 396                 params.param2 |= dep->saved_state;
 397         }
 398
 399         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 400                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 401
 402         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 403                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 404                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 405                 dep->stream_capable = true;
 406         }
 407
 408         if (!usb_endpoint_xfer_control(desc))
 409                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 410
 411         /*
 412          * We are doing 1:1 mapping for endpoints, meaning
 413          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 414          * so on. We consider the direction bit as part of the physical
 415          * endpoint number. So USB endpoint 0x81 is 0x03.
 416          */
 417         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 418
 419         /*
 420          * We must use the lower 16 TX FIFOs even though
 421          * HW might have more
 422          */
 423         if (dep->direction)
 424                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 425
 426         if (desc->bInterval) {
 427                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 428                 dep->interval = 1 << (desc->bInterval - 1);
 429         }
 430
 431         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 432                         DWC3_DEPCMD_SETEPCONFIG, &params);
 433 }
 434
 435 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 436 {
 437         struct dwc3_gadget_ep_cmd_params params;
 438
 439         memset(&params, 0x00, sizeof(params));
 440
 441         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 442
 443         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 444                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 445 }
 446
 447 /**
 448  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 449  * @dep: endpoint to be initialized
 450  * @desc: USB Endpoint Descriptor
 451  *
 452  * Caller should take care of locking
 453  */
 454 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 455                 const struct usb_endpoint_descriptor *desc,
 456                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 457                 bool ignore, bool restore)
 458 {
 459         struct dwc3             *dwc = dep->dwc;
 460         u32                     reg;
 461         int                     ret;
 462
 463         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 464
 465         if (!(dep->flags & DWC3_EP_ENABLED)) {
 466                 ret = dwc3_gadget_start_config(dwc, dep);
 467                 if (ret)
 468                         return ret;
 469         }
 470
 471         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 472                         restore);
 473         if (ret)
 474                 return ret;
 475
 476         if (!(dep->flags & DWC3_EP_ENABLED)) {
 477                 struct dwc3_trb *trb_st_hw;
 478                 struct dwc3_trb *trb_link;
 479
 480                 dep->endpoint.desc = desc;
 481                 dep->comp_desc = comp_desc;
 482                 dep->type = usb_endpoint_type(desc);
 483                 dep->flags |= DWC3_EP_ENABLED;
 484
 485                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 486                 reg |= DWC3_DALEPENA_EP(dep->number);
 487                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 488
 489                 if (!usb_endpoint_xfer_isoc(desc))
 490                         goto out;
 491
 492                 /* Link TRB for ISOC. The HWO bit is never reset */
 493                 trb_st_hw = &dep->trb_pool[0];
 494
 495                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 496                 memset(trb_link, 0, sizeof(*trb_link));
 497
 498                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 499                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 500                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 501                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 502         }
 503
 504 out:
 505         switch (usb_endpoint_type(desc)) {
 506         case USB_ENDPOINT_XFER_CONTROL:
 507                 /* don't change name */
 508                 break;
 509         case USB_ENDPOINT_XFER_ISOC:
 510                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 511                 break;
 512         case USB_ENDPOINT_XFER_BULK:
 513                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 514                 break;
 515         case USB_ENDPOINT_XFER_INT:
 516                 strlcat(dep->name, "-int", sizeof(dep->name));
 517                 break;
 518         default:
 519                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 520         }
 521
 522         return 0;
 523 }
 524
 525 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 526 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 527 {
 528         struct dwc3_request             *req;
 529
 530         if (!list_empty(&dep->started_list)) {
 531                 dwc3_stop_active_transfer(dwc, dep->number, true);
 532
 533                 /* - giveback all requests to gadget driver */
 534                 while (!list_empty(&dep->started_list)) {
 535                         req = next_request(&dep->started_list);
 536
 537                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 538                 }
 539         }
 540
 541         while (!list_empty(&dep->pending_list)) {
 542                 req = next_request(&dep->pending_list);
 543
 544                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 545         }
 546 }
 547
 548 /**
 549  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 550  * @dep: the endpoint to disable
 551  *
 552  * This function also removes requests which are currently processed ny the
 553  * hardware and those which are not yet scheduled.
 554  * Caller should take care of locking.
 555  */
 556 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 557 {
 558         struct dwc3             *dwc = dep->dwc;
 559         u32                     reg;
 560
 561         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 562
 563         dwc3_remove_requests(dwc, dep);
 564
 565         /* make sure HW endpoint isn't stalled */
 566         if (dep->flags & DWC3_EP_STALL)
 567                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 568
 569         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 570         reg &= ~DWC3_DALEPENA_EP(dep->number);
 571         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 572
 573         dep->stream_capable = false;
 574         dep->endpoint.desc = NULL;
 575         dep->comp_desc = NULL;
 576         dep->type = 0;
 577         dep->flags = 0;
 578
 579         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 580                         dep->number >> 1,
 581                         (dep->number & 1) ? "in" : "out");
 582
 583         return 0;
 584 }
 585
 586 /* -------------------------------------------------------------------------- */
 587
 588 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 589                 const struct usb_endpoint_descriptor *desc)
 590 {
 591         return -EINVAL;
 592 }
 593
 594 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 595 {
 596         return -EINVAL;
 597 }
 598
 599 /* -------------------------------------------------------------------------- */
 600
 601 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 602                 const struct usb_endpoint_descriptor *desc)
 603 {
 604         struct dwc3_ep                  *dep;
 605         struct dwc3                     *dwc;
 606         unsigned long                   flags;
 607         int                             ret;
 608
 609         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 610                 pr_debug("dwc3: invalid parameters\n");
 611                 return -EINVAL;
 612         }
 613
 614         if (!desc->wMaxPacketSize) {
 615                 pr_debug("dwc3: missing wMaxPacketSize\n");
 616                 return -EINVAL;
 617         }
 618
 619         dep = to_dwc3_ep(ep);
 620         dwc = dep->dwc;
 621
 622         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 623                                         "%s is already enabled\n",
 624                                         dep->name))
 625                 return 0;
 626
 627         spin_lock_irqsave(&dwc->lock, flags);
 628         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 629         spin_unlock_irqrestore(&dwc->lock, flags);
 630
 631         return ret;
 632 }
 633
 634 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 635 {
 636         struct dwc3_ep                  *dep;
 637         struct dwc3                     *dwc;
 638         unsigned long                   flags;
 639         int                             ret;
 640
 641         if (!ep) {
 642                 pr_debug("dwc3: invalid parameters\n");
 643                 return -EINVAL;
 644         }
 645
 646         dep = to_dwc3_ep(ep);
 647         dwc = dep->dwc;
 648
 649         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 650                                         "%s is already disabled\n",
 651                                         dep->name))
 652                 return 0;
 653
 654         spin_lock_irqsave(&dwc->lock, flags);
 655         ret = __dwc3_gadget_ep_disable(dep);
 656         spin_unlock_irqrestore(&dwc->lock, flags);
 657
 658         return ret;
 659 }
 660
 661 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 662         gfp_t gfp_flags)
 663 {
 664         struct dwc3_request             *req;
 665         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 666
 667         req = kzalloc(sizeof(*req), gfp_flags);
 668         if (!req)
 669                 return NULL;
 670
 671         req->epnum      = dep->number;
 672         req->dep        = dep;
 673
 674         trace_dwc3_alloc_request(req);
 675
 676         return &req->request;
 677 }
 678
 679 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 680                 struct usb_request *request)
 681 {
 682         struct dwc3_request             *req = to_dwc3_request(request);
 683
 684         trace_dwc3_free_request(req);
 685         kfree(req);
 686 }
 687
 688 /**
 689  * dwc3_prepare_one_trb - setup one TRB from one request
 690  * @dep: endpoint for which this request is prepared
 691  * @req: dwc3_request pointer
 692  */
 693 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 694                 struct dwc3_request *req, dma_addr_t dma,
 695                 unsigned length, unsigned last, unsigned chain, unsigned node)
 696 {
 697         struct dwc3_trb         *trb;
 698
 699         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 700                         dep->name, req, (unsigned long long) dma,
 701                         length, last ? " last" : "",
 702                         chain ? " chain" : "");
 703
 704
 705         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 706
 707         if (!req->trb) {
 708                 dwc3_gadget_move_started_request(req);
 709                 req->trb = trb;
 710                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 711                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 712         }
 713
 714         dep->free_slot++;
 715         /* Skip the LINK-TRB on ISOC */
 716         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 717                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 718                 dep->free_slot++;
 719
 720         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 721         trb->bpl = lower_32_bits(dma);
 722         trb->bph = upper_32_bits(dma);
 723
 724         switch (usb_endpoint_type(dep->endpoint.desc)) {
 725         case USB_ENDPOINT_XFER_CONTROL:
 726                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 727                 break;
 728
 729         case USB_ENDPOINT_XFER_ISOC:
 730                 if (!node)
 731                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 732                 else
 733                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 734
 735                 /* always enable Interrupt on Missed ISOC */
 736                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 737                 break;
 738
 739         case USB_ENDPOINT_XFER_BULK:
 740         case USB_ENDPOINT_XFER_INT:
 741                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 742                 break;
 743         default:
 744                 /*
 745                  * This is only possible with faulty memory because we
 746                  * checked it already :)
 747                  */
 748                 BUG();
 749         }
 750
 751         /* always enable Continue on Short Packet */
 752         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 753
 754         if (!req->request.no_interrupt)
 755                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 756
 757         if (last)
 758                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 759
 760         if (chain)
 761                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 762
 763         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 764                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 765
 766         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 767
 768         trace_dwc3_prepare_trb(dep, trb);
 769 }
 770
 771 /*
 772  * dwc3_prepare_trbs - setup TRBs from requests
 773  * @dep: endpoint for which requests are being prepared
 774  * @starting: true if the endpoint is idle and no requests are queued.
 775  *
 776  * The function goes through the requests list and sets up TRBs for the
 777  * transfers. The function returns once there are no more TRBs available or
 778  * it runs out of requests.
 779  */
 780 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 781 {
 782         struct dwc3_request     *req, *n;
 783         u32                     trbs_left;
 784         u32                     max;
 785         unsigned int            last_one = 0;
 786
 787         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 788
 789         /* the first request must not be queued */
 790         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 791
 792         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 793         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 794                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 795                 if (trbs_left > max)
 796                         trbs_left = max;
 797         }
 798
 799         /*
 800          * If busy & slot are equal than it is either full or empty. If we are
 801          * starting to process requests then we are empty. Otherwise we are
 802          * full and don't do anything
 803          */
 804         if (!trbs_left) {
 805                 if (!starting)
 806                         return;
 807                 trbs_left = DWC3_TRB_NUM;
 808                 /*
 809                  * In case we start from scratch, we queue the ISOC requests
 810                  * starting from slot 1. This is done because we use ring
 811                  * buffer and have no LST bit to stop us. Instead, we place
 812                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 813                  * after the first request so we start at slot 1 and have
 814                  * 7 requests proceed before we hit the first IOC.
 815                  * Other transfer types don't use the ring buffer and are
 816                  * processed from the first TRB until the last one. Since we
 817                  * don't wrap around we have to start at the beginning.
 818                  */
 819                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 820                         dep->busy_slot = 1;
 821                         dep->free_slot = 1;
 822                 } else {
 823                         dep->busy_slot = 0;
 824                         dep->free_slot = 0;
 825                 }
 826         }
 827
 828         /* The last TRB is a link TRB, not used for xfer */
 829         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 830                 return;
 831
 832         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 833                 unsigned        length;
 834                 dma_addr_t      dma;
 835                 last_one = false;
 836
 837                 if (req->request.num_mapped_sgs > 0) {
 838                         struct usb_request *request = &req->request;
 839                         struct scatterlist *sg = request->sg;
 840                         struct scatterlist *s;
 841                         int             i;
 842
 843                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 844                                 unsigned chain = true;
 845
 846                                 length = sg_dma_len(s);
 847                                 dma = sg_dma_address(s);
 848
 849                                 if (i == (request->num_mapped_sgs - 1) ||
 850                                                 sg_is_last(s)) {
 851                                         if (list_empty(&dep->pending_list))
 852                                                 last_one = true;
 853                                         chain = false;
 854                                 }
 855
 856                                 trbs_left--;
 857                                 if (!trbs_left)
 858                                         last_one = true;
 859
 860                                 if (last_one)
 861                                         chain = false;
 862
 863                                 dwc3_prepare_one_trb(dep, req, dma, length,
 864                                                 last_one, chain, i);
 865
 866                                 if (last_one)
 867                                         break;
 868                         }
 869
 870                         if (last_one)
 871                                 break;
 872                 } else {
 873                         dma = req->request.dma;
 874                         length = req->request.length;
 875                         trbs_left--;
 876
 877                         if (!trbs_left)
 878                                 last_one = 1;
 879
 880                         /* Is this the last request? */
 881                         if (list_is_last(&req->list, &dep->pending_list))
 882                                 last_one = 1;
 883
 884                         dwc3_prepare_one_trb(dep, req, dma, length,
 885                                         last_one, false, 0);
 886
 887                         if (last_one)
 888                                 break;
 889                 }
 890         }
 891 }
 892
 893 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 894                 int start_new)
 895 {
 896         struct dwc3_gadget_ep_cmd_params params;
 897         struct dwc3_request             *req;
 898         struct dwc3                     *dwc = dep->dwc;
 899         int                             ret;
 900         u32                             cmd;
 901
 902         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 903                 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
 904                 return -EBUSY;
 905         }
 906
 907         /*
 908          * If we are getting here after a short-out-packet we don't enqueue any
 909          * new requests as we try to set the IOC bit only on the last request.
 910          */
 911         if (start_new) {
 912                 if (list_empty(&dep->started_list))
 913                         dwc3_prepare_trbs(dep, start_new);
 914
 915                 /* req points to the first request which will be sent */
 916                 req = next_request(&dep->started_list);
 917         } else {
 918                 dwc3_prepare_trbs(dep, start_new);
 919
 920                 /*
 921                  * req points to the first request where HWO changed from 0 to 1
 922                  */
 923                 req = next_request(&dep->started_list);
 924         }
 925         if (!req) {
 926                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 927                 return 0;
 928         }
 929
 930         memset(&params, 0, sizeof(params));
 931
 932         if (start_new) {
 933                 params.param0 = upper_32_bits(req->trb_dma);
 934                 params.param1 = lower_32_bits(req->trb_dma);
 935                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 936         } else {
 937                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 938         }
 939
 940         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 941         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 942         if (ret < 0) {
 943                 /*
 944                  * FIXME we need to iterate over the list of requests
 945                  * here and stop, unmap, free and del each of the linked
 946                  * requests instead of what we do now.
 947                  */
 948                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 949                                 req->direction);
 950                 list_del(&req->list);
 951                 return ret;
 952         }
 953
 954         dep->flags |= DWC3_EP_BUSY;
 955
 956         if (start_new) {
 957                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 958                                 dep->number);
 959                 WARN_ON_ONCE(!dep->resource_index);
 960         }
 961
 962         return 0;
 963 }
 964
 965 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
 966                 struct dwc3_ep *dep, u32 cur_uf)
 967 {
 968         u32 uf;
 969
 970         if (list_empty(&dep->pending_list)) {
 971                 dwc3_trace(trace_dwc3_gadget,
 972                                 "ISOC ep %s run out for requests",
 973                                 dep->name);
 974                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 975                 return;
 976         }
 977
 978         /* 4 micro frames in the future */
 979         uf = cur_uf + dep->interval * 4;
 980
 981         __dwc3_gadget_kick_transfer(dep, uf, 1);
 982 }
 983
 984 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
 985                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
 986 {
 987         u32 cur_uf, mask;
 988
 989         mask = ~(dep->interval - 1);
 990         cur_uf = event->parameters & mask;
 991
 992         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
 993 }
 994
 995 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 996 {
 997         struct dwc3             *dwc = dep->dwc;
 998         int                     ret;
 999
1000         if (!dep->endpoint.desc) {
1001                 dwc3_trace(trace_dwc3_gadget,
1002                                 "trying to queue request %p to disabled %s\n",
1003                                 &req->request, dep->endpoint.name);
1004                 return -ESHUTDOWN;
1005         }
1006
1007         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1008                                 &req->request, req->dep->name)) {
1009                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1010                                 &req->request, req->dep->name);
1011                 return -EINVAL;
1012         }
1013
1014         req->request.actual     = 0;
1015         req->request.status     = -EINPROGRESS;
1016         req->direction          = dep->direction;
1017         req->epnum              = dep->number;
1018
1019         trace_dwc3_ep_queue(req);
1020
1021         /*
1022          * We only add to our list of requests now and
1023          * start consuming the list once we get XferNotReady
1024          * IRQ.
1025          *
1026          * That way, we avoid doing anything that we don't need
1027          * to do now and defer it until the point we receive a
1028          * particular token from the Host side.
1029          *
1030          * This will also avoid Host cancelling URBs due to too
1031          * many NAKs.
1032          */
1033         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1034                         dep->direction);
1035         if (ret)
1036                 return ret;
1037
1038         list_add_tail(&req->list, &dep->pending_list);
1039
1040         /*
1041          * If there are no pending requests and the endpoint isn't already
1042          * busy, we will just start the request straight away.
1043          *
1044          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1045          * little bit faster.
1046          */
1047         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1048                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1049                         !(dep->flags & DWC3_EP_BUSY)) {
1050                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1051                 goto out;
1052         }
1053
1054         /*
1055          * There are a few special cases:
1056          *
1057          * 1. XferNotReady with empty list of requests. We need to kick the
1058          *    transfer here in that situation, otherwise we will be NAKing
1059          *    forever. If we get XferNotReady before gadget driver has a
1060          *    chance to queue a request, we will ACK the IRQ but won't be
1061          *    able to receive the data until the next request is queued.
1062          *    The following code is handling exactly that.
1063          *
1064          */
1065         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1066                 /*
1067                  * If xfernotready is already elapsed and it is a case
1068                  * of isoc transfer, then issue END TRANSFER, so that
1069                  * you can receive xfernotready again and can have
1070                  * notion of current microframe.
1071                  */
1072                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1073                         if (list_empty(&dep->started_list)) {
1074                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1075                                 dep->flags = DWC3_EP_ENABLED;
1076                         }
1077                         return 0;
1078                 }
1079
1080                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1081                 if (!ret)
1082                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1083
1084                 goto out;
1085         }
1086
1087         /*
1088          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1089          *    kick the transfer here after queuing a request, otherwise the
1090          *    core may not see the modified TRB(s).
1091          */
1092         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1093                         (dep->flags & DWC3_EP_BUSY) &&
1094                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1095                 WARN_ON_ONCE(!dep->resource_index);
1096                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1097                                 false);
1098                 goto out;
1099         }
1100
1101         /*
1102          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1103          * right away, otherwise host will not know we have streams to be
1104          * handled.
1105          */
1106         if (dep->stream_capable)
1107                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1108
1109 out:
1110         if (ret && ret != -EBUSY)
1111                 dwc3_trace(trace_dwc3_gadget,
1112                                 "%s: failed to kick transfers\n",
1113                                 dep->name);
1114         if (ret == -EBUSY)
1115                 ret = 0;
1116
1117         return ret;
1118 }
1119
1120 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1121                 struct usb_request *request)
1122 {
1123         dwc3_gadget_ep_free_request(ep, request);
1124 }
1125
1126 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1127 {
1128         struct dwc3_request             *req;
1129         struct usb_request              *request;
1130         struct usb_ep                   *ep = &dep->endpoint;
1131
1132         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1133         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1134         if (!request)
1135                 return -ENOMEM;
1136
1137         request->length = 0;
1138         request->buf = dwc->zlp_buf;
1139         request->complete = __dwc3_gadget_ep_zlp_complete;
1140
1141         req = to_dwc3_request(request);
1142
1143         return __dwc3_gadget_ep_queue(dep, req);
1144 }
1145
1146 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1147         gfp_t gfp_flags)
1148 {
1149         struct dwc3_request             *req = to_dwc3_request(request);
1150         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1151         struct dwc3                     *dwc = dep->dwc;
1152
1153         unsigned long                   flags;
1154
1155         int                             ret;
1156
1157         spin_lock_irqsave(&dwc->lock, flags);
1158         ret = __dwc3_gadget_ep_queue(dep, req);
1159
1160         /*
1161          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1162          * setting request->zero, instead of doing magic, we will just queue an
1163          * extra usb_request ourselves so that it gets handled the same way as
1164          * any other request.
1165          */
1166         if (ret == 0 && request->zero && request->length &&
1167             (request->length % ep->maxpacket == 0))
1168                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1169
1170         spin_unlock_irqrestore(&dwc->lock, flags);
1171
1172         return ret;
1173 }
1174
1175 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1176                 struct usb_request *request)
1177 {
1178         struct dwc3_request             *req = to_dwc3_request(request);
1179         struct dwc3_request             *r = NULL;
1180
1181         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1182         struct dwc3                     *dwc = dep->dwc;
1183
1184         unsigned long                   flags;
1185         int                             ret = 0;
1186
1187         trace_dwc3_ep_dequeue(req);
1188
1189         spin_lock_irqsave(&dwc->lock, flags);
1190
1191         list_for_each_entry(r, &dep->pending_list, list) {
1192                 if (r == req)
1193                         break;
1194         }
1195
1196         if (r != req) {
1197                 list_for_each_entry(r, &dep->started_list, list) {
1198                         if (r == req)
1199                                 break;
1200                 }
1201                 if (r == req) {
1202                         /* wait until it is processed */
1203                         dwc3_stop_active_transfer(dwc, dep->number, true);
1204                         goto out1;
1205                 }
1206                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1207                                 request, ep->name);
1208                 ret = -EINVAL;
1209                 goto out0;
1210         }
1211
1212 out1:
1213         /* giveback the request */
1214         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1215
1216 out0:
1217         spin_unlock_irqrestore(&dwc->lock, flags);
1218
1219         return ret;
1220 }
1221
1222 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1223 {
1224         struct dwc3_gadget_ep_cmd_params        params;
1225         struct dwc3                             *dwc = dep->dwc;
1226         int                                     ret;
1227
1228         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1229                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1230                 return -EINVAL;
1231         }
1232
1233         memset(&params, 0x00, sizeof(params));
1234
1235         if (value) {
1236                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1237                                 (!list_empty(&dep->started_list) ||
1238                                  !list_empty(&dep->pending_list)))) {
1239                         dwc3_trace(trace_dwc3_gadget,
1240                                         "%s: pending request, cannot halt\n",
1241                                         dep->name);
1242                         return -EAGAIN;
1243                 }
1244
1245                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1246                         DWC3_DEPCMD_SETSTALL, &params);
1247                 if (ret)
1248                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1249                                         dep->name);
1250                 else
1251                         dep->flags |= DWC3_EP_STALL;
1252         } else {
1253                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1254                         DWC3_DEPCMD_CLEARSTALL, &params);
1255                 if (ret)
1256                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1257                                         dep->name);
1258                 else
1259                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1260         }
1261
1262         return ret;
1263 }
1264
1265 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1266 {
1267         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1268         struct dwc3                     *dwc = dep->dwc;
1269
1270         unsigned long                   flags;
1271
1272         int                             ret;
1273
1274         spin_lock_irqsave(&dwc->lock, flags);
1275         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1276         spin_unlock_irqrestore(&dwc->lock, flags);
1277
1278         return ret;
1279 }
1280
1281 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1282 {
1283         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1284         struct dwc3                     *dwc = dep->dwc;
1285         unsigned long                   flags;
1286         int                             ret;
1287
1288         spin_lock_irqsave(&dwc->lock, flags);
1289         dep->flags |= DWC3_EP_WEDGE;
1290
1291         if (dep->number == 0 || dep->number == 1)
1292                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1293         else
1294                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1295         spin_unlock_irqrestore(&dwc->lock, flags);
1296
1297         return ret;
1298 }
1299
1300 /* -------------------------------------------------------------------------- */
1301
1302 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1303         .bLength        = USB_DT_ENDPOINT_SIZE,
1304         .bDescriptorType = USB_DT_ENDPOINT,
1305         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1306 };
1307
1308 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1309         .enable         = dwc3_gadget_ep0_enable,
1310         .disable        = dwc3_gadget_ep0_disable,
1311         .alloc_request  = dwc3_gadget_ep_alloc_request,
1312         .free_request   = dwc3_gadget_ep_free_request,
1313         .queue          = dwc3_gadget_ep0_queue,
1314         .dequeue        = dwc3_gadget_ep_dequeue,
1315         .set_halt       = dwc3_gadget_ep0_set_halt,
1316         .set_wedge      = dwc3_gadget_ep_set_wedge,
1317 };
1318
1319 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1320         .enable         = dwc3_gadget_ep_enable,
1321         .disable        = dwc3_gadget_ep_disable,
1322         .alloc_request  = dwc3_gadget_ep_alloc_request,
1323         .free_request   = dwc3_gadget_ep_free_request,
1324         .queue          = dwc3_gadget_ep_queue,
1325         .dequeue        = dwc3_gadget_ep_dequeue,
1326         .set_halt       = dwc3_gadget_ep_set_halt,
1327         .set_wedge      = dwc3_gadget_ep_set_wedge,
1328 };
1329
1330 /* -------------------------------------------------------------------------- */
1331
1332 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1333 {
1334         struct dwc3             *dwc = gadget_to_dwc(g);
1335         u32                     reg;
1336
1337         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1338         return DWC3_DSTS_SOFFN(reg);
1339 }
1340
1341 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1342 {
1343         struct dwc3             *dwc = gadget_to_dwc(g);
1344
1345         unsigned long           timeout;
1346         unsigned long           flags;
1347
1348         u32                     reg;
1349
1350         int                     ret = 0;
1351
1352         u8                      link_state;
1353         u8                      speed;
1354
1355         spin_lock_irqsave(&dwc->lock, flags);
1356
1357         /*
1358          * According to the Databook Remote wakeup request should
1359          * be issued only when the device is in early suspend state.
1360          *
1361          * We can check that via USB Link State bits in DSTS register.
1362          */
1363         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1364
1365         speed = reg & DWC3_DSTS_CONNECTSPD;
1366         if ((speed == DWC3_DSTS_SUPERSPEED) ||
1367             (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1368                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1369                 ret = -EINVAL;
1370                 goto out;
1371         }
1372
1373         link_state = DWC3_DSTS_USBLNKST(reg);
1374
1375         switch (link_state) {
1376         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1377         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1378                 break;
1379         default:
1380                 dwc3_trace(trace_dwc3_gadget,
1381                                 "can't wakeup from '%s'\n",
1382                                 dwc3_gadget_link_string(link_state));
1383                 ret = -EINVAL;
1384                 goto out;
1385         }
1386
1387         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1388         if (ret < 0) {
1389                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1390                 goto out;
1391         }
1392
1393         /* Recent versions do this automatically */
1394         if (dwc->revision < DWC3_REVISION_194A) {
1395                 /* write zeroes to Link Change Request */
1396                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1397                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1398                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1399         }
1400
1401         /* poll until Link State changes to ON */
1402         timeout = jiffies + msecs_to_jiffies(100);
1403
1404         while (!time_after(jiffies, timeout)) {
1405                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1406
1407                 /* in HS, means ON */
1408                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1409                         break;
1410         }
1411
1412         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1413                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1414                 ret = -EINVAL;
1415         }
1416
1417 out:
1418         spin_unlock_irqrestore(&dwc->lock, flags);
1419
1420         return ret;
1421 }
1422
1423 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1424                 int is_selfpowered)
1425 {
1426         struct dwc3             *dwc = gadget_to_dwc(g);
1427         unsigned long           flags;
1428
1429         spin_lock_irqsave(&dwc->lock, flags);
1430         g->is_selfpowered = !!is_selfpowered;
1431         spin_unlock_irqrestore(&dwc->lock, flags);
1432
1433         return 0;
1434 }
1435
1436 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1437 {
1438         u32                     reg;
1439         u32                     timeout = 500;
1440
1441         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1442         if (is_on) {
1443                 if (dwc->revision <= DWC3_REVISION_187A) {
1444                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1445                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1446                 }
1447
1448                 if (dwc->revision >= DWC3_REVISION_194A)
1449                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1450                 reg |= DWC3_DCTL_RUN_STOP;
1451
1452                 if (dwc->has_hibernation)
1453                         reg |= DWC3_DCTL_KEEP_CONNECT;
1454
1455                 dwc->pullups_connected = true;
1456         } else {
1457                 reg &= ~DWC3_DCTL_RUN_STOP;
1458
1459                 if (dwc->has_hibernation && !suspend)
1460                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1461
1462                 dwc->pullups_connected = false;
1463         }
1464
1465         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1466
1467         do {
1468                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1469                 if (is_on) {
1470                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1471                                 break;
1472                 } else {
1473                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1474                                 break;
1475                 }
1476                 timeout--;
1477                 if (!timeout)
1478                         return -ETIMEDOUT;
1479                 udelay(1);
1480         } while (1);
1481
1482         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1483                         dwc->gadget_driver
1484                         ? dwc->gadget_driver->function : "no-function",
1485                         is_on ? "connect" : "disconnect");
1486
1487         return 0;
1488 }
1489
1490 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1491 {
1492         struct dwc3             *dwc = gadget_to_dwc(g);
1493         unsigned long           flags;
1494         int                     ret;
1495
1496         is_on = !!is_on;
1497
1498         spin_lock_irqsave(&dwc->lock, flags);
1499         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1500         spin_unlock_irqrestore(&dwc->lock, flags);
1501
1502         return ret;
1503 }
1504
1505 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1506 {
1507         u32                     reg;
1508
1509         /* Enable all but Start and End of Frame IRQs */
1510         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1511                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1512                         DWC3_DEVTEN_CMDCMPLTEN |
1513                         DWC3_DEVTEN_ERRTICERREN |
1514                         DWC3_DEVTEN_WKUPEVTEN |
1515                         DWC3_DEVTEN_ULSTCNGEN |
1516                         DWC3_DEVTEN_CONNECTDONEEN |
1517                         DWC3_DEVTEN_USBRSTEN |
1518                         DWC3_DEVTEN_DISCONNEVTEN);
1519
1520         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1521 }
1522
1523 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1524 {
1525         /* mask all interrupts */
1526         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1527 }
1528
1529 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1530 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1531
1532 static int dwc3_gadget_start(struct usb_gadget *g,
1533                 struct usb_gadget_driver *driver)
1534 {
1535         struct dwc3             *dwc = gadget_to_dwc(g);
1536         struct dwc3_ep          *dep;
1537         unsigned long           flags;
1538         int                     ret = 0;
1539         int                     irq;
1540         u32                     reg;
1541
1542         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1543         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1544                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1545         if (ret) {
1546                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1547                                 irq, ret);
1548                 goto err0;
1549         }
1550
1551         spin_lock_irqsave(&dwc->lock, flags);
1552
1553         if (dwc->gadget_driver) {
1554                 dev_err(dwc->dev, "%s is already bound to %s\n",
1555                                 dwc->gadget.name,
1556                                 dwc->gadget_driver->driver.name);
1557                 ret = -EBUSY;
1558                 goto err1;
1559         }
1560
1561         dwc->gadget_driver      = driver;
1562
1563         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1564         reg &= ~(DWC3_DCFG_SPEED_MASK);
1565
1566         /**
1567          * WORKAROUND: DWC3 revision < 2.20a have an issue
1568          * which would cause metastability state on Run/Stop
1569          * bit if we try to force the IP to USB2-only mode.
1570          *
1571          * Because of that, we cannot configure the IP to any
1572          * speed other than the SuperSpeed
1573          *
1574          * Refers to:
1575          *
1576          * STAR#9000525659: Clock Domain Crossing on DCTL in
1577          * USB 2.0 Mode
1578          */
1579         if (dwc->revision < DWC3_REVISION_220A) {
1580                 reg |= DWC3_DCFG_SUPERSPEED;
1581         } else {
1582                 switch (dwc->maximum_speed) {
1583                 case USB_SPEED_LOW:
1584                         reg |= DWC3_DSTS_LOWSPEED;
1585                         break;
1586                 case USB_SPEED_FULL:
1587                         reg |= DWC3_DSTS_FULLSPEED1;
1588                         break;
1589                 case USB_SPEED_HIGH:
1590                         reg |= DWC3_DSTS_HIGHSPEED;
1591                         break;
1592                 case USB_SPEED_SUPER_PLUS:
1593                         reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1594                         break;
1595                 default:
1596                         dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1597                                 dwc->maximum_speed);
1598                         /* fall through */
1599                 case USB_SPEED_SUPER:
1600                         reg |= DWC3_DCFG_SUPERSPEED;
1601                         break;
1602                 }
1603         }
1604         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1605
1606         /* Start with SuperSpeed Default */
1607         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1608
1609         dep = dwc->eps[0];
1610         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1611                         false);
1612         if (ret) {
1613                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1614                 goto err2;
1615         }
1616
1617         dep = dwc->eps[1];
1618         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1619                         false);
1620         if (ret) {
1621                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1622                 goto err3;
1623         }
1624
1625         /* begin to receive SETUP packets */
1626         dwc->ep0state = EP0_SETUP_PHASE;
1627         dwc3_ep0_out_start(dwc);
1628
1629         dwc3_gadget_enable_irq(dwc);
1630
1631         spin_unlock_irqrestore(&dwc->lock, flags);
1632
1633         return 0;
1634
1635 err3:
1636         __dwc3_gadget_ep_disable(dwc->eps[0]);
1637
1638 err2:
1639         dwc->gadget_driver = NULL;
1640
1641 err1:
1642         spin_unlock_irqrestore(&dwc->lock, flags);
1643
1644         free_irq(irq, dwc->ev_buf);
1645
1646 err0:
1647         return ret;
1648 }
1649
1650 static int dwc3_gadget_stop(struct usb_gadget *g)
1651 {
1652         struct dwc3             *dwc = gadget_to_dwc(g);
1653         unsigned long           flags;
1654         int                     irq;
1655
1656         spin_lock_irqsave(&dwc->lock, flags);
1657
1658         dwc3_gadget_disable_irq(dwc);
1659         __dwc3_gadget_ep_disable(dwc->eps[0]);
1660         __dwc3_gadget_ep_disable(dwc->eps[1]);
1661
1662         dwc->gadget_driver      = NULL;
1663
1664         spin_unlock_irqrestore(&dwc->lock, flags);
1665
1666         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1667         free_irq(irq, dwc->ev_buf);
1668
1669         return 0;
1670 }
1671
1672 static const struct usb_gadget_ops dwc3_gadget_ops = {
1673         .get_frame              = dwc3_gadget_get_frame,
1674         .wakeup                 = dwc3_gadget_wakeup,
1675         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1676         .pullup                 = dwc3_gadget_pullup,
1677         .udc_start              = dwc3_gadget_start,
1678         .udc_stop               = dwc3_gadget_stop,
1679 };
1680
1681 /* -------------------------------------------------------------------------- */
1682
1683 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1684                 u8 num, u32 direction)
1685 {
1686         struct dwc3_ep                  *dep;
1687         u8                              i;
1688
1689         for (i = 0; i < num; i++) {
1690                 u8 epnum = (i << 1) | (!!direction);
1691
1692                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1693                 if (!dep)
1694                         return -ENOMEM;
1695
1696                 dep->dwc = dwc;
1697                 dep->number = epnum;
1698                 dep->direction = !!direction;
1699                 dwc->eps[epnum] = dep;
1700
1701                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1702                                 (epnum & 1) ? "in" : "out");
1703
1704                 dep->endpoint.name = dep->name;
1705
1706                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1707
1708                 if (epnum == 0 || epnum == 1) {
1709                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1710                         dep->endpoint.maxburst = 1;
1711                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1712                         if (!epnum)
1713                                 dwc->gadget.ep0 = &dep->endpoint;
1714                 } else {
1715                         int             ret;
1716
1717                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1718                         dep->endpoint.max_streams = 15;
1719                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1720                         list_add_tail(&dep->endpoint.ep_list,
1721                                         &dwc->gadget.ep_list);
1722
1723                         ret = dwc3_alloc_trb_pool(dep);
1724                         if (ret)
1725                                 return ret;
1726                 }
1727
1728                 if (epnum == 0 || epnum == 1) {
1729                         dep->endpoint.caps.type_control = true;
1730                 } else {
1731                         dep->endpoint.caps.type_iso = true;
1732                         dep->endpoint.caps.type_bulk = true;
1733                         dep->endpoint.caps.type_int = true;
1734                 }
1735
1736                 dep->endpoint.caps.dir_in = !!direction;
1737                 dep->endpoint.caps.dir_out = !direction;
1738
1739                 INIT_LIST_HEAD(&dep->pending_list);
1740                 INIT_LIST_HEAD(&dep->started_list);
1741         }
1742
1743         return 0;
1744 }
1745
1746 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1747 {
1748         int                             ret;
1749
1750         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1751
1752         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1753         if (ret < 0) {
1754                 dwc3_trace(trace_dwc3_gadget,
1755                                 "failed to allocate OUT endpoints");
1756                 return ret;
1757         }
1758
1759         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1760         if (ret < 0) {
1761                 dwc3_trace(trace_dwc3_gadget,
1762                                 "failed to allocate IN endpoints");
1763                 return ret;
1764         }
1765
1766         return 0;
1767 }
1768
1769 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1770 {
1771         struct dwc3_ep                  *dep;
1772         u8                              epnum;
1773
1774         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1775                 dep = dwc->eps[epnum];
1776                 if (!dep)
1777                         continue;
1778                 /*
1779                  * Physical endpoints 0 and 1 are special; they form the
1780                  * bi-directional USB endpoint 0.
1781                  *
1782                  * For those two physical endpoints, we don't allocate a TRB
1783                  * pool nor do we add them the endpoints list. Due to that, we
1784                  * shouldn't do these two operations otherwise we would end up
1785                  * with all sorts of bugs when removing dwc3.ko.
1786                  */
1787                 if (epnum != 0 && epnum != 1) {
1788                         dwc3_free_trb_pool(dep);
1789                         list_del(&dep->endpoint.ep_list);
1790                 }
1791
1792                 kfree(dep);
1793         }
1794 }
1795
1796 /* -------------------------------------------------------------------------- */
1797
1798 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1799                 struct dwc3_request *req, struct dwc3_trb *trb,
1800                 const struct dwc3_event_depevt *event, int status)
1801 {
1802         unsigned int            count;
1803         unsigned int            s_pkt = 0;
1804         unsigned int            trb_status;
1805
1806         trace_dwc3_complete_trb(dep, trb);
1807
1808         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1809                 /*
1810                  * We continue despite the error. There is not much we
1811                  * can do. If we don't clean it up we loop forever. If
1812                  * we skip the TRB then it gets overwritten after a
1813                  * while since we use them in a ring buffer. A BUG()
1814                  * would help. Lets hope that if this occurs, someone
1815                  * fixes the root cause instead of looking away :)
1816                  */
1817                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1818                                 dep->name, trb);
1819         count = trb->size & DWC3_TRB_SIZE_MASK;
1820
1821         if (dep->direction) {
1822                 if (count) {
1823                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1824                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1825                                 dwc3_trace(trace_dwc3_gadget,
1826                                                 "%s: incomplete IN transfer\n",
1827                                                 dep->name);
1828                                 /*
1829                                  * If missed isoc occurred and there is
1830                                  * no request queued then issue END
1831                                  * TRANSFER, so that core generates
1832                                  * next xfernotready and we will issue
1833                                  * a fresh START TRANSFER.
1834                                  * If there are still queued request
1835                                  * then wait, do not issue either END
1836                                  * or UPDATE TRANSFER, just attach next
1837                                  * request in pending_list during
1838                                  * giveback.If any future queued request
1839                                  * is successfully transferred then we
1840                                  * will issue UPDATE TRANSFER for all
1841                                  * request in the pending_list.
1842                                  */
1843                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1844                         } else {
1845                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1846                                                 dep->name);
1847                                 status = -ECONNRESET;
1848                         }
1849                 } else {
1850                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1851                 }
1852         } else {
1853                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1854                         s_pkt = 1;
1855         }
1856
1857         /*
1858          * We assume here we will always receive the entire data block
1859          * which we should receive. Meaning, if we program RX to
1860          * receive 4K but we receive only 2K, we assume that's all we
1861          * should receive and we simply bounce the request back to the
1862          * gadget driver for further processing.
1863          */
1864         req->request.actual += req->request.length - count;
1865         if (s_pkt)
1866                 return 1;
1867         if ((event->status & DEPEVT_STATUS_LST) &&
1868                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1869                                 DWC3_TRB_CTRL_HWO)))
1870                 return 1;
1871         if ((event->status & DEPEVT_STATUS_IOC) &&
1872                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1873                 return 1;
1874         return 0;
1875 }
1876
1877 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1878                 const struct dwc3_event_depevt *event, int status)
1879 {
1880         struct dwc3_request     *req;
1881         struct dwc3_trb         *trb;
1882         unsigned int            slot;
1883         unsigned int            i;
1884         int                     ret;
1885
1886         do {
1887                 req = next_request(&dep->started_list);
1888                 if (WARN_ON_ONCE(!req))
1889                         return 1;
1890
1891                 i = 0;
1892                 do {
1893                         slot = req->start_slot + i;
1894                         if ((slot == DWC3_TRB_NUM - 1) &&
1895                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1896                                 slot++;
1897                         slot %= DWC3_TRB_NUM;
1898                         trb = &dep->trb_pool[slot];
1899
1900                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1901                                         event, status);
1902                         if (ret)
1903                                 break;
1904                 } while (++i < req->request.num_mapped_sgs);
1905
1906                 dwc3_gadget_giveback(dep, req, status);
1907
1908                 if (ret)
1909                         break;
1910         } while (1);
1911
1912         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1913                         list_empty(&dep->started_list)) {
1914                 if (list_empty(&dep->pending_list)) {
1915                         /*
1916                          * If there is no entry in request list then do
1917                          * not issue END TRANSFER now. Just set PENDING
1918                          * flag, so that END TRANSFER is issued when an
1919                          * entry is added into request list.
1920                          */
1921                         dep->flags = DWC3_EP_PENDING_REQUEST;
1922                 } else {
1923                         dwc3_stop_active_transfer(dwc, dep->number, true);
1924                         dep->flags = DWC3_EP_ENABLED;
1925                 }
1926                 return 1;
1927         }
1928
1929         return 1;
1930 }
1931
1932 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1933                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1934 {
1935         unsigned                status = 0;
1936         int                     clean_busy;
1937         u32                     is_xfer_complete;
1938
1939         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
1940
1941         if (event->status & DEPEVT_STATUS_BUSERR)
1942                 status = -ECONNRESET;
1943
1944         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1945         if (clean_busy && (is_xfer_complete ||
1946                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
1947                 dep->flags &= ~DWC3_EP_BUSY;
1948
1949         /*
1950          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1951          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1952          */
1953         if (dwc->revision < DWC3_REVISION_183A) {
1954                 u32             reg;
1955                 int             i;
1956
1957                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1958                         dep = dwc->eps[i];
1959
1960                         if (!(dep->flags & DWC3_EP_ENABLED))
1961                                 continue;
1962
1963                         if (!list_empty(&dep->started_list))
1964                                 return;
1965                 }
1966
1967                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1968                 reg |= dwc->u1u2;
1969                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1970
1971                 dwc->u1u2 = 0;
1972         }
1973
1974         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1975                 int ret;
1976
1977                 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
1978                 if (!ret || ret == -EBUSY)
1979                         return;
1980         }
1981 }
1982
1983 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1984                 const struct dwc3_event_depevt *event)
1985 {
1986         struct dwc3_ep          *dep;
1987         u8                      epnum = event->endpoint_number;
1988
1989         dep = dwc->eps[epnum];
1990
1991         if (!(dep->flags & DWC3_EP_ENABLED))
1992                 return;
1993
1994         if (epnum == 0 || epnum == 1) {
1995                 dwc3_ep0_interrupt(dwc, event);
1996                 return;
1997         }
1998
1999         switch (event->endpoint_event) {
2000         case DWC3_DEPEVT_XFERCOMPLETE:
2001                 dep->resource_index = 0;
2002
2003                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2004                         dwc3_trace(trace_dwc3_gadget,
2005                                         "%s is an Isochronous endpoint\n",
2006                                         dep->name);
2007                         return;
2008                 }
2009
2010                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2011                 break;
2012         case DWC3_DEPEVT_XFERINPROGRESS:
2013                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2014                 break;
2015         case DWC3_DEPEVT_XFERNOTREADY:
2016                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2017                         dwc3_gadget_start_isoc(dwc, dep, event);
2018                 } else {
2019                         int active;
2020                         int ret;
2021
2022                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2023
2024                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2025                                         dep->name, active ? "Transfer Active"
2026                                         : "Transfer Not Active");
2027
2028                         ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2029                         if (!ret || ret == -EBUSY)
2030                                 return;
2031
2032                         dwc3_trace(trace_dwc3_gadget,
2033                                         "%s: failed to kick transfers\n",
2034                                         dep->name);
2035                 }
2036
2037                 break;
2038         case DWC3_DEPEVT_STREAMEVT:
2039                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2040                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2041                                         dep->name);
2042                         return;
2043                 }
2044
2045                 switch (event->status) {
2046                 case DEPEVT_STREAMEVT_FOUND:
2047                         dwc3_trace(trace_dwc3_gadget,
2048                                         "Stream %d found and started",
2049                                         event->parameters);
2050
2051                         break;
2052                 case DEPEVT_STREAMEVT_NOTFOUND:
2053                         /* FALLTHROUGH */
2054                 default:
2055                         dwc3_trace(trace_dwc3_gadget,
2056                                         "unable to find suitable stream\n");
2057                 }
2058                 break;
2059         case DWC3_DEPEVT_RXTXFIFOEVT:
2060                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2061                 break;
2062         case DWC3_DEPEVT_EPCMDCMPLT:
2063                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2064                 break;
2065         }
2066 }
2067
2068 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2069 {
2070         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2071                 spin_unlock(&dwc->lock);
2072                 dwc->gadget_driver->disconnect(&dwc->gadget);
2073                 spin_lock(&dwc->lock);
2074         }
2075 }
2076
2077 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2078 {
2079         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2080                 spin_unlock(&dwc->lock);
2081                 dwc->gadget_driver->suspend(&dwc->gadget);
2082                 spin_lock(&dwc->lock);
2083         }
2084 }
2085
2086 static void dwc3_resume_gadget(struct dwc3 *dwc)
2087 {
2088         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2089                 spin_unlock(&dwc->lock);
2090                 dwc->gadget_driver->resume(&dwc->gadget);
2091                 spin_lock(&dwc->lock);
2092         }
2093 }
2094
2095 static void dwc3_reset_gadget(struct dwc3 *dwc)
2096 {
2097         if (!dwc->gadget_driver)
2098                 return;
2099
2100         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2101                 spin_unlock(&dwc->lock);
2102                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2103                 spin_lock(&dwc->lock);
2104         }
2105 }
2106
2107 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2108 {
2109         struct dwc3_ep *dep;
2110         struct dwc3_gadget_ep_cmd_params params;
2111         u32 cmd;
2112         int ret;
2113
2114         dep = dwc->eps[epnum];
2115
2116         if (!dep->resource_index)
2117                 return;
2118
2119         /*
2120          * NOTICE: We are violating what the Databook says about the
2121          * EndTransfer command. Ideally we would _always_ wait for the
2122          * EndTransfer Command Completion IRQ, but that's causing too
2123          * much trouble synchronizing between us and gadget driver.
2124          *
2125          * We have discussed this with the IP Provider and it was
2126          * suggested to giveback all requests here, but give HW some
2127          * extra time to synchronize with the interconnect. We're using
2128          * an arbitrary 100us delay for that.
2129          *
2130          * Note also that a similar handling was tested by Synopsys
2131          * (thanks a lot Paul) and nothing bad has come out of it.
2132          * In short, what we're doing is:
2133          *
2134          * - Issue EndTransfer WITH CMDIOC bit set
2135          * - Wait 100us
2136          */
2137
2138         cmd = DWC3_DEPCMD_ENDTRANSFER;
2139         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2140         cmd |= DWC3_DEPCMD_CMDIOC;
2141         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2142         memset(&params, 0, sizeof(params));
2143         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2144         WARN_ON_ONCE(ret);
2145         dep->resource_index = 0;
2146         dep->flags &= ~DWC3_EP_BUSY;
2147         udelay(100);
2148 }
2149
2150 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2151 {
2152         u32 epnum;
2153
2154         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2155                 struct dwc3_ep *dep;
2156
2157                 dep = dwc->eps[epnum];
2158                 if (!dep)
2159                         continue;
2160
2161                 if (!(dep->flags & DWC3_EP_ENABLED))
2162                         continue;
2163
2164                 dwc3_remove_requests(dwc, dep);
2165         }
2166 }
2167
2168 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2169 {
2170         u32 epnum;
2171
2172         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2173                 struct dwc3_ep *dep;
2174                 struct dwc3_gadget_ep_cmd_params params;
2175                 int ret;
2176
2177                 dep = dwc->eps[epnum];
2178                 if (!dep)
2179                         continue;
2180
2181                 if (!(dep->flags & DWC3_EP_STALL))
2182                         continue;
2183
2184                 dep->flags &= ~DWC3_EP_STALL;
2185
2186                 memset(&params, 0, sizeof(params));
2187                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2188                                 DWC3_DEPCMD_CLEARSTALL, &params);
2189                 WARN_ON_ONCE(ret);
2190         }
2191 }
2192
2193 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2194 {
2195         int                     reg;
2196
2197         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2198         reg &= ~DWC3_DCTL_INITU1ENA;
2199         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2200
2201         reg &= ~DWC3_DCTL_INITU2ENA;
2202         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2203
2204         dwc3_disconnect_gadget(dwc);
2205
2206         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2207         dwc->setup_packet_pending = false;
2208         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2209 }
2210
2211 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2212 {
2213         u32                     reg;
2214
2215         /*
2216          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2217          * would cause a missing Disconnect Event if there's a
2218          * pending Setup Packet in the FIFO.
2219          *
2220          * There's no suggested workaround on the official Bug
2221          * report, which states that "unless the driver/application
2222          * is doing any special handling of a disconnect event,
2223          * there is no functional issue".
2224          *
2225          * Unfortunately, it turns out that we _do_ some special
2226          * handling of a disconnect event, namely complete all
2227          * pending transfers, notify gadget driver of the
2228          * disconnection, and so on.
2229          *
2230          * Our suggested workaround is to follow the Disconnect
2231          * Event steps here, instead, based on a setup_packet_pending
2232          * flag. Such flag gets set whenever we have a SETUP_PENDING
2233          * status for EP0 TRBs and gets cleared on XferComplete for the
2234          * same endpoint.
2235          *
2236          * Refers to:
2237          *
2238          * STAR#9000466709: RTL: Device : Disconnect event not
2239          * generated if setup packet pending in FIFO
2240          */
2241         if (dwc->revision < DWC3_REVISION_188A) {
2242                 if (dwc->setup_packet_pending)
2243                         dwc3_gadget_disconnect_interrupt(dwc);
2244         }
2245
2246         dwc3_reset_gadget(dwc);
2247
2248         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2249         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2250         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2251         dwc->test_mode = false;
2252
2253         dwc3_stop_active_transfers(dwc);
2254         dwc3_clear_stall_all_ep(dwc);
2255
2256         /* Reset device address to zero */
2257         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2258         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2259         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2260 }
2261
2262 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2263 {
2264         u32 reg;
2265         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2266
2267         /*
2268          * We change the clock only at SS but I dunno why I would want to do
2269          * this. Maybe it becomes part of the power saving plan.
2270          */
2271
2272         if ((speed != DWC3_DSTS_SUPERSPEED) &&
2273             (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2274                 return;
2275
2276         /*
2277          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2278          * each time on Connect Done.
2279          */
2280         if (!usb30_clock)
2281                 return;
2282
2283         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2284         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2285         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2286 }
2287
2288 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2289 {
2290         struct dwc3_ep          *dep;
2291         int                     ret;
2292         u32                     reg;
2293         u8                      speed;
2294
2295         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2296         speed = reg & DWC3_DSTS_CONNECTSPD;
2297         dwc->speed = speed;
2298
2299         dwc3_update_ram_clk_sel(dwc, speed);
2300
2301         switch (speed) {
2302         case DWC3_DCFG_SUPERSPEED_PLUS:
2303                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2304                 dwc->gadget.ep0->maxpacket = 512;
2305                 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2306                 break;
2307         case DWC3_DCFG_SUPERSPEED:
2308                 /*
2309                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2310                  * would cause a missing USB3 Reset event.
2311                  *
2312                  * In such situations, we should force a USB3 Reset
2313                  * event by calling our dwc3_gadget_reset_interrupt()
2314                  * routine.
2315                  *
2316                  * Refers to:
2317                  *
2318                  * STAR#9000483510: RTL: SS : USB3 reset event may
2319                  * not be generated always when the link enters poll
2320                  */
2321                 if (dwc->revision < DWC3_REVISION_190A)
2322                         dwc3_gadget_reset_interrupt(dwc);
2323
2324                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2325                 dwc->gadget.ep0->maxpacket = 512;
2326                 dwc->gadget.speed = USB_SPEED_SUPER;
2327                 break;
2328         case DWC3_DCFG_HIGHSPEED:
2329                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2330                 dwc->gadget.ep0->maxpacket = 64;
2331                 dwc->gadget.speed = USB_SPEED_HIGH;
2332                 break;
2333         case DWC3_DCFG_FULLSPEED2:
2334         case DWC3_DCFG_FULLSPEED1:
2335                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2336                 dwc->gadget.ep0->maxpacket = 64;
2337                 dwc->gadget.speed = USB_SPEED_FULL;
2338                 break;
2339         case DWC3_DCFG_LOWSPEED:
2340                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2341                 dwc->gadget.ep0->maxpacket = 8;
2342                 dwc->gadget.speed = USB_SPEED_LOW;
2343                 break;
2344         }
2345
2346         /* Enable USB2 LPM Capability */
2347
2348         if ((dwc->revision > DWC3_REVISION_194A) &&
2349             (speed != DWC3_DCFG_SUPERSPEED) &&
2350             (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2351                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2352                 reg |= DWC3_DCFG_LPM_CAP;
2353                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2354
2355                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2356                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2357
2358                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2359
2360                 /*
2361                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2362                  * DCFG.LPMCap is set, core responses with an ACK and the
2363                  * BESL value in the LPM token is less than or equal to LPM
2364                  * NYET threshold.
2365                  */
2366                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2367                                 && dwc->has_lpm_erratum,
2368                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2369
2370                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2371                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2372
2373                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2374         } else {
2375                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2376                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2377                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2378         }
2379
2380         dep = dwc->eps[0];
2381         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2382                         false);
2383         if (ret) {
2384                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2385                 return;
2386         }
2387
2388         dep = dwc->eps[1];
2389         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2390                         false);
2391         if (ret) {
2392                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2393                 return;
2394         }
2395
2396         /*
2397          * Configure PHY via GUSB3PIPECTLn if required.
2398          *
2399          * Update GTXFIFOSIZn
2400          *
2401          * In both cases reset values should be sufficient.
2402          */
2403 }
2404
2405 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2406 {
2407         /*
2408          * TODO take core out of low power mode when that's
2409          * implemented.
2410          */
2411
2412         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2413                 spin_unlock(&dwc->lock);
2414                 dwc->gadget_driver->resume(&dwc->gadget);
2415                 spin_lock(&dwc->lock);
2416         }
2417 }
2418
2419 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2420                 unsigned int evtinfo)
2421 {
2422         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2423         unsigned int            pwropt;
2424
2425         /*
2426          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2427          * Hibernation mode enabled which would show up when device detects
2428          * host-initiated U3 exit.
2429          *
2430          * In that case, device will generate a Link State Change Interrupt
2431          * from U3 to RESUME which is only necessary if Hibernation is
2432          * configured in.
2433          *
2434          * There are no functional changes due to such spurious event and we
2435          * just need to ignore it.
2436          *
2437          * Refers to:
2438          *
2439          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2440          * operational mode
2441          */
2442         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2443         if ((dwc->revision < DWC3_REVISION_250A) &&
2444                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2445                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2446                                 (next == DWC3_LINK_STATE_RESUME)) {
2447                         dwc3_trace(trace_dwc3_gadget,
2448                                         "ignoring transition U3 -> Resume");
2449                         return;
2450                 }
2451         }
2452
2453         /*
2454          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2455          * on the link partner, the USB session might do multiple entry/exit
2456          * of low power states before a transfer takes place.
2457          *
2458          * Due to this problem, we might experience lower throughput. The
2459          * suggested workaround is to disable DCTL[12:9] bits if we're
2460          * transitioning from U1/U2 to U0 and enable those bits again
2461          * after a transfer completes and there are no pending transfers
2462          * on any of the enabled endpoints.
2463          *
2464          * This is the first half of that workaround.
2465          *
2466          * Refers to:
2467          *
2468          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2469          * core send LGO_Ux entering U0
2470          */
2471         if (dwc->revision < DWC3_REVISION_183A) {
2472                 if (next == DWC3_LINK_STATE_U0) {
2473                         u32     u1u2;
2474                         u32     reg;
2475
2476                         switch (dwc->link_state) {
2477                         case DWC3_LINK_STATE_U1:
2478                         case DWC3_LINK_STATE_U2:
2479                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2480                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2481                                                 | DWC3_DCTL_ACCEPTU2ENA
2482                                                 | DWC3_DCTL_INITU1ENA
2483                                                 | DWC3_DCTL_ACCEPTU1ENA);
2484
2485                                 if (!dwc->u1u2)
2486                                         dwc->u1u2 = reg & u1u2;
2487
2488                                 reg &= ~u1u2;
2489
2490                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2491                                 break;
2492                         default:
2493                                 /* do nothing */
2494                                 break;
2495                         }
2496                 }
2497         }
2498
2499         switch (next) {
2500         case DWC3_LINK_STATE_U1:
2501                 if (dwc->speed == USB_SPEED_SUPER)
2502                         dwc3_suspend_gadget(dwc);
2503                 break;
2504         case DWC3_LINK_STATE_U2:
2505         case DWC3_LINK_STATE_U3:
2506                 dwc3_suspend_gadget(dwc);
2507                 break;
2508         case DWC3_LINK_STATE_RESUME:
2509                 dwc3_resume_gadget(dwc);
2510                 break;
2511         default:
2512                 /* do nothing */
2513                 break;
2514         }
2515
2516         dwc->link_state = next;
2517 }
2518
2519 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2520                 unsigned int evtinfo)
2521 {
2522         unsigned int is_ss = evtinfo & BIT(4);
2523
2524         /**
2525          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2526          * have a known issue which can cause USB CV TD.9.23 to fail
2527          * randomly.
2528          *
2529          * Because of this issue, core could generate bogus hibernation
2530          * events which SW needs to ignore.
2531          *
2532          * Refers to:
2533          *
2534          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2535          * Device Fallback from SuperSpeed
2536          */
2537         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2538                 return;
2539
2540         /* enter hibernation here */
2541 }
2542
2543 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2544                 const struct dwc3_event_devt *event)
2545 {
2546         switch (event->type) {
2547         case DWC3_DEVICE_EVENT_DISCONNECT:
2548                 dwc3_gadget_disconnect_interrupt(dwc);
2549                 break;
2550         case DWC3_DEVICE_EVENT_RESET:
2551                 dwc3_gadget_reset_interrupt(dwc);
2552                 break;
2553         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2554                 dwc3_gadget_conndone_interrupt(dwc);
2555                 break;
2556         case DWC3_DEVICE_EVENT_WAKEUP:
2557                 dwc3_gadget_wakeup_interrupt(dwc);
2558                 break;
2559         case DWC3_DEVICE_EVENT_HIBER_REQ:
2560                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2561                                         "unexpected hibernation event\n"))
2562                         break;
2563
2564                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2565                 break;
2566         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2567                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2568                 break;
2569         case DWC3_DEVICE_EVENT_EOPF:
2570                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2571                 break;
2572         case DWC3_DEVICE_EVENT_SOF:
2573                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2574                 break;
2575         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2576                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2577                 break;
2578         case DWC3_DEVICE_EVENT_CMD_CMPL:
2579                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2580                 break;
2581         case DWC3_DEVICE_EVENT_OVERFLOW:
2582                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2583                 break;
2584         default:
2585                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2586         }
2587 }
2588
2589 static void dwc3_process_event_entry(struct dwc3 *dwc,
2590                 const union dwc3_event *event)
2591 {
2592         trace_dwc3_event(event->raw);
2593
2594         /* Endpoint IRQ, handle it and return early */
2595         if (event->type.is_devspec == 0) {
2596                 /* depevt */
2597                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2598         }
2599
2600         switch (event->type.type) {
2601         case DWC3_EVENT_TYPE_DEV:
2602                 dwc3_gadget_interrupt(dwc, &event->devt);
2603                 break;
2604         /* REVISIT what to do with Carkit and I2C events ? */
2605         default:
2606                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2607         }
2608 }
2609
2610 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2611 {
2612         struct dwc3 *dwc = evt->dwc;
2613         irqreturn_t ret = IRQ_NONE;
2614         int left;
2615         u32 reg;
2616
2617         left = evt->count;
2618
2619         if (!(evt->flags & DWC3_EVENT_PENDING))
2620                 return IRQ_NONE;
2621
2622         while (left > 0) {
2623                 union dwc3_event event;
2624
2625                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2626
2627                 dwc3_process_event_entry(dwc, &event);
2628
2629                 /*
2630                  * FIXME we wrap around correctly to the next entry as
2631                  * almost all entries are 4 bytes in size. There is one
2632                  * entry which has 12 bytes which is a regular entry
2633                  * followed by 8 bytes data. ATM I don't know how
2634                  * things are organized if we get next to the a
2635                  * boundary so I worry about that once we try to handle
2636                  * that.
2637                  */
2638                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2639                 left -= 4;
2640
2641                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2642         }
2643
2644         evt->count = 0;
2645         evt->flags &= ~DWC3_EVENT_PENDING;
2646         ret = IRQ_HANDLED;
2647
2648         /* Unmask interrupt */
2649         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2650         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2651         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2652
2653         return ret;
2654 }
2655
2656 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2657 {
2658         struct dwc3_event_buffer *evt = _evt;
2659         struct dwc3 *dwc = evt->dwc;
2660         unsigned long flags;
2661         irqreturn_t ret = IRQ_NONE;
2662
2663         spin_lock_irqsave(&dwc->lock, flags);
2664         ret = dwc3_process_event_buf(evt);
2665         spin_unlock_irqrestore(&dwc->lock, flags);
2666
2667         return ret;
2668 }
2669
2670 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2671 {
2672         struct dwc3 *dwc = evt->dwc;
2673         u32 count;
2674         u32 reg;
2675
2676         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2677         count &= DWC3_GEVNTCOUNT_MASK;
2678         if (!count)
2679                 return IRQ_NONE;
2680
2681         evt->count = count;
2682         evt->flags |= DWC3_EVENT_PENDING;
2683
2684         /* Mask interrupt */
2685         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2686         reg |= DWC3_GEVNTSIZ_INTMASK;
2687         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2688
2689         return IRQ_WAKE_THREAD;
2690 }
2691
2692 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2693 {
2694         struct dwc3_event_buffer        *evt = _evt;
2695
2696         return dwc3_check_event_buf(evt);
2697 }
2698
2699 /**
2700  * dwc3_gadget_init - Initializes gadget related registers
2701  * @dwc: pointer to our controller context structure
2702  *
2703  * Returns 0 on success otherwise negative errno.
2704  */
2705 int dwc3_gadget_init(struct dwc3 *dwc)
2706 {
2707         int                                     ret;
2708
2709         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2710                         &dwc->ctrl_req_addr, GFP_KERNEL);
2711         if (!dwc->ctrl_req) {
2712                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2713                 ret = -ENOMEM;
2714                 goto err0;
2715         }
2716
2717         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2718                         &dwc->ep0_trb_addr, GFP_KERNEL);
2719         if (!dwc->ep0_trb) {
2720                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2721                 ret = -ENOMEM;
2722                 goto err1;
2723         }
2724
2725         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2726         if (!dwc->setup_buf) {
2727                 ret = -ENOMEM;
2728                 goto err2;
2729         }
2730
2731         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2732                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2733                         GFP_KERNEL);
2734         if (!dwc->ep0_bounce) {
2735                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2736                 ret = -ENOMEM;
2737                 goto err3;
2738         }
2739
2740         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2741         if (!dwc->zlp_buf) {
2742                 ret = -ENOMEM;
2743                 goto err4;
2744         }
2745
2746         dwc->gadget.ops                 = &dwc3_gadget_ops;
2747         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2748         dwc->gadget.sg_supported        = true;
2749         dwc->gadget.name                = "dwc3-gadget";
2750         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2751
2752         /*
2753          * FIXME We might be setting max_speed to <SUPER, however versions
2754          * <2.20a of dwc3 have an issue with metastability (documented
2755          * elsewhere in this driver) which tells us we can't set max speed to
2756          * anything lower than SUPER.
2757          *
2758          * Because gadget.max_speed is only used by composite.c and function
2759          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2760          * to happen so we avoid sending SuperSpeed Capability descriptor
2761          * together with our BOS descriptor as that could confuse host into
2762          * thinking we can handle super speed.
2763          *
2764          * Note that, in fact, we won't even support GetBOS requests when speed
2765          * is less than super speed because we don't have means, yet, to tell
2766          * composite.c that we are USB 2.0 + LPM ECN.
2767          */
2768         if (dwc->revision < DWC3_REVISION_220A)
2769                 dwc3_trace(trace_dwc3_gadget,
2770                                 "Changing max_speed on rev %08x\n",
2771                                 dwc->revision);
2772
2773         dwc->gadget.max_speed           = dwc->maximum_speed;
2774
2775         /*
2776          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2777          * on ep out.
2778          */
2779         dwc->gadget.quirk_ep_out_aligned_size = true;
2780
2781         /*
2782          * REVISIT: Here we should clear all pending IRQs to be
2783          * sure we're starting from a well known location.
2784          */
2785
2786         ret = dwc3_gadget_init_endpoints(dwc);
2787         if (ret)
2788                 goto err5;
2789
2790         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2791         if (ret) {
2792                 dev_err(dwc->dev, "failed to register udc\n");
2793                 goto err5;
2794         }
2795
2796         return 0;
2797
2798 err5:
2799         kfree(dwc->zlp_buf);
2800
2801 err4:
2802         dwc3_gadget_free_endpoints(dwc);
2803         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2804                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2805
2806 err3:
2807         kfree(dwc->setup_buf);
2808
2809 err2:
2810         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2811                         dwc->ep0_trb, dwc->ep0_trb_addr);
2812
2813 err1:
2814         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2815                         dwc->ctrl_req, dwc->ctrl_req_addr);
2816
2817 err0:
2818         return ret;
2819 }
2820
2821 /* -------------------------------------------------------------------------- */
2822
2823 void dwc3_gadget_exit(struct dwc3 *dwc)
2824 {
2825         usb_del_gadget_udc(&dwc->gadget);
2826
2827         dwc3_gadget_free_endpoints(dwc);
2828
2829         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2830                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2831
2832         kfree(dwc->setup_buf);
2833         kfree(dwc->zlp_buf);
2834
2835         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2836                         dwc->ep0_trb, dwc->ep0_trb_addr);
2837
2838         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2839                         dwc->ctrl_req, dwc->ctrl_req_addr);
2840 }
2841
2842 int dwc3_gadget_suspend(struct dwc3 *dwc)
2843 {
2844         if (dwc->pullups_connected) {
2845                 dwc3_gadget_disable_irq(dwc);
2846                 dwc3_gadget_run_stop(dwc, true, true);
2847         }
2848
2849         __dwc3_gadget_ep_disable(dwc->eps[0]);
2850         __dwc3_gadget_ep_disable(dwc->eps[1]);
2851
2852         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2853
2854         return 0;
2855 }
2856
2857 int dwc3_gadget_resume(struct dwc3 *dwc)
2858 {
2859         struct dwc3_ep          *dep;
2860         int                     ret;
2861
2862         /* Start with SuperSpeed Default */
2863         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2864
2865         dep = dwc->eps[0];
2866         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2867                         false);
2868         if (ret)
2869                 goto err0;
2870
2871         dep = dwc->eps[1];
2872         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2873                         false);
2874         if (ret)
2875                 goto err1;
2876
2877         /* begin to receive SETUP packets */
2878         dwc->ep0state = EP0_SETUP_PHASE;
2879         dwc3_ep0_out_start(dwc);
2880
2881         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2882
2883         if (dwc->pullups_connected) {
2884                 dwc3_gadget_enable_irq(dwc);
2885                 dwc3_gadget_run_stop(dwc, true, false);
2886         }
2887
2888         return 0;
2889
2890 err1:
2891         __dwc3_gadget_ep_disable(dwc->eps[0]);
2892
2893 err0:
2894         return ret;
2895 }