drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 /*
  72  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  73  * address of the TRB.
  74  */
  75 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  76                 union xhci_trb *trb)
  77 {
  78         unsigned long segment_offset;
  79
  80         if (!seg || !trb || trb < seg->trbs)
  81                 return 0;
  82         /* offset in TRBs */
  83         segment_offset = trb - seg->trbs;
  84         if (segment_offset > TRBS_PER_SEGMENT)
  85                 return 0;
  86         return seg->dma + (segment_offset * sizeof(*trb));
  87 }
  88
  89 /* Does this link TRB point to the first segment in a ring,
  90  * or was the previous TRB the last TRB on the last segment in the ERST?
  91  */
  92 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  93                 struct xhci_segment *seg, union xhci_trb *trb)
  94 {
  95         if (ring == xhci->event_ring)
  96                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
  97                         (seg->next == xhci->event_ring->first_seg);
  98         else
  99                 return trb->link.control & LINK_TOGGLE;
 100 }
 101
 102 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 103  * segment?  I.e. would the updated event TRB pointer step off the end of the
 104  * event seg?
 105  */
 106 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 107                 struct xhci_segment *seg, union xhci_trb *trb)
 108 {
 109         if (ring == xhci->event_ring)
 110                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 111         else
 112                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 113 }
 114
 115 static inline int enqueue_is_link_trb(struct xhci_ring *ring)
 116 {
 117         struct xhci_link_trb *link = &ring->enqueue->link;
 118         return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
 119 }
 120
 121 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 122  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 123  * effect the ring dequeue or enqueue pointers.
 124  */
 125 static void next_trb(struct xhci_hcd *xhci,
 126                 struct xhci_ring *ring,
 127                 struct xhci_segment **seg,
 128                 union xhci_trb **trb)
 129 {
 130         if (last_trb(xhci, ring, *seg, *trb)) {
 131                 *seg = (*seg)->next;
 132                 *trb = ((*seg)->trbs);
 133         } else {
 134                 *trb = (*trb)++;
 135         }
 136 }
 137
 138 /*
 139  * See Cycle bit rules. SW is the consumer for the event ring only.
 140  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 141  */
 142 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 143 {
 144         union xhci_trb *next = ++(ring->dequeue);
 145         unsigned long long addr;
 146
 147         ring->deq_updates++;
 148         /* Update the dequeue pointer further if that was a link TRB or we're at
 149          * the end of an event ring segment (which doesn't have link TRBS)
 150          */
 151         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 152                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 153                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 154                         if (!in_interrupt())
 155                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 156                                                 ring,
 157                                                 (unsigned int) ring->cycle_state);
 158                 }
 159                 ring->deq_seg = ring->deq_seg->next;
 160                 ring->dequeue = ring->deq_seg->trbs;
 161                 next = ring->dequeue;
 162         }
 163         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 164         if (ring == xhci->event_ring)
 165                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 166         else if (ring == xhci->cmd_ring)
 167                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 168         else
 169                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 170 }
 171
 172 /*
 173  * See Cycle bit rules. SW is the consumer for the event ring only.
 174  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 175  *
 176  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 177  * chain bit is set), then set the chain bit in all the following link TRBs.
 178  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 179  * have their chain bit cleared (so that each Link TRB is a separate TD).
 180  *
 181  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 182  * set, but other sections talk about dealing with the chain bit set.  This was
 183  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 184  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 185  */
 186 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 187 {
 188         u32 chain;
 189         union xhci_trb *next;
 190         unsigned long long addr;
 191
 192         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 193         next = ++(ring->enqueue);
 194
 195         ring->enq_updates++;
 196         /* Update the dequeue pointer further if that was a link TRB or we're at
 197          * the end of an event ring segment (which doesn't have link TRBS)
 198          */
 199         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 200                 if (!consumer) {
 201                         if (ring != xhci->event_ring) {
 202                                 if (chain) {
 203                                         next->link.control |= TRB_CHAIN;
 204
 205                                         /* Give this link TRB to the hardware */
 206                                         wmb();
 207                                         next->link.control ^= TRB_CYCLE;
 208                                 } else {
 209                                         break;
 210                                 }
 211                         }
 212                         /* Toggle the cycle bit after the last ring segment. */
 213                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 214                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 215                                 if (!in_interrupt())
 216                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 217                                                         ring,
 218                                                         (unsigned int) ring->cycle_state);
 219                         }
 220                 }
 221                 ring->enq_seg = ring->enq_seg->next;
 222                 ring->enqueue = ring->enq_seg->trbs;
 223                 next = ring->enqueue;
 224         }
 225         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 226         if (ring == xhci->event_ring)
 227                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 228         else if (ring == xhci->cmd_ring)
 229                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 230         else
 231                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 232 }
 233
 234 /*
 235  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 236  * above.
 237  * FIXME: this would be simpler and faster if we just kept track of the number
 238  * of free TRBs in a ring.
 239  */
 240 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 241                 unsigned int num_trbs)
 242 {
 243         int i;
 244         union xhci_trb *enq = ring->enqueue;
 245         struct xhci_segment *enq_seg = ring->enq_seg;
 246         struct xhci_segment *cur_seg;
 247         unsigned int left_on_ring;
 248
 249         /* If we are currently pointing to a link TRB, advance the
 250          * enqueue pointer before checking for space */
 251         while (last_trb(xhci, ring, enq_seg, enq)) {
 252                 enq_seg = enq_seg->next;
 253                 enq = enq_seg->trbs;
 254         }
 255
 256         /* Check if ring is empty */
 257         if (enq == ring->dequeue) {
 258                 /* Can't use link trbs */
 259                 left_on_ring = TRBS_PER_SEGMENT - 1;
 260                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 261                                 cur_seg = cur_seg->next)
 262                         left_on_ring += TRBS_PER_SEGMENT - 1;
 263
 264                 /* Always need one TRB free in the ring. */
 265                 left_on_ring -= 1;
 266                 if (num_trbs > left_on_ring) {
 267                         xhci_warn(xhci, "Not enough room on ring; "
 268                                         "need %u TRBs, %u TRBs left\n",
 269                                         num_trbs, left_on_ring);
 270                         return 0;
 271                 }
 272                 return 1;
 273         }
 274         /* Make sure there's an extra empty TRB available */
 275         for (i = 0; i <= num_trbs; ++i) {
 276                 if (enq == ring->dequeue)
 277                         return 0;
 278                 enq++;
 279                 while (last_trb(xhci, ring, enq_seg, enq)) {
 280                         enq_seg = enq_seg->next;
 281                         enq = enq_seg->trbs;
 282                 }
 283         }
 284         return 1;
 285 }
 286
 287 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
 288 {
 289         u64 temp;
 290         dma_addr_t deq;
 291
 292         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
 293                         xhci->event_ring->dequeue);
 294         if (deq == 0 && !in_interrupt())
 295                 xhci_warn(xhci, "WARN something wrong with SW event ring "
 296                                 "dequeue ptr.\n");
 297         /* Update HC event ring dequeue pointer */
 298         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 299         temp &= ERST_PTR_MASK;
 300         /* Don't clear the EHB bit (which is RW1C) because
 301          * there might be more events to service.
 302          */
 303         temp &= ~ERST_EHB;
 304         xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
 305         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
 306                         &xhci->ir_set->erst_dequeue);
 307 }
 308
 309 /* Ring the host controller doorbell after placing a command on the ring */
 310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 311 {
 312         u32 temp;
 313
 314         xhci_dbg(xhci, "// Ding dong!\n");
 315         temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
 316         xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
 317         /* Flush PCI posted writes */
 318         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 319 }
 320
 321 static void ring_ep_doorbell(struct xhci_hcd *xhci,
 322                 unsigned int slot_id,
 323                 unsigned int ep_index,
 324                 unsigned int stream_id)
 325 {
 326         struct xhci_virt_ep *ep;
 327         unsigned int ep_state;
 328         u32 field;
 329         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 330
 331         ep = &xhci->devs[slot_id]->eps[ep_index];
 332         ep_state = ep->ep_state;
 333         /* Don't ring the doorbell for this endpoint if there are pending
 334          * cancellations because the we don't want to interrupt processing.
 335          * We don't want to restart any stream rings if there's a set dequeue
 336          * pointer command pending because the device can choose to start any
 337          * stream once the endpoint is on the HW schedule.
 338          * FIXME - check all the stream rings for pending cancellations.
 339          */
 340         if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING)
 341                         && !(ep_state & EP_HALTED)) {
 342                 field = xhci_readl(xhci, db_addr) & DB_MASK;
 343                 field |= EPI_TO_DB(ep_index) | STREAM_ID_TO_DB(stream_id);
 344                 xhci_writel(xhci, field, db_addr);
 345                 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
 346                  * isn't time-critical and we shouldn't make the CPU wait for
 347                  * the flush.
 348                  */
 349                 xhci_readl(xhci, db_addr);
 350         }
 351 }
 352
 353 /* Ring the doorbell for any rings with pending URBs */
 354 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 355                 unsigned int slot_id,
 356                 unsigned int ep_index)
 357 {
 358         unsigned int stream_id;
 359         struct xhci_virt_ep *ep;
 360
 361         ep = &xhci->devs[slot_id]->eps[ep_index];
 362
 363         /* A ring has pending URBs if its TD list is not empty */
 364         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 365                 if (!(list_empty(&ep->ring->td_list)))
 366                         ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 367                 return;
 368         }
 369
 370         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 371                         stream_id++) {
 372                 struct xhci_stream_info *stream_info = ep->stream_info;
 373                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 374                         ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
 375         }
 376 }
 377
 378 /*
 379  * Find the segment that trb is in.  Start searching in start_seg.
 380  * If we must move past a segment that has a link TRB with a toggle cycle state
 381  * bit set, then we will toggle the value pointed at by cycle_state.
 382  */
 383 static struct xhci_segment *find_trb_seg(
 384                 struct xhci_segment *start_seg,
 385                 union xhci_trb  *trb, int *cycle_state)
 386 {
 387         struct xhci_segment *cur_seg = start_seg;
 388         struct xhci_generic_trb *generic_trb;
 389
 390         while (cur_seg->trbs > trb ||
 391                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 392                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 393                 if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK &&
 394                                 (generic_trb->field[3] & LINK_TOGGLE))
 395                         *cycle_state = ~(*cycle_state) & 0x1;
 396                 cur_seg = cur_seg->next;
 397                 if (cur_seg == start_seg)
 398                         /* Looped over the entire list.  Oops! */
 399                         return NULL;
 400         }
 401         return cur_seg;
 402 }
 403
 404 /*
 405  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 406  * Record the new state of the xHC's endpoint ring dequeue segment,
 407  * dequeue pointer, and new consumer cycle state in state.
 408  * Update our internal representation of the ring's dequeue pointer.
 409  *
 410  * We do this in three jumps:
 411  *  - First we update our new ring state to be the same as when the xHC stopped.
 412  *  - Then we traverse the ring to find the segment that contains
 413  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 414  *    any link TRBs with the toggle cycle bit set.
 415  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 416  *    if we've moved it past a link TRB with the toggle cycle bit set.
 417  */
 418 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 419                 unsigned int slot_id, unsigned int ep_index,
 420                 unsigned int stream_id, struct xhci_td *cur_td,
 421                 struct xhci_dequeue_state *state)
 422 {
 423         struct xhci_virt_device *dev = xhci->devs[slot_id];
 424         struct xhci_ring *ep_ring;
 425         struct xhci_generic_trb *trb;
 426         struct xhci_ep_ctx *ep_ctx;
 427         dma_addr_t addr;
 428
 429         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 430                         ep_index, stream_id);
 431         if (!ep_ring) {
 432                 xhci_warn(xhci, "WARN can't find new dequeue state "
 433                                 "for invalid stream ID %u.\n",
 434                                 stream_id);
 435                 return;
 436         }
 437         state->new_cycle_state = 0;
 438         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 439         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 440                         dev->eps[ep_index].stopped_trb,
 441                         &state->new_cycle_state);
 442         if (!state->new_deq_seg)
 443                 BUG();
 444         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 445         xhci_dbg(xhci, "Finding endpoint context\n");
 446         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 447         state->new_cycle_state = 0x1 & ep_ctx->deq;
 448
 449         state->new_deq_ptr = cur_td->last_trb;
 450         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 451         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 452                         state->new_deq_ptr,
 453                         &state->new_cycle_state);
 454         if (!state->new_deq_seg)
 455                 BUG();
 456
 457         trb = &state->new_deq_ptr->generic;
 458         if (TRB_TYPE(trb->field[3]) == TRB_LINK &&
 459                                 (trb->field[3] & LINK_TOGGLE))
 460                 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
 461         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 462
 463         /* Don't update the ring cycle state for the producer (us). */
 464         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 465                         state->new_deq_seg);
 466         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 467         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 468                         (unsigned long long) addr);
 469         xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
 470         ep_ring->dequeue = state->new_deq_ptr;
 471         ep_ring->deq_seg = state->new_deq_seg;
 472 }
 473
 474 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 475                 struct xhci_td *cur_td)
 476 {
 477         struct xhci_segment *cur_seg;
 478         union xhci_trb *cur_trb;
 479
 480         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 481                         true;
 482                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 483                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 484                                 TRB_TYPE(TRB_LINK)) {
 485                         /* Unchain any chained Link TRBs, but
 486                          * leave the pointers intact.
 487                          */
 488                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 489                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 490                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 491                                         "in seg %p (0x%llx dma)\n",
 492                                         cur_trb,
 493                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 494                                         cur_seg,
 495                                         (unsigned long long)cur_seg->dma);
 496                 } else {
 497                         cur_trb->generic.field[0] = 0;
 498                         cur_trb->generic.field[1] = 0;
 499                         cur_trb->generic.field[2] = 0;
 500                         /* Preserve only the cycle bit of this TRB */
 501                         cur_trb->generic.field[3] &= TRB_CYCLE;
 502                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 503                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 504                                         "in seg %p (0x%llx dma)\n",
 505                                         cur_trb,
 506                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 507                                         cur_seg,
 508                                         (unsigned long long)cur_seg->dma);
 509                 }
 510                 if (cur_trb == cur_td->last_trb)
 511                         break;
 512         }
 513 }
 514
 515 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 516                 unsigned int ep_index, unsigned int stream_id,
 517                 struct xhci_segment *deq_seg,
 518                 union xhci_trb *deq_ptr, u32 cycle_state);
 519
 520 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 521                 unsigned int slot_id, unsigned int ep_index,
 522                 unsigned int stream_id,
 523                 struct xhci_dequeue_state *deq_state)
 524 {
 525         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 526
 527         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 528                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 529                         deq_state->new_deq_seg,
 530                         (unsigned long long)deq_state->new_deq_seg->dma,
 531                         deq_state->new_deq_ptr,
 532                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 533                         deq_state->new_cycle_state);
 534         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 535                         deq_state->new_deq_seg,
 536                         deq_state->new_deq_ptr,
 537                         (u32) deq_state->new_cycle_state);
 538         /* Stop the TD queueing code from ringing the doorbell until
 539          * this command completes.  The HC won't set the dequeue pointer
 540          * if the ring is running, and ringing the doorbell starts the
 541          * ring running.
 542          */
 543         ep->ep_state |= SET_DEQ_PENDING;
 544 }
 545
 546 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 547                 struct xhci_virt_ep *ep)
 548 {
 549         ep->ep_state &= ~EP_HALT_PENDING;
 550         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 551          * timer is running on another CPU, we don't decrement stop_cmds_pending
 552          * (since we didn't successfully stop the watchdog timer).
 553          */
 554         if (del_timer(&ep->stop_cmd_timer))
 555                 ep->stop_cmds_pending--;
 556 }
 557
 558 /* Must be called with xhci->lock held in interrupt context */
 559 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 560                 struct xhci_td *cur_td, int status, char *adjective)
 561 {
 562         struct usb_hcd *hcd = xhci_to_hcd(xhci);
 563
 564         cur_td->urb->hcpriv = NULL;
 565         usb_hcd_unlink_urb_from_ep(hcd, cur_td->urb);
 566         xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, cur_td->urb);
 567
 568         spin_unlock(&xhci->lock);
 569         usb_hcd_giveback_urb(hcd, cur_td->urb, status);
 570         kfree(cur_td);
 571         spin_lock(&xhci->lock);
 572         xhci_dbg(xhci, "%s URB given back\n", adjective);
 573 }
 574
 575 /*
 576  * When we get a command completion for a Stop Endpoint Command, we need to
 577  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 578  *
 579  *  1. If the HW was in the middle of processing the TD that needs to be
 580  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 581  *     in the TD with a Set Dequeue Pointer Command.
 582  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 583  *     bit cleared) so that the HW will skip over them.
 584  */
 585 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 586                 union xhci_trb *trb)
 587 {
 588         unsigned int slot_id;
 589         unsigned int ep_index;
 590         struct xhci_ring *ep_ring;
 591         struct xhci_virt_ep *ep;
 592         struct list_head *entry;
 593         struct xhci_td *cur_td = NULL;
 594         struct xhci_td *last_unlinked_td;
 595
 596         struct xhci_dequeue_state deq_state;
 597
 598         memset(&deq_state, 0, sizeof(deq_state));
 599         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 600         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 601         ep = &xhci->devs[slot_id]->eps[ep_index];
 602
 603         if (list_empty(&ep->cancelled_td_list)) {
 604                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 605                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 606                 return;
 607         }
 608
 609         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 610          * We have the xHCI lock, so nothing can modify this list until we drop
 611          * it.  We're also in the event handler, so we can't get re-interrupted
 612          * if another Stop Endpoint command completes
 613          */
 614         list_for_each(entry, &ep->cancelled_td_list) {
 615                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 616                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 617                                 cur_td->first_trb,
 618                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 619                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 620                 if (!ep_ring) {
 621                         /* This shouldn't happen unless a driver is mucking
 622                          * with the stream ID after submission.  This will
 623                          * leave the TD on the hardware ring, and the hardware
 624                          * will try to execute it, and may access a buffer
 625                          * that has already been freed.  In the best case, the
 626                          * hardware will execute it, and the event handler will
 627                          * ignore the completion event for that TD, since it was
 628                          * removed from the td_list for that endpoint.  In
 629                          * short, don't muck with the stream ID after
 630                          * submission.
 631                          */
 632                         xhci_warn(xhci, "WARN Cancelled URB %p "
 633                                         "has invalid stream ID %u.\n",
 634                                         cur_td->urb,
 635                                         cur_td->urb->stream_id);
 636                         goto remove_finished_td;
 637                 }
 638                 /*
 639                  * If we stopped on the TD we need to cancel, then we have to
 640                  * move the xHC endpoint ring dequeue pointer past this TD.
 641                  */
 642                 if (cur_td == ep->stopped_td)
 643                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 644                                         cur_td->urb->stream_id,
 645                                         cur_td, &deq_state);
 646                 else
 647                         td_to_noop(xhci, ep_ring, cur_td);
 648 remove_finished_td:
 649                 /*
 650                  * The event handler won't see a completion for this TD anymore,
 651                  * so remove it from the endpoint ring's TD list.  Keep it in
 652                  * the cancelled TD list for URB completion later.
 653                  */
 654                 list_del(&cur_td->td_list);
 655         }
 656         last_unlinked_td = cur_td;
 657         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 658
 659         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 660         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 661                 xhci_queue_new_dequeue_state(xhci,
 662                                 slot_id, ep_index,
 663                                 ep->stopped_td->urb->stream_id,
 664                                 &deq_state);
 665                 xhci_ring_cmd_db(xhci);
 666         } else {
 667                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 668                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 669         }
 670         ep->stopped_td = NULL;
 671         ep->stopped_trb = NULL;
 672
 673         /*
 674          * Drop the lock and complete the URBs in the cancelled TD list.
 675          * New TDs to be cancelled might be added to the end of the list before
 676          * we can complete all the URBs for the TDs we already unlinked.
 677          * So stop when we've completed the URB for the last TD we unlinked.
 678          */
 679         do {
 680                 cur_td = list_entry(ep->cancelled_td_list.next,
 681                                 struct xhci_td, cancelled_td_list);
 682                 list_del(&cur_td->cancelled_td_list);
 683
 684                 /* Clean up the cancelled URB */
 685                 /* Doesn't matter what we pass for status, since the core will
 686                  * just overwrite it (because the URB has been unlinked).
 687                  */
 688                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 689
 690                 /* Stop processing the cancelled list if the watchdog timer is
 691                  * running.
 692                  */
 693                 if (xhci->xhc_state & XHCI_STATE_DYING)
 694                         return;
 695         } while (cur_td != last_unlinked_td);
 696
 697         /* Return to the event handler with xhci->lock re-acquired */
 698 }
 699
 700 /* Watchdog timer function for when a stop endpoint command fails to complete.
 701  * In this case, we assume the host controller is broken or dying or dead.  The
 702  * host may still be completing some other events, so we have to be careful to
 703  * let the event ring handler and the URB dequeueing/enqueueing functions know
 704  * through xhci->state.
 705  *
 706  * The timer may also fire if the host takes a very long time to respond to the
 707  * command, and the stop endpoint command completion handler cannot delete the
 708  * timer before the timer function is called.  Another endpoint cancellation may
 709  * sneak in before the timer function can grab the lock, and that may queue
 710  * another stop endpoint command and add the timer back.  So we cannot use a
 711  * simple flag to say whether there is a pending stop endpoint command for a
 712  * particular endpoint.
 713  *
 714  * Instead we use a combination of that flag and a counter for the number of
 715  * pending stop endpoint commands.  If the timer is the tail end of the last
 716  * stop endpoint command, and the endpoint's command is still pending, we assume
 717  * the host is dying.
 718  */
 719 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 720 {
 721         struct xhci_hcd *xhci;
 722         struct xhci_virt_ep *ep;
 723         struct xhci_virt_ep *temp_ep;
 724         struct xhci_ring *ring;
 725         struct xhci_td *cur_td;
 726         int ret, i, j;
 727
 728         ep = (struct xhci_virt_ep *) arg;
 729         xhci = ep->xhci;
 730
 731         spin_lock(&xhci->lock);
 732
 733         ep->stop_cmds_pending--;
 734         if (xhci->xhc_state & XHCI_STATE_DYING) {
 735                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 736                                 "xHCI as DYING, exiting.\n");
 737                 spin_unlock(&xhci->lock);
 738                 return;
 739         }
 740         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 741                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 742                                 "exiting.\n");
 743                 spin_unlock(&xhci->lock);
 744                 return;
 745         }
 746
 747         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 748         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 749         /* Oops, HC is dead or dying or at least not responding to the stop
 750          * endpoint command.
 751          */
 752         xhci->xhc_state |= XHCI_STATE_DYING;
 753         /* Disable interrupts from the host controller and start halting it */
 754         xhci_quiesce(xhci);
 755         spin_unlock(&xhci->lock);
 756
 757         ret = xhci_halt(xhci);
 758
 759         spin_lock(&xhci->lock);
 760         if (ret < 0) {
 761                 /* This is bad; the host is not responding to commands and it's
 762                  * not allowing itself to be halted.  At least interrupts are
 763                  * disabled, so we can set HC_STATE_HALT and notify the
 764                  * USB core.  But if we call usb_hc_died(), it will attempt to
 765                  * disconnect all device drivers under this host.  Those
 766                  * disconnect() methods will wait for all URBs to be unlinked,
 767                  * so we must complete them.
 768                  */
 769                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 770                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 771                 /* We could turn all TDs on the rings to no-ops.  This won't
 772                  * help if the host has cached part of the ring, and is slow if
 773                  * we want to preserve the cycle bit.  Skip it and hope the host
 774                  * doesn't touch the memory.
 775                  */
 776         }
 777         for (i = 0; i < MAX_HC_SLOTS; i++) {
 778                 if (!xhci->devs[i])
 779                         continue;
 780                 for (j = 0; j < 31; j++) {
 781                         temp_ep = &xhci->devs[i]->eps[j];
 782                         ring = temp_ep->ring;
 783                         if (!ring)
 784                                 continue;
 785                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 786                                         "ep index %u\n", i, j);
 787                         while (!list_empty(&ring->td_list)) {
 788                                 cur_td = list_first_entry(&ring->td_list,
 789                                                 struct xhci_td,
 790                                                 td_list);
 791                                 list_del(&cur_td->td_list);
 792                                 if (!list_empty(&cur_td->cancelled_td_list))
 793                                         list_del(&cur_td->cancelled_td_list);
 794                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 795                                                 -ESHUTDOWN, "killed");
 796                         }
 797                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 798                                 cur_td = list_first_entry(
 799                                                 &temp_ep->cancelled_td_list,
 800                                                 struct xhci_td,
 801                                                 cancelled_td_list);
 802                                 list_del(&cur_td->cancelled_td_list);
 803                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 804                                                 -ESHUTDOWN, "killed");
 805                         }
 806                 }
 807         }
 808         spin_unlock(&xhci->lock);
 809         xhci_to_hcd(xhci)->state = HC_STATE_HALT;
 810         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 811         usb_hc_died(xhci_to_hcd(xhci));
 812         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 813 }
 814
 815 /*
 816  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 817  * we need to clear the set deq pending flag in the endpoint ring state, so that
 818  * the TD queueing code can ring the doorbell again.  We also need to ring the
 819  * endpoint doorbell to restart the ring, but only if there aren't more
 820  * cancellations pending.
 821  */
 822 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 823                 struct xhci_event_cmd *event,
 824                 union xhci_trb *trb)
 825 {
 826         unsigned int slot_id;
 827         unsigned int ep_index;
 828         unsigned int stream_id;
 829         struct xhci_ring *ep_ring;
 830         struct xhci_virt_device *dev;
 831         struct xhci_ep_ctx *ep_ctx;
 832         struct xhci_slot_ctx *slot_ctx;
 833
 834         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 835         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 836         stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
 837         dev = xhci->devs[slot_id];
 838
 839         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 840         if (!ep_ring) {
 841                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 842                                 "freed stream ID %u\n",
 843                                 stream_id);
 844                 /* XXX: Harmless??? */
 845                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 846                 return;
 847         }
 848
 849         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 850         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 851
 852         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 853                 unsigned int ep_state;
 854                 unsigned int slot_state;
 855
 856                 switch (GET_COMP_CODE(event->status)) {
 857                 case COMP_TRB_ERR:
 858                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 859                                         "of stream ID configuration\n");
 860                         break;
 861                 case COMP_CTX_STATE:
 862                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 863                                         "to incorrect slot or ep state.\n");
 864                         ep_state = ep_ctx->ep_info;
 865                         ep_state &= EP_STATE_MASK;
 866                         slot_state = slot_ctx->dev_state;
 867                         slot_state = GET_SLOT_STATE(slot_state);
 868                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 869                                         slot_state, ep_state);
 870                         break;
 871                 case COMP_EBADSLT:
 872                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 873                                         "slot %u was not enabled.\n", slot_id);
 874                         break;
 875                 default:
 876                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 877                                         "completion code of %u.\n",
 878                                         GET_COMP_CODE(event->status));
 879                         break;
 880                 }
 881                 /* OK what do we do now?  The endpoint state is hosed, and we
 882                  * should never get to this point if the synchronization between
 883                  * queueing, and endpoint state are correct.  This might happen
 884                  * if the device gets disconnected after we've finished
 885                  * cancelling URBs, which might not be an error...
 886                  */
 887         } else {
 888                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 889                                 ep_ctx->deq);
 890         }
 891
 892         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 893         /* Restart any rings with pending URBs */
 894         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 895 }
 896
 897 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 898                 struct xhci_event_cmd *event,
 899                 union xhci_trb *trb)
 900 {
 901         int slot_id;
 902         unsigned int ep_index;
 903
 904         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 905         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 906         /* This command will only fail if the endpoint wasn't halted,
 907          * but we don't care.
 908          */
 909         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 910                         (unsigned int) GET_COMP_CODE(event->status));
 911
 912         /* HW with the reset endpoint quirk needs to have a configure endpoint
 913          * command complete before the endpoint can be used.  Queue that here
 914          * because the HW can't handle two commands being queued in a row.
 915          */
 916         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
 917                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
 918                 xhci_queue_configure_endpoint(xhci,
 919                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
 920                                 false);
 921                 xhci_ring_cmd_db(xhci);
 922         } else {
 923                 /* Clear our internal halted state and restart the ring(s) */
 924                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
 925                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 926         }
 927 }
 928
 929 /* Check to see if a command in the device's command queue matches this one.
 930  * Signal the completion or free the command, and return 1.  Return 0 if the
 931  * completed command isn't at the head of the command list.
 932  */
 933 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
 934                 struct xhci_virt_device *virt_dev,
 935                 struct xhci_event_cmd *event)
 936 {
 937         struct xhci_command *command;
 938
 939         if (list_empty(&virt_dev->cmd_list))
 940                 return 0;
 941
 942         command = list_entry(virt_dev->cmd_list.next,
 943                         struct xhci_command, cmd_list);
 944         if (xhci->cmd_ring->dequeue != command->command_trb)
 945                 return 0;
 946
 947         command->status =
 948                 GET_COMP_CODE(event->status);
 949         list_del(&command->cmd_list);
 950         if (command->completion)
 951                 complete(command->completion);
 952         else
 953                 xhci_free_command(xhci, command);
 954         return 1;
 955 }
 956
 957 static void handle_cmd_completion(struct xhci_hcd *xhci,
 958                 struct xhci_event_cmd *event)
 959 {
 960         int slot_id = TRB_TO_SLOT_ID(event->flags);
 961         u64 cmd_dma;
 962         dma_addr_t cmd_dequeue_dma;
 963         struct xhci_input_control_ctx *ctrl_ctx;
 964         struct xhci_virt_device *virt_dev;
 965         unsigned int ep_index;
 966         struct xhci_ring *ep_ring;
 967         unsigned int ep_state;
 968
 969         cmd_dma = event->cmd_trb;
 970         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
 971                         xhci->cmd_ring->dequeue);
 972         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
 973         if (cmd_dequeue_dma == 0) {
 974                 xhci->error_bitmask |= 1 << 4;
 975                 return;
 976         }
 977         /* Does the DMA address match our internal dequeue pointer address? */
 978         if (cmd_dma != (u64) cmd_dequeue_dma) {
 979                 xhci->error_bitmask |= 1 << 5;
 980                 return;
 981         }
 982         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
 983         case TRB_TYPE(TRB_ENABLE_SLOT):
 984                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
 985                         xhci->slot_id = slot_id;
 986                 else
 987                         xhci->slot_id = 0;
 988                 complete(&xhci->addr_dev);
 989                 break;
 990         case TRB_TYPE(TRB_DISABLE_SLOT):
 991                 if (xhci->devs[slot_id])
 992                         xhci_free_virt_device(xhci, slot_id);
 993                 break;
 994         case TRB_TYPE(TRB_CONFIG_EP):
 995                 virt_dev = xhci->devs[slot_id];
 996                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
 997                         break;
 998                 /*
 999                  * Configure endpoint commands can come from the USB core
1000                  * configuration or alt setting changes, or because the HW
1001                  * needed an extra configure endpoint command after a reset
1002                  * endpoint command or streams were being configured.
1003                  * If the command was for a halted endpoint, the xHCI driver
1004                  * is not waiting on the configure endpoint command.
1005                  */
1006                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1007                                 virt_dev->in_ctx);
1008                 /* Input ctx add_flags are the endpoint index plus one */
1009                 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1010                 /* A usb_set_interface() call directly after clearing a halted
1011                  * condition may race on this quirky hardware.  Not worth
1012                  * worrying about, since this is prototype hardware.  Not sure
1013                  * if this will work for streams, but streams support was
1014                  * untested on this prototype.
1015                  */
1016                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1017                                 ep_index != (unsigned int) -1 &&
1018                                 ctrl_ctx->add_flags - SLOT_FLAG ==
1019                                         ctrl_ctx->drop_flags) {
1020                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1021                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1022                         if (!(ep_state & EP_HALTED))
1023                                 goto bandwidth_change;
1024                         xhci_dbg(xhci, "Completed config ep cmd - "
1025                                         "last ep index = %d, state = %d\n",
1026                                         ep_index, ep_state);
1027                         /* Clear internal halted state and restart ring(s) */
1028                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1029                                 ~EP_HALTED;
1030                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1031                         break;
1032                 }
1033 bandwidth_change:
1034                 xhci_dbg(xhci, "Completed config ep cmd\n");
1035                 xhci->devs[slot_id]->cmd_status =
1036                         GET_COMP_CODE(event->status);
1037                 complete(&xhci->devs[slot_id]->cmd_completion);
1038                 break;
1039         case TRB_TYPE(TRB_EVAL_CONTEXT):
1040                 virt_dev = xhci->devs[slot_id];
1041                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1042                         break;
1043                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1044                 complete(&xhci->devs[slot_id]->cmd_completion);
1045                 break;
1046         case TRB_TYPE(TRB_ADDR_DEV):
1047                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1048                 complete(&xhci->addr_dev);
1049                 break;
1050         case TRB_TYPE(TRB_STOP_RING):
1051                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
1052                 break;
1053         case TRB_TYPE(TRB_SET_DEQ):
1054                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1055                 break;
1056         case TRB_TYPE(TRB_CMD_NOOP):
1057                 ++xhci->noops_handled;
1058                 break;
1059         case TRB_TYPE(TRB_RESET_EP):
1060                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1061                 break;
1062         case TRB_TYPE(TRB_RESET_DEV):
1063                 xhci_dbg(xhci, "Completed reset device command.\n");
1064                 slot_id = TRB_TO_SLOT_ID(
1065                                 xhci->cmd_ring->dequeue->generic.field[3]);
1066                 virt_dev = xhci->devs[slot_id];
1067                 if (virt_dev)
1068                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1069                 else
1070                         xhci_warn(xhci, "Reset device command completion "
1071                                         "for disabled slot %u\n", slot_id);
1072                 break;
1073         default:
1074                 /* Skip over unknown commands on the event ring */
1075                 xhci->error_bitmask |= 1 << 6;
1076                 break;
1077         }
1078         inc_deq(xhci, xhci->cmd_ring, false);
1079 }
1080
1081 static void handle_port_status(struct xhci_hcd *xhci,
1082                 union xhci_trb *event)
1083 {
1084         u32 port_id;
1085
1086         /* Port status change events always have a successful completion code */
1087         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1088                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1089                 xhci->error_bitmask |= 1 << 8;
1090         }
1091         /* FIXME: core doesn't care about all port link state changes yet */
1092         port_id = GET_PORT_ID(event->generic.field[0]);
1093         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1094
1095         /* Update event ring dequeue pointer before dropping the lock */
1096         inc_deq(xhci, xhci->event_ring, true);
1097         xhci_set_hc_event_deq(xhci);
1098
1099         spin_unlock(&xhci->lock);
1100         /* Pass this up to the core */
1101         usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
1102         spin_lock(&xhci->lock);
1103 }
1104
1105 /*
1106  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1107  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1108  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1109  * returns 0.
1110  */
1111 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1112                 union xhci_trb  *start_trb,
1113                 union xhci_trb  *end_trb,
1114                 dma_addr_t      suspect_dma)
1115 {
1116         dma_addr_t start_dma;
1117         dma_addr_t end_seg_dma;
1118         dma_addr_t end_trb_dma;
1119         struct xhci_segment *cur_seg;
1120
1121         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1122         cur_seg = start_seg;
1123
1124         do {
1125                 if (start_dma == 0)
1126                         return NULL;
1127                 /* We may get an event for a Link TRB in the middle of a TD */
1128                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1129                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1130                 /* If the end TRB isn't in this segment, this is set to 0 */
1131                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1132
1133                 if (end_trb_dma > 0) {
1134                         /* The end TRB is in this segment, so suspect should be here */
1135                         if (start_dma <= end_trb_dma) {
1136                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1137                                         return cur_seg;
1138                         } else {
1139                                 /* Case for one segment with
1140                                  * a TD wrapped around to the top
1141                                  */
1142                                 if ((suspect_dma >= start_dma &&
1143                                                         suspect_dma <= end_seg_dma) ||
1144                                                 (suspect_dma >= cur_seg->dma &&
1145                                                  suspect_dma <= end_trb_dma))
1146                                         return cur_seg;
1147                         }
1148                         return NULL;
1149                 } else {
1150                         /* Might still be somewhere in this segment */
1151                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1152                                 return cur_seg;
1153                 }
1154                 cur_seg = cur_seg->next;
1155                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1156         } while (cur_seg != start_seg);
1157
1158         return NULL;
1159 }
1160
1161 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1162                 unsigned int slot_id, unsigned int ep_index,
1163                 unsigned int stream_id,
1164                 struct xhci_td *td, union xhci_trb *event_trb)
1165 {
1166         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1167         ep->ep_state |= EP_HALTED;
1168         ep->stopped_td = td;
1169         ep->stopped_trb = event_trb;
1170         ep->stopped_stream = stream_id;
1171
1172         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1173         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1174
1175         ep->stopped_td = NULL;
1176         ep->stopped_trb = NULL;
1177         ep->stopped_stream = 0;
1178
1179         xhci_ring_cmd_db(xhci);
1180 }
1181
1182 /* Check if an error has halted the endpoint ring.  The class driver will
1183  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1184  * However, a babble and other errors also halt the endpoint ring, and the class
1185  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1186  * Ring Dequeue Pointer command manually.
1187  */
1188 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1189                 struct xhci_ep_ctx *ep_ctx,
1190                 unsigned int trb_comp_code)
1191 {
1192         /* TRB completion codes that may require a manual halt cleanup */
1193         if (trb_comp_code == COMP_TX_ERR ||
1194                         trb_comp_code == COMP_BABBLE ||
1195                         trb_comp_code == COMP_SPLIT_ERR)
1196                 /* The 0.96 spec says a babbling control endpoint
1197                  * is not halted. The 0.96 spec says it is.  Some HW
1198                  * claims to be 0.95 compliant, but it halts the control
1199                  * endpoint anyway.  Check if a babble halted the
1200                  * endpoint.
1201                  */
1202                 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1203                         return 1;
1204
1205         return 0;
1206 }
1207
1208 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1209 {
1210         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1211                 /* Vendor defined "informational" completion code,
1212                  * treat as not-an-error.
1213                  */
1214                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1215                                 trb_comp_code);
1216                 xhci_dbg(xhci, "Treating code as success.\n");
1217                 return 1;
1218         }
1219         return 0;
1220 }
1221
1222 /*
1223  * If this function returns an error condition, it means it got a Transfer
1224  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1225  * At this point, the host controller is probably hosed and should be reset.
1226  */
1227 static int handle_tx_event(struct xhci_hcd *xhci,
1228                 struct xhci_transfer_event *event)
1229 {
1230         struct xhci_virt_device *xdev;
1231         struct xhci_virt_ep *ep;
1232         struct xhci_ring *ep_ring;
1233         unsigned int slot_id;
1234         int ep_index;
1235         struct xhci_td *td = NULL;
1236         dma_addr_t event_dma;
1237         struct xhci_segment *event_seg;
1238         union xhci_trb *event_trb;
1239         struct urb *urb = NULL;
1240         int status = -EINPROGRESS;
1241         struct xhci_ep_ctx *ep_ctx;
1242         u32 trb_comp_code;
1243
1244         xhci_dbg(xhci, "In %s\n", __func__);
1245         slot_id = TRB_TO_SLOT_ID(event->flags);
1246         xdev = xhci->devs[slot_id];
1247         if (!xdev) {
1248                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1249                 return -ENODEV;
1250         }
1251
1252         /* Endpoint ID is 1 based, our index is zero based */
1253         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1254         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1255         ep = &xdev->eps[ep_index];
1256         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1257         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1258         if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1259                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1260                                 "or incorrect stream ring\n");
1261                 return -ENODEV;
1262         }
1263
1264         event_dma = event->buffer;
1265         /* This TRB should be in the TD at the head of this ring's TD list */
1266         xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
1267         if (list_empty(&ep_ring->td_list)) {
1268                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
1269                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1270                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1271                                 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1272                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1273                 urb = NULL;
1274                 goto cleanup;
1275         }
1276         xhci_dbg(xhci, "%s - getting list entry\n", __func__);
1277         td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1278
1279         /* Is this a TRB in the currently executing TD? */
1280         xhci_dbg(xhci, "%s - looking for TD\n", __func__);
1281         event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1282                         td->last_trb, event_dma);
1283         xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
1284         if (!event_seg) {
1285                 /* HC is busted, give up! */
1286                 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
1287                 return -ESHUTDOWN;
1288         }
1289         event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
1290         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1291                         (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1292         xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
1293                         lower_32_bits(event->buffer));
1294         xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
1295                         upper_32_bits(event->buffer));
1296         xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
1297                         (unsigned int) event->transfer_len);
1298         xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
1299                         (unsigned int) event->flags);
1300
1301         /* Look for common error cases */
1302         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1303         switch (trb_comp_code) {
1304         /* Skip codes that require special handling depending on
1305          * transfer type
1306          */
1307         case COMP_SUCCESS:
1308         case COMP_SHORT_TX:
1309                 break;
1310         case COMP_STOP:
1311                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1312                 break;
1313         case COMP_STOP_INVAL:
1314                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1315                 break;
1316         case COMP_STALL:
1317                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1318                 ep->ep_state |= EP_HALTED;
1319                 status = -EPIPE;
1320                 break;
1321         case COMP_TRB_ERR:
1322                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1323                 status = -EILSEQ;
1324                 break;
1325         case COMP_SPLIT_ERR:
1326         case COMP_TX_ERR:
1327                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1328                 status = -EPROTO;
1329                 break;
1330         case COMP_BABBLE:
1331                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1332                 status = -EOVERFLOW;
1333                 break;
1334         case COMP_DB_ERR:
1335                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1336                 status = -ENOSR;
1337                 break;
1338         default:
1339                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1340                         status = 0;
1341                         break;
1342                 }
1343                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
1344                 urb = NULL;
1345                 goto cleanup;
1346         }
1347         /* Now update the urb's actual_length and give back to the core */
1348         /* Was this a control transfer? */
1349         if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
1350                 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1351                 switch (trb_comp_code) {
1352                 case COMP_SUCCESS:
1353                         if (event_trb == ep_ring->dequeue) {
1354                                 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
1355                                 status = -ESHUTDOWN;
1356                         } else if (event_trb != td->last_trb) {
1357                                 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
1358                                 status = -ESHUTDOWN;
1359                         } else {
1360                                 xhci_dbg(xhci, "Successful control transfer!\n");
1361                                 status = 0;
1362                         }
1363                         break;
1364                 case COMP_SHORT_TX:
1365                         xhci_warn(xhci, "WARN: short transfer on control ep\n");
1366                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1367                                 status = -EREMOTEIO;
1368                         else
1369                                 status = 0;
1370                         break;
1371
1372                 default:
1373                         if (!xhci_requires_manual_halt_cleanup(xhci,
1374                                                 ep_ctx, trb_comp_code))
1375                                 break;
1376                         xhci_dbg(xhci, "TRB error code %u, "
1377                                         "halted endpoint index = %u\n",
1378                                         trb_comp_code, ep_index);
1379                         /* else fall through */
1380                 case COMP_STALL:
1381                         /* Did we transfer part of the data (middle) phase? */
1382                         if (event_trb != ep_ring->dequeue &&
1383                                         event_trb != td->last_trb)
1384                                 td->urb->actual_length =
1385                                         td->urb->transfer_buffer_length
1386                                         - TRB_LEN(event->transfer_len);
1387                         else
1388                                 td->urb->actual_length = 0;
1389
1390                         xhci_cleanup_halted_endpoint(xhci,
1391                                         slot_id, ep_index, 0, td, event_trb);
1392                         goto td_cleanup;
1393                 }
1394                 /*
1395                  * Did we transfer any data, despite the errors that might have
1396                  * happened?  I.e. did we get past the setup stage?
1397                  */
1398                 if (event_trb != ep_ring->dequeue) {
1399                         /* The event was for the status stage */
1400                         if (event_trb == td->last_trb) {
1401                                 if (td->urb->actual_length != 0) {
1402                                         /* Don't overwrite a previously set error code */
1403                                         if ((status == -EINPROGRESS ||
1404                                                                 status == 0) &&
1405                                                         (td->urb->transfer_flags
1406                                                          & URB_SHORT_NOT_OK))
1407                                                 /* Did we already see a short data stage? */
1408                                                 status = -EREMOTEIO;
1409                                 } else {
1410                                         td->urb->actual_length =
1411                                                 td->urb->transfer_buffer_length;
1412                                 }
1413                         } else {
1414                         /* Maybe the event was for the data stage? */
1415                                 if (trb_comp_code != COMP_STOP_INVAL) {
1416                                         /* We didn't stop on a link TRB in the middle */
1417                                         td->urb->actual_length =
1418                                                 td->urb->transfer_buffer_length -
1419                                                 TRB_LEN(event->transfer_len);
1420                                         xhci_dbg(xhci, "Waiting for status stage event\n");
1421                                         urb = NULL;
1422                                         goto cleanup;
1423                                 }
1424                         }
1425                 }
1426         } else {
1427                 switch (trb_comp_code) {
1428                 case COMP_SUCCESS:
1429                         /* Double check that the HW transferred everything. */
1430                         if (event_trb != td->last_trb) {
1431                                 xhci_warn(xhci, "WARN Successful completion "
1432                                                 "on short TX\n");
1433                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1434                                         status = -EREMOTEIO;
1435                                 else
1436                                         status = 0;
1437                         } else {
1438                                 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1439                                         xhci_dbg(xhci, "Successful bulk "
1440                                                         "transfer!\n");
1441                                 else
1442                                         xhci_dbg(xhci, "Successful interrupt "
1443                                                         "transfer!\n");
1444                                 status = 0;
1445                         }
1446                         break;
1447                 case COMP_SHORT_TX:
1448                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1449                                 status = -EREMOTEIO;
1450                         else
1451                                 status = 0;
1452                         break;
1453                 default:
1454                         /* Others already handled above */
1455                         break;
1456                 }
1457                 dev_dbg(&td->urb->dev->dev,
1458                                 "ep %#x - asked for %d bytes, "
1459                                 "%d bytes untransferred\n",
1460                                 td->urb->ep->desc.bEndpointAddress,
1461                                 td->urb->transfer_buffer_length,
1462                                 TRB_LEN(event->transfer_len));
1463                 /* Fast path - was this the last TRB in the TD for this URB? */
1464                 if (event_trb == td->last_trb) {
1465                         if (TRB_LEN(event->transfer_len) != 0) {
1466                                 td->urb->actual_length =
1467                                         td->urb->transfer_buffer_length -
1468                                         TRB_LEN(event->transfer_len);
1469                                 if (td->urb->transfer_buffer_length <
1470                                                 td->urb->actual_length) {
1471                                         xhci_warn(xhci, "HC gave bad length "
1472                                                         "of %d bytes left\n",
1473                                                         TRB_LEN(event->transfer_len));
1474                                         td->urb->actual_length = 0;
1475                                         if (td->urb->transfer_flags &
1476                                                         URB_SHORT_NOT_OK)
1477                                                 status = -EREMOTEIO;
1478                                         else
1479                                                 status = 0;
1480                                 }
1481                                 /* Don't overwrite a previously set error code */
1482                                 if (status == -EINPROGRESS) {
1483                                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1484                                                 status = -EREMOTEIO;
1485                                         else
1486                                                 status = 0;
1487                                 }
1488                         } else {
1489                                 td->urb->actual_length = td->urb->transfer_buffer_length;
1490                                 /* Ignore a short packet completion if the
1491                                  * untransferred length was zero.
1492                                  */
1493                                 if (status == -EREMOTEIO)
1494                                         status = 0;
1495                         }
1496                 } else {
1497                         /* Slow path - walk the list, starting from the dequeue
1498                          * pointer, to get the actual length transferred.
1499                          */
1500                         union xhci_trb *cur_trb;
1501                         struct xhci_segment *cur_seg;
1502
1503                         td->urb->actual_length = 0;
1504                         for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1505                                         cur_trb != event_trb;
1506                                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1507                                 if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP &&
1508                                                 TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK)
1509                                         td->urb->actual_length +=
1510                                                 TRB_LEN(cur_trb->generic.field[2]);
1511                         }
1512                         /* If the ring didn't stop on a Link or No-op TRB, add
1513                          * in the actual bytes transferred from the Normal TRB
1514                          */
1515                         if (trb_comp_code != COMP_STOP_INVAL)
1516                                 td->urb->actual_length +=
1517                                         TRB_LEN(cur_trb->generic.field[2]) -
1518                                         TRB_LEN(event->transfer_len);
1519                 }
1520         }
1521         if (trb_comp_code == COMP_STOP_INVAL ||
1522                         trb_comp_code == COMP_STOP) {
1523                 /* The Endpoint Stop Command completion will take care of any
1524                  * stopped TDs.  A stopped TD may be restarted, so don't update
1525                  * the ring dequeue pointer or take this TD off any lists yet.
1526                  */
1527                 ep->stopped_td = td;
1528                 ep->stopped_trb = event_trb;
1529         } else {
1530                 if (trb_comp_code == COMP_STALL) {
1531                         /* The transfer is completed from the driver's
1532                          * perspective, but we need to issue a set dequeue
1533                          * command for this stalled endpoint to move the dequeue
1534                          * pointer past the TD.  We can't do that here because
1535                          * the halt condition must be cleared first.  Let the
1536                          * USB class driver clear the stall later.
1537                          */
1538                         ep->stopped_td = td;
1539                         ep->stopped_trb = event_trb;
1540                         ep->stopped_stream = ep_ring->stream_id;
1541                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1542                                         ep_ctx, trb_comp_code)) {
1543                         /* Other types of errors halt the endpoint, but the
1544                          * class driver doesn't call usb_reset_endpoint() unless
1545                          * the error is -EPIPE.  Clear the halted status in the
1546                          * xHCI hardware manually.
1547                          */
1548                         xhci_cleanup_halted_endpoint(xhci,
1549                                         slot_id, ep_index, ep_ring->stream_id, td, event_trb);
1550                 } else {
1551                         /* Update ring dequeue pointer */
1552                         while (ep_ring->dequeue != td->last_trb)
1553                                 inc_deq(xhci, ep_ring, false);
1554                         inc_deq(xhci, ep_ring, false);
1555                 }
1556
1557 td_cleanup:
1558                 /* Clean up the endpoint's TD list */
1559                 urb = td->urb;
1560                 /* Do one last check of the actual transfer length.
1561                  * If the host controller said we transferred more data than
1562                  * the buffer length, urb->actual_length will be a very big
1563                  * number (since it's unsigned).  Play it safe and say we didn't
1564                  * transfer anything.
1565                  */
1566                 if (urb->actual_length > urb->transfer_buffer_length) {
1567                         xhci_warn(xhci, "URB transfer length is wrong, "
1568                                         "xHC issue? req. len = %u, "
1569                                         "act. len = %u\n",
1570                                         urb->transfer_buffer_length,
1571                                         urb->actual_length);
1572                         urb->actual_length = 0;
1573                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1574                                 status = -EREMOTEIO;
1575                         else
1576                                 status = 0;
1577                 }
1578                 list_del(&td->td_list);
1579                 /* Was this TD slated to be cancelled but completed anyway? */
1580                 if (!list_empty(&td->cancelled_td_list))
1581                         list_del(&td->cancelled_td_list);
1582
1583                 /* Leave the TD around for the reset endpoint function to use
1584                  * (but only if it's not a control endpoint, since we already
1585                  * queued the Set TR dequeue pointer command for stalled
1586                  * control endpoints).
1587                  */
1588                 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1589                         (trb_comp_code != COMP_STALL &&
1590                                 trb_comp_code != COMP_BABBLE)) {
1591                         kfree(td);
1592                 }
1593                 urb->hcpriv = NULL;
1594         }
1595 cleanup:
1596         inc_deq(xhci, xhci->event_ring, true);
1597         xhci_set_hc_event_deq(xhci);
1598
1599         /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1600         if (urb) {
1601                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1602                 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1603                                 urb, urb->actual_length, status);
1604                 spin_unlock(&xhci->lock);
1605                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1606                 spin_lock(&xhci->lock);
1607         }
1608         return 0;
1609 }
1610
1611 /*
1612  * This function handles all OS-owned events on the event ring.  It may drop
1613  * xhci->lock between event processing (e.g. to pass up port status changes).
1614  */
1615 void xhci_handle_event(struct xhci_hcd *xhci)
1616 {
1617         union xhci_trb *event;
1618         int update_ptrs = 1;
1619         int ret;
1620
1621         xhci_dbg(xhci, "In %s\n", __func__);
1622         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1623                 xhci->error_bitmask |= 1 << 1;
1624                 return;
1625         }
1626
1627         event = xhci->event_ring->dequeue;
1628         /* Does the HC or OS own the TRB? */
1629         if ((event->event_cmd.flags & TRB_CYCLE) !=
1630                         xhci->event_ring->cycle_state) {
1631                 xhci->error_bitmask |= 1 << 2;
1632                 return;
1633         }
1634         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1635
1636         /* FIXME: Handle more event types. */
1637         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1638         case TRB_TYPE(TRB_COMPLETION):
1639                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1640                 handle_cmd_completion(xhci, &event->event_cmd);
1641                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1642                 break;
1643         case TRB_TYPE(TRB_PORT_STATUS):
1644                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1645                 handle_port_status(xhci, event);
1646                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1647                 update_ptrs = 0;
1648                 break;
1649         case TRB_TYPE(TRB_TRANSFER):
1650                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1651                 ret = handle_tx_event(xhci, &event->trans_event);
1652                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1653                 if (ret < 0)
1654                         xhci->error_bitmask |= 1 << 9;
1655                 else
1656                         update_ptrs = 0;
1657                 break;
1658         default:
1659                 xhci->error_bitmask |= 1 << 3;
1660         }
1661         /* Any of the above functions may drop and re-acquire the lock, so check
1662          * to make sure a watchdog timer didn't mark the host as non-responsive.
1663          */
1664         if (xhci->xhc_state & XHCI_STATE_DYING) {
1665                 xhci_dbg(xhci, "xHCI host dying, returning from "
1666                                 "event handler.\n");
1667                 return;
1668         }
1669
1670         if (update_ptrs) {
1671                 /* Update SW and HC event ring dequeue pointer */
1672                 inc_deq(xhci, xhci->event_ring, true);
1673                 xhci_set_hc_event_deq(xhci);
1674         }
1675         /* Are there more items on the event ring? */
1676         xhci_handle_event(xhci);
1677 }
1678
1679 /****           Endpoint Ring Operations        ****/
1680
1681 /*
1682  * Generic function for queueing a TRB on a ring.
1683  * The caller must have checked to make sure there's room on the ring.
1684  */
1685 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1686                 bool consumer,
1687                 u32 field1, u32 field2, u32 field3, u32 field4)
1688 {
1689         struct xhci_generic_trb *trb;
1690
1691         trb = &ring->enqueue->generic;
1692         trb->field[0] = field1;
1693         trb->field[1] = field2;
1694         trb->field[2] = field3;
1695         trb->field[3] = field4;
1696         inc_enq(xhci, ring, consumer);
1697 }
1698
1699 /*
1700  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1701  * FIXME allocate segments if the ring is full.
1702  */
1703 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1704                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1705 {
1706         /* Make sure the endpoint has been added to xHC schedule */
1707         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1708         switch (ep_state) {
1709         case EP_STATE_DISABLED:
1710                 /*
1711                  * USB core changed config/interfaces without notifying us,
1712                  * or hardware is reporting the wrong state.
1713                  */
1714                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1715                 return -ENOENT;
1716         case EP_STATE_ERROR:
1717                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1718                 /* FIXME event handling code for error needs to clear it */
1719                 /* XXX not sure if this should be -ENOENT or not */
1720                 return -EINVAL;
1721         case EP_STATE_HALTED:
1722                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1723         case EP_STATE_STOPPED:
1724         case EP_STATE_RUNNING:
1725                 break;
1726         default:
1727                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1728                 /*
1729                  * FIXME issue Configure Endpoint command to try to get the HC
1730                  * back into a known state.
1731                  */
1732                 return -EINVAL;
1733         }
1734         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1735                 /* FIXME allocate more room */
1736                 xhci_err(xhci, "ERROR no room on ep ring\n");
1737                 return -ENOMEM;
1738         }
1739
1740         if (enqueue_is_link_trb(ep_ring)) {
1741                 struct xhci_ring *ring = ep_ring;
1742                 union xhci_trb *next;
1743                 unsigned long long addr;
1744
1745                 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
1746                 next = ring->enqueue;
1747
1748                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
1749
1750                         /* If we're not dealing with 0.95 hardware,
1751                          * clear the chain bit.
1752                          */
1753                         if (!xhci_link_trb_quirk(xhci))
1754                                 next->link.control &= ~TRB_CHAIN;
1755                         else
1756                                 next->link.control |= TRB_CHAIN;
1757
1758                         wmb();
1759                         next->link.control ^= (u32) TRB_CYCLE;
1760
1761                         /* Toggle the cycle bit after the last ring segment. */
1762                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
1763                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
1764                                 if (!in_interrupt()) {
1765                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
1766                                                 "state for ring %p = %i\n",
1767                                                 ring, (unsigned int)ring->cycle_state);
1768                                 }
1769                         }
1770                         ring->enq_seg = ring->enq_seg->next;
1771                         ring->enqueue = ring->enq_seg->trbs;
1772                         next = ring->enqueue;
1773                 }
1774         }
1775
1776         return 0;
1777 }
1778
1779 static int prepare_transfer(struct xhci_hcd *xhci,
1780                 struct xhci_virt_device *xdev,
1781                 unsigned int ep_index,
1782                 unsigned int stream_id,
1783                 unsigned int num_trbs,
1784                 struct urb *urb,
1785                 struct xhci_td **td,
1786                 gfp_t mem_flags)
1787 {
1788         int ret;
1789         struct xhci_ring *ep_ring;
1790         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1791
1792         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
1793         if (!ep_ring) {
1794                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
1795                                 stream_id);
1796                 return -EINVAL;
1797         }
1798
1799         ret = prepare_ring(xhci, ep_ring,
1800                         ep_ctx->ep_info & EP_STATE_MASK,
1801                         num_trbs, mem_flags);
1802         if (ret)
1803                 return ret;
1804         *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1805         if (!*td)
1806                 return -ENOMEM;
1807         INIT_LIST_HEAD(&(*td)->td_list);
1808         INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1809
1810         ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1811         if (unlikely(ret)) {
1812                 kfree(*td);
1813                 return ret;
1814         }
1815
1816         (*td)->urb = urb;
1817         urb->hcpriv = (void *) (*td);
1818         /* Add this TD to the tail of the endpoint ring's TD list */
1819         list_add_tail(&(*td)->td_list, &ep_ring->td_list);
1820         (*td)->start_seg = ep_ring->enq_seg;
1821         (*td)->first_trb = ep_ring->enqueue;
1822
1823         return 0;
1824 }
1825
1826 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1827 {
1828         int num_sgs, num_trbs, running_total, temp, i;
1829         struct scatterlist *sg;
1830
1831         sg = NULL;
1832         num_sgs = urb->num_sgs;
1833         temp = urb->transfer_buffer_length;
1834
1835         xhci_dbg(xhci, "count sg list trbs: \n");
1836         num_trbs = 0;
1837         for_each_sg(urb->sg, sg, num_sgs, i) {
1838                 unsigned int previous_total_trbs = num_trbs;
1839                 unsigned int len = sg_dma_len(sg);
1840
1841                 /* Scatter gather list entries may cross 64KB boundaries */
1842                 running_total = TRB_MAX_BUFF_SIZE -
1843                         (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1844                 if (running_total != 0)
1845                         num_trbs++;
1846
1847                 /* How many more 64KB chunks to transfer, how many more TRBs? */
1848                 while (running_total < sg_dma_len(sg)) {
1849                         num_trbs++;
1850                         running_total += TRB_MAX_BUFF_SIZE;
1851                 }
1852                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1853                                 i, (unsigned long long)sg_dma_address(sg),
1854                                 len, len, num_trbs - previous_total_trbs);
1855
1856                 len = min_t(int, len, temp);
1857                 temp -= len;
1858                 if (temp == 0)
1859                         break;
1860         }
1861         xhci_dbg(xhci, "\n");
1862         if (!in_interrupt())
1863                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1864                                 urb->ep->desc.bEndpointAddress,
1865                                 urb->transfer_buffer_length,
1866                                 num_trbs);
1867         return num_trbs;
1868 }
1869
1870 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1871 {
1872         if (num_trbs != 0)
1873                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1874                                 "TRBs, %d left\n", __func__,
1875                                 urb->ep->desc.bEndpointAddress, num_trbs);
1876         if (running_total != urb->transfer_buffer_length)
1877                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1878                                 "queued %#x (%d), asked for %#x (%d)\n",
1879                                 __func__,
1880                                 urb->ep->desc.bEndpointAddress,
1881                                 running_total, running_total,
1882                                 urb->transfer_buffer_length,
1883                                 urb->transfer_buffer_length);
1884 }
1885
1886 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1887                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
1888                 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1889 {
1890         /*
1891          * Pass all the TRBs to the hardware at once and make sure this write
1892          * isn't reordered.
1893          */
1894         wmb();
1895         start_trb->field[3] |= start_cycle;
1896         ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
1897 }
1898
1899 /*
1900  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
1901  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
1902  * (comprised of sg list entries) can take several service intervals to
1903  * transmit.
1904  */
1905 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1906                 struct urb *urb, int slot_id, unsigned int ep_index)
1907 {
1908         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
1909                         xhci->devs[slot_id]->out_ctx, ep_index);
1910         int xhci_interval;
1911         int ep_interval;
1912
1913         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
1914         ep_interval = urb->interval;
1915         /* Convert to microframes */
1916         if (urb->dev->speed == USB_SPEED_LOW ||
1917                         urb->dev->speed == USB_SPEED_FULL)
1918                 ep_interval *= 8;
1919         /* FIXME change this to a warning and a suggestion to use the new API
1920          * to set the polling interval (once the API is added).
1921          */
1922         if (xhci_interval != ep_interval) {
1923                 if (!printk_ratelimit())
1924                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
1925                                         " (%d microframe%s) than xHCI "
1926                                         "(%d microframe%s)\n",
1927                                         ep_interval,
1928                                         ep_interval == 1 ? "" : "s",
1929                                         xhci_interval,
1930                                         xhci_interval == 1 ? "" : "s");
1931                 urb->interval = xhci_interval;
1932                 /* Convert back to frames for LS/FS devices */
1933                 if (urb->dev->speed == USB_SPEED_LOW ||
1934                                 urb->dev->speed == USB_SPEED_FULL)
1935                         urb->interval /= 8;
1936         }
1937         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
1938 }
1939
1940 /*
1941  * The TD size is the number of bytes remaining in the TD (including this TRB),
1942  * right shifted by 10.
1943  * It must fit in bits 21:17, so it can't be bigger than 31.
1944  */
1945 static u32 xhci_td_remainder(unsigned int remainder)
1946 {
1947         u32 max = (1 << (21 - 17 + 1)) - 1;
1948
1949         if ((remainder >> 10) >= max)
1950                 return max << 17;
1951         else
1952                 return (remainder >> 10) << 17;
1953 }
1954
1955 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1956                 struct urb *urb, int slot_id, unsigned int ep_index)
1957 {
1958         struct xhci_ring *ep_ring;
1959         unsigned int num_trbs;
1960         struct xhci_td *td;
1961         struct scatterlist *sg;
1962         int num_sgs;
1963         int trb_buff_len, this_sg_len, running_total;
1964         bool first_trb;
1965         u64 addr;
1966
1967         struct xhci_generic_trb *start_trb;
1968         int start_cycle;
1969
1970         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1971         if (!ep_ring)
1972                 return -EINVAL;
1973
1974         num_trbs = count_sg_trbs_needed(xhci, urb);
1975         num_sgs = urb->num_sgs;
1976
1977         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1978                         ep_index, urb->stream_id,
1979                         num_trbs, urb, &td, mem_flags);
1980         if (trb_buff_len < 0)
1981                 return trb_buff_len;
1982         /*
1983          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1984          * until we've finished creating all the other TRBs.  The ring's cycle
1985          * state may change as we enqueue the other TRBs, so save it too.
1986          */
1987         start_trb = &ep_ring->enqueue->generic;
1988         start_cycle = ep_ring->cycle_state;
1989
1990         running_total = 0;
1991         /*
1992          * How much data is in the first TRB?
1993          *
1994          * There are three forces at work for TRB buffer pointers and lengths:
1995          * 1. We don't want to walk off the end of this sg-list entry buffer.
1996          * 2. The transfer length that the driver requested may be smaller than
1997          *    the amount of memory allocated for this scatter-gather list.
1998          * 3. TRBs buffers can't cross 64KB boundaries.
1999          */
2000         sg = urb->sg;
2001         addr = (u64) sg_dma_address(sg);
2002         this_sg_len = sg_dma_len(sg);
2003         trb_buff_len = TRB_MAX_BUFF_SIZE -
2004                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2005         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2006         if (trb_buff_len > urb->transfer_buffer_length)
2007                 trb_buff_len = urb->transfer_buffer_length;
2008         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2009                         trb_buff_len);
2010
2011         first_trb = true;
2012         /* Queue the first TRB, even if it's zero-length */
2013         do {
2014                 u32 field = 0;
2015                 u32 length_field = 0;
2016                 u32 remainder = 0;
2017
2018                 /* Don't change the cycle bit of the first TRB until later */
2019                 if (first_trb)
2020                         first_trb = false;
2021                 else
2022                         field |= ep_ring->cycle_state;
2023
2024                 /* Chain all the TRBs together; clear the chain bit in the last
2025                  * TRB to indicate it's the last TRB in the chain.
2026                  */
2027                 if (num_trbs > 1) {
2028                         field |= TRB_CHAIN;
2029                 } else {
2030                         /* FIXME - add check for ZERO_PACKET flag before this */
2031                         td->last_trb = ep_ring->enqueue;
2032                         field |= TRB_IOC;
2033                 }
2034                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2035                                 "64KB boundary at %#x, end dma = %#x\n",
2036                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2037                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2038                                 (unsigned int) addr + trb_buff_len);
2039                 if (TRB_MAX_BUFF_SIZE -
2040                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
2041                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2042                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2043                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2044                                         (unsigned int) addr + trb_buff_len);
2045                 }
2046                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2047                                 running_total) ;
2048                 length_field = TRB_LEN(trb_buff_len) |
2049                         remainder |
2050                         TRB_INTR_TARGET(0);
2051                 queue_trb(xhci, ep_ring, false,
2052                                 lower_32_bits(addr),
2053                                 upper_32_bits(addr),
2054                                 length_field,
2055                                 /* We always want to know if the TRB was short,
2056                                  * or we won't get an event when it completes.
2057                                  * (Unless we use event data TRBs, which are a
2058                                  * waste of space and HC resources.)
2059                                  */
2060                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2061                 --num_trbs;
2062                 running_total += trb_buff_len;
2063
2064                 /* Calculate length for next transfer --
2065                  * Are we done queueing all the TRBs for this sg entry?
2066                  */
2067                 this_sg_len -= trb_buff_len;
2068                 if (this_sg_len == 0) {
2069                         --num_sgs;
2070                         if (num_sgs == 0)
2071                                 break;
2072                         sg = sg_next(sg);
2073                         addr = (u64) sg_dma_address(sg);
2074                         this_sg_len = sg_dma_len(sg);
2075                 } else {
2076                         addr += trb_buff_len;
2077                 }
2078
2079                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2080                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2081                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2082                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2083                         trb_buff_len =
2084                                 urb->transfer_buffer_length - running_total;
2085         } while (running_total < urb->transfer_buffer_length);
2086
2087         check_trb_math(urb, num_trbs, running_total);
2088         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2089                         start_cycle, start_trb, td);
2090         return 0;
2091 }
2092
2093 /* This is very similar to what ehci-q.c qtd_fill() does */
2094 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2095                 struct urb *urb, int slot_id, unsigned int ep_index)
2096 {
2097         struct xhci_ring *ep_ring;
2098         struct xhci_td *td;
2099         int num_trbs;
2100         struct xhci_generic_trb *start_trb;
2101         bool first_trb;
2102         int start_cycle;
2103         u32 field, length_field;
2104
2105         int running_total, trb_buff_len, ret;
2106         u64 addr;
2107
2108         if (urb->num_sgs)
2109                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2110
2111         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2112         if (!ep_ring)
2113                 return -EINVAL;
2114
2115         num_trbs = 0;
2116         /* How much data is (potentially) left before the 64KB boundary? */
2117         running_total = TRB_MAX_BUFF_SIZE -
2118                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2119
2120         /* If there's some data on this 64KB chunk, or we have to send a
2121          * zero-length transfer, we need at least one TRB
2122          */
2123         if (running_total != 0 || urb->transfer_buffer_length == 0)
2124                 num_trbs++;
2125         /* How many more 64KB chunks to transfer, how many more TRBs? */
2126         while (running_total < urb->transfer_buffer_length) {
2127                 num_trbs++;
2128                 running_total += TRB_MAX_BUFF_SIZE;
2129         }
2130         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2131
2132         if (!in_interrupt())
2133                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
2134                                 urb->ep->desc.bEndpointAddress,
2135                                 urb->transfer_buffer_length,
2136                                 urb->transfer_buffer_length,
2137                                 (unsigned long long)urb->transfer_dma,
2138                                 num_trbs);
2139
2140         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2141                         ep_index, urb->stream_id,
2142                         num_trbs, urb, &td, mem_flags);
2143         if (ret < 0)
2144                 return ret;
2145
2146         /*
2147          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2148          * until we've finished creating all the other TRBs.  The ring's cycle
2149          * state may change as we enqueue the other TRBs, so save it too.
2150          */
2151         start_trb = &ep_ring->enqueue->generic;
2152         start_cycle = ep_ring->cycle_state;
2153
2154         running_total = 0;
2155         /* How much data is in the first TRB? */
2156         addr = (u64) urb->transfer_dma;
2157         trb_buff_len = TRB_MAX_BUFF_SIZE -
2158                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2159         if (urb->transfer_buffer_length < trb_buff_len)
2160                 trb_buff_len = urb->transfer_buffer_length;
2161
2162         first_trb = true;
2163
2164         /* Queue the first TRB, even if it's zero-length */
2165         do {
2166                 u32 remainder = 0;
2167                 field = 0;
2168
2169                 /* Don't change the cycle bit of the first TRB until later */
2170                 if (first_trb)
2171                         first_trb = false;
2172                 else
2173                         field |= ep_ring->cycle_state;
2174
2175                 /* Chain all the TRBs together; clear the chain bit in the last
2176                  * TRB to indicate it's the last TRB in the chain.
2177                  */
2178                 if (num_trbs > 1) {
2179                         field |= TRB_CHAIN;
2180                 } else {
2181                         /* FIXME - add check for ZERO_PACKET flag before this */
2182                         td->last_trb = ep_ring->enqueue;
2183                         field |= TRB_IOC;
2184                 }
2185                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2186                                 running_total);
2187                 length_field = TRB_LEN(trb_buff_len) |
2188                         remainder |
2189                         TRB_INTR_TARGET(0);
2190                 queue_trb(xhci, ep_ring, false,
2191                                 lower_32_bits(addr),
2192                                 upper_32_bits(addr),
2193                                 length_field,
2194                                 /* We always want to know if the TRB was short,
2195                                  * or we won't get an event when it completes.
2196                                  * (Unless we use event data TRBs, which are a
2197                                  * waste of space and HC resources.)
2198                                  */
2199                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2200                 --num_trbs;
2201                 running_total += trb_buff_len;
2202
2203                 /* Calculate length for next transfer */
2204                 addr += trb_buff_len;
2205                 trb_buff_len = urb->transfer_buffer_length - running_total;
2206                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2207                         trb_buff_len = TRB_MAX_BUFF_SIZE;
2208         } while (running_total < urb->transfer_buffer_length);
2209
2210         check_trb_math(urb, num_trbs, running_total);
2211         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2212                         start_cycle, start_trb, td);
2213         return 0;
2214 }
2215
2216 /* Caller must have locked xhci->lock */
2217 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2218                 struct urb *urb, int slot_id, unsigned int ep_index)
2219 {
2220         struct xhci_ring *ep_ring;
2221         int num_trbs;
2222         int ret;
2223         struct usb_ctrlrequest *setup;
2224         struct xhci_generic_trb *start_trb;
2225         int start_cycle;
2226         u32 field, length_field;
2227         struct xhci_td *td;
2228
2229         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2230         if (!ep_ring)
2231                 return -EINVAL;
2232
2233         /*
2234          * Need to copy setup packet into setup TRB, so we can't use the setup
2235          * DMA address.
2236          */
2237         if (!urb->setup_packet)
2238                 return -EINVAL;
2239
2240         if (!in_interrupt())
2241                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2242                                 slot_id, ep_index);
2243         /* 1 TRB for setup, 1 for status */
2244         num_trbs = 2;
2245         /*
2246          * Don't need to check if we need additional event data and normal TRBs,
2247          * since data in control transfers will never get bigger than 16MB
2248          * XXX: can we get a buffer that crosses 64KB boundaries?
2249          */
2250         if (urb->transfer_buffer_length > 0)
2251                 num_trbs++;
2252         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2253                         ep_index, urb->stream_id,
2254                         num_trbs, urb, &td, mem_flags);
2255         if (ret < 0)
2256                 return ret;
2257
2258         /*
2259          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2260          * until we've finished creating all the other TRBs.  The ring's cycle
2261          * state may change as we enqueue the other TRBs, so save it too.
2262          */
2263         start_trb = &ep_ring->enqueue->generic;
2264         start_cycle = ep_ring->cycle_state;
2265
2266         /* Queue setup TRB - see section 6.4.1.2.1 */
2267         /* FIXME better way to translate setup_packet into two u32 fields? */
2268         setup = (struct usb_ctrlrequest *) urb->setup_packet;
2269         queue_trb(xhci, ep_ring, false,
2270                         /* FIXME endianness is probably going to bite my ass here. */
2271                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2272                         setup->wIndex | setup->wLength << 16,
2273                         TRB_LEN(8) | TRB_INTR_TARGET(0),
2274                         /* Immediate data in pointer */
2275                         TRB_IDT | TRB_TYPE(TRB_SETUP));
2276
2277         /* If there's data, queue data TRBs */
2278         field = 0;
2279         length_field = TRB_LEN(urb->transfer_buffer_length) |
2280                 xhci_td_remainder(urb->transfer_buffer_length) |
2281                 TRB_INTR_TARGET(0);
2282         if (urb->transfer_buffer_length > 0) {
2283                 if (setup->bRequestType & USB_DIR_IN)
2284                         field |= TRB_DIR_IN;
2285                 queue_trb(xhci, ep_ring, false,
2286                                 lower_32_bits(urb->transfer_dma),
2287                                 upper_32_bits(urb->transfer_dma),
2288                                 length_field,
2289                                 /* Event on short tx */
2290                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2291         }
2292
2293         /* Save the DMA address of the last TRB in the TD */
2294         td->last_trb = ep_ring->enqueue;
2295
2296         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2297         /* If the device sent data, the status stage is an OUT transfer */
2298         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2299                 field = 0;
2300         else
2301                 field = TRB_DIR_IN;
2302         queue_trb(xhci, ep_ring, false,
2303                         0,
2304                         0,
2305                         TRB_INTR_TARGET(0),
2306                         /* Event on completion */
2307                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2308
2309         giveback_first_trb(xhci, slot_id, ep_index, 0,
2310                         start_cycle, start_trb, td);
2311         return 0;
2312 }
2313
2314 /****           Command Ring Operations         ****/
2315
2316 /* Generic function for queueing a command TRB on the command ring.
2317  * Check to make sure there's room on the command ring for one command TRB.
2318  * Also check that there's room reserved for commands that must not fail.
2319  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
2320  * then only check for the number of reserved spots.
2321  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
2322  * because the command event handler may want to resubmit a failed command.
2323  */
2324 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
2325                 u32 field3, u32 field4, bool command_must_succeed)
2326 {
2327         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
2328         if (!command_must_succeed)
2329                 reserved_trbs++;
2330
2331         if (!room_on_ring(xhci, xhci->cmd_ring, reserved_trbs)) {
2332                 if (!in_interrupt())
2333                         xhci_err(xhci, "ERR: No room for command on command ring\n");
2334                 if (command_must_succeed)
2335                         xhci_err(xhci, "ERR: Reserved TRB counting for "
2336                                         "unfailable commands failed.\n");
2337                 return -ENOMEM;
2338         }
2339         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
2340                         field4 | xhci->cmd_ring->cycle_state);
2341         return 0;
2342 }
2343
2344 /* Queue a no-op command on the command ring */
2345 static int queue_cmd_noop(struct xhci_hcd *xhci)
2346 {
2347         return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
2348 }
2349
2350 /*
2351  * Place a no-op command on the command ring to test the command and
2352  * event ring.
2353  */
2354 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
2355 {
2356         if (queue_cmd_noop(xhci) < 0)
2357                 return NULL;
2358         xhci->noops_submitted++;
2359         return xhci_ring_cmd_db;
2360 }
2361
2362 /* Queue a slot enable or disable request on the command ring */
2363 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
2364 {
2365         return queue_command(xhci, 0, 0, 0,
2366                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
2367 }
2368
2369 /* Queue an address device command TRB */
2370 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2371                 u32 slot_id)
2372 {
2373         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2374                         upper_32_bits(in_ctx_ptr), 0,
2375                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
2376                         false);
2377 }
2378
2379 /* Queue a reset device command TRB */
2380 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
2381 {
2382         return queue_command(xhci, 0, 0, 0,
2383                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
2384                         false);
2385 }
2386
2387 /* Queue a configure endpoint command TRB */
2388 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2389                 u32 slot_id, bool command_must_succeed)
2390 {
2391         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2392                         upper_32_bits(in_ctx_ptr), 0,
2393                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
2394                         command_must_succeed);
2395 }
2396
2397 /* Queue an evaluate context command TRB */
2398 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2399                 u32 slot_id)
2400 {
2401         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2402                         upper_32_bits(in_ctx_ptr), 0,
2403                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
2404                         false);
2405 }
2406
2407 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
2408                 unsigned int ep_index)
2409 {
2410         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2411         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2412         u32 type = TRB_TYPE(TRB_STOP_RING);
2413
2414         return queue_command(xhci, 0, 0, 0,
2415                         trb_slot_id | trb_ep_index | type, false);
2416 }
2417
2418 /* Set Transfer Ring Dequeue Pointer command.
2419  * This should not be used for endpoints that have streams enabled.
2420  */
2421 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
2422                 unsigned int ep_index, unsigned int stream_id,
2423                 struct xhci_segment *deq_seg,
2424                 union xhci_trb *deq_ptr, u32 cycle_state)
2425 {
2426         dma_addr_t addr;
2427         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2428         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2429         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
2430         u32 type = TRB_TYPE(TRB_SET_DEQ);
2431
2432         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
2433         if (addr == 0) {
2434                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
2435                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
2436                                 deq_seg, deq_ptr);
2437                 return 0;
2438         }
2439         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
2440                         upper_32_bits(addr), trb_stream_id,
2441                         trb_slot_id | trb_ep_index | type, false);
2442 }
2443
2444 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
2445                 unsigned int ep_index)
2446 {
2447         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2448         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2449         u32 type = TRB_TYPE(TRB_RESET_EP);
2450
2451         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
2452                         false);
2453 }