drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70 #include "xhci-trace.h"
  71
  72 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  73                 struct xhci_virt_device *virt_dev,
  74                 struct xhci_event_cmd *event);
  75
  76 /*
  77  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  78  * address of the TRB.
  79  */
  80 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  81                 union xhci_trb *trb)
  82 {
  83         unsigned long segment_offset;
  84
  85         if (!seg || !trb || trb < seg->trbs)
  86                 return 0;
  87         /* offset in TRBs */
  88         segment_offset = trb - seg->trbs;
  89         if (segment_offset > TRBS_PER_SEGMENT)
  90                 return 0;
  91         return seg->dma + (segment_offset * sizeof(*trb));
  92 }
  93
  94 /* Does this link TRB point to the first segment in a ring,
  95  * or was the previous TRB the last TRB on the last segment in the ERST?
  96  */
  97 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  98                 struct xhci_segment *seg, union xhci_trb *trb)
  99 {
 100         if (ring == xhci->event_ring)
 101                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 102                         (seg->next == xhci->event_ring->first_seg);
 103         else
 104                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 105 }
 106
 107 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 108  * segment?  I.e. would the updated event TRB pointer step off the end of the
 109  * event seg?
 110  */
 111 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 112                 struct xhci_segment *seg, union xhci_trb *trb)
 113 {
 114         if (ring == xhci->event_ring)
 115                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 116         else
 117                 return TRB_TYPE_LINK_LE32(trb->link.control);
 118 }
 119
 120 static int enqueue_is_link_trb(struct xhci_ring *ring)
 121 {
 122         struct xhci_link_trb *link = &ring->enqueue->link;
 123         return TRB_TYPE_LINK_LE32(link->control);
 124 }
 125
 126 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring)
 127 {
 128         /* Enqueue pointer can be left pointing to the link TRB,
 129          * we must handle that
 130          */
 131         if (TRB_TYPE_LINK_LE32(ring->enqueue->link.control))
 132                 return ring->enq_seg->next->trbs;
 133         return ring->enqueue;
 134 }
 135
 136 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 137  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 138  * effect the ring dequeue or enqueue pointers.
 139  */
 140 static void next_trb(struct xhci_hcd *xhci,
 141                 struct xhci_ring *ring,
 142                 struct xhci_segment **seg,
 143                 union xhci_trb **trb)
 144 {
 145         if (last_trb(xhci, ring, *seg, *trb)) {
 146                 *seg = (*seg)->next;
 147                 *trb = ((*seg)->trbs);
 148         } else {
 149                 (*trb)++;
 150         }
 151 }
 152
 153 /*
 154  * See Cycle bit rules. SW is the consumer for the event ring only.
 155  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 156  */
 157 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 158 {
 159         unsigned long long addr;
 160
 161         ring->deq_updates++;
 162
 163         /*
 164          * If this is not event ring, and the dequeue pointer
 165          * is not on a link TRB, there is one more usable TRB
 166          */
 167         if (ring->type != TYPE_EVENT &&
 168                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 169                 ring->num_trbs_free++;
 170
 171         do {
 172                 /*
 173                  * Update the dequeue pointer further if that was a link TRB or
 174                  * we're at the end of an event ring segment (which doesn't have
 175                  * link TRBS)
 176                  */
 177                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 178                         if (ring->type == TYPE_EVENT &&
 179                                         last_trb_on_last_seg(xhci, ring,
 180                                                 ring->deq_seg, ring->dequeue)) {
 181                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 182                         }
 183                         ring->deq_seg = ring->deq_seg->next;
 184                         ring->dequeue = ring->deq_seg->trbs;
 185                 } else {
 186                         ring->dequeue++;
 187                 }
 188         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 189
 190         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 191 }
 192
 193 /*
 194  * See Cycle bit rules. SW is the consumer for the event ring only.
 195  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 196  *
 197  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 198  * chain bit is set), then set the chain bit in all the following link TRBs.
 199  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 200  * have their chain bit cleared (so that each Link TRB is a separate TD).
 201  *
 202  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 203  * set, but other sections talk about dealing with the chain bit set.  This was
 204  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 205  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 206  *
 207  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 208  *                      prepare_transfer()?
 209  */
 210 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 211                         bool more_trbs_coming)
 212 {
 213         u32 chain;
 214         union xhci_trb *next;
 215         unsigned long long addr;
 216
 217         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 218         /* If this is not event ring, there is one less usable TRB */
 219         if (ring->type != TYPE_EVENT &&
 220                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 221                 ring->num_trbs_free--;
 222         next = ++(ring->enqueue);
 223
 224         ring->enq_updates++;
 225         /* Update the dequeue pointer further if that was a link TRB or we're at
 226          * the end of an event ring segment (which doesn't have link TRBS)
 227          */
 228         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 229                 if (ring->type != TYPE_EVENT) {
 230                         /*
 231                          * If the caller doesn't plan on enqueueing more
 232                          * TDs before ringing the doorbell, then we
 233                          * don't want to give the link TRB to the
 234                          * hardware just yet.  We'll give the link TRB
 235                          * back in prepare_ring() just before we enqueue
 236                          * the TD at the top of the ring.
 237                          */
 238                         if (!chain && !more_trbs_coming)
 239                                 break;
 240
 241                         /* If we're not dealing with 0.95 hardware or
 242                          * isoc rings on AMD 0.96 host,
 243                          * carry over the chain bit of the previous TRB
 244                          * (which may mean the chain bit is cleared).
 245                          */
 246                         if (!(ring->type == TYPE_ISOC &&
 247                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
 248                                                 && !xhci_link_trb_quirk(xhci)) {
 249                                 next->link.control &=
 250                                         cpu_to_le32(~TRB_CHAIN);
 251                                 next->link.control |=
 252                                         cpu_to_le32(chain);
 253                         }
 254                         /* Give this link TRB to the hardware */
 255                         wmb();
 256                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
 257
 258                         /* Toggle the cycle bit after the last ring segment. */
 259                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 260                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 261                         }
 262                 }
 263                 ring->enq_seg = ring->enq_seg->next;
 264                 ring->enqueue = ring->enq_seg->trbs;
 265                 next = ring->enqueue;
 266         }
 267         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 268 }
 269
 270 /*
 271  * Check to see if there's room to enqueue num_trbs on the ring and make sure
 272  * enqueue pointer will not advance into dequeue segment. See rules above.
 273  */
 274 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 275                 unsigned int num_trbs)
 276 {
 277         int num_trbs_in_deq_seg;
 278
 279         if (ring->num_trbs_free < num_trbs)
 280                 return 0;
 281
 282         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 283                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 284                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 285                         return 0;
 286         }
 287
 288         return 1;
 289 }
 290
 291 /* Ring the host controller doorbell after placing a command on the ring */
 292 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 293 {
 294         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 295                 return;
 296
 297         xhci_dbg(xhci, "// Ding dong!\n");
 298         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 299         /* Flush PCI posted writes */
 300         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 301 }
 302
 303 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 304 {
 305         u64 temp_64;
 306         int ret;
 307
 308         xhci_dbg(xhci, "Abort command ring\n");
 309
 310         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 311                 xhci_dbg(xhci, "The command ring isn't running, "
 312                                 "Have the command ring been stopped?\n");
 313                 return 0;
 314         }
 315
 316         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 317         if (!(temp_64 & CMD_RING_RUNNING)) {
 318                 xhci_dbg(xhci, "Command ring had been stopped\n");
 319                 return 0;
 320         }
 321         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 322         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 323                         &xhci->op_regs->cmd_ring);
 324
 325         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 326          * time the completion od all xHCI commands, including
 327          * the Command Abort operation. If software doesn't see
 328          * CRR negated in a timely manner (e.g. longer than 5
 329          * seconds), then it should assume that the there are
 330          * larger problems with the xHC and assert HCRST.
 331          */
 332         ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
 333                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 334         if (ret < 0) {
 335                 xhci_err(xhci, "Stopped the command ring failed, "
 336                                 "maybe the host is dead\n");
 337                 xhci->xhc_state |= XHCI_STATE_DYING;
 338                 xhci_quiesce(xhci);
 339                 xhci_halt(xhci);
 340                 return -ESHUTDOWN;
 341         }
 342
 343         return 0;
 344 }
 345
 346 static int xhci_queue_cd(struct xhci_hcd *xhci,
 347                 struct xhci_command *command,
 348                 union xhci_trb *cmd_trb)
 349 {
 350         struct xhci_cd *cd;
 351         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 352         if (!cd)
 353                 return -ENOMEM;
 354         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 355
 356         cd->command = command;
 357         cd->cmd_trb = cmd_trb;
 358         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 359
 360         return 0;
 361 }
 362
 363 /*
 364  * Cancel the command which has issue.
 365  *
 366  * Some commands may hang due to waiting for acknowledgement from
 367  * usb device. It is outside of the xHC's ability to control and
 368  * will cause the command ring is blocked. When it occurs software
 369  * should intervene to recover the command ring.
 370  * See Section 4.6.1.1 and 4.6.1.2
 371  */
 372 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 373                 union xhci_trb *cmd_trb)
 374 {
 375         int retval = 0;
 376         unsigned long flags;
 377
 378         spin_lock_irqsave(&xhci->lock, flags);
 379
 380         if (xhci->xhc_state & XHCI_STATE_DYING) {
 381                 xhci_warn(xhci, "Abort the command ring,"
 382                                 " but the xHCI is dead.\n");
 383                 retval = -ESHUTDOWN;
 384                 goto fail;
 385         }
 386
 387         /* queue the cmd desriptor to cancel_cmd_list */
 388         retval = xhci_queue_cd(xhci, command, cmd_trb);
 389         if (retval) {
 390                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 391                 goto fail;
 392         }
 393
 394         /* abort command ring */
 395         retval = xhci_abort_cmd_ring(xhci);
 396         if (retval) {
 397                 xhci_err(xhci, "Abort command ring failed\n");
 398                 if (unlikely(retval == -ESHUTDOWN)) {
 399                         spin_unlock_irqrestore(&xhci->lock, flags);
 400                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 401                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 402                         return retval;
 403                 }
 404         }
 405
 406 fail:
 407         spin_unlock_irqrestore(&xhci->lock, flags);
 408         return retval;
 409 }
 410
 411 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 412                 unsigned int slot_id,
 413                 unsigned int ep_index,
 414                 unsigned int stream_id)
 415 {
 416         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 417         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 418         unsigned int ep_state = ep->ep_state;
 419
 420         /* Don't ring the doorbell for this endpoint if there are pending
 421          * cancellations because we don't want to interrupt processing.
 422          * We don't want to restart any stream rings if there's a set dequeue
 423          * pointer command pending because the device can choose to start any
 424          * stream once the endpoint is on the HW schedule.
 425          * FIXME - check all the stream rings for pending cancellations.
 426          */
 427         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 428             (ep_state & EP_HALTED))
 429                 return;
 430         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 431         /* The CPU has better things to do at this point than wait for a
 432          * write-posting flush.  It'll get there soon enough.
 433          */
 434 }
 435
 436 /* Ring the doorbell for any rings with pending URBs */
 437 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 438                 unsigned int slot_id,
 439                 unsigned int ep_index)
 440 {
 441         unsigned int stream_id;
 442         struct xhci_virt_ep *ep;
 443
 444         ep = &xhci->devs[slot_id]->eps[ep_index];
 445
 446         /* A ring has pending URBs if its TD list is not empty */
 447         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 448                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 449                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 450                 return;
 451         }
 452
 453         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 454                         stream_id++) {
 455                 struct xhci_stream_info *stream_info = ep->stream_info;
 456                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 457                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 458                                                 stream_id);
 459         }
 460 }
 461
 462 /*
 463  * Find the segment that trb is in.  Start searching in start_seg.
 464  * If we must move past a segment that has a link TRB with a toggle cycle state
 465  * bit set, then we will toggle the value pointed at by cycle_state.
 466  */
 467 static struct xhci_segment *find_trb_seg(
 468                 struct xhci_segment *start_seg,
 469                 union xhci_trb  *trb, int *cycle_state)
 470 {
 471         struct xhci_segment *cur_seg = start_seg;
 472         struct xhci_generic_trb *generic_trb;
 473
 474         while (cur_seg->trbs > trb ||
 475                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 476                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 477                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 478                         *cycle_state ^= 0x1;
 479                 cur_seg = cur_seg->next;
 480                 if (cur_seg == start_seg)
 481                         /* Looped over the entire list.  Oops! */
 482                         return NULL;
 483         }
 484         return cur_seg;
 485 }
 486
 487
 488 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 489                 unsigned int slot_id, unsigned int ep_index,
 490                 unsigned int stream_id)
 491 {
 492         struct xhci_virt_ep *ep;
 493
 494         ep = &xhci->devs[slot_id]->eps[ep_index];
 495         /* Common case: no streams */
 496         if (!(ep->ep_state & EP_HAS_STREAMS))
 497                 return ep->ring;
 498
 499         if (stream_id == 0) {
 500                 xhci_warn(xhci,
 501                                 "WARN: Slot ID %u, ep index %u has streams, "
 502                                 "but URB has no stream ID.\n",
 503                                 slot_id, ep_index);
 504                 return NULL;
 505         }
 506
 507         if (stream_id < ep->stream_info->num_streams)
 508                 return ep->stream_info->stream_rings[stream_id];
 509
 510         xhci_warn(xhci,
 511                         "WARN: Slot ID %u, ep index %u has "
 512                         "stream IDs 1 to %u allocated, "
 513                         "but stream ID %u is requested.\n",
 514                         slot_id, ep_index,
 515                         ep->stream_info->num_streams - 1,
 516                         stream_id);
 517         return NULL;
 518 }
 519
 520 /* Get the right ring for the given URB.
 521  * If the endpoint supports streams, boundary check the URB's stream ID.
 522  * If the endpoint doesn't support streams, return the singular endpoint ring.
 523  */
 524 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 525                 struct urb *urb)
 526 {
 527         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 528                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 529 }
 530
 531 /*
 532  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 533  * Record the new state of the xHC's endpoint ring dequeue segment,
 534  * dequeue pointer, and new consumer cycle state in state.
 535  * Update our internal representation of the ring's dequeue pointer.
 536  *
 537  * We do this in three jumps:
 538  *  - First we update our new ring state to be the same as when the xHC stopped.
 539  *  - Then we traverse the ring to find the segment that contains
 540  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 541  *    any link TRBs with the toggle cycle bit set.
 542  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 543  *    if we've moved it past a link TRB with the toggle cycle bit set.
 544  *
 545  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 546  * with correct __le32 accesses they should work fine.  Only users of this are
 547  * in here.
 548  */
 549 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 550                 unsigned int slot_id, unsigned int ep_index,
 551                 unsigned int stream_id, struct xhci_td *cur_td,
 552                 struct xhci_dequeue_state *state)
 553 {
 554         struct xhci_virt_device *dev = xhci->devs[slot_id];
 555         struct xhci_ring *ep_ring;
 556         struct xhci_generic_trb *trb;
 557         struct xhci_ep_ctx *ep_ctx;
 558         dma_addr_t addr;
 559
 560         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 561                         ep_index, stream_id);
 562         if (!ep_ring) {
 563                 xhci_warn(xhci, "WARN can't find new dequeue state "
 564                                 "for invalid stream ID %u.\n",
 565                                 stream_id);
 566                 return;
 567         }
 568         state->new_cycle_state = 0;
 569         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 570                         "Finding segment containing stopped TRB.");
 571         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 572                         dev->eps[ep_index].stopped_trb,
 573                         &state->new_cycle_state);
 574         if (!state->new_deq_seg) {
 575                 WARN_ON(1);
 576                 return;
 577         }
 578
 579         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 580         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 581                         "Finding endpoint context");
 582         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 583         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 584
 585         state->new_deq_ptr = cur_td->last_trb;
 586         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 587                         "Finding segment containing last TRB in TD.");
 588         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 589                         state->new_deq_ptr,
 590                         &state->new_cycle_state);
 591         if (!state->new_deq_seg) {
 592                 WARN_ON(1);
 593                 return;
 594         }
 595
 596         trb = &state->new_deq_ptr->generic;
 597         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 598             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 599                 state->new_cycle_state ^= 0x1;
 600         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 601
 602         /*
 603          * If there is only one segment in a ring, find_trb_seg()'s while loop
 604          * will not run, and it will return before it has a chance to see if it
 605          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 606          * ended just before the link TRB on a one-segment ring, or if the TD
 607          * wrapped around the top of the ring, because it doesn't have the TD in
 608          * question.  Look for the one-segment case where stalled TRB's address
 609          * is greater than the new dequeue pointer address.
 610          */
 611         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 612                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 613                 state->new_cycle_state ^= 0x1;
 614         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 615                         "Cycle state = 0x%x", state->new_cycle_state);
 616
 617         /* Don't update the ring cycle state for the producer (us). */
 618         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 619                         "New dequeue segment = %p (virtual)",
 620                         state->new_deq_seg);
 621         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 622         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 623                         "New dequeue pointer = 0x%llx (DMA)",
 624                         (unsigned long long) addr);
 625 }
 626
 627 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 628  * (The last TRB actually points to the ring enqueue pointer, which is not part
 629  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 630  */
 631 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 632                 struct xhci_td *cur_td, bool flip_cycle)
 633 {
 634         struct xhci_segment *cur_seg;
 635         union xhci_trb *cur_trb;
 636
 637         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 638                         true;
 639                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 640                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 641                         /* Unchain any chained Link TRBs, but
 642                          * leave the pointers intact.
 643                          */
 644                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 645                         /* Flip the cycle bit (link TRBs can't be the first
 646                          * or last TRB).
 647                          */
 648                         if (flip_cycle)
 649                                 cur_trb->generic.field[3] ^=
 650                                         cpu_to_le32(TRB_CYCLE);
 651                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 652                                         "Cancel (unchain) link TRB");
 653                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 654                                         "Address = %p (0x%llx dma); "
 655                                         "in seg %p (0x%llx dma)",
 656                                         cur_trb,
 657                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 658                                         cur_seg,
 659                                         (unsigned long long)cur_seg->dma);
 660                 } else {
 661                         cur_trb->generic.field[0] = 0;
 662                         cur_trb->generic.field[1] = 0;
 663                         cur_trb->generic.field[2] = 0;
 664                         /* Preserve only the cycle bit of this TRB */
 665                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 666                         /* Flip the cycle bit except on the first or last TRB */
 667                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 668                                         cur_trb != cur_td->last_trb)
 669                                 cur_trb->generic.field[3] ^=
 670                                         cpu_to_le32(TRB_CYCLE);
 671                         cur_trb->generic.field[3] |= cpu_to_le32(
 672                                 TRB_TYPE(TRB_TR_NOOP));
 673                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 674                                         "TRB to noop at offset 0x%llx",
 675                                         (unsigned long long)
 676                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 677                 }
 678                 if (cur_trb == cur_td->last_trb)
 679                         break;
 680         }
 681 }
 682
 683 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 684                 unsigned int ep_index, unsigned int stream_id,
 685                 struct xhci_segment *deq_seg,
 686                 union xhci_trb *deq_ptr, u32 cycle_state);
 687
 688 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 689                 unsigned int slot_id, unsigned int ep_index,
 690                 unsigned int stream_id,
 691                 struct xhci_dequeue_state *deq_state)
 692 {
 693         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 694
 695         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 696                         "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 697                         "new deq ptr = %p (0x%llx dma), new cycle = %u",
 698                         deq_state->new_deq_seg,
 699                         (unsigned long long)deq_state->new_deq_seg->dma,
 700                         deq_state->new_deq_ptr,
 701                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 702                         deq_state->new_cycle_state);
 703         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 704                         deq_state->new_deq_seg,
 705                         deq_state->new_deq_ptr,
 706                         (u32) deq_state->new_cycle_state);
 707         /* Stop the TD queueing code from ringing the doorbell until
 708          * this command completes.  The HC won't set the dequeue pointer
 709          * if the ring is running, and ringing the doorbell starts the
 710          * ring running.
 711          */
 712         ep->ep_state |= SET_DEQ_PENDING;
 713 }
 714
 715 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 716                 struct xhci_virt_ep *ep)
 717 {
 718         ep->ep_state &= ~EP_HALT_PENDING;
 719         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 720          * timer is running on another CPU, we don't decrement stop_cmds_pending
 721          * (since we didn't successfully stop the watchdog timer).
 722          */
 723         if (del_timer(&ep->stop_cmd_timer))
 724                 ep->stop_cmds_pending--;
 725 }
 726
 727 /* Must be called with xhci->lock held in interrupt context */
 728 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 729                 struct xhci_td *cur_td, int status, char *adjective)
 730 {
 731         struct usb_hcd *hcd;
 732         struct urb      *urb;
 733         struct urb_priv *urb_priv;
 734
 735         urb = cur_td->urb;
 736         urb_priv = urb->hcpriv;
 737         urb_priv->td_cnt++;
 738         hcd = bus_to_hcd(urb->dev->bus);
 739
 740         /* Only giveback urb when this is the last td in urb */
 741         if (urb_priv->td_cnt == urb_priv->length) {
 742                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 743                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 744                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 745                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 746                                         usb_amd_quirk_pll_enable();
 747                         }
 748                 }
 749                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 750
 751                 spin_unlock(&xhci->lock);
 752                 usb_hcd_giveback_urb(hcd, urb, status);
 753                 xhci_urb_free_priv(xhci, urb_priv);
 754                 spin_lock(&xhci->lock);
 755         }
 756 }
 757
 758 /*
 759  * When we get a command completion for a Stop Endpoint Command, we need to
 760  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 761  *
 762  *  1. If the HW was in the middle of processing the TD that needs to be
 763  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 764  *     in the TD with a Set Dequeue Pointer Command.
 765  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 766  *     bit cleared) so that the HW will skip over them.
 767  */
 768 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 769                 union xhci_trb *trb, struct xhci_event_cmd *event)
 770 {
 771         unsigned int slot_id;
 772         unsigned int ep_index;
 773         struct xhci_virt_device *virt_dev;
 774         struct xhci_ring *ep_ring;
 775         struct xhci_virt_ep *ep;
 776         struct list_head *entry;
 777         struct xhci_td *cur_td = NULL;
 778         struct xhci_td *last_unlinked_td;
 779
 780         struct xhci_dequeue_state deq_state;
 781
 782         if (unlikely(TRB_TO_SUSPEND_PORT(
 783                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 784                 slot_id = TRB_TO_SLOT_ID(
 785                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 786                 virt_dev = xhci->devs[slot_id];
 787                 if (virt_dev)
 788                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 789                                 event);
 790                 else
 791                         xhci_warn(xhci, "Stop endpoint command "
 792                                 "completion for disabled slot %u\n",
 793                                 slot_id);
 794                 return;
 795         }
 796
 797         memset(&deq_state, 0, sizeof(deq_state));
 798         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 799         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 800         ep = &xhci->devs[slot_id]->eps[ep_index];
 801
 802         if (list_empty(&ep->cancelled_td_list)) {
 803                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 804                 ep->stopped_td = NULL;
 805                 ep->stopped_trb = NULL;
 806                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 807                 return;
 808         }
 809
 810         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 811          * We have the xHCI lock, so nothing can modify this list until we drop
 812          * it.  We're also in the event handler, so we can't get re-interrupted
 813          * if another Stop Endpoint command completes
 814          */
 815         list_for_each(entry, &ep->cancelled_td_list) {
 816                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 817                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 818                                 "Removing canceled TD starting at 0x%llx (dma).",
 819                                 (unsigned long long)xhci_trb_virt_to_dma(
 820                                         cur_td->start_seg, cur_td->first_trb));
 821                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 822                 if (!ep_ring) {
 823                         /* This shouldn't happen unless a driver is mucking
 824                          * with the stream ID after submission.  This will
 825                          * leave the TD on the hardware ring, and the hardware
 826                          * will try to execute it, and may access a buffer
 827                          * that has already been freed.  In the best case, the
 828                          * hardware will execute it, and the event handler will
 829                          * ignore the completion event for that TD, since it was
 830                          * removed from the td_list for that endpoint.  In
 831                          * short, don't muck with the stream ID after
 832                          * submission.
 833                          */
 834                         xhci_warn(xhci, "WARN Cancelled URB %p "
 835                                         "has invalid stream ID %u.\n",
 836                                         cur_td->urb,
 837                                         cur_td->urb->stream_id);
 838                         goto remove_finished_td;
 839                 }
 840                 /*
 841                  * If we stopped on the TD we need to cancel, then we have to
 842                  * move the xHC endpoint ring dequeue pointer past this TD.
 843                  */
 844                 if (cur_td == ep->stopped_td)
 845                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 846                                         cur_td->urb->stream_id,
 847                                         cur_td, &deq_state);
 848                 else
 849                         td_to_noop(xhci, ep_ring, cur_td, false);
 850 remove_finished_td:
 851                 /*
 852                  * The event handler won't see a completion for this TD anymore,
 853                  * so remove it from the endpoint ring's TD list.  Keep it in
 854                  * the cancelled TD list for URB completion later.
 855                  */
 856                 list_del_init(&cur_td->td_list);
 857         }
 858         last_unlinked_td = cur_td;
 859         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 860
 861         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 862         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 863                 xhci_queue_new_dequeue_state(xhci,
 864                                 slot_id, ep_index,
 865                                 ep->stopped_td->urb->stream_id,
 866                                 &deq_state);
 867                 xhci_ring_cmd_db(xhci);
 868         } else {
 869                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 870                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 871         }
 872         ep->stopped_td = NULL;
 873         ep->stopped_trb = NULL;
 874
 875         /*
 876          * Drop the lock and complete the URBs in the cancelled TD list.
 877          * New TDs to be cancelled might be added to the end of the list before
 878          * we can complete all the URBs for the TDs we already unlinked.
 879          * So stop when we've completed the URB for the last TD we unlinked.
 880          */
 881         do {
 882                 cur_td = list_entry(ep->cancelled_td_list.next,
 883                                 struct xhci_td, cancelled_td_list);
 884                 list_del_init(&cur_td->cancelled_td_list);
 885
 886                 /* Clean up the cancelled URB */
 887                 /* Doesn't matter what we pass for status, since the core will
 888                  * just overwrite it (because the URB has been unlinked).
 889                  */
 890                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 891
 892                 /* Stop processing the cancelled list if the watchdog timer is
 893                  * running.
 894                  */
 895                 if (xhci->xhc_state & XHCI_STATE_DYING)
 896                         return;
 897         } while (cur_td != last_unlinked_td);
 898
 899         /* Return to the event handler with xhci->lock re-acquired */
 900 }
 901
 902 /* Watchdog timer function for when a stop endpoint command fails to complete.
 903  * In this case, we assume the host controller is broken or dying or dead.  The
 904  * host may still be completing some other events, so we have to be careful to
 905  * let the event ring handler and the URB dequeueing/enqueueing functions know
 906  * through xhci->state.
 907  *
 908  * The timer may also fire if the host takes a very long time to respond to the
 909  * command, and the stop endpoint command completion handler cannot delete the
 910  * timer before the timer function is called.  Another endpoint cancellation may
 911  * sneak in before the timer function can grab the lock, and that may queue
 912  * another stop endpoint command and add the timer back.  So we cannot use a
 913  * simple flag to say whether there is a pending stop endpoint command for a
 914  * particular endpoint.
 915  *
 916  * Instead we use a combination of that flag and a counter for the number of
 917  * pending stop endpoint commands.  If the timer is the tail end of the last
 918  * stop endpoint command, and the endpoint's command is still pending, we assume
 919  * the host is dying.
 920  */
 921 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 922 {
 923         struct xhci_hcd *xhci;
 924         struct xhci_virt_ep *ep;
 925         struct xhci_virt_ep *temp_ep;
 926         struct xhci_ring *ring;
 927         struct xhci_td *cur_td;
 928         int ret, i, j;
 929         unsigned long flags;
 930
 931         ep = (struct xhci_virt_ep *) arg;
 932         xhci = ep->xhci;
 933
 934         spin_lock_irqsave(&xhci->lock, flags);
 935
 936         ep->stop_cmds_pending--;
 937         if (xhci->xhc_state & XHCI_STATE_DYING) {
 938                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 939                                 "Stop EP timer ran, but another timer marked "
 940                                 "xHCI as DYING, exiting.");
 941                 spin_unlock_irqrestore(&xhci->lock, flags);
 942                 return;
 943         }
 944         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 945                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 946                                 "Stop EP timer ran, but no command pending, "
 947                                 "exiting.");
 948                 spin_unlock_irqrestore(&xhci->lock, flags);
 949                 return;
 950         }
 951
 952         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 953         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 954         /* Oops, HC is dead or dying or at least not responding to the stop
 955          * endpoint command.
 956          */
 957         xhci->xhc_state |= XHCI_STATE_DYING;
 958         /* Disable interrupts from the host controller and start halting it */
 959         xhci_quiesce(xhci);
 960         spin_unlock_irqrestore(&xhci->lock, flags);
 961
 962         ret = xhci_halt(xhci);
 963
 964         spin_lock_irqsave(&xhci->lock, flags);
 965         if (ret < 0) {
 966                 /* This is bad; the host is not responding to commands and it's
 967                  * not allowing itself to be halted.  At least interrupts are
 968                  * disabled. If we call usb_hc_died(), it will attempt to
 969                  * disconnect all device drivers under this host.  Those
 970                  * disconnect() methods will wait for all URBs to be unlinked,
 971                  * so we must complete them.
 972                  */
 973                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 974                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 975                 /* We could turn all TDs on the rings to no-ops.  This won't
 976                  * help if the host has cached part of the ring, and is slow if
 977                  * we want to preserve the cycle bit.  Skip it and hope the host
 978                  * doesn't touch the memory.
 979                  */
 980         }
 981         for (i = 0; i < MAX_HC_SLOTS; i++) {
 982                 if (!xhci->devs[i])
 983                         continue;
 984                 for (j = 0; j < 31; j++) {
 985                         temp_ep = &xhci->devs[i]->eps[j];
 986                         ring = temp_ep->ring;
 987                         if (!ring)
 988                                 continue;
 989                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 990                                         "Killing URBs for slot ID %u, "
 991                                         "ep index %u", i, j);
 992                         while (!list_empty(&ring->td_list)) {
 993                                 cur_td = list_first_entry(&ring->td_list,
 994                                                 struct xhci_td,
 995                                                 td_list);
 996                                 list_del_init(&cur_td->td_list);
 997                                 if (!list_empty(&cur_td->cancelled_td_list))
 998                                         list_del_init(&cur_td->cancelled_td_list);
 999                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1000                                                 -ESHUTDOWN, "killed");
1001                         }
1002                         while (!list_empty(&temp_ep->cancelled_td_list)) {
1003                                 cur_td = list_first_entry(
1004                                                 &temp_ep->cancelled_td_list,
1005                                                 struct xhci_td,
1006                                                 cancelled_td_list);
1007                                 list_del_init(&cur_td->cancelled_td_list);
1008                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1009                                                 -ESHUTDOWN, "killed");
1010                         }
1011                 }
1012         }
1013         spin_unlock_irqrestore(&xhci->lock, flags);
1014         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1015                         "Calling usb_hc_died()");
1016         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1017         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1018                         "xHCI host controller is dead.");
1019 }
1020
1021
1022 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1023                 struct xhci_virt_device *dev,
1024                 struct xhci_ring *ep_ring,
1025                 unsigned int ep_index)
1026 {
1027         union xhci_trb *dequeue_temp;
1028         int num_trbs_free_temp;
1029         bool revert = false;
1030
1031         num_trbs_free_temp = ep_ring->num_trbs_free;
1032         dequeue_temp = ep_ring->dequeue;
1033
1034         /* If we get two back-to-back stalls, and the first stalled transfer
1035          * ends just before a link TRB, the dequeue pointer will be left on
1036          * the link TRB by the code in the while loop.  So we have to update
1037          * the dequeue pointer one segment further, or we'll jump off
1038          * the segment into la-la-land.
1039          */
1040         if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1041                 ep_ring->deq_seg = ep_ring->deq_seg->next;
1042                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1043         }
1044
1045         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1046                 /* We have more usable TRBs */
1047                 ep_ring->num_trbs_free++;
1048                 ep_ring->dequeue++;
1049                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1050                                 ep_ring->dequeue)) {
1051                         if (ep_ring->dequeue ==
1052                                         dev->eps[ep_index].queued_deq_ptr)
1053                                 break;
1054                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1055                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1056                 }
1057                 if (ep_ring->dequeue == dequeue_temp) {
1058                         revert = true;
1059                         break;
1060                 }
1061         }
1062
1063         if (revert) {
1064                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1065                 ep_ring->num_trbs_free = num_trbs_free_temp;
1066         }
1067 }
1068
1069 /*
1070  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1071  * we need to clear the set deq pending flag in the endpoint ring state, so that
1072  * the TD queueing code can ring the doorbell again.  We also need to ring the
1073  * endpoint doorbell to restart the ring, but only if there aren't more
1074  * cancellations pending.
1075  */
1076 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1077                 struct xhci_event_cmd *event,
1078                 union xhci_trb *trb)
1079 {
1080         unsigned int slot_id;
1081         unsigned int ep_index;
1082         unsigned int stream_id;
1083         struct xhci_ring *ep_ring;
1084         struct xhci_virt_device *dev;
1085         struct xhci_ep_ctx *ep_ctx;
1086         struct xhci_slot_ctx *slot_ctx;
1087
1088         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1089         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1090         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1091         dev = xhci->devs[slot_id];
1092
1093         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1094         if (!ep_ring) {
1095                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1096                                 "freed stream ID %u\n",
1097                                 stream_id);
1098                 /* XXX: Harmless??? */
1099                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1100                 return;
1101         }
1102
1103         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1104         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1105
1106         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1107                 unsigned int ep_state;
1108                 unsigned int slot_state;
1109
1110                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1111                 case COMP_TRB_ERR:
1112                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1113                                         "of stream ID configuration\n");
1114                         break;
1115                 case COMP_CTX_STATE:
1116                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1117                                         "to incorrect slot or ep state.\n");
1118                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1119                         ep_state &= EP_STATE_MASK;
1120                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1121                         slot_state = GET_SLOT_STATE(slot_state);
1122                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1123                                         "Slot state = %u, EP state = %u",
1124                                         slot_state, ep_state);
1125                         break;
1126                 case COMP_EBADSLT:
1127                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1128                                         "slot %u was not enabled.\n", slot_id);
1129                         break;
1130                 default:
1131                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1132                                         "completion code of %u.\n",
1133                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1134                         break;
1135                 }
1136                 /* OK what do we do now?  The endpoint state is hosed, and we
1137                  * should never get to this point if the synchronization between
1138                  * queueing, and endpoint state are correct.  This might happen
1139                  * if the device gets disconnected after we've finished
1140                  * cancelling URBs, which might not be an error...
1141                  */
1142         } else {
1143                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1144                         "Successful Set TR Deq Ptr cmd, deq = @%08llx",
1145                          le64_to_cpu(ep_ctx->deq));
1146                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1147                                          dev->eps[ep_index].queued_deq_ptr) ==
1148                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1149                         /* Update the ring's dequeue segment and dequeue pointer
1150                          * to reflect the new position.
1151                          */
1152                         update_ring_for_set_deq_completion(xhci, dev,
1153                                 ep_ring, ep_index);
1154                 } else {
1155                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1156                                         "Ptr command & xHCI internal state.\n");
1157                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1158                                         dev->eps[ep_index].queued_deq_seg,
1159                                         dev->eps[ep_index].queued_deq_ptr);
1160                 }
1161         }
1162
1163         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1164         dev->eps[ep_index].queued_deq_seg = NULL;
1165         dev->eps[ep_index].queued_deq_ptr = NULL;
1166         /* Restart any rings with pending URBs */
1167         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1168 }
1169
1170 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1171                 struct xhci_event_cmd *event,
1172                 union xhci_trb *trb)
1173 {
1174         int slot_id;
1175         unsigned int ep_index;
1176
1177         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1178         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1179         /* This command will only fail if the endpoint wasn't halted,
1180          * but we don't care.
1181          */
1182         xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1183                 "Ignoring reset ep completion code of %u",
1184                  GET_COMP_CODE(le32_to_cpu(event->status)));
1185
1186         /* HW with the reset endpoint quirk needs to have a configure endpoint
1187          * command complete before the endpoint can be used.  Queue that here
1188          * because the HW can't handle two commands being queued in a row.
1189          */
1190         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1191                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1192                                 "Queueing configure endpoint command");
1193                 xhci_queue_configure_endpoint(xhci,
1194                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1195                                 false);
1196                 xhci_ring_cmd_db(xhci);
1197         } else {
1198                 /* Clear our internal halted state and restart the ring(s) */
1199                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1200                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1201         }
1202 }
1203
1204 /* Complete the command and detele it from the devcie's command queue.
1205  */
1206 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1207                 struct xhci_command *command, u32 status)
1208 {
1209         command->status = status;
1210         list_del(&command->cmd_list);
1211         if (command->completion)
1212                 complete(command->completion);
1213         else
1214                 xhci_free_command(xhci, command);
1215 }
1216
1217
1218 /* Check to see if a command in the device's command queue matches this one.
1219  * Signal the completion or free the command, and return 1.  Return 0 if the
1220  * completed command isn't at the head of the command list.
1221  */
1222 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1223                 struct xhci_virt_device *virt_dev,
1224                 struct xhci_event_cmd *event)
1225 {
1226         struct xhci_command *command;
1227
1228         if (list_empty(&virt_dev->cmd_list))
1229                 return 0;
1230
1231         command = list_entry(virt_dev->cmd_list.next,
1232                         struct xhci_command, cmd_list);
1233         if (xhci->cmd_ring->dequeue != command->command_trb)
1234                 return 0;
1235
1236         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1237                         GET_COMP_CODE(le32_to_cpu(event->status)));
1238         return 1;
1239 }
1240
1241 /*
1242  * Finding the command trb need to be cancelled and modifying it to
1243  * NO OP command. And if the command is in device's command wait
1244  * list, finishing and freeing it.
1245  *
1246  * If we can't find the command trb, we think it had already been
1247  * executed.
1248  */
1249 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1250 {
1251         struct xhci_segment *cur_seg;
1252         union xhci_trb *cmd_trb;
1253         u32 cycle_state;
1254
1255         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1256                 return;
1257
1258         /* find the current segment of command ring */
1259         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1260                         xhci->cmd_ring->dequeue, &cycle_state);
1261
1262         if (!cur_seg) {
1263                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1264                                 xhci->cmd_ring->dequeue,
1265                                 (unsigned long long)
1266                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1267                                         xhci->cmd_ring->dequeue));
1268                 xhci_debug_ring(xhci, xhci->cmd_ring);
1269                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1270                 return;
1271         }
1272
1273         /* find the command trb matched by cd from command ring */
1274         for (cmd_trb = xhci->cmd_ring->dequeue;
1275                         cmd_trb != xhci->cmd_ring->enqueue;
1276                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1277                 /* If the trb is link trb, continue */
1278                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1279                         continue;
1280
1281                 if (cur_cd->cmd_trb == cmd_trb) {
1282
1283                         /* If the command in device's command list, we should
1284                          * finish it and free the command structure.
1285                          */
1286                         if (cur_cd->command)
1287                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1288                                         cur_cd->command, COMP_CMD_STOP);
1289
1290                         /* get cycle state from the origin command trb */
1291                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1292                                 & TRB_CYCLE;
1293
1294                         /* modify the command trb to NO OP command */
1295                         cmd_trb->generic.field[0] = 0;
1296                         cmd_trb->generic.field[1] = 0;
1297                         cmd_trb->generic.field[2] = 0;
1298                         cmd_trb->generic.field[3] = cpu_to_le32(
1299                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1300                         break;
1301                 }
1302         }
1303 }
1304
1305 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1306 {
1307         struct xhci_cd *cur_cd, *next_cd;
1308
1309         if (list_empty(&xhci->cancel_cmd_list))
1310                 return;
1311
1312         list_for_each_entry_safe(cur_cd, next_cd,
1313                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1314                 xhci_cmd_to_noop(xhci, cur_cd);
1315                 list_del(&cur_cd->cancel_cmd_list);
1316                 kfree(cur_cd);
1317         }
1318 }
1319
1320 /*
1321  * traversing the cancel_cmd_list. If the command descriptor according
1322  * to cmd_trb is found, the function free it and return 1, otherwise
1323  * return 0.
1324  */
1325 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1326                 union xhci_trb *cmd_trb)
1327 {
1328         struct xhci_cd *cur_cd, *next_cd;
1329
1330         if (list_empty(&xhci->cancel_cmd_list))
1331                 return 0;
1332
1333         list_for_each_entry_safe(cur_cd, next_cd,
1334                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1335                 if (cur_cd->cmd_trb == cmd_trb) {
1336                         if (cur_cd->command)
1337                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1338                                         cur_cd->command, COMP_CMD_STOP);
1339                         list_del(&cur_cd->cancel_cmd_list);
1340                         kfree(cur_cd);
1341                         return 1;
1342                 }
1343         }
1344
1345         return 0;
1346 }
1347
1348 /*
1349  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1350  * trb pointed by the command ring dequeue pointer is the trb we want to
1351  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1352  * traverse the cancel_cmd_list to trun the all of the commands according
1353  * to command descriptor to NO-OP trb.
1354  */
1355 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1356                 int cmd_trb_comp_code)
1357 {
1358         int cur_trb_is_good = 0;
1359
1360         /* Searching the cmd trb pointed by the command ring dequeue
1361          * pointer in command descriptor list. If it is found, free it.
1362          */
1363         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1364                         xhci->cmd_ring->dequeue);
1365
1366         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1367                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1368         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1369                 /* traversing the cancel_cmd_list and canceling
1370                  * the command according to command descriptor
1371                  */
1372                 xhci_cancel_cmd_in_cd_list(xhci);
1373
1374                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1375                 /*
1376                  * ring command ring doorbell again to restart the
1377                  * command ring
1378                  */
1379                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1380                         xhci_ring_cmd_db(xhci);
1381         }
1382         return cur_trb_is_good;
1383 }
1384
1385 static void handle_cmd_completion(struct xhci_hcd *xhci,
1386                 struct xhci_event_cmd *event)
1387 {
1388         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1389         u64 cmd_dma;
1390         dma_addr_t cmd_dequeue_dma;
1391         struct xhci_input_control_ctx *ctrl_ctx;
1392         struct xhci_virt_device *virt_dev;
1393         unsigned int ep_index;
1394         struct xhci_ring *ep_ring;
1395         unsigned int ep_state;
1396
1397         cmd_dma = le64_to_cpu(event->cmd_trb);
1398         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1399                         xhci->cmd_ring->dequeue);
1400         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1401         if (cmd_dequeue_dma == 0) {
1402                 xhci->error_bitmask |= 1 << 4;
1403                 return;
1404         }
1405         /* Does the DMA address match our internal dequeue pointer address? */
1406         if (cmd_dma != (u64) cmd_dequeue_dma) {
1407                 xhci->error_bitmask |= 1 << 5;
1408                 return;
1409         }
1410
1411         trace_xhci_cmd_completion(&xhci->cmd_ring->dequeue->generic,
1412                                         (struct xhci_generic_trb *) event);
1413
1414         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1415                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1416                 /* If the return value is 0, we think the trb pointed by
1417                  * command ring dequeue pointer is a good trb. The good
1418                  * trb means we don't want to cancel the trb, but it have
1419                  * been stopped by host. So we should handle it normally.
1420                  * Otherwise, driver should invoke inc_deq() and return.
1421                  */
1422                 if (handle_stopped_cmd_ring(xhci,
1423                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1424                         inc_deq(xhci, xhci->cmd_ring);
1425                         return;
1426                 }
1427                 /* There is no command to handle if we get a stop event when the
1428                  * command ring is empty, event->cmd_trb points to the next
1429                  * unset command
1430                  */
1431                 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1432                         return;
1433         }
1434
1435         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1436                 & TRB_TYPE_BITMASK) {
1437         case TRB_TYPE(TRB_ENABLE_SLOT):
1438                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1439                         xhci->slot_id = slot_id;
1440                 else
1441                         xhci->slot_id = 0;
1442                 complete(&xhci->addr_dev);
1443                 break;
1444         case TRB_TYPE(TRB_DISABLE_SLOT):
1445                 if (xhci->devs[slot_id]) {
1446                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1447                                 /* Delete default control endpoint resources */
1448                                 xhci_free_device_endpoint_resources(xhci,
1449                                                 xhci->devs[slot_id], true);
1450                         xhci_free_virt_device(xhci, slot_id);
1451                 }
1452                 break;
1453         case TRB_TYPE(TRB_CONFIG_EP):
1454                 virt_dev = xhci->devs[slot_id];
1455                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1456                         break;
1457                 /*
1458                  * Configure endpoint commands can come from the USB core
1459                  * configuration or alt setting changes, or because the HW
1460                  * needed an extra configure endpoint command after a reset
1461                  * endpoint command or streams were being configured.
1462                  * If the command was for a halted endpoint, the xHCI driver
1463                  * is not waiting on the configure endpoint command.
1464                  */
1465                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1466                                 virt_dev->in_ctx);
1467                 if (!ctrl_ctx) {
1468                         xhci_warn(xhci, "Could not get input context, bad type.\n");
1469                         break;
1470                 }
1471                 /* Input ctx add_flags are the endpoint index plus one */
1472                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1473                 /* A usb_set_interface() call directly after clearing a halted
1474                  * condition may race on this quirky hardware.  Not worth
1475                  * worrying about, since this is prototype hardware.  Not sure
1476                  * if this will work for streams, but streams support was
1477                  * untested on this prototype.
1478                  */
1479                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1480                                 ep_index != (unsigned int) -1 &&
1481                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1482                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1483                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1484                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1485                         if (!(ep_state & EP_HALTED))
1486                                 goto bandwidth_change;
1487                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1488                                         "Completed config ep cmd - "
1489                                         "last ep index = %d, state = %d",
1490                                         ep_index, ep_state);
1491                         /* Clear internal halted state and restart ring(s) */
1492                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1493                                 ~EP_HALTED;
1494                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1495                         break;
1496                 }
1497 bandwidth_change:
1498                 xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
1499                                 "Completed config ep cmd");
1500                 xhci->devs[slot_id]->cmd_status =
1501                         GET_COMP_CODE(le32_to_cpu(event->status));
1502                 complete(&xhci->devs[slot_id]->cmd_completion);
1503                 break;
1504         case TRB_TYPE(TRB_EVAL_CONTEXT):
1505                 virt_dev = xhci->devs[slot_id];
1506                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1507                         break;
1508                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1509                 complete(&xhci->devs[slot_id]->cmd_completion);
1510                 break;
1511         case TRB_TYPE(TRB_ADDR_DEV):
1512                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1513                 complete(&xhci->addr_dev);
1514                 break;
1515         case TRB_TYPE(TRB_STOP_RING):
1516                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1517                 break;
1518         case TRB_TYPE(TRB_SET_DEQ):
1519                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1520                 break;
1521         case TRB_TYPE(TRB_CMD_NOOP):
1522                 break;
1523         case TRB_TYPE(TRB_RESET_EP):
1524                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1525                 break;
1526         case TRB_TYPE(TRB_RESET_DEV):
1527                 xhci_dbg(xhci, "Completed reset device command.\n");
1528                 slot_id = TRB_TO_SLOT_ID(
1529                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1530                 virt_dev = xhci->devs[slot_id];
1531                 if (virt_dev)
1532                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1533                 else
1534                         xhci_warn(xhci, "Reset device command completion "
1535                                         "for disabled slot %u\n", slot_id);
1536                 break;
1537         case TRB_TYPE(TRB_NEC_GET_FW):
1538                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1539                         xhci->error_bitmask |= 1 << 6;
1540                         break;
1541                 }
1542                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1543                         "NEC firmware version %2x.%02x",
1544                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1545                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1546                 break;
1547         default:
1548                 /* Skip over unknown commands on the event ring */
1549                 xhci->error_bitmask |= 1 << 6;
1550                 break;
1551         }
1552         inc_deq(xhci, xhci->cmd_ring);
1553 }
1554
1555 static void handle_vendor_event(struct xhci_hcd *xhci,
1556                 union xhci_trb *event)
1557 {
1558         u32 trb_type;
1559
1560         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1561         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1562         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1563                 handle_cmd_completion(xhci, &event->event_cmd);
1564 }
1565
1566 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1567  * port registers -- USB 3.0 and USB 2.0).
1568  *
1569  * Returns a zero-based port number, which is suitable for indexing into each of
1570  * the split roothubs' port arrays and bus state arrays.
1571  * Add one to it in order to call xhci_find_slot_id_by_port.
1572  */
1573 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1574                 struct xhci_hcd *xhci, u32 port_id)
1575 {
1576         unsigned int i;
1577         unsigned int num_similar_speed_ports = 0;
1578
1579         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1580          * and usb2_ports are 0-based indexes.  Count the number of similar
1581          * speed ports, up to 1 port before this port.
1582          */
1583         for (i = 0; i < (port_id - 1); i++) {
1584                 u8 port_speed = xhci->port_array[i];
1585
1586                 /*
1587                  * Skip ports that don't have known speeds, or have duplicate
1588                  * Extended Capabilities port speed entries.
1589                  */
1590                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1591                         continue;
1592
1593                 /*
1594                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1595                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1596                  * matches the device speed, it's a similar speed port.
1597                  */
1598                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1599                         num_similar_speed_ports++;
1600         }
1601         return num_similar_speed_ports;
1602 }
1603
1604 static void handle_device_notification(struct xhci_hcd *xhci,
1605                 union xhci_trb *event)
1606 {
1607         u32 slot_id;
1608         struct usb_device *udev;
1609
1610         slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
1611         if (!xhci->devs[slot_id]) {
1612                 xhci_warn(xhci, "Device Notification event for "
1613                                 "unused slot %u\n", slot_id);
1614                 return;
1615         }
1616
1617         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1618                         slot_id);
1619         udev = xhci->devs[slot_id]->udev;
1620         if (udev && udev->parent)
1621                 usb_wakeup_notification(udev->parent, udev->portnum);
1622 }
1623
1624 static void handle_port_status(struct xhci_hcd *xhci,
1625                 union xhci_trb *event)
1626 {
1627         struct usb_hcd *hcd;
1628         u32 port_id;
1629         u32 temp, temp1;
1630         int max_ports;
1631         int slot_id;
1632         unsigned int faked_port_index;
1633         u8 major_revision;
1634         struct xhci_bus_state *bus_state;
1635         __le32 __iomem **port_array;
1636         bool bogus_port_status = false;
1637
1638         /* Port status change events always have a successful completion code */
1639         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1640                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1641                 xhci->error_bitmask |= 1 << 8;
1642         }
1643         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1644         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1645
1646         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1647         if ((port_id <= 0) || (port_id > max_ports)) {
1648                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1649                 inc_deq(xhci, xhci->event_ring);
1650                 return;
1651         }
1652
1653         /* Figure out which usb_hcd this port is attached to:
1654          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1655          */
1656         major_revision = xhci->port_array[port_id - 1];
1657
1658         /* Find the right roothub. */
1659         hcd = xhci_to_hcd(xhci);
1660         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1661                 hcd = xhci->shared_hcd;
1662
1663         if (major_revision == 0) {
1664                 xhci_warn(xhci, "Event for port %u not in "
1665                                 "Extended Capabilities, ignoring.\n",
1666                                 port_id);
1667                 bogus_port_status = true;
1668                 goto cleanup;
1669         }
1670         if (major_revision == DUPLICATE_ENTRY) {
1671                 xhci_warn(xhci, "Event for port %u duplicated in"
1672                                 "Extended Capabilities, ignoring.\n",
1673                                 port_id);
1674                 bogus_port_status = true;
1675                 goto cleanup;
1676         }
1677
1678         /*
1679          * Hardware port IDs reported by a Port Status Change Event include USB
1680          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1681          * resume event, but we first need to translate the hardware port ID
1682          * into the index into the ports on the correct split roothub, and the
1683          * correct bus_state structure.
1684          */
1685         bus_state = &xhci->bus_state[hcd_index(hcd)];
1686         if (hcd->speed == HCD_USB3)
1687                 port_array = xhci->usb3_ports;
1688         else
1689                 port_array = xhci->usb2_ports;
1690         /* Find the faked port hub number */
1691         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1692                         port_id);
1693
1694         temp = xhci_readl(xhci, port_array[faked_port_index]);
1695         if (hcd->state == HC_STATE_SUSPENDED) {
1696                 xhci_dbg(xhci, "resume root hub\n");
1697                 usb_hcd_resume_root_hub(hcd);
1698         }
1699
1700         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1701                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1702
1703                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1704                 if (!(temp1 & CMD_RUN)) {
1705                         xhci_warn(xhci, "xHC is not running.\n");
1706                         goto cleanup;
1707                 }
1708
1709                 if (DEV_SUPERSPEED(temp)) {
1710                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1711                         /* Set a flag to say the port signaled remote wakeup,
1712                          * so we can tell the difference between the end of
1713                          * device and host initiated resume.
1714                          */
1715                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1716                         xhci_test_and_clear_bit(xhci, port_array,
1717                                         faked_port_index, PORT_PLC);
1718                         xhci_set_link_state(xhci, port_array, faked_port_index,
1719                                                 XDEV_U0);
1720                         /* Need to wait until the next link state change
1721                          * indicates the device is actually in U0.
1722                          */
1723                         bogus_port_status = true;
1724                         goto cleanup;
1725                 } else {
1726                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1727                         bus_state->resume_done[faked_port_index] = jiffies +
1728                                 msecs_to_jiffies(20);
1729                         set_bit(faked_port_index, &bus_state->resuming_ports);
1730                         mod_timer(&hcd->rh_timer,
1731                                   bus_state->resume_done[faked_port_index]);
1732                         /* Do the rest in GetPortStatus */
1733                 }
1734         }
1735
1736         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1737                         DEV_SUPERSPEED(temp)) {
1738                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1739                 /* We've just brought the device into U0 through either the
1740                  * Resume state after a device remote wakeup, or through the
1741                  * U3Exit state after a host-initiated resume.  If it's a device
1742                  * initiated remote wake, don't pass up the link state change,
1743                  * so the roothub behavior is consistent with external
1744                  * USB 3.0 hub behavior.
1745                  */
1746                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1747                                 faked_port_index + 1);
1748                 if (slot_id && xhci->devs[slot_id])
1749                         xhci_ring_device(xhci, slot_id);
1750                 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1751                         bus_state->port_remote_wakeup &=
1752                                 ~(1 << faked_port_index);
1753                         xhci_test_and_clear_bit(xhci, port_array,
1754                                         faked_port_index, PORT_PLC);
1755                         usb_wakeup_notification(hcd->self.root_hub,
1756                                         faked_port_index + 1);
1757                         bogus_port_status = true;
1758                         goto cleanup;
1759                 }
1760         }
1761
1762         if (hcd->speed != HCD_USB3)
1763                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1764                                         PORT_PLC);
1765
1766 cleanup:
1767         /* Update event ring dequeue pointer before dropping the lock */
1768         inc_deq(xhci, xhci->event_ring);
1769
1770         /* Don't make the USB core poll the roothub if we got a bad port status
1771          * change event.  Besides, at that point we can't tell which roothub
1772          * (USB 2.0 or USB 3.0) to kick.
1773          */
1774         if (bogus_port_status)
1775                 return;
1776
1777         /*
1778          * xHCI port-status-change events occur when the "or" of all the
1779          * status-change bits in the portsc register changes from 0 to 1.
1780          * New status changes won't cause an event if any other change
1781          * bits are still set.  When an event occurs, switch over to
1782          * polling to avoid losing status changes.
1783          */
1784         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1785         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1786         spin_unlock(&xhci->lock);
1787         /* Pass this up to the core */
1788         usb_hcd_poll_rh_status(hcd);
1789         spin_lock(&xhci->lock);
1790 }
1791
1792 /*
1793  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1794  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1795  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1796  * returns 0.
1797  */
1798 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1799                 union xhci_trb  *start_trb,
1800                 union xhci_trb  *end_trb,
1801                 dma_addr_t      suspect_dma)
1802 {
1803         dma_addr_t start_dma;
1804         dma_addr_t end_seg_dma;
1805         dma_addr_t end_trb_dma;
1806         struct xhci_segment *cur_seg;
1807
1808         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1809         cur_seg = start_seg;
1810
1811         do {
1812                 if (start_dma == 0)
1813                         return NULL;
1814                 /* We may get an event for a Link TRB in the middle of a TD */
1815                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1816                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1817                 /* If the end TRB isn't in this segment, this is set to 0 */
1818                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1819
1820                 if (end_trb_dma > 0) {
1821                         /* The end TRB is in this segment, so suspect should be here */
1822                         if (start_dma <= end_trb_dma) {
1823                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1824                                         return cur_seg;
1825                         } else {
1826                                 /* Case for one segment with
1827                                  * a TD wrapped around to the top
1828                                  */
1829                                 if ((suspect_dma >= start_dma &&
1830                                                         suspect_dma <= end_seg_dma) ||
1831                                                 (suspect_dma >= cur_seg->dma &&
1832                                                  suspect_dma <= end_trb_dma))
1833                                         return cur_seg;
1834                         }
1835                         return NULL;
1836                 } else {
1837                         /* Might still be somewhere in this segment */
1838                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1839                                 return cur_seg;
1840                 }
1841                 cur_seg = cur_seg->next;
1842                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1843         } while (cur_seg != start_seg);
1844
1845         return NULL;
1846 }
1847
1848 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1849                 unsigned int slot_id, unsigned int ep_index,
1850                 unsigned int stream_id,
1851                 struct xhci_td *td, union xhci_trb *event_trb)
1852 {
1853         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1854         ep->ep_state |= EP_HALTED;
1855         ep->stopped_td = td;
1856         ep->stopped_trb = event_trb;
1857         ep->stopped_stream = stream_id;
1858
1859         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1860         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1861
1862         ep->stopped_td = NULL;
1863         ep->stopped_trb = NULL;
1864         ep->stopped_stream = 0;
1865
1866         xhci_ring_cmd_db(xhci);
1867 }
1868
1869 /* Check if an error has halted the endpoint ring.  The class driver will
1870  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1871  * However, a babble and other errors also halt the endpoint ring, and the class
1872  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1873  * Ring Dequeue Pointer command manually.
1874  */
1875 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1876                 struct xhci_ep_ctx *ep_ctx,
1877                 unsigned int trb_comp_code)
1878 {
1879         /* TRB completion codes that may require a manual halt cleanup */
1880         if (trb_comp_code == COMP_TX_ERR ||
1881                         trb_comp_code == COMP_BABBLE ||
1882                         trb_comp_code == COMP_SPLIT_ERR)
1883                 /* The 0.96 spec says a babbling control endpoint
1884                  * is not halted. The 0.96 spec says it is.  Some HW
1885                  * claims to be 0.95 compliant, but it halts the control
1886                  * endpoint anyway.  Check if a babble halted the
1887                  * endpoint.
1888                  */
1889                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1890                     cpu_to_le32(EP_STATE_HALTED))
1891                         return 1;
1892
1893         return 0;
1894 }
1895
1896 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1897 {
1898         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1899                 /* Vendor defined "informational" completion code,
1900                  * treat as not-an-error.
1901                  */
1902                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1903                                 trb_comp_code);
1904                 xhci_dbg(xhci, "Treating code as success.\n");
1905                 return 1;
1906         }
1907         return 0;
1908 }
1909
1910 /*
1911  * Finish the td processing, remove the td from td list;
1912  * Return 1 if the urb can be given back.
1913  */
1914 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1915         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1916         struct xhci_virt_ep *ep, int *status, bool skip)
1917 {
1918         struct xhci_virt_device *xdev;
1919         struct xhci_ring *ep_ring;
1920         unsigned int slot_id;
1921         int ep_index;
1922         struct urb *urb = NULL;
1923         struct xhci_ep_ctx *ep_ctx;
1924         int ret = 0;
1925         struct urb_priv *urb_priv;
1926         u32 trb_comp_code;
1927
1928         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1929         xdev = xhci->devs[slot_id];
1930         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1931         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1932         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1933         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1934
1935         if (skip)
1936                 goto td_cleanup;
1937
1938         if (trb_comp_code == COMP_STOP_INVAL ||
1939                         trb_comp_code == COMP_STOP) {
1940                 /* The Endpoint Stop Command completion will take care of any
1941                  * stopped TDs.  A stopped TD may be restarted, so don't update
1942                  * the ring dequeue pointer or take this TD off any lists yet.
1943                  */
1944                 ep->stopped_td = td;
1945                 ep->stopped_trb = event_trb;
1946                 return 0;
1947         } else {
1948                 if (trb_comp_code == COMP_STALL) {
1949                         /* The transfer is completed from the driver's
1950                          * perspective, but we need to issue a set dequeue
1951                          * command for this stalled endpoint to move the dequeue
1952                          * pointer past the TD.  We can't do that here because
1953                          * the halt condition must be cleared first.  Let the
1954                          * USB class driver clear the stall later.
1955                          */
1956                         ep->stopped_td = td;
1957                         ep->stopped_trb = event_trb;
1958                         ep->stopped_stream = ep_ring->stream_id;
1959                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1960                                         ep_ctx, trb_comp_code)) {
1961                         /* Other types of errors halt the endpoint, but the
1962                          * class driver doesn't call usb_reset_endpoint() unless
1963                          * the error is -EPIPE.  Clear the halted status in the
1964                          * xHCI hardware manually.
1965                          */
1966                         xhci_cleanup_halted_endpoint(xhci,
1967                                         slot_id, ep_index, ep_ring->stream_id,
1968                                         td, event_trb);
1969                 } else {
1970                         /* Update ring dequeue pointer */
1971                         while (ep_ring->dequeue != td->last_trb)
1972                                 inc_deq(xhci, ep_ring);
1973                         inc_deq(xhci, ep_ring);
1974                 }
1975
1976 td_cleanup:
1977                 /* Clean up the endpoint's TD list */
1978                 urb = td->urb;
1979                 urb_priv = urb->hcpriv;
1980
1981                 /* Do one last check of the actual transfer length.
1982                  * If the host controller said we transferred more data than
1983                  * the buffer length, urb->actual_length will be a very big
1984                  * number (since it's unsigned).  Play it safe and say we didn't
1985                  * transfer anything.
1986                  */
1987                 if (urb->actual_length > urb->transfer_buffer_length) {
1988                         xhci_warn(xhci, "URB transfer length is wrong, "
1989                                         "xHC issue? req. len = %u, "
1990                                         "act. len = %u\n",
1991                                         urb->transfer_buffer_length,
1992                                         urb->actual_length);
1993                         urb->actual_length = 0;
1994                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1995                                 *status = -EREMOTEIO;
1996                         else
1997                                 *status = 0;
1998                 }
1999                 list_del_init(&td->td_list);
2000                 /* Was this TD slated to be cancelled but completed anyway? */
2001                 if (!list_empty(&td->cancelled_td_list))
2002                         list_del_init(&td->cancelled_td_list);
2003
2004                 urb_priv->td_cnt++;
2005                 /* Giveback the urb when all the tds are completed */
2006                 if (urb_priv->td_cnt == urb_priv->length) {
2007                         ret = 1;
2008                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2009                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
2010                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
2011                                         == 0) {
2012                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
2013                                                 usb_amd_quirk_pll_enable();
2014                                 }
2015                         }
2016                 }
2017         }
2018
2019         return ret;
2020 }
2021
2022 /*
2023  * Process control tds, update urb status and actual_length.
2024  */
2025 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2026         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2027         struct xhci_virt_ep *ep, int *status)
2028 {
2029         struct xhci_virt_device *xdev;
2030         struct xhci_ring *ep_ring;
2031         unsigned int slot_id;
2032         int ep_index;
2033         struct xhci_ep_ctx *ep_ctx;
2034         u32 trb_comp_code;
2035
2036         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2037         xdev = xhci->devs[slot_id];
2038         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2039         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2040         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2041         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2042
2043         switch (trb_comp_code) {
2044         case COMP_SUCCESS:
2045                 if (event_trb == ep_ring->dequeue) {
2046                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2047                                         "without IOC set??\n");
2048                         *status = -ESHUTDOWN;
2049                 } else if (event_trb != td->last_trb) {
2050                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2051                                         "without IOC set??\n");
2052                         *status = -ESHUTDOWN;
2053                 } else {
2054                         *status = 0;
2055                 }
2056                 break;
2057         case COMP_SHORT_TX:
2058                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2059                         *status = -EREMOTEIO;
2060                 else
2061                         *status = 0;
2062                 break;
2063         case COMP_STOP_INVAL:
2064         case COMP_STOP:
2065                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2066         default:
2067                 if (!xhci_requires_manual_halt_cleanup(xhci,
2068                                         ep_ctx, trb_comp_code))
2069                         break;
2070                 xhci_dbg(xhci, "TRB error code %u, "
2071                                 "halted endpoint index = %u\n",
2072                                 trb_comp_code, ep_index);
2073                 /* else fall through */
2074         case COMP_STALL:
2075                 /* Did we transfer part of the data (middle) phase? */
2076                 if (event_trb != ep_ring->dequeue &&
2077                                 event_trb != td->last_trb)
2078                         td->urb->actual_length =
2079                                 td->urb->transfer_buffer_length -
2080                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2081                 else
2082                         td->urb->actual_length = 0;
2083
2084                 xhci_cleanup_halted_endpoint(xhci,
2085                         slot_id, ep_index, 0, td, event_trb);
2086                 return finish_td(xhci, td, event_trb, event, ep, status, true);
2087         }
2088         /*
2089          * Did we transfer any data, despite the errors that might have
2090          * happened?  I.e. did we get past the setup stage?
2091          */
2092         if (event_trb != ep_ring->dequeue) {
2093                 /* The event was for the status stage */
2094                 if (event_trb == td->last_trb) {
2095                         if (td->urb->actual_length != 0) {
2096                                 /* Don't overwrite a previously set error code
2097                                  */
2098                                 if ((*status == -EINPROGRESS || *status == 0) &&
2099                                                 (td->urb->transfer_flags
2100                                                  & URB_SHORT_NOT_OK))
2101                                         /* Did we already see a short data
2102                                          * stage? */
2103                                         *status = -EREMOTEIO;
2104                         } else {
2105                                 td->urb->actual_length =
2106                                         td->urb->transfer_buffer_length;
2107                         }
2108                 } else {
2109                 /* Maybe the event was for the data stage? */
2110                         td->urb->actual_length =
2111                                 td->urb->transfer_buffer_length -
2112                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2113                         xhci_dbg(xhci, "Waiting for status "
2114                                         "stage event\n");
2115                         return 0;
2116                 }
2117         }
2118
2119         return finish_td(xhci, td, event_trb, event, ep, status, false);
2120 }
2121
2122 /*
2123  * Process isochronous tds, update urb packet status and actual_length.
2124  */
2125 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2126         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2127         struct xhci_virt_ep *ep, int *status)
2128 {
2129         struct xhci_ring *ep_ring;
2130         struct urb_priv *urb_priv;
2131         int idx;
2132         int len = 0;
2133         union xhci_trb *cur_trb;
2134         struct xhci_segment *cur_seg;
2135         struct usb_iso_packet_descriptor *frame;
2136         u32 trb_comp_code;
2137         bool skip_td = false;
2138
2139         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2140         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2141         urb_priv = td->urb->hcpriv;
2142         idx = urb_priv->td_cnt;
2143         frame = &td->urb->iso_frame_desc[idx];
2144
2145         /* handle completion code */
2146         switch (trb_comp_code) {
2147         case COMP_SUCCESS:
2148                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2149                         frame->status = 0;
2150                         break;
2151                 }
2152                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2153                         trb_comp_code = COMP_SHORT_TX;
2154         case COMP_SHORT_TX:
2155                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2156                                 -EREMOTEIO : 0;
2157                 break;
2158         case COMP_BW_OVER:
2159                 frame->status = -ECOMM;
2160                 skip_td = true;
2161                 break;
2162         case COMP_BUFF_OVER:
2163         case COMP_BABBLE:
2164                 frame->status = -EOVERFLOW;
2165                 skip_td = true;
2166                 break;
2167         case COMP_DEV_ERR:
2168         case COMP_STALL:
2169         case COMP_TX_ERR:
2170                 frame->status = -EPROTO;
2171                 skip_td = true;
2172                 break;
2173         case COMP_STOP:
2174         case COMP_STOP_INVAL:
2175                 break;
2176         default:
2177                 frame->status = -1;
2178                 break;
2179         }
2180
2181         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2182                 frame->actual_length = frame->length;
2183                 td->urb->actual_length += frame->length;
2184         } else {
2185                 for (cur_trb = ep_ring->dequeue,
2186                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2187                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2188                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2189                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2190                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2191                 }
2192                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2193                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2194
2195                 if (trb_comp_code != COMP_STOP_INVAL) {
2196                         frame->actual_length = len;
2197                         td->urb->actual_length += len;
2198                 }
2199         }
2200
2201         return finish_td(xhci, td, event_trb, event, ep, status, false);
2202 }
2203
2204 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2205                         struct xhci_transfer_event *event,
2206                         struct xhci_virt_ep *ep, int *status)
2207 {
2208         struct xhci_ring *ep_ring;
2209         struct urb_priv *urb_priv;
2210         struct usb_iso_packet_descriptor *frame;
2211         int idx;
2212
2213         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2214         urb_priv = td->urb->hcpriv;
2215         idx = urb_priv->td_cnt;
2216         frame = &td->urb->iso_frame_desc[idx];
2217
2218         /* The transfer is partly done. */
2219         frame->status = -EXDEV;
2220
2221         /* calc actual length */
2222         frame->actual_length = 0;
2223
2224         /* Update ring dequeue pointer */
2225         while (ep_ring->dequeue != td->last_trb)
2226                 inc_deq(xhci, ep_ring);
2227         inc_deq(xhci, ep_ring);
2228
2229         return finish_td(xhci, td, NULL, event, ep, status, true);
2230 }
2231
2232 /*
2233  * Process bulk and interrupt tds, update urb status and actual_length.
2234  */
2235 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2236         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2237         struct xhci_virt_ep *ep, int *status)
2238 {
2239         struct xhci_ring *ep_ring;
2240         union xhci_trb *cur_trb;
2241         struct xhci_segment *cur_seg;
2242         u32 trb_comp_code;
2243
2244         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2245         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2246
2247         switch (trb_comp_code) {
2248         case COMP_SUCCESS:
2249                 /* Double check that the HW transferred everything. */
2250                 if (event_trb != td->last_trb ||
2251                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2252                         xhci_warn(xhci, "WARN Successful completion "
2253                                         "on short TX\n");
2254                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2255                                 *status = -EREMOTEIO;
2256                         else
2257                                 *status = 0;
2258                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2259                                 trb_comp_code = COMP_SHORT_TX;
2260                 } else {
2261                         *status = 0;
2262                 }
2263                 break;
2264         case COMP_SHORT_TX:
2265                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2266                         *status = -EREMOTEIO;
2267                 else
2268                         *status = 0;
2269                 break;
2270         default:
2271                 /* Others already handled above */
2272                 break;
2273         }
2274         if (trb_comp_code == COMP_SHORT_TX)
2275                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2276                                 "%d bytes untransferred\n",
2277                                 td->urb->ep->desc.bEndpointAddress,
2278                                 td->urb->transfer_buffer_length,
2279                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2280         /* Fast path - was this the last TRB in the TD for this URB? */
2281         if (event_trb == td->last_trb) {
2282                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2283                         td->urb->actual_length =
2284                                 td->urb->transfer_buffer_length -
2285                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2286                         if (td->urb->transfer_buffer_length <
2287                                         td->urb->actual_length) {
2288                                 xhci_warn(xhci, "HC gave bad length "
2289                                                 "of %d bytes left\n",
2290                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2291                                 td->urb->actual_length = 0;
2292                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2293                                         *status = -EREMOTEIO;
2294                                 else
2295                                         *status = 0;
2296                         }
2297                         /* Don't overwrite a previously set error code */
2298                         if (*status == -EINPROGRESS) {
2299                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2300                                         *status = -EREMOTEIO;
2301                                 else
2302                                         *status = 0;
2303                         }
2304                 } else {
2305                         td->urb->actual_length =
2306                                 td->urb->transfer_buffer_length;
2307                         /* Ignore a short packet completion if the
2308                          * untransferred length was zero.
2309                          */
2310                         if (*status == -EREMOTEIO)
2311                                 *status = 0;
2312                 }
2313         } else {
2314                 /* Slow path - walk the list, starting from the dequeue
2315                  * pointer, to get the actual length transferred.
2316                  */
2317                 td->urb->actual_length = 0;
2318                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2319                                 cur_trb != event_trb;
2320                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2321                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2322                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2323                                 td->urb->actual_length +=
2324                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2325                 }
2326                 /* If the ring didn't stop on a Link or No-op TRB, add
2327                  * in the actual bytes transferred from the Normal TRB
2328                  */
2329                 if (trb_comp_code != COMP_STOP_INVAL)
2330                         td->urb->actual_length +=
2331                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2332                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2333         }
2334
2335         return finish_td(xhci, td, event_trb, event, ep, status, false);
2336 }
2337
2338 /*
2339  * If this function returns an error condition, it means it got a Transfer
2340  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2341  * At this point, the host controller is probably hosed and should be reset.
2342  */
2343 static int handle_tx_event(struct xhci_hcd *xhci,
2344                 struct xhci_transfer_event *event)
2345         __releases(&xhci->lock)
2346         __acquires(&xhci->lock)
2347 {
2348         struct xhci_virt_device *xdev;
2349         struct xhci_virt_ep *ep;
2350         struct xhci_ring *ep_ring;
2351         unsigned int slot_id;
2352         int ep_index;
2353         struct xhci_td *td = NULL;
2354         dma_addr_t event_dma;
2355         struct xhci_segment *event_seg;
2356         union xhci_trb *event_trb;
2357         struct urb *urb = NULL;
2358         int status = -EINPROGRESS;
2359         struct urb_priv *urb_priv;
2360         struct xhci_ep_ctx *ep_ctx;
2361         struct list_head *tmp;
2362         u32 trb_comp_code;
2363         int ret = 0;
2364         int td_num = 0;
2365
2366         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2367         xdev = xhci->devs[slot_id];
2368         if (!xdev) {
2369                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2370                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2371                          (unsigned long long) xhci_trb_virt_to_dma(
2372                                  xhci->event_ring->deq_seg,
2373                                  xhci->event_ring->dequeue),
2374                          lower_32_bits(le64_to_cpu(event->buffer)),
2375                          upper_32_bits(le64_to_cpu(event->buffer)),
2376                          le32_to_cpu(event->transfer_len),
2377                          le32_to_cpu(event->flags));
2378                 xhci_dbg(xhci, "Event ring:\n");
2379                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2380                 return -ENODEV;
2381         }
2382
2383         /* Endpoint ID is 1 based, our index is zero based */
2384         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2385         ep = &xdev->eps[ep_index];
2386         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2387         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2388         if (!ep_ring ||
2389             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2390             EP_STATE_DISABLED) {
2391                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2392                                 "or incorrect stream ring\n");
2393                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2394                          (unsigned long long) xhci_trb_virt_to_dma(
2395                                  xhci->event_ring->deq_seg,
2396                                  xhci->event_ring->dequeue),
2397                          lower_32_bits(le64_to_cpu(event->buffer)),
2398                          upper_32_bits(le64_to_cpu(event->buffer)),
2399                          le32_to_cpu(event->transfer_len),
2400                          le32_to_cpu(event->flags));
2401                 xhci_dbg(xhci, "Event ring:\n");
2402                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2403                 return -ENODEV;
2404         }
2405
2406         /* Count current td numbers if ep->skip is set */
2407         if (ep->skip) {
2408                 list_for_each(tmp, &ep_ring->td_list)
2409                         td_num++;
2410         }
2411
2412         event_dma = le64_to_cpu(event->buffer);
2413         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2414         /* Look for common error cases */
2415         switch (trb_comp_code) {
2416         /* Skip codes that require special handling depending on
2417          * transfer type
2418          */
2419         case COMP_SUCCESS:
2420                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2421                         break;
2422                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2423                         trb_comp_code = COMP_SHORT_TX;
2424                 else
2425                         xhci_warn_ratelimited(xhci,
2426                                         "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2427         case COMP_SHORT_TX:
2428                 break;
2429         case COMP_STOP:
2430                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2431                 break;
2432         case COMP_STOP_INVAL:
2433                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2434                 break;
2435         case COMP_STALL:
2436                 xhci_dbg(xhci, "Stalled endpoint\n");
2437                 ep->ep_state |= EP_HALTED;
2438                 status = -EPIPE;
2439                 break;
2440         case COMP_TRB_ERR:
2441                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2442                 status = -EILSEQ;
2443                 break;
2444         case COMP_SPLIT_ERR:
2445         case COMP_TX_ERR:
2446                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2447                 status = -EPROTO;
2448                 break;
2449         case COMP_BABBLE:
2450                 xhci_dbg(xhci, "Babble error on endpoint\n");
2451                 status = -EOVERFLOW;
2452                 break;
2453         case COMP_DB_ERR:
2454                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2455                 status = -ENOSR;
2456                 break;
2457         case COMP_BW_OVER:
2458                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2459                 break;
2460         case COMP_BUFF_OVER:
2461                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2462                 break;
2463         case COMP_UNDERRUN:
2464                 /*
2465                  * When the Isoch ring is empty, the xHC will generate
2466                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2467                  * Underrun Event for OUT Isoch endpoint.
2468                  */
2469                 xhci_dbg(xhci, "underrun event on endpoint\n");
2470                 if (!list_empty(&ep_ring->td_list))
2471                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2472                                         "still with TDs queued?\n",
2473                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2474                                  ep_index);
2475                 goto cleanup;
2476         case COMP_OVERRUN:
2477                 xhci_dbg(xhci, "overrun event on endpoint\n");
2478                 if (!list_empty(&ep_ring->td_list))
2479                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2480                                         "still with TDs queued?\n",
2481                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2482                                  ep_index);
2483                 goto cleanup;
2484         case COMP_DEV_ERR:
2485                 xhci_warn(xhci, "WARN: detect an incompatible device");
2486                 status = -EPROTO;
2487                 break;
2488         case COMP_MISSED_INT:
2489                 /*
2490                  * When encounter missed service error, one or more isoc tds
2491                  * may be missed by xHC.
2492                  * Set skip flag of the ep_ring; Complete the missed tds as
2493                  * short transfer when process the ep_ring next time.
2494                  */
2495                 ep->skip = true;
2496                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2497                 goto cleanup;
2498         default:
2499                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2500                         status = 0;
2501                         break;
2502                 }
2503                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2504                                 "busted\n");
2505                 goto cleanup;
2506         }
2507
2508         do {
2509                 /* This TRB should be in the TD at the head of this ring's
2510                  * TD list.
2511                  */
2512                 if (list_empty(&ep_ring->td_list)) {
2513                         /*
2514                          * A stopped endpoint may generate an extra completion
2515                          * event if the device was suspended.  Don't print
2516                          * warnings.
2517                          */
2518                         if (!(trb_comp_code == COMP_STOP ||
2519                                                 trb_comp_code == COMP_STOP_INVAL)) {
2520                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2521                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2522                                                 ep_index);
2523                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2524                                                 (le32_to_cpu(event->flags) &
2525                                                  TRB_TYPE_BITMASK)>>10);
2526                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2527                         }
2528                         if (ep->skip) {
2529                                 ep->skip = false;
2530                                 xhci_dbg(xhci, "td_list is empty while skip "
2531                                                 "flag set. Clear skip flag.\n");
2532                         }
2533                         ret = 0;
2534                         goto cleanup;
2535                 }
2536
2537                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2538                 if (ep->skip && td_num == 0) {
2539                         ep->skip = false;
2540                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2541                                                 "Clear skip flag.\n");
2542                         ret = 0;
2543                         goto cleanup;
2544                 }
2545
2546                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2547                 if (ep->skip)
2548                         td_num--;
2549
2550                 /* Is this a TRB in the currently executing TD? */
2551                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2552                                 td->last_trb, event_dma);
2553
2554                 /*
2555                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2556                  * is not in the current TD pointed by ep_ring->dequeue because
2557                  * that the hardware dequeue pointer still at the previous TRB
2558                  * of the current TD. The previous TRB maybe a Link TD or the
2559                  * last TRB of the previous TD. The command completion handle
2560                  * will take care the rest.
2561                  */
2562                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2563                         ret = 0;
2564                         goto cleanup;
2565                 }
2566
2567                 if (!event_seg) {
2568                         if (!ep->skip ||
2569                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2570                                 /* Some host controllers give a spurious
2571                                  * successful event after a short transfer.
2572                                  * Ignore it.
2573                                  */
2574                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2575                                                 ep_ring->last_td_was_short) {
2576                                         ep_ring->last_td_was_short = false;
2577                                         ret = 0;
2578                                         goto cleanup;
2579                                 }
2580                                 /* HC is busted, give up! */
2581                                 xhci_err(xhci,
2582                                         "ERROR Transfer event TRB DMA ptr not "
2583                                         "part of current TD\n");
2584                                 return -ESHUTDOWN;
2585                         }
2586
2587                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2588                         goto cleanup;
2589                 }
2590                 if (trb_comp_code == COMP_SHORT_TX)
2591                         ep_ring->last_td_was_short = true;
2592                 else
2593                         ep_ring->last_td_was_short = false;
2594
2595                 if (ep->skip) {
2596                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2597                         ep->skip = false;
2598                 }
2599
2600                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2601                                                 sizeof(*event_trb)];
2602                 /*
2603                  * No-op TRB should not trigger interrupts.
2604                  * If event_trb is a no-op TRB, it means the
2605                  * corresponding TD has been cancelled. Just ignore
2606                  * the TD.
2607                  */
2608                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2609                         xhci_dbg(xhci,
2610                                  "event_trb is a no-op TRB. Skip it\n");
2611                         goto cleanup;
2612                 }
2613
2614                 /* Now update the urb's actual_length and give back to
2615                  * the core
2616                  */
2617                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2618                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2619                                                  &status);
2620                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2621                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2622                                                  &status);
2623                 else
2624                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2625                                                  ep, &status);
2626
2627 cleanup:
2628                 /*
2629                  * Do not update event ring dequeue pointer if ep->skip is set.
2630                  * Will roll back to continue process missed tds.
2631                  */
2632                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2633                         inc_deq(xhci, xhci->event_ring);
2634                 }
2635
2636                 if (ret) {
2637                         urb = td->urb;
2638                         urb_priv = urb->hcpriv;
2639                         /* Leave the TD around for the reset endpoint function
2640                          * to use(but only if it's not a control endpoint,
2641                          * since we already queued the Set TR dequeue pointer
2642                          * command for stalled control endpoints).
2643                          */
2644                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2645                                 (trb_comp_code != COMP_STALL &&
2646                                         trb_comp_code != COMP_BABBLE))
2647                                 xhci_urb_free_priv(xhci, urb_priv);
2648                         else
2649                                 kfree(urb_priv);
2650
2651                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2652                         if ((urb->actual_length != urb->transfer_buffer_length &&
2653                                                 (urb->transfer_flags &
2654                                                  URB_SHORT_NOT_OK)) ||
2655                                         (status != 0 &&
2656                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2657                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2658                                                 "expected = %d, status = %d\n",
2659                                                 urb, urb->actual_length,
2660                                                 urb->transfer_buffer_length,
2661                                                 status);
2662                         spin_unlock(&xhci->lock);
2663                         /* EHCI, UHCI, and OHCI always unconditionally set the
2664                          * urb->status of an isochronous endpoint to 0.
2665                          */
2666                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2667                                 status = 0;
2668                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2669                         spin_lock(&xhci->lock);
2670                 }
2671
2672         /*
2673          * If ep->skip is set, it means there are missed tds on the
2674          * endpoint ring need to take care of.
2675          * Process them as short transfer until reach the td pointed by
2676          * the event.
2677          */
2678         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2679
2680         return 0;
2681 }
2682
2683 /*
2684  * This function handles all OS-owned events on the event ring.  It may drop
2685  * xhci->lock between event processing (e.g. to pass up port status changes).
2686  * Returns >0 for "possibly more events to process" (caller should call again),
2687  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2688  */
2689 static int xhci_handle_event(struct xhci_hcd *xhci)
2690 {
2691         union xhci_trb *event;
2692         int update_ptrs = 1;
2693         int ret;
2694
2695         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2696                 xhci->error_bitmask |= 1 << 1;
2697                 return 0;
2698         }
2699
2700         event = xhci->event_ring->dequeue;
2701         /* Does the HC or OS own the TRB? */
2702         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2703             xhci->event_ring->cycle_state) {
2704                 xhci->error_bitmask |= 1 << 2;
2705                 return 0;
2706         }
2707
2708         /*
2709          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2710          * speculative reads of the event's flags/data below.
2711          */
2712         rmb();
2713         /* FIXME: Handle more event types. */
2714         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2715         case TRB_TYPE(TRB_COMPLETION):
2716                 handle_cmd_completion(xhci, &event->event_cmd);
2717                 break;
2718         case TRB_TYPE(TRB_PORT_STATUS):
2719                 handle_port_status(xhci, event);
2720                 update_ptrs = 0;
2721                 break;
2722         case TRB_TYPE(TRB_TRANSFER):
2723                 ret = handle_tx_event(xhci, &event->trans_event);
2724                 if (ret < 0)
2725                         xhci->error_bitmask |= 1 << 9;
2726                 else
2727                         update_ptrs = 0;
2728                 break;
2729         case TRB_TYPE(TRB_DEV_NOTE):
2730                 handle_device_notification(xhci, event);
2731                 break;
2732         default:
2733                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2734                     TRB_TYPE(48))
2735                         handle_vendor_event(xhci, event);
2736                 else
2737                         xhci->error_bitmask |= 1 << 3;
2738         }
2739         /* Any of the above functions may drop and re-acquire the lock, so check
2740          * to make sure a watchdog timer didn't mark the host as non-responsive.
2741          */
2742         if (xhci->xhc_state & XHCI_STATE_DYING) {
2743                 xhci_dbg(xhci, "xHCI host dying, returning from "
2744                                 "event handler.\n");
2745                 return 0;
2746         }
2747
2748         if (update_ptrs)
2749                 /* Update SW event ring dequeue pointer */
2750                 inc_deq(xhci, xhci->event_ring);
2751
2752         /* Are there more items on the event ring?  Caller will call us again to
2753          * check.
2754          */
2755         return 1;
2756 }
2757
2758 /*
2759  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2760  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2761  * indicators of an event TRB error, but we check the status *first* to be safe.
2762  */
2763 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2764 {
2765         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2766         u32 status;
2767         u64 temp_64;
2768         union xhci_trb *event_ring_deq;
2769         dma_addr_t deq;
2770
2771         spin_lock(&xhci->lock);
2772         /* Check if the xHC generated the interrupt, or the irq is shared */
2773         status = xhci_readl(xhci, &xhci->op_regs->status);
2774         if (status == 0xffffffff)
2775                 goto hw_died;
2776
2777         if (!(status & STS_EINT)) {
2778                 spin_unlock(&xhci->lock);
2779                 return IRQ_NONE;
2780         }
2781         if (status & STS_FATAL) {
2782                 xhci_warn(xhci, "WARNING: Host System Error\n");
2783                 xhci_halt(xhci);
2784 hw_died:
2785                 spin_unlock(&xhci->lock);
2786                 return -ESHUTDOWN;
2787         }
2788
2789         /*
2790          * Clear the op reg interrupt status first,
2791          * so we can receive interrupts from other MSI-X interrupters.
2792          * Write 1 to clear the interrupt status.
2793          */
2794         status |= STS_EINT;
2795         xhci_writel(xhci, status, &xhci->op_regs->status);
2796         /* FIXME when MSI-X is supported and there are multiple vectors */
2797         /* Clear the MSI-X event interrupt status */
2798
2799         if (hcd->irq) {
2800                 u32 irq_pending;
2801                 /* Acknowledge the PCI interrupt */
2802                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2803                 irq_pending |= IMAN_IP;
2804                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2805         }
2806
2807         if (xhci->xhc_state & XHCI_STATE_DYING) {
2808                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2809                                 "Shouldn't IRQs be disabled?\n");
2810                 /* Clear the event handler busy flag (RW1C);
2811                  * the event ring should be empty.
2812                  */
2813                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2814                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2815                                 &xhci->ir_set->erst_dequeue);
2816                 spin_unlock(&xhci->lock);
2817
2818                 return IRQ_HANDLED;
2819         }
2820
2821         event_ring_deq = xhci->event_ring->dequeue;
2822         /* FIXME this should be a delayed service routine
2823          * that clears the EHB.
2824          */
2825         while (xhci_handle_event(xhci) > 0) {}
2826
2827         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2828         /* If necessary, update the HW's version of the event ring deq ptr. */
2829         if (event_ring_deq != xhci->event_ring->dequeue) {
2830                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2831                                 xhci->event_ring->dequeue);
2832                 if (deq == 0)
2833                         xhci_warn(xhci, "WARN something wrong with SW event "
2834                                         "ring dequeue ptr.\n");
2835                 /* Update HC event ring dequeue pointer */
2836                 temp_64 &= ERST_PTR_MASK;
2837                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2838         }
2839
2840         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2841         temp_64 |= ERST_EHB;
2842         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2843
2844         spin_unlock(&xhci->lock);
2845
2846         return IRQ_HANDLED;
2847 }
2848
2849 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2850 {
2851         return xhci_irq(hcd);
2852 }
2853
2854 /****           Endpoint Ring Operations        ****/
2855
2856 /*
2857  * Generic function for queueing a TRB on a ring.
2858  * The caller must have checked to make sure there's room on the ring.
2859  *
2860  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2861  *                      prepare_transfer()?
2862  */
2863 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2864                 bool more_trbs_coming,
2865                 u32 field1, u32 field2, u32 field3, u32 field4)
2866 {
2867         struct xhci_generic_trb *trb;
2868
2869         trb = &ring->enqueue->generic;
2870         trb->field[0] = cpu_to_le32(field1);
2871         trb->field[1] = cpu_to_le32(field2);
2872         trb->field[2] = cpu_to_le32(field3);
2873         trb->field[3] = cpu_to_le32(field4);
2874         inc_enq(xhci, ring, more_trbs_coming);
2875 }
2876
2877 /*
2878  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2879  * FIXME allocate segments if the ring is full.
2880  */
2881 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2882                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2883 {
2884         unsigned int num_trbs_needed;
2885
2886         /* Make sure the endpoint has been added to xHC schedule */
2887         switch (ep_state) {
2888         case EP_STATE_DISABLED:
2889                 /*
2890                  * USB core changed config/interfaces without notifying us,
2891                  * or hardware is reporting the wrong state.
2892                  */
2893                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2894                 return -ENOENT;
2895         case EP_STATE_ERROR:
2896                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2897                 /* FIXME event handling code for error needs to clear it */
2898                 /* XXX not sure if this should be -ENOENT or not */
2899                 return -EINVAL;
2900         case EP_STATE_HALTED:
2901                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2902         case EP_STATE_STOPPED:
2903         case EP_STATE_RUNNING:
2904                 break;
2905         default:
2906                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2907                 /*
2908                  * FIXME issue Configure Endpoint command to try to get the HC
2909                  * back into a known state.
2910                  */
2911                 return -EINVAL;
2912         }
2913
2914         while (1) {
2915                 if (room_on_ring(xhci, ep_ring, num_trbs))
2916                         break;
2917
2918                 if (ep_ring == xhci->cmd_ring) {
2919                         xhci_err(xhci, "Do not support expand command ring\n");
2920                         return -ENOMEM;
2921                 }
2922
2923                 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2924                                 "ERROR no room on ep ring, try ring expansion");
2925                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2926                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2927                                         mem_flags)) {
2928                         xhci_err(xhci, "Ring expansion failed\n");
2929                         return -ENOMEM;
2930                 }
2931         }
2932
2933         if (enqueue_is_link_trb(ep_ring)) {
2934                 struct xhci_ring *ring = ep_ring;
2935                 union xhci_trb *next;
2936
2937                 next = ring->enqueue;
2938
2939                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2940                         /* If we're not dealing with 0.95 hardware or isoc rings
2941                          * on AMD 0.96 host, clear the chain bit.
2942                          */
2943                         if (!xhci_link_trb_quirk(xhci) &&
2944                                         !(ring->type == TYPE_ISOC &&
2945                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
2946                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2947                         else
2948                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2949
2950                         wmb();
2951                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2952
2953                         /* Toggle the cycle bit after the last ring segment. */
2954                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2955                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2956                         }
2957                         ring->enq_seg = ring->enq_seg->next;
2958                         ring->enqueue = ring->enq_seg->trbs;
2959                         next = ring->enqueue;
2960                 }
2961         }
2962
2963         return 0;
2964 }
2965
2966 static int prepare_transfer(struct xhci_hcd *xhci,
2967                 struct xhci_virt_device *xdev,
2968                 unsigned int ep_index,
2969                 unsigned int stream_id,
2970                 unsigned int num_trbs,
2971                 struct urb *urb,
2972                 unsigned int td_index,
2973                 gfp_t mem_flags)
2974 {
2975         int ret;
2976         struct urb_priv *urb_priv;
2977         struct xhci_td  *td;
2978         struct xhci_ring *ep_ring;
2979         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2980
2981         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2982         if (!ep_ring) {
2983                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2984                                 stream_id);
2985                 return -EINVAL;
2986         }
2987
2988         ret = prepare_ring(xhci, ep_ring,
2989                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2990                            num_trbs, mem_flags);
2991         if (ret)
2992                 return ret;
2993
2994         urb_priv = urb->hcpriv;
2995         td = urb_priv->td[td_index];
2996
2997         INIT_LIST_HEAD(&td->td_list);
2998         INIT_LIST_HEAD(&td->cancelled_td_list);
2999
3000         if (td_index == 0) {
3001                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3002                 if (unlikely(ret))
3003                         return ret;
3004         }
3005
3006         td->urb = urb;
3007         /* Add this TD to the tail of the endpoint ring's TD list */
3008         list_add_tail(&td->td_list, &ep_ring->td_list);
3009         td->start_seg = ep_ring->enq_seg;
3010         td->first_trb = ep_ring->enqueue;
3011
3012         urb_priv->td[td_index] = td;
3013
3014         return 0;
3015 }
3016
3017 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
3018 {
3019         int num_sgs, num_trbs, running_total, temp, i;
3020         struct scatterlist *sg;
3021
3022         sg = NULL;
3023         num_sgs = urb->num_mapped_sgs;
3024         temp = urb->transfer_buffer_length;
3025
3026         num_trbs = 0;
3027         for_each_sg(urb->sg, sg, num_sgs, i) {
3028                 unsigned int len = sg_dma_len(sg);
3029
3030                 /* Scatter gather list entries may cross 64KB boundaries */
3031                 running_total = TRB_MAX_BUFF_SIZE -
3032                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3033                 running_total &= TRB_MAX_BUFF_SIZE - 1;
3034                 if (running_total != 0)
3035                         num_trbs++;
3036
3037                 /* How many more 64KB chunks to transfer, how many more TRBs? */
3038                 while (running_total < sg_dma_len(sg) && running_total < temp) {
3039                         num_trbs++;
3040                         running_total += TRB_MAX_BUFF_SIZE;
3041                 }
3042                 len = min_t(int, len, temp);
3043                 temp -= len;
3044                 if (temp == 0)
3045                         break;
3046         }
3047         return num_trbs;
3048 }
3049
3050 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3051 {
3052         if (num_trbs != 0)
3053                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3054                                 "TRBs, %d left\n", __func__,
3055                                 urb->ep->desc.bEndpointAddress, num_trbs);
3056         if (running_total != urb->transfer_buffer_length)
3057                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3058                                 "queued %#x (%d), asked for %#x (%d)\n",
3059                                 __func__,
3060                                 urb->ep->desc.bEndpointAddress,
3061                                 running_total, running_total,
3062                                 urb->transfer_buffer_length,
3063                                 urb->transfer_buffer_length);
3064 }
3065
3066 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3067                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3068                 struct xhci_generic_trb *start_trb)
3069 {
3070         /*
3071          * Pass all the TRBs to the hardware at once and make sure this write
3072          * isn't reordered.
3073          */
3074         wmb();
3075         if (start_cycle)
3076                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3077         else
3078                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3079         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3080 }
3081
3082 /*
3083  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3084  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3085  * (comprised of sg list entries) can take several service intervals to
3086  * transmit.
3087  */
3088 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3089                 struct urb *urb, int slot_id, unsigned int ep_index)
3090 {
3091         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3092                         xhci->devs[slot_id]->out_ctx, ep_index);
3093         int xhci_interval;
3094         int ep_interval;
3095
3096         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3097         ep_interval = urb->interval;
3098         /* Convert to microframes */
3099         if (urb->dev->speed == USB_SPEED_LOW ||
3100                         urb->dev->speed == USB_SPEED_FULL)
3101                 ep_interval *= 8;
3102         /* FIXME change this to a warning and a suggestion to use the new API
3103          * to set the polling interval (once the API is added).
3104          */
3105         if (xhci_interval != ep_interval) {
3106                 dev_dbg_ratelimited(&urb->dev->dev,
3107                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3108                                 ep_interval, ep_interval == 1 ? "" : "s",
3109                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3110                 urb->interval = xhci_interval;
3111                 /* Convert back to frames for LS/FS devices */
3112                 if (urb->dev->speed == USB_SPEED_LOW ||
3113                                 urb->dev->speed == USB_SPEED_FULL)
3114                         urb->interval /= 8;
3115         }
3116         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3117 }
3118
3119 /*
3120  * The TD size is the number of bytes remaining in the TD (including this TRB),
3121  * right shifted by 10.
3122  * It must fit in bits 21:17, so it can't be bigger than 31.
3123  */
3124 static u32 xhci_td_remainder(unsigned int remainder)
3125 {
3126         u32 max = (1 << (21 - 17 + 1)) - 1;
3127
3128         if ((remainder >> 10) >= max)
3129                 return max << 17;
3130         else
3131                 return (remainder >> 10) << 17;
3132 }
3133
3134 /*
3135  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3136  * packets remaining in the TD (*not* including this TRB).
3137  *
3138  * Total TD packet count = total_packet_count =
3139  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3140  *
3141  * Packets transferred up to and including this TRB = packets_transferred =
3142  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3143  *
3144  * TD size = total_packet_count - packets_transferred
3145  *
3146  * It must fit in bits 21:17, so it can't be bigger than 31.
3147  * The last TRB in a TD must have the TD size set to zero.
3148  */
3149 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3150                 unsigned int total_packet_count, struct urb *urb,
3151                 unsigned int num_trbs_left)
3152 {
3153         int packets_transferred;
3154
3155         /* One TRB with a zero-length data packet. */
3156         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3157                 return 0;
3158
3159         /* All the TRB queueing functions don't count the current TRB in
3160          * running_total.
3161          */
3162         packets_transferred = (running_total + trb_buff_len) /
3163                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3164
3165         if ((total_packet_count - packets_transferred) > 31)
3166                 return 31 << 17;
3167         return (total_packet_count - packets_transferred) << 17;
3168 }
3169
3170 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3171                 struct urb *urb, int slot_id, unsigned int ep_index)
3172 {
3173         struct xhci_ring *ep_ring;
3174         unsigned int num_trbs;
3175         struct urb_priv *urb_priv;
3176         struct xhci_td *td;
3177         struct scatterlist *sg;
3178         int num_sgs;
3179         int trb_buff_len, this_sg_len, running_total;
3180         unsigned int total_packet_count;
3181         bool first_trb;
3182         u64 addr;
3183         bool more_trbs_coming;
3184
3185         struct xhci_generic_trb *start_trb;
3186         int start_cycle;
3187
3188         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3189         if (!ep_ring)
3190                 return -EINVAL;
3191
3192         num_trbs = count_sg_trbs_needed(xhci, urb);
3193         num_sgs = urb->num_mapped_sgs;
3194         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3195                         usb_endpoint_maxp(&urb->ep->desc));
3196
3197         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3198                         ep_index, urb->stream_id,
3199                         num_trbs, urb, 0, mem_flags);
3200         if (trb_buff_len < 0)
3201                 return trb_buff_len;
3202
3203         urb_priv = urb->hcpriv;
3204         td = urb_priv->td[0];
3205
3206         /*
3207          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3208          * until we've finished creating all the other TRBs.  The ring's cycle
3209          * state may change as we enqueue the other TRBs, so save it too.
3210          */
3211         start_trb = &ep_ring->enqueue->generic;
3212         start_cycle = ep_ring->cycle_state;
3213
3214         running_total = 0;
3215         /*
3216          * How much data is in the first TRB?
3217          *
3218          * There are three forces at work for TRB buffer pointers and lengths:
3219          * 1. We don't want to walk off the end of this sg-list entry buffer.
3220          * 2. The transfer length that the driver requested may be smaller than
3221          *    the amount of memory allocated for this scatter-gather list.
3222          * 3. TRBs buffers can't cross 64KB boundaries.
3223          */
3224         sg = urb->sg;
3225         addr = (u64) sg_dma_address(sg);
3226         this_sg_len = sg_dma_len(sg);
3227         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3228         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3229         if (trb_buff_len > urb->transfer_buffer_length)
3230                 trb_buff_len = urb->transfer_buffer_length;
3231
3232         first_trb = true;
3233         /* Queue the first TRB, even if it's zero-length */
3234         do {
3235                 u32 field = 0;
3236                 u32 length_field = 0;
3237                 u32 remainder = 0;
3238
3239                 /* Don't change the cycle bit of the first TRB until later */
3240                 if (first_trb) {
3241                         first_trb = false;
3242                         if (start_cycle == 0)
3243                                 field |= 0x1;
3244                 } else
3245                         field |= ep_ring->cycle_state;
3246
3247                 /* Chain all the TRBs together; clear the chain bit in the last
3248                  * TRB to indicate it's the last TRB in the chain.
3249                  */
3250                 if (num_trbs > 1) {
3251                         field |= TRB_CHAIN;
3252                 } else {
3253                         /* FIXME - add check for ZERO_PACKET flag before this */
3254                         td->last_trb = ep_ring->enqueue;
3255                         field |= TRB_IOC;
3256                 }
3257
3258                 /* Only set interrupt on short packet for IN endpoints */
3259                 if (usb_urb_dir_in(urb))
3260                         field |= TRB_ISP;
3261
3262                 if (TRB_MAX_BUFF_SIZE -
3263                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3264                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3265                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3266                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3267                                         (unsigned int) addr + trb_buff_len);
3268                 }
3269
3270                 /* Set the TRB length, TD size, and interrupter fields. */
3271                 if (xhci->hci_version < 0x100) {
3272                         remainder = xhci_td_remainder(
3273                                         urb->transfer_buffer_length -
3274                                         running_total);
3275                 } else {
3276                         remainder = xhci_v1_0_td_remainder(running_total,
3277                                         trb_buff_len, total_packet_count, urb,
3278                                         num_trbs - 1);
3279                 }
3280                 length_field = TRB_LEN(trb_buff_len) |
3281                         remainder |
3282                         TRB_INTR_TARGET(0);
3283
3284                 if (num_trbs > 1)
3285                         more_trbs_coming = true;
3286                 else
3287                         more_trbs_coming = false;
3288                 queue_trb(xhci, ep_ring, more_trbs_coming,
3289                                 lower_32_bits(addr),
3290                                 upper_32_bits(addr),
3291                                 length_field,
3292                                 field | TRB_TYPE(TRB_NORMAL));
3293                 --num_trbs;
3294                 running_total += trb_buff_len;
3295
3296                 /* Calculate length for next transfer --
3297                  * Are we done queueing all the TRBs for this sg entry?
3298                  */
3299                 this_sg_len -= trb_buff_len;
3300                 if (this_sg_len == 0) {
3301                         --num_sgs;
3302                         if (num_sgs == 0)
3303                                 break;
3304                         sg = sg_next(sg);
3305                         addr = (u64) sg_dma_address(sg);
3306                         this_sg_len = sg_dma_len(sg);
3307                 } else {
3308                         addr += trb_buff_len;
3309                 }
3310
3311                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3312                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3313                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3314                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3315                         trb_buff_len =
3316                                 urb->transfer_buffer_length - running_total;
3317         } while (running_total < urb->transfer_buffer_length);
3318
3319         check_trb_math(urb, num_trbs, running_total);
3320         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3321                         start_cycle, start_trb);
3322         return 0;
3323 }
3324
3325 /* This is very similar to what ehci-q.c qtd_fill() does */
3326 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3327                 struct urb *urb, int slot_id, unsigned int ep_index)
3328 {
3329         struct xhci_ring *ep_ring;
3330         struct urb_priv *urb_priv;
3331         struct xhci_td *td;
3332         int num_trbs;
3333         struct xhci_generic_trb *start_trb;
3334         bool first_trb;
3335         bool more_trbs_coming;
3336         int start_cycle;
3337         u32 field, length_field;
3338
3339         int running_total, trb_buff_len, ret;
3340         unsigned int total_packet_count;
3341         u64 addr;
3342
3343         if (urb->num_sgs)
3344                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3345
3346         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3347         if (!ep_ring)
3348                 return -EINVAL;
3349
3350         num_trbs = 0;
3351         /* How much data is (potentially) left before the 64KB boundary? */
3352         running_total = TRB_MAX_BUFF_SIZE -
3353                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3354         running_total &= TRB_MAX_BUFF_SIZE - 1;
3355
3356         /* If there's some data on this 64KB chunk, or we have to send a
3357          * zero-length transfer, we need at least one TRB
3358          */
3359         if (running_total != 0 || urb->transfer_buffer_length == 0)
3360                 num_trbs++;
3361         /* How many more 64KB chunks to transfer, how many more TRBs? */
3362         while (running_total < urb->transfer_buffer_length) {
3363                 num_trbs++;
3364                 running_total += TRB_MAX_BUFF_SIZE;
3365         }
3366         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3367
3368         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3369                         ep_index, urb->stream_id,
3370                         num_trbs, urb, 0, mem_flags);
3371         if (ret < 0)
3372                 return ret;
3373
3374         urb_priv = urb->hcpriv;
3375         td = urb_priv->td[0];
3376
3377         /*
3378          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3379          * until we've finished creating all the other TRBs.  The ring's cycle
3380          * state may change as we enqueue the other TRBs, so save it too.
3381          */
3382         start_trb = &ep_ring->enqueue->generic;
3383         start_cycle = ep_ring->cycle_state;
3384
3385         running_total = 0;
3386         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3387                         usb_endpoint_maxp(&urb->ep->desc));
3388         /* How much data is in the first TRB? */
3389         addr = (u64) urb->transfer_dma;
3390         trb_buff_len = TRB_MAX_BUFF_SIZE -
3391                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3392         if (trb_buff_len > urb->transfer_buffer_length)
3393                 trb_buff_len = urb->transfer_buffer_length;
3394
3395         first_trb = true;
3396
3397         /* Queue the first TRB, even if it's zero-length */
3398         do {
3399                 u32 remainder = 0;
3400                 field = 0;
3401
3402                 /* Don't change the cycle bit of the first TRB until later */
3403                 if (first_trb) {
3404                         first_trb = false;
3405                         if (start_cycle == 0)
3406                                 field |= 0x1;
3407                 } else
3408                         field |= ep_ring->cycle_state;
3409
3410                 /* Chain all the TRBs together; clear the chain bit in the last
3411                  * TRB to indicate it's the last TRB in the chain.
3412                  */
3413                 if (num_trbs > 1) {
3414                         field |= TRB_CHAIN;
3415                 } else {
3416                         /* FIXME - add check for ZERO_PACKET flag before this */
3417                         td->last_trb = ep_ring->enqueue;
3418                         field |= TRB_IOC;
3419                 }
3420
3421                 /* Only set interrupt on short packet for IN endpoints */
3422                 if (usb_urb_dir_in(urb))
3423                         field |= TRB_ISP;
3424
3425                 /* Set the TRB length, TD size, and interrupter fields. */
3426                 if (xhci->hci_version < 0x100) {
3427                         remainder = xhci_td_remainder(
3428                                         urb->transfer_buffer_length -
3429                                         running_total);
3430                 } else {
3431                         remainder = xhci_v1_0_td_remainder(running_total,
3432                                         trb_buff_len, total_packet_count, urb,
3433                                         num_trbs - 1);
3434                 }
3435                 length_field = TRB_LEN(trb_buff_len) |
3436                         remainder |
3437                         TRB_INTR_TARGET(0);
3438
3439                 if (num_trbs > 1)
3440                         more_trbs_coming = true;
3441                 else
3442                         more_trbs_coming = false;
3443                 queue_trb(xhci, ep_ring, more_trbs_coming,
3444                                 lower_32_bits(addr),
3445                                 upper_32_bits(addr),
3446                                 length_field,
3447                                 field | TRB_TYPE(TRB_NORMAL));
3448                 --num_trbs;
3449                 running_total += trb_buff_len;
3450
3451                 /* Calculate length for next transfer */
3452                 addr += trb_buff_len;
3453                 trb_buff_len = urb->transfer_buffer_length - running_total;
3454                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3455                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3456         } while (running_total < urb->transfer_buffer_length);
3457
3458         check_trb_math(urb, num_trbs, running_total);
3459         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3460                         start_cycle, start_trb);
3461         return 0;
3462 }
3463
3464 /* Caller must have locked xhci->lock */
3465 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3466                 struct urb *urb, int slot_id, unsigned int ep_index)
3467 {
3468         struct xhci_ring *ep_ring;
3469         int num_trbs;
3470         int ret;
3471         struct usb_ctrlrequest *setup;
3472         struct xhci_generic_trb *start_trb;
3473         int start_cycle;
3474         u32 field, length_field;
3475         struct urb_priv *urb_priv;
3476         struct xhci_td *td;
3477
3478         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3479         if (!ep_ring)
3480                 return -EINVAL;
3481
3482         /*
3483          * Need to copy setup packet into setup TRB, so we can't use the setup
3484          * DMA address.
3485          */
3486         if (!urb->setup_packet)
3487                 return -EINVAL;
3488
3489         /* 1 TRB for setup, 1 for status */
3490         num_trbs = 2;
3491         /*
3492          * Don't need to check if we need additional event data and normal TRBs,
3493          * since data in control transfers will never get bigger than 16MB
3494          * XXX: can we get a buffer that crosses 64KB boundaries?
3495          */
3496         if (urb->transfer_buffer_length > 0)
3497                 num_trbs++;
3498         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3499                         ep_index, urb->stream_id,
3500                         num_trbs, urb, 0, mem_flags);
3501         if (ret < 0)
3502                 return ret;
3503
3504         urb_priv = urb->hcpriv;
3505         td = urb_priv->td[0];
3506
3507         /*
3508          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3509          * until we've finished creating all the other TRBs.  The ring's cycle
3510          * state may change as we enqueue the other TRBs, so save it too.
3511          */
3512         start_trb = &ep_ring->enqueue->generic;
3513         start_cycle = ep_ring->cycle_state;
3514
3515         /* Queue setup TRB - see section 6.4.1.2.1 */
3516         /* FIXME better way to translate setup_packet into two u32 fields? */
3517         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3518         field = 0;
3519         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3520         if (start_cycle == 0)
3521                 field |= 0x1;
3522
3523         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3524         if (xhci->hci_version == 0x100) {
3525                 if (urb->transfer_buffer_length > 0) {
3526                         if (setup->bRequestType & USB_DIR_IN)
3527                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3528                         else
3529                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3530                 }
3531         }
3532
3533         queue_trb(xhci, ep_ring, true,
3534                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3535                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3536                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3537                   /* Immediate data in pointer */
3538                   field);
3539
3540         /* If there's data, queue data TRBs */
3541         /* Only set interrupt on short packet for IN endpoints */
3542         if (usb_urb_dir_in(urb))
3543                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3544         else
3545                 field = TRB_TYPE(TRB_DATA);
3546
3547         length_field = TRB_LEN(urb->transfer_buffer_length) |
3548                 xhci_td_remainder(urb->transfer_buffer_length) |
3549                 TRB_INTR_TARGET(0);
3550         if (urb->transfer_buffer_length > 0) {
3551                 if (setup->bRequestType & USB_DIR_IN)
3552                         field |= TRB_DIR_IN;
3553                 queue_trb(xhci, ep_ring, true,
3554                                 lower_32_bits(urb->transfer_dma),
3555                                 upper_32_bits(urb->transfer_dma),
3556                                 length_field,
3557                                 field | ep_ring->cycle_state);
3558         }
3559
3560         /* Save the DMA address of the last TRB in the TD */
3561         td->last_trb = ep_ring->enqueue;
3562
3563         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3564         /* If the device sent data, the status stage is an OUT transfer */
3565         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3566                 field = 0;
3567         else
3568                 field = TRB_DIR_IN;
3569         queue_trb(xhci, ep_ring, false,
3570                         0,
3571                         0,
3572                         TRB_INTR_TARGET(0),
3573                         /* Event on completion */
3574                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3575
3576         giveback_first_trb(xhci, slot_id, ep_index, 0,
3577                         start_cycle, start_trb);
3578         return 0;
3579 }
3580
3581 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3582                 struct urb *urb, int i)
3583 {
3584         int num_trbs = 0;
3585         u64 addr, td_len;
3586
3587         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3588         td_len = urb->iso_frame_desc[i].length;
3589
3590         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3591                         TRB_MAX_BUFF_SIZE);
3592         if (num_trbs == 0)
3593                 num_trbs++;
3594
3595         return num_trbs;
3596 }
3597
3598 /*
3599  * The transfer burst count field of the isochronous TRB defines the number of
3600  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3601  * devices can burst up to bMaxBurst number of packets per service interval.
3602  * This field is zero based, meaning a value of zero in the field means one
3603  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3604  * zero.  Only xHCI 1.0 host controllers support this field.
3605  */
3606 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3607                 struct usb_device *udev,
3608                 struct urb *urb, unsigned int total_packet_count)
3609 {
3610         unsigned int max_burst;
3611
3612         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3613                 return 0;
3614
3615         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3616         return roundup(total_packet_count, max_burst + 1) - 1;
3617 }
3618
3619 /*
3620  * Returns the number of packets in the last "burst" of packets.  This field is
3621  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3622  * the last burst packet count is equal to the total number of packets in the
3623  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3624  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3625  * contain 1 to (bMaxBurst + 1) packets.
3626  */
3627 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3628                 struct usb_device *udev,
3629                 struct urb *urb, unsigned int total_packet_count)
3630 {
3631         unsigned int max_burst;
3632         unsigned int residue;
3633
3634         if (xhci->hci_version < 0x100)
3635                 return 0;
3636
3637         switch (udev->speed) {
3638         case USB_SPEED_SUPER:
3639                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3640                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3641                 residue = total_packet_count % (max_burst + 1);
3642                 /* If residue is zero, the last burst contains (max_burst + 1)
3643                  * number of packets, but the TLBPC field is zero-based.
3644                  */
3645                 if (residue == 0)
3646                         return max_burst;
3647                 return residue - 1;
3648         default:
3649                 if (total_packet_count == 0)
3650                         return 0;
3651                 return total_packet_count - 1;
3652         }
3653 }
3654
3655 /* This is for isoc transfer */
3656 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3657                 struct urb *urb, int slot_id, unsigned int ep_index)
3658 {
3659         struct xhci_ring *ep_ring;
3660         struct urb_priv *urb_priv;
3661         struct xhci_td *td;
3662         int num_tds, trbs_per_td;
3663         struct xhci_generic_trb *start_trb;
3664         bool first_trb;
3665         int start_cycle;
3666         u32 field, length_field;
3667         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3668         u64 start_addr, addr;
3669         int i, j;
3670         bool more_trbs_coming;
3671
3672         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3673
3674         num_tds = urb->number_of_packets;
3675         if (num_tds < 1) {
3676                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3677                 return -EINVAL;
3678         }
3679
3680         start_addr = (u64) urb->transfer_dma;
3681         start_trb = &ep_ring->enqueue->generic;
3682         start_cycle = ep_ring->cycle_state;
3683
3684         urb_priv = urb->hcpriv;
3685         /* Queue the first TRB, even if it's zero-length */
3686         for (i = 0; i < num_tds; i++) {
3687                 unsigned int total_packet_count;
3688                 unsigned int burst_count;
3689                 unsigned int residue;
3690
3691                 first_trb = true;
3692                 running_total = 0;
3693                 addr = start_addr + urb->iso_frame_desc[i].offset;
3694                 td_len = urb->iso_frame_desc[i].length;
3695                 td_remain_len = td_len;
3696                 total_packet_count = DIV_ROUND_UP(td_len,
3697                                 GET_MAX_PACKET(
3698                                         usb_endpoint_maxp(&urb->ep->desc)));
3699                 /* A zero-length transfer still involves at least one packet. */
3700                 if (total_packet_count == 0)
3701                         total_packet_count++;
3702                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3703                                 total_packet_count);
3704                 residue = xhci_get_last_burst_packet_count(xhci,
3705                                 urb->dev, urb, total_packet_count);
3706
3707                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3708
3709                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3710                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3711                 if (ret < 0) {
3712                         if (i == 0)
3713                                 return ret;
3714                         goto cleanup;
3715                 }
3716
3717                 td = urb_priv->td[i];
3718                 for (j = 0; j < trbs_per_td; j++) {
3719                         u32 remainder = 0;
3720                         field = 0;
3721
3722                         if (first_trb) {
3723                                 field = TRB_TBC(burst_count) |
3724                                         TRB_TLBPC(residue);
3725                                 /* Queue the isoc TRB */
3726                                 field |= TRB_TYPE(TRB_ISOC);
3727                                 /* Assume URB_ISO_ASAP is set */
3728                                 field |= TRB_SIA;
3729                                 if (i == 0) {
3730                                         if (start_cycle == 0)
3731                                                 field |= 0x1;
3732                                 } else
3733                                         field |= ep_ring->cycle_state;
3734                                 first_trb = false;
3735                         } else {
3736                                 /* Queue other normal TRBs */
3737                                 field |= TRB_TYPE(TRB_NORMAL);
3738                                 field |= ep_ring->cycle_state;
3739                         }
3740
3741                         /* Only set interrupt on short packet for IN EPs */
3742                         if (usb_urb_dir_in(urb))
3743                                 field |= TRB_ISP;
3744
3745                         /* Chain all the TRBs together; clear the chain bit in
3746                          * the last TRB to indicate it's the last TRB in the
3747                          * chain.
3748                          */
3749                         if (j < trbs_per_td - 1) {
3750                                 field |= TRB_CHAIN;
3751                                 more_trbs_coming = true;
3752                         } else {
3753                                 td->last_trb = ep_ring->enqueue;
3754                                 field |= TRB_IOC;
3755                                 if (xhci->hci_version == 0x100 &&
3756                                                 !(xhci->quirks &
3757                                                         XHCI_AVOID_BEI)) {
3758                                         /* Set BEI bit except for the last td */
3759                                         if (i < num_tds - 1)
3760                                                 field |= TRB_BEI;
3761                                 }
3762                                 more_trbs_coming = false;
3763                         }
3764
3765                         /* Calculate TRB length */
3766                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3767                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3768                         if (trb_buff_len > td_remain_len)
3769                                 trb_buff_len = td_remain_len;
3770
3771                         /* Set the TRB length, TD size, & interrupter fields. */
3772                         if (xhci->hci_version < 0x100) {
3773                                 remainder = xhci_td_remainder(
3774                                                 td_len - running_total);
3775                         } else {
3776                                 remainder = xhci_v1_0_td_remainder(
3777                                                 running_total, trb_buff_len,
3778                                                 total_packet_count, urb,
3779                                                 (trbs_per_td - j - 1));
3780                         }
3781                         length_field = TRB_LEN(trb_buff_len) |
3782                                 remainder |
3783                                 TRB_INTR_TARGET(0);
3784
3785                         queue_trb(xhci, ep_ring, more_trbs_coming,
3786                                 lower_32_bits(addr),
3787                                 upper_32_bits(addr),
3788                                 length_field,
3789                                 field);
3790                         running_total += trb_buff_len;
3791
3792                         addr += trb_buff_len;
3793                         td_remain_len -= trb_buff_len;
3794                 }
3795
3796                 /* Check TD length */
3797                 if (running_total != td_len) {
3798                         xhci_err(xhci, "ISOC TD length unmatch\n");
3799                         ret = -EINVAL;
3800                         goto cleanup;
3801                 }
3802         }
3803
3804         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3805                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3806                         usb_amd_quirk_pll_disable();
3807         }
3808         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3809
3810         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3811                         start_cycle, start_trb);
3812         return 0;
3813 cleanup:
3814         /* Clean up a partially enqueued isoc transfer. */
3815
3816         for (i--; i >= 0; i--)
3817                 list_del_init(&urb_priv->td[i]->td_list);
3818
3819         /* Use the first TD as a temporary variable to turn the TDs we've queued
3820          * into No-ops with a software-owned cycle bit. That way the hardware
3821          * won't accidentally start executing bogus TDs when we partially
3822          * overwrite them.  td->first_trb and td->start_seg are already set.
3823          */
3824         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3825         /* Every TRB except the first & last will have its cycle bit flipped. */
3826         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3827
3828         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3829         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3830         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3831         ep_ring->cycle_state = start_cycle;
3832         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3833         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3834         return ret;
3835 }
3836
3837 /*
3838  * Check transfer ring to guarantee there is enough room for the urb.
3839  * Update ISO URB start_frame and interval.
3840  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3841  * update the urb->start_frame by now.
3842  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3843  */
3844 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3845                 struct urb *urb, int slot_id, unsigned int ep_index)
3846 {
3847         struct xhci_virt_device *xdev;
3848         struct xhci_ring *ep_ring;
3849         struct xhci_ep_ctx *ep_ctx;
3850         int start_frame;
3851         int xhci_interval;
3852         int ep_interval;
3853         int num_tds, num_trbs, i;
3854         int ret;
3855
3856         xdev = xhci->devs[slot_id];
3857         ep_ring = xdev->eps[ep_index].ring;
3858         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3859
3860         num_trbs = 0;
3861         num_tds = urb->number_of_packets;
3862         for (i = 0; i < num_tds; i++)
3863                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3864
3865         /* Check the ring to guarantee there is enough room for the whole urb.
3866          * Do not insert any td of the urb to the ring if the check failed.
3867          */
3868         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3869                            num_trbs, mem_flags);
3870         if (ret)
3871                 return ret;
3872
3873         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3874         start_frame &= 0x3fff;
3875
3876         urb->start_frame = start_frame;
3877         if (urb->dev->speed == USB_SPEED_LOW ||
3878                         urb->dev->speed == USB_SPEED_FULL)
3879                 urb->start_frame >>= 3;
3880
3881         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3882         ep_interval = urb->interval;
3883         /* Convert to microframes */
3884         if (urb->dev->speed == USB_SPEED_LOW ||
3885                         urb->dev->speed == USB_SPEED_FULL)
3886                 ep_interval *= 8;
3887         /* FIXME change this to a warning and a suggestion to use the new API
3888          * to set the polling interval (once the API is added).
3889          */
3890         if (xhci_interval != ep_interval) {
3891                 dev_dbg_ratelimited(&urb->dev->dev,
3892                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3893                                 ep_interval, ep_interval == 1 ? "" : "s",
3894                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3895                 urb->interval = xhci_interval;
3896                 /* Convert back to frames for LS/FS devices */
3897                 if (urb->dev->speed == USB_SPEED_LOW ||
3898                                 urb->dev->speed == USB_SPEED_FULL)
3899                         urb->interval /= 8;
3900         }
3901         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3902
3903         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3904 }
3905
3906 /****           Command Ring Operations         ****/
3907
3908 /* Generic function for queueing a command TRB on the command ring.
3909  * Check to make sure there's room on the command ring for one command TRB.
3910  * Also check that there's room reserved for commands that must not fail.
3911  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3912  * then only check for the number of reserved spots.
3913  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3914  * because the command event handler may want to resubmit a failed command.
3915  */
3916 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3917                 u32 field3, u32 field4, bool command_must_succeed)
3918 {
3919         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3920         int ret;
3921
3922         if (!command_must_succeed)
3923                 reserved_trbs++;
3924
3925         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3926                         reserved_trbs, GFP_ATOMIC);
3927         if (ret < 0) {
3928                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3929                 if (command_must_succeed)
3930                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3931                                         "unfailable commands failed.\n");
3932                 return ret;
3933         }
3934         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3935                         field4 | xhci->cmd_ring->cycle_state);
3936         return 0;
3937 }
3938
3939 /* Queue a slot enable or disable request on the command ring */
3940 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3941 {
3942         return queue_command(xhci, 0, 0, 0,
3943                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3944 }
3945
3946 /* Queue an address device command TRB */
3947 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3948                 u32 slot_id)
3949 {
3950         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3951                         upper_32_bits(in_ctx_ptr), 0,
3952                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3953                         false);
3954 }
3955
3956 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3957                 u32 field1, u32 field2, u32 field3, u32 field4)
3958 {
3959         return queue_command(xhci, field1, field2, field3, field4, false);
3960 }
3961
3962 /* Queue a reset device command TRB */
3963 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3964 {
3965         return queue_command(xhci, 0, 0, 0,
3966                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3967                         false);
3968 }
3969
3970 /* Queue a configure endpoint command TRB */
3971 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3972                 u32 slot_id, bool command_must_succeed)
3973 {
3974         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3975                         upper_32_bits(in_ctx_ptr), 0,
3976                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3977                         command_must_succeed);
3978 }
3979
3980 /* Queue an evaluate context command TRB */
3981 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3982                 u32 slot_id, bool command_must_succeed)
3983 {
3984         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3985                         upper_32_bits(in_ctx_ptr), 0,
3986                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3987                         command_must_succeed);
3988 }
3989
3990 /*
3991  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3992  * activity on an endpoint that is about to be suspended.
3993  */
3994 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3995                 unsigned int ep_index, int suspend)
3996 {
3997         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3998         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3999         u32 type = TRB_TYPE(TRB_STOP_RING);
4000         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4001
4002         return queue_command(xhci, 0, 0, 0,
4003                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
4004 }
4005
4006 /* Set Transfer Ring Dequeue Pointer command.
4007  * This should not be used for endpoints that have streams enabled.
4008  */
4009 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
4010                 unsigned int ep_index, unsigned int stream_id,
4011                 struct xhci_segment *deq_seg,
4012                 union xhci_trb *deq_ptr, u32 cycle_state)
4013 {
4014         dma_addr_t addr;
4015         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4016         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4017         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4018         u32 type = TRB_TYPE(TRB_SET_DEQ);
4019         struct xhci_virt_ep *ep;
4020
4021         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4022         if (addr == 0) {
4023                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4024                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4025                                 deq_seg, deq_ptr);
4026                 return 0;
4027         }
4028         ep = &xhci->devs[slot_id]->eps[ep_index];
4029         if ((ep->ep_state & SET_DEQ_PENDING)) {
4030                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4031                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4032                 return 0;
4033         }
4034         ep->queued_deq_seg = deq_seg;
4035         ep->queued_deq_ptr = deq_ptr;
4036         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
4037                         upper_32_bits(addr), trb_stream_id,
4038                         trb_slot_id | trb_ep_index | type, false);
4039 }
4040
4041 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4042                 unsigned int ep_index)
4043 {
4044         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4045         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4046         u32 type = TRB_TYPE(TRB_RESET_EP);
4047
4048         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4049                         false);
4050 }