drivers/video/exynos/exynos_dp_core.c

   1 /*
   2  * Samsung SoC DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/io.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/delay.h>
  21 #include <linux/of.h>
  22
  23 #include <video/exynos_dp.h>
  24
  25 #include <plat/cpu.h>
  26
  27 #include "exynos_dp_core.h"
  28
  29 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
  30 {
  31         exynos_dp_reset(dp);
  32
  33         /* SW defined function Normal operation */
  34         exynos_dp_enable_sw_function(dp);
  35
  36         exynos_dp_init_analog_func(dp);
  37
  38         exynos_dp_init_hpd(dp);
  39         exynos_dp_init_aux(dp);
  40
  41         return 0;
  42 }
  43
  44 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
  45 {
  46         int timeout_loop = 0;
  47
  48         exynos_dp_init_hpd(dp);
  49
  50         udelay(200);
  51
  52         while (exynos_dp_get_plug_in_status(dp) != 0) {
  53                 timeout_loop++;
  54                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
  55                         dev_err(dp->dev, "failed to get hpd plug status\n");
  56                         return -ETIMEDOUT;
  57                 }
  58                 udelay(10);
  59         }
  60
  61         return 0;
  62 }
  63
  64 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  65 {
  66         int i;
  67         unsigned char sum = 0;
  68
  69         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  70                 sum = sum + edid_data[i];
  71
  72         return sum;
  73 }
  74
  75 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
  76 {
  77         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  78         unsigned int extend_block = 0;
  79         unsigned char sum;
  80         unsigned char test_vector;
  81         int retval;
  82
  83         /*
  84          * EDID device address is 0x50.
  85          * However, if necessary, you must have set upper address
  86          * into E-EDID in I2C device, 0x30.
  87          */
  88
  89         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  90         exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
  91                                 EDID_EXTENSION_FLAG,
  92                                 &extend_block);
  93
  94         if (extend_block > 0) {
  95                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
  96
  97                 /* Read EDID data */
  98                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
  99                                                 EDID_HEADER_PATTERN,
 100                                                 EDID_BLOCK_LENGTH,
 101                                                 &edid[EDID_HEADER_PATTERN]);
 102                 if (retval != 0) {
 103                         dev_err(dp->dev, "EDID Read failed!\n");
 104                         return -EIO;
 105                 }
 106                 sum = exynos_dp_calc_edid_check_sum(edid);
 107                 if (sum != 0) {
 108                         dev_err(dp->dev, "EDID bad checksum!\n");
 109                         return -EIO;
 110                 }
 111
 112                 /* Read additional EDID data */
 113                 retval = exynos_dp_read_bytes_from_i2c(dp,
 114                                 I2C_EDID_DEVICE_ADDR,
 115                                 EDID_BLOCK_LENGTH,
 116                                 EDID_BLOCK_LENGTH,
 117                                 &edid[EDID_BLOCK_LENGTH]);
 118                 if (retval != 0) {
 119                         dev_err(dp->dev, "EDID Read failed!\n");
 120                         return -EIO;
 121                 }
 122                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 123                 if (sum != 0) {
 124                         dev_err(dp->dev, "EDID bad checksum!\n");
 125                         return -EIO;
 126                 }
 127
 128                 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
 129                                         &test_vector);
 130                 if (test_vector & DPCD_TEST_EDID_READ) {
 131                         exynos_dp_write_byte_to_dpcd(dp,
 132                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 133                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 134                         exynos_dp_write_byte_to_dpcd(dp,
 135                                 DPCD_ADDR_TEST_RESPONSE,
 136                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 137                 }
 138         } else {
 139                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
 140
 141                 /* Read EDID data */
 142                 retval = exynos_dp_read_bytes_from_i2c(dp,
 143                                 I2C_EDID_DEVICE_ADDR,
 144                                 EDID_HEADER_PATTERN,
 145                                 EDID_BLOCK_LENGTH,
 146                                 &edid[EDID_HEADER_PATTERN]);
 147                 if (retval != 0) {
 148                         dev_err(dp->dev, "EDID Read failed!\n");
 149                         return -EIO;
 150                 }
 151                 sum = exynos_dp_calc_edid_check_sum(edid);
 152                 if (sum != 0) {
 153                         dev_err(dp->dev, "EDID bad checksum!\n");
 154                         return -EIO;
 155                 }
 156
 157                 exynos_dp_read_byte_from_dpcd(dp,
 158                         DPCD_ADDR_TEST_REQUEST,
 159                         &test_vector);
 160                 if (test_vector & DPCD_TEST_EDID_READ) {
 161                         exynos_dp_write_byte_to_dpcd(dp,
 162                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 163                                 edid[EDID_CHECKSUM]);
 164                         exynos_dp_write_byte_to_dpcd(dp,
 165                                 DPCD_ADDR_TEST_RESPONSE,
 166                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 167                 }
 168         }
 169
 170         dev_err(dp->dev, "EDID Read success!\n");
 171         return 0;
 172 }
 173
 174 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 175 {
 176         u8 buf[12];
 177         int i;
 178         int retval;
 179
 180         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 181         exynos_dp_read_bytes_from_dpcd(dp,
 182                 DPCD_ADDR_DPCD_REV,
 183                 12, buf);
 184
 185         /* Read EDID */
 186         for (i = 0; i < 3; i++) {
 187                 retval = exynos_dp_read_edid(dp);
 188                 if (retval == 0)
 189                         break;
 190         }
 191
 192         return retval;
 193 }
 194
 195 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 196                                                 bool enable)
 197 {
 198         u8 data;
 199
 200         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
 201
 202         if (enable)
 203                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 204                         DPCD_ENHANCED_FRAME_EN |
 205                         DPCD_LANE_COUNT_SET(data));
 206         else
 207                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 208                         DPCD_LANE_COUNT_SET(data));
 209 }
 210
 211 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
 212 {
 213         u8 data;
 214         int retval;
 215
 216         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 217         retval = DPCD_ENHANCED_FRAME_CAP(data);
 218
 219         return retval;
 220 }
 221
 222 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
 223 {
 224         u8 data;
 225
 226         data = exynos_dp_is_enhanced_mode_available(dp);
 227         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
 228         exynos_dp_enable_enhanced_mode(dp, data);
 229 }
 230
 231 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 232 {
 233         exynos_dp_set_training_pattern(dp, DP_NONE);
 234
 235         exynos_dp_write_byte_to_dpcd(dp,
 236                 DPCD_ADDR_TRAINING_PATTERN_SET,
 237                 DPCD_TRAINING_PATTERN_DISABLED);
 238 }
 239
 240 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
 241                                         int pre_emphasis, int lane)
 242 {
 243         switch (lane) {
 244         case 0:
 245                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 246                 break;
 247         case 1:
 248                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 249                 break;
 250
 251         case 2:
 252                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 253                 break;
 254
 255         case 3:
 256                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 257                 break;
 258         }
 259 }
 260
 261 static int exynos_dp_link_start(struct exynos_dp_device *dp)
 262 {
 263         int ret;
 264         u8 buf[5];
 265         int lane;
 266         int lane_count;
 267
 268         lane_count = dp->link_train.lane_count;
 269
 270         dp->link_train.lt_state = CLOCK_RECOVERY;
 271         dp->link_train.eq_loop = 0;
 272
 273         for (lane = 0; lane < lane_count; lane++)
 274                 dp->link_train.cr_loop[lane] = 0;
 275
 276         /* Set sink to D0 (Sink Not Ready) mode. */
 277         ret = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
 278                                 DPCD_SET_POWER_STATE_D0);
 279         if (ret)
 280                 return ret;
 281
 282         /* Set link rate and count as you want to establish*/
 283         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 284         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
 285
 286         /* Setup RX configuration */
 287         buf[0] = dp->link_train.link_rate;
 288         buf[1] = dp->link_train.lane_count;
 289         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
 290                                 2, buf);
 291         if (ret)
 292                 return ret;
 293
 294         /* Set TX pre-emphasis to minimum */
 295         for (lane = 0; lane < lane_count; lane++)
 296                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 297                         PRE_EMPHASIS_LEVEL_0, lane);
 298
 299         /* Set training pattern 1 */
 300         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 301
 302         /* Set RX training pattern */
 303         buf[0] = DPCD_SCRAMBLING_DISABLED |
 304                  DPCD_TRAINING_PATTERN_1;
 305         for (lane = 1; lane <= lane_count; lane++)
 306                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 307                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 308         ret = exynos_dp_write_bytes_to_dpcd(dp,
 309                 DPCD_ADDR_TRAINING_PATTERN_SET,
 310                 lane_count + 1, buf);
 311         if (ret)
 312                 return ret;
 313
 314         return ret;
 315 }
 316
 317 static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
 318 {
 319         int shift = (lane & 1) * 4;
 320         u8 link_value = link_status[lane>>1];
 321
 322         return (link_value >> shift) & 0xf;
 323 }
 324
 325 static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
 326 {
 327         int lane;
 328         u8 lane_status;
 329
 330         for (lane = 0; lane < lane_count; lane++) {
 331                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 332                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 333                         return -EINVAL;
 334         }
 335         return 0;
 336 }
 337
 338 static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count)
 339 {
 340         int lane;
 341         u8 lane_align;
 342         u8 lane_status;
 343
 344         lane_align = link_status[2];
 345         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 346                 return -EINVAL;
 347
 348         for (lane = 0; lane < lane_count; lane++) {
 349                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 350                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 351                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 352                         return -EINVAL;
 353         }
 354         return 0;
 355 }
 356
 357 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 358                                                         int lane)
 359 {
 360         int shift = (lane & 1) * 4;
 361         u8 link_value = adjust_request[lane>>1];
 362
 363         return (link_value >> shift) & 0x3;
 364 }
 365
 366 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 367                                         u8 adjust_request[2],
 368                                         int lane)
 369 {
 370         int shift = (lane & 1) * 4;
 371         u8 link_value = adjust_request[lane>>1];
 372
 373         return ((link_value >> shift) & 0xc) >> 2;
 374 }
 375
 376 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 377                                         u8 training_lane_set, int lane)
 378 {
 379         switch (lane) {
 380         case 0:
 381                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
 382                 break;
 383         case 1:
 384                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
 385                 break;
 386
 387         case 2:
 388                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
 389                 break;
 390
 391         case 3:
 392                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
 393                 break;
 394         }
 395 }
 396
 397 static unsigned int exynos_dp_get_lane_link_training(
 398                                 struct exynos_dp_device *dp,
 399                                 int lane)
 400 {
 401         u32 reg = 0;
 402
 403         switch (lane) {
 404         case 0:
 405                 reg = exynos_dp_get_lane0_link_training(dp);
 406                 break;
 407         case 1:
 408                 reg = exynos_dp_get_lane1_link_training(dp);
 409                 break;
 410         case 2:
 411                 reg = exynos_dp_get_lane2_link_training(dp);
 412                 break;
 413         case 3:
 414                 reg = exynos_dp_get_lane3_link_training(dp);
 415                 break;
 416         }
 417
 418         return reg;
 419 }
 420
 421 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 422 {
 423         if (dp->link_train.link_rate == LINK_RATE_2_70GBPS) {
 424                 /* set to reduced bit rate */
 425                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 426                 dev_err(dp->dev, "set to bandwidth %.2x\n",
 427                         dp->link_train.link_rate);
 428                 dp->link_train.lt_state = START;
 429         } else {
 430                 exynos_dp_training_pattern_dis(dp);
 431                 /* set enhanced mode if available */
 432                 exynos_dp_set_enhanced_mode(dp);
 433                 dp->link_train.lt_state = FAILED;
 434         }
 435 }
 436
 437 static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp,
 438                                 u8 adjust_request[2])
 439 {
 440         int lane;
 441         int lane_count;
 442         u8 voltage_swing;
 443         u8 pre_emphasis;
 444         u8 training_lane;
 445
 446         lane_count = dp->link_train.lane_count;
 447         for (lane = 0; lane < lane_count; lane++) {
 448                 voltage_swing = exynos_dp_get_adjust_request_voltage(
 449                                                 adjust_request, lane);
 450                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 451                                                 adjust_request, lane);
 452                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 453                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 454
 455                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 456                    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 457                         training_lane |= DPCD_MAX_SWING_REACHED;
 458                         training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 459                 }
 460                 dp->link_train.training_lane[lane] = training_lane;
 461         }
 462 }
 463
 464 static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
 465                                         u8 voltage_swing)
 466 {
 467         int lane;
 468         int lane_count;
 469
 470         lane_count = dp->link_train.lane_count;
 471         for (lane = 0; lane < lane_count; lane++) {
 472                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 473                         dp->link_train.cr_loop[lane] == MAX_CR_LOOP)
 474                         return -EINVAL;
 475         }
 476         return 0;
 477 }
 478
 479 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 480 {
 481         int ret;
 482         u8 data;
 483         u8 link_status[6];
 484         int lane;
 485         int lane_count;
 486         u8 buf[5];
 487
 488         u8 adjust_request[2];
 489         u8 voltage_swing = 0;
 490         u8 pre_emphasis;
 491         u8 training_lane;
 492
 493         udelay(100);
 494
 495         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
 496                                 6, link_status);
 497         if (ret)
 498                 return ret;
 499
 500         lane_count = dp->link_train.lane_count;
 501
 502         adjust_request[0] = link_status[4];
 503         adjust_request[1] = link_status[5];
 504
 505         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 506                 /* set training pattern 2 for EQ */
 507                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 508
 509                 exynos_dp_get_adjust_train(dp, adjust_request);
 510
 511                 buf[0] = DPCD_SCRAMBLING_DISABLED |
 512                          DPCD_TRAINING_PATTERN_2;
 513                 ret = exynos_dp_write_byte_to_dpcd(dp,
 514                         DPCD_ADDR_TRAINING_PATTERN_SET,
 515                         buf[0]);
 516                 if (ret)
 517                         return ret;
 518
 519                 for (lane = 0; lane < lane_count; lane++) {
 520                         exynos_dp_set_lane_link_training(dp,
 521                                 dp->link_train.training_lane[lane],
 522                                 lane);
 523                         buf[lane] = dp->link_train.training_lane[lane];
 524                         ret = exynos_dp_write_byte_to_dpcd(dp,
 525                                 DPCD_ADDR_TRAINING_LANE0_SET + lane,
 526                                 buf[lane]);
 527                         if (ret)
 528                                 return ret;
 529                 }
 530                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 531         } else {
 532                 for (lane = 0; lane < lane_count; lane++) {
 533                         training_lane = exynos_dp_get_lane_link_training(
 534                                                         dp, lane);
 535                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 536                                                         adjust_request, lane);
 537                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 538                                                         adjust_request, lane);
 539                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) &&
 540                             (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis))
 541                                 dp->link_train.cr_loop[lane]++;
 542                         dp->link_train.training_lane[lane] = training_lane;
 543                 }
 544
 545                 if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) {
 546                         exynos_dp_reduce_link_rate(dp);
 547                 } else {
 548                         exynos_dp_get_adjust_train(dp, adjust_request);
 549
 550                         for (lane = 0; lane < lane_count; lane++) {
 551                                 exynos_dp_set_lane_link_training(dp,
 552                                         dp->link_train.training_lane[lane],
 553                                         lane);
 554                                 buf[lane] = dp->link_train.training_lane[lane];
 555                                 ret = exynos_dp_write_byte_to_dpcd(dp,
 556                                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 557                                         buf[lane]);
 558                                 if (ret)
 559                                         return ret;
 560                         }
 561                 }
 562         }
 563
 564         return ret;
 565 }
 566
 567 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 568 {
 569         int ret;
 570         u8 link_status[6];
 571         int lane;
 572         int lane_count;
 573         u8 buf[5];
 574         u32 reg;
 575
 576         u8 adjust_request[2];
 577
 578         udelay(400);
 579
 580         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
 581                                 6, link_status);
 582         if (ret)
 583                 return ret;
 584         lane_count = dp->link_train.lane_count;
 585
 586         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 587                 adjust_request[0] = link_status[4];
 588                 adjust_request[1] = link_status[5];
 589
 590                 if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
 591                         /* traing pattern Set to Normal */
 592                         exynos_dp_training_pattern_dis(dp);
 593
 594                         dev_info(dp->dev, "Link Training success!\n");
 595
 596                         exynos_dp_get_link_bandwidth(dp, &reg);
 597                         dp->link_train.link_rate = reg;
 598                         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 599                                 dp->link_train.link_rate);
 600
 601                         exynos_dp_get_lane_count(dp, &reg);
 602                         dp->link_train.lane_count = reg;
 603                         dev_dbg(dp->dev, "final lane count = %.2x\n",
 604                                 dp->link_train.lane_count);
 605                         /* set enhanced mode if available */
 606                         exynos_dp_set_enhanced_mode(dp);
 607
 608                         dp->link_train.lt_state = FINISHED;
 609                 } else {
 610                         /* not all locked */
 611                         dp->link_train.eq_loop++;
 612
 613                         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 614                                 exynos_dp_reduce_link_rate(dp);
 615                         } else {
 616                                 exynos_dp_get_adjust_train(dp, adjust_request);
 617
 618                                 for (lane = 0; lane < lane_count; lane++) {
 619                                         exynos_dp_set_lane_link_training(dp,
 620                                                 dp->link_train.training_lane[lane],
 621                                                 lane);
 622                                         buf[lane] = dp->link_train.training_lane[lane];
 623                                         ret = exynos_dp_write_byte_to_dpcd(dp,
 624                                                 DPCD_ADDR_TRAINING_LANE0_SET + lane,
 625                                                 buf[lane]);
 626                                         if (ret)
 627                                                 return ret;
 628                                 }
 629                         }
 630                 }
 631         } else {
 632                 exynos_dp_reduce_link_rate(dp);
 633         }
 634
 635         return ret;
 636 }
 637
 638 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 639                         u8 *bandwidth)
 640 {
 641         u8 data;
 642
 643         /*
 644          * For DP rev.1.1, Maximum link rate of Main Link lanes
 645          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 646          */
 647         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
 648         *bandwidth = data;
 649 }
 650
 651 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 652                         u8 *lane_count)
 653 {
 654         u8 data;
 655
 656         /*
 657          * For DP rev.1.1, Maximum number of Main Link lanes
 658          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 659          */
 660         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 661         *lane_count = DPCD_MAX_LANE_COUNT(data);
 662 }
 663
 664 static void exynos_dp_init_training(struct exynos_dp_device *dp,
 665                         enum link_lane_count_type max_lane,
 666                         enum link_rate_type max_rate)
 667 {
 668         /*
 669          * MACRO_RST must be applied after the PLL_LOCK to avoid
 670          * the DP inter pair skew issue for at least 10 us
 671          */
 672         exynos_dp_reset_macro(dp);
 673
 674         /* Initialize by reading RX's DPCD */
 675         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 676         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 677
 678         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 679            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 680                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 681                         dp->link_train.link_rate);
 682                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 683         }
 684
 685         if (dp->link_train.lane_count == 0) {
 686                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 687                         dp->link_train.lane_count);
 688                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 689         }
 690
 691         /* Setup TX lane count & rate */
 692         if (dp->link_train.lane_count > max_lane)
 693                 dp->link_train.lane_count = max_lane;
 694         if (dp->link_train.link_rate > max_rate)
 695                 dp->link_train.link_rate = max_rate;
 696
 697         /* All DP analog module power up */
 698         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 699 }
 700
 701 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 702 {
 703         int ret = 0, training_finished = 0;
 704
 705         /* Turn off unnecessary lane */
 706         if (dp->link_train.lane_count == 1)
 707                 exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
 708
 709         if (dp->link_train.lane_count <= 2) {
 710                 exynos_dp_set_analog_power_down(dp, CH2_BLOCK, 1);
 711                 exynos_dp_set_analog_power_down(dp, CH3_BLOCK, 1);
 712         }
 713
 714         dp->link_train.lt_state = START;
 715
 716         /* Process here */
 717         while (!ret && !training_finished) {
 718                 switch (dp->link_train.lt_state) {
 719                 case START:
 720                         ret = exynos_dp_link_start(dp);
 721                         break;
 722                 case CLOCK_RECOVERY:
 723                         ret = exynos_dp_process_clock_recovery(dp);
 724                         break;
 725                 case EQUALIZER_TRAINING:
 726                         ret = exynos_dp_process_equalizer_training(dp);
 727                         break;
 728                 case FINISHED:
 729                         training_finished = 1;
 730                         break;
 731                 case FAILED:
 732                         return -EREMOTEIO;
 733                 }
 734         }
 735         if (ret)
 736                 dev_err(dp->dev, "eDP link training failed (%d)\n", ret);
 737
 738         return ret;
 739 }
 740
 741 static int exynos_dp_set_hw_link_train(struct exynos_dp_device *dp,
 742                                 u32 max_lane,
 743                                 u32 max_rate)
 744 {
 745         u32 status;
 746         int lane;
 747
 748         exynos_dp_stop_video(dp);
 749
 750         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 751                 dev_err(dp->dev, "PLL is not locked yet.\n");
 752                 return -EINVAL;
 753         }
 754
 755         exynos_dp_reset_macro(dp);
 756
 757         /* Set TX pre-emphasis to minimum */
 758         for (lane = 0; lane < max_lane; lane++)
 759                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 760                                 PRE_EMPHASIS_LEVEL_0, lane);
 761
 762         /* All DP analog module power up */
 763         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 764
 765         /* Initialize by reading RX's DPCD */
 766         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 767         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 768
 769         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 770                 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 771                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 772                         dp->link_train.link_rate);
 773                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 774         }
 775
 776         if (dp->link_train.lane_count == 0) {
 777                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 778                         dp->link_train.lane_count);
 779                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 780         }
 781
 782         /* Setup TX lane count & rate */
 783         if (dp->link_train.lane_count > max_lane)
 784                 dp->link_train.lane_count = max_lane;
 785         if (dp->link_train.link_rate > max_rate)
 786                 dp->link_train.link_rate = max_rate;
 787
 788         /* Set link rate and count as you want to establish*/
 789         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 790         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 791
 792         /* Set sink to D0 (Sink Not Ready) mode. */
 793         exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
 794                                                 DPCD_SET_POWER_STATE_D0);
 795
 796         /* Enable H/W Link Training */
 797         status = exynos_dp_enable_hw_link_training(dp);
 798
 799         if (status != 0) {
 800                 dev_err(dp->dev, " H/W link training failure: 0x%x\n", status);
 801                 return -EINVAL;
 802         }
 803
 804         exynos_dp_get_link_bandwidth(dp, &status);
 805         dp->link_train.link_rate = status;
 806         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 807                                 dp->link_train.link_rate);
 808
 809         exynos_dp_get_lane_count(dp, &status);
 810         dp->link_train.lane_count = status;
 811         dev_dbg(dp->dev, "final lane count = %.2x\n",
 812                                 dp->link_train.lane_count);
 813
 814         return 0;
 815 }
 816
 817 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 818                                 u32 count,
 819                                 u32 bwtype)
 820 {
 821         int i;
 822         int retval;
 823
 824         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 825                 exynos_dp_init_training(dp, count, bwtype);
 826                 retval = exynos_dp_sw_link_training(dp);
 827                 if (retval == 0)
 828                         break;
 829
 830                 udelay(100);
 831         }
 832
 833         return retval;
 834 }
 835
 836 static int exynos_dp_config_video(struct exynos_dp_device *dp,
 837                         struct video_info *video_info)
 838 {
 839         int retval = 0;
 840         int timeout_loop = 0;
 841         int done_count = 0;
 842
 843         exynos_dp_config_video_slave_mode(dp, video_info);
 844
 845         exynos_dp_set_video_color_format(dp, video_info->color_depth,
 846                         video_info->color_space,
 847                         video_info->dynamic_range,
 848                         video_info->ycbcr_coeff);
 849
 850         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 851                 dev_err(dp->dev, "PLL is not locked yet.\n");
 852                 return -EINVAL;
 853         }
 854
 855         for (;;) {
 856                 timeout_loop++;
 857                 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
 858                         break;
 859                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 860                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 861                         return -ETIMEDOUT;
 862                 }
 863
 864                 mdelay(100);
 865         }
 866
 867         /* Set to use the register calculated M/N video */
 868         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 869
 870         /* For video bist, Video timing must be generated by register */
 871         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 872
 873         /* Disable video mute */
 874         exynos_dp_enable_video_mute(dp, 0);
 875
 876         /* Configure video slave mode */
 877         exynos_dp_enable_video_master(dp, 0);
 878
 879         /* Enable video */
 880         exynos_dp_start_video(dp);
 881
 882         timeout_loop = 0;
 883
 884         for (;;) {
 885                 timeout_loop++;
 886                 if (exynos_dp_is_video_stream_on(dp) == 0) {
 887                         done_count++;
 888                         if (done_count > 10)
 889                                 break;
 890                 } else if (done_count) {
 891                         done_count = 0;
 892                 }
 893                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 894                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 895                         return -ETIMEDOUT;
 896                 }
 897
 898                 mdelay(100);
 899         }
 900
 901         if (retval != 0)
 902                 dev_err(dp->dev, "Video stream is not detected!\n");
 903
 904         return retval;
 905 }
 906
 907 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 908 {
 909         u8 data;
 910
 911         if (enable) {
 912                 exynos_dp_enable_scrambling(dp);
 913
 914                 exynos_dp_read_byte_from_dpcd(dp,
 915                         DPCD_ADDR_TRAINING_PATTERN_SET,
 916                         &data);
 917                 exynos_dp_write_byte_to_dpcd(dp,
 918                         DPCD_ADDR_TRAINING_PATTERN_SET,
 919                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 920         } else {
 921                 exynos_dp_disable_scrambling(dp);
 922
 923                 exynos_dp_read_byte_from_dpcd(dp,
 924                         DPCD_ADDR_TRAINING_PATTERN_SET,
 925                         &data);
 926                 exynos_dp_write_byte_to_dpcd(dp,
 927                         DPCD_ADDR_TRAINING_PATTERN_SET,
 928                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
 929         }
 930 }
 931
 932 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 933 {
 934         struct exynos_dp_device *dp = arg;
 935
 936         dev_err(dp->dev, "exynos_dp_irq_handler\n");
 937         return IRQ_HANDLED;
 938 }
 939
 940 static int __devinit exynos_dp_probe(struct platform_device *pdev)
 941 {
 942         struct resource *res;
 943         struct exynos_dp_device *dp;
 944         struct exynos_dp_platdata *pdata;
 945
 946         int ret = 0;
 947
 948         pdata = pdev->dev.platform_data;
 949         if (!pdata) {
 950                 dev_err(&pdev->dev, "no platform data\n");
 951                 return -EINVAL;
 952         }
 953
 954         dp = kzalloc(sizeof(struct exynos_dp_device), GFP_KERNEL);
 955         if (!dp) {
 956                 dev_err(&pdev->dev, "no memory for device data\n");
 957                 return -ENOMEM;
 958         }
 959
 960         dp->dev = &pdev->dev;
 961
 962         dp->clock = clk_get(&pdev->dev, "dp");
 963         if (IS_ERR(dp->clock)) {
 964                 dev_err(&pdev->dev, "failed to get clock\n");
 965                 ret = PTR_ERR(dp->clock);
 966                 goto err_dp;
 967         }
 968
 969         clk_enable(dp->clock);
 970
 971         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 972         if (!res) {
 973                 dev_err(&pdev->dev, "failed to get registers\n");
 974                 ret = -EINVAL;
 975                 goto err_clock;
 976         }
 977
 978         res = request_mem_region(res->start, resource_size(res),
 979                                 dev_name(&pdev->dev));
 980         if (!res) {
 981                 dev_err(&pdev->dev, "failed to request registers region\n");
 982                 ret = -EINVAL;
 983                 goto err_clock;
 984         }
 985
 986         dp->res = res;
 987
 988         dp->reg_base = ioremap(res->start, resource_size(res));
 989         if (!dp->reg_base) {
 990                 dev_err(&pdev->dev, "failed to ioremap\n");
 991                 ret = -ENOMEM;
 992                 goto err_req_region;
 993         }
 994
 995         dp->irq = platform_get_irq(pdev, 0);
 996         if (!dp->irq) {
 997                 dev_err(&pdev->dev, "failed to get irq\n");
 998                 ret = -ENODEV;
 999                 goto err_ioremap;
1000         }
1001
1002         dp->video_info = pdata->video_info;
1003         if (pdata->phy_init)
1004                 pdata->phy_init();
1005
1006         exynos_dp_init_dp(dp);
1007
1008         ret = request_irq(dp->irq, exynos_dp_irq_handler, 0,
1009                         "exynos-dp", dp);
1010         if (ret) {
1011                 dev_err(&pdev->dev, "failed to request irq\n");
1012                 goto err_ioremap;
1013         }
1014
1015         ret = exynos_dp_detect_hpd(dp);
1016         if (ret) {
1017                 dev_err(&pdev->dev, "unable to detect hpd\n");
1018                 goto err_irq;
1019         }
1020
1021         exynos_dp_handle_edid(dp);
1022
1023         if (pdata->training_type == SW_LINK_TRAINING)
1024                 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
1025                                                 dp->video_info->link_rate);
1026         else
1027                 ret = exynos_dp_set_hw_link_train(dp,
1028                         dp->video_info->lane_count, dp->video_info->link_rate);
1029         if (ret) {
1030                 dev_err(&pdev->dev, "unable to do link train\n");
1031                 goto err_irq;
1032         }
1033
1034         exynos_dp_enable_scramble(dp, 1);
1035         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
1036         exynos_dp_enable_enhanced_mode(dp, 1);
1037
1038         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
1039         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
1040
1041         exynos_dp_init_video(dp);
1042         ret = exynos_dp_config_video(dp, dp->video_info);
1043         if (ret) {
1044                 dev_err(&pdev->dev, "unable to config video\n");
1045                 goto err_irq;
1046         }
1047
1048         platform_set_drvdata(pdev, dp);
1049
1050         return 0;
1051
1052 err_irq:
1053         free_irq(dp->irq, dp);
1054 err_ioremap:
1055         iounmap(dp->reg_base);
1056 err_req_region:
1057         release_mem_region(res->start, resource_size(res));
1058 err_clock:
1059         clk_put(dp->clock);
1060 err_dp:
1061         kfree(dp);
1062
1063         return ret;
1064 }
1065
1066 static int __devexit exynos_dp_remove(struct platform_device *pdev)
1067 {
1068         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1069         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1070
1071         if (pdata && pdata->phy_exit)
1072                 pdata->phy_exit();
1073
1074         free_irq(dp->irq, dp);
1075         iounmap(dp->reg_base);
1076
1077         clk_disable(dp->clock);
1078         clk_put(dp->clock);
1079
1080         release_mem_region(dp->res->start, resource_size(dp->res));
1081
1082         kfree(dp);
1083
1084         return 0;
1085 }
1086
1087 #ifdef CONFIG_PM_SLEEP
1088 static int exynos_dp_suspend(struct device *dev)
1089 {
1090         struct platform_device *pdev = to_platform_device(dev);
1091         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1092         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1093
1094         if (pdata && pdata->phy_exit)
1095                 pdata->phy_exit();
1096
1097         clk_disable(dp->clock);
1098
1099         return 0;
1100 }
1101
1102 static int exynos_dp_resume(struct device *dev)
1103 {
1104         struct platform_device *pdev = to_platform_device(dev);
1105         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1106         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1107
1108         if (pdata && pdata->phy_init)
1109                 pdata->phy_init();
1110
1111         clk_enable(dp->clock);
1112
1113         exynos_dp_init_dp(dp);
1114
1115         exynos_dp_detect_hpd(dp);
1116         exynos_dp_handle_edid(dp);
1117
1118         if (pdata->training_type == SW_LINK_TRAINING)
1119                 exynos_dp_set_link_train(dp, dp->video_info->lane_count,
1120                                                 dp->video_info->link_rate);
1121         else
1122                 exynos_dp_set_hw_link_train(dp,
1123                         dp->video_info->lane_count, dp->video_info->link_rate);
1124
1125         exynos_dp_enable_scramble(dp, 1);
1126         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
1127         exynos_dp_enable_enhanced_mode(dp, 1);
1128
1129         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
1130         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
1131
1132         exynos_dp_init_video(dp);
1133         exynos_dp_config_video(dp, dp->video_info);
1134
1135         return 0;
1136 }
1137 #endif
1138
1139 static const struct dev_pm_ops exynos_dp_pm_ops = {
1140         SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1141 };
1142
1143 #ifdef CONFIG_OF
1144 static const struct of_device_id exynos_dp_match[] = {
1145         { .compatible = "samsung,exynos5-dp" },
1146         {},
1147 };
1148 MODULE_DEVICE_TABLE(of, exynos_dp_match);
1149 #endif
1150
1151 static struct platform_driver exynos_dp_driver = {
1152         .probe          = exynos_dp_probe,
1153         .remove         = __devexit_p(exynos_dp_remove),
1154         .driver         = {
1155                 .name   = "s5p-dp",
1156                 .owner  = THIS_MODULE,
1157                 .pm     = &exynos_dp_pm_ops,
1158                 .of_match_table = of_match_ptr(exynos_dp_match),
1159         },
1160 };
1161
1162 static int __init exynos_dp_init(void)
1163 {
1164         return platform_driver_probe(&exynos_dp_driver, exynos_dp_probe);
1165 }
1166
1167 static void __exit exynos_dp_exit(void)
1168 {
1169         platform_driver_unregister(&exynos_dp_driver);
1170 }
1171 /* TODO: Register as module_platform_driver */
1172 /* Currently, we make it late_initcall to make */
1173 /* sure that s3c-fb is probed before DP driver */
1174 late_initcall(exynos_dp_init);
1175 module_exit(exynos_dp_exit);
1176
1177 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1178 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1179 MODULE_LICENSE("GPL");