drivers/video/exynos/exynos_dp_core.c

   1 /*
   2  * Samsung SoC DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/io.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/delay.h>
  21 #include <linux/of.h>
  22
  23 #include <video/exynos_dp.h>
  24
  25 #include <plat/cpu.h>
  26
  27 #include "exynos_dp_core.h"
  28
  29 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
  30 {
  31         exynos_dp_reset(dp);
  32
  33         /* SW defined function Normal operation */
  34         exynos_dp_enable_sw_function(dp);
  35
  36         exynos_dp_init_analog_func(dp);
  37
  38         exynos_dp_init_hpd(dp);
  39         exynos_dp_init_aux(dp);
  40
  41         return 0;
  42 }
  43
  44 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
  45 {
  46         int timeout_loop = 0;
  47
  48         exynos_dp_init_hpd(dp);
  49
  50         udelay(200);
  51
  52         while (exynos_dp_get_plug_in_status(dp) != 0) {
  53                 timeout_loop++;
  54                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
  55                         dev_err(dp->dev, "failed to get hpd plug status\n");
  56                         return -ETIMEDOUT;
  57                 }
  58                 udelay(10);
  59         }
  60
  61         return 0;
  62 }
  63
  64 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  65 {
  66         int i;
  67         unsigned char sum = 0;
  68
  69         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  70                 sum = sum + edid_data[i];
  71
  72         return sum;
  73 }
  74
  75 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
  76 {
  77         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  78         unsigned int extend_block = 0;
  79         unsigned char sum;
  80         unsigned char test_vector;
  81         int retval;
  82
  83         /*
  84          * EDID device address is 0x50.
  85          * However, if necessary, you must have set upper address
  86          * into E-EDID in I2C device, 0x30.
  87          */
  88
  89         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  90         exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
  91                                 EDID_EXTENSION_FLAG,
  92                                 &extend_block);
  93
  94         if (extend_block > 0) {
  95                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
  96
  97                 /* Read EDID data */
  98                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
  99                                                 EDID_HEADER_PATTERN,
 100                                                 EDID_BLOCK_LENGTH,
 101                                                 &edid[EDID_HEADER_PATTERN]);
 102                 if (retval != 0) {
 103                         dev_err(dp->dev, "EDID Read failed!\n");
 104                         return -EIO;
 105                 }
 106                 sum = exynos_dp_calc_edid_check_sum(edid);
 107                 if (sum != 0) {
 108                         dev_err(dp->dev, "EDID bad checksum!\n");
 109                         return -EIO;
 110                 }
 111
 112                 /* Read additional EDID data */
 113                 retval = exynos_dp_read_bytes_from_i2c(dp,
 114                                 I2C_EDID_DEVICE_ADDR,
 115                                 EDID_BLOCK_LENGTH,
 116                                 EDID_BLOCK_LENGTH,
 117                                 &edid[EDID_BLOCK_LENGTH]);
 118                 if (retval != 0) {
 119                         dev_err(dp->dev, "EDID Read failed!\n");
 120                         return -EIO;
 121                 }
 122                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 123                 if (sum != 0) {
 124                         dev_err(dp->dev, "EDID bad checksum!\n");
 125                         return -EIO;
 126                 }
 127
 128                 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
 129                                         &test_vector);
 130                 if (test_vector & DPCD_TEST_EDID_READ) {
 131                         exynos_dp_write_byte_to_dpcd(dp,
 132                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 133                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 134                         exynos_dp_write_byte_to_dpcd(dp,
 135                                 DPCD_ADDR_TEST_RESPONSE,
 136                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 137                 }
 138         } else {
 139                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
 140
 141                 /* Read EDID data */
 142                 retval = exynos_dp_read_bytes_from_i2c(dp,
 143                                 I2C_EDID_DEVICE_ADDR,
 144                                 EDID_HEADER_PATTERN,
 145                                 EDID_BLOCK_LENGTH,
 146                                 &edid[EDID_HEADER_PATTERN]);
 147                 if (retval != 0) {
 148                         dev_err(dp->dev, "EDID Read failed!\n");
 149                         return -EIO;
 150                 }
 151                 sum = exynos_dp_calc_edid_check_sum(edid);
 152                 if (sum != 0) {
 153                         dev_err(dp->dev, "EDID bad checksum!\n");
 154                         return -EIO;
 155                 }
 156
 157                 exynos_dp_read_byte_from_dpcd(dp,
 158                         DPCD_ADDR_TEST_REQUEST,
 159                         &test_vector);
 160                 if (test_vector & DPCD_TEST_EDID_READ) {
 161                         exynos_dp_write_byte_to_dpcd(dp,
 162                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 163                                 edid[EDID_CHECKSUM]);
 164                         exynos_dp_write_byte_to_dpcd(dp,
 165                                 DPCD_ADDR_TEST_RESPONSE,
 166                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 167                 }
 168         }
 169
 170         dev_err(dp->dev, "EDID Read success!\n");
 171         return 0;
 172 }
 173
 174 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 175 {
 176         u8 buf[12];
 177         int i;
 178         int retval;
 179
 180         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 181         exynos_dp_read_bytes_from_dpcd(dp,
 182                 DPCD_ADDR_DPCD_REV,
 183                 12, buf);
 184
 185         /* Read EDID */
 186         for (i = 0; i < 3; i++) {
 187                 retval = exynos_dp_read_edid(dp);
 188                 if (retval == 0)
 189                         break;
 190         }
 191
 192         return retval;
 193 }
 194
 195 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 196                                                 bool enable)
 197 {
 198         u8 data;
 199
 200         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
 201
 202         if (enable)
 203                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 204                         DPCD_ENHANCED_FRAME_EN |
 205                         DPCD_LANE_COUNT_SET(data));
 206         else
 207                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 208                         DPCD_LANE_COUNT_SET(data));
 209 }
 210
 211 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
 212 {
 213         u8 data;
 214         int retval;
 215
 216         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 217         retval = DPCD_ENHANCED_FRAME_CAP(data);
 218
 219         return retval;
 220 }
 221
 222 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
 223 {
 224         u8 data;
 225
 226         data = exynos_dp_is_enhanced_mode_available(dp);
 227         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
 228         exynos_dp_enable_enhanced_mode(dp, data);
 229 }
 230
 231 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 232 {
 233         exynos_dp_set_training_pattern(dp, DP_NONE);
 234
 235         exynos_dp_write_byte_to_dpcd(dp,
 236                 DPCD_ADDR_TRAINING_PATTERN_SET,
 237                 DPCD_TRAINING_PATTERN_DISABLED);
 238 }
 239
 240 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
 241                                         int pre_emphasis, int lane)
 242 {
 243         switch (lane) {
 244         case 0:
 245                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 246                 break;
 247         case 1:
 248                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 249                 break;
 250
 251         case 2:
 252                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 253                 break;
 254
 255         case 3:
 256                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 257                 break;
 258         }
 259 }
 260
 261 static int exynos_dp_link_start(struct exynos_dp_device *dp)
 262 {
 263         int ret, lane, lane_count;
 264         u8 buf[4];
 265
 266         lane_count = dp->link_train.lane_count;
 267
 268         dp->link_train.lt_state = CLOCK_RECOVERY;
 269         dp->link_train.eq_loop = 0;
 270
 271         for (lane = 0; lane < lane_count; lane++)
 272                 dp->link_train.cr_loop[lane] = 0;
 273
 274         /* Set sink to D0 (Sink Not Ready) mode. */
 275         ret = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
 276                                 DPCD_SET_POWER_STATE_D0);
 277         if (ret)
 278                 return ret;
 279
 280         /* Set link rate and count as you want to establish*/
 281         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 282         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
 283
 284         /* Setup RX configuration */
 285         buf[0] = dp->link_train.link_rate;
 286         buf[1] = dp->link_train.lane_count;
 287         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, 2, buf);
 288         if (ret)
 289                 return ret;
 290
 291         /* Set TX pre-emphasis to minimum */
 292         for (lane = 0; lane < lane_count; lane++)
 293                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 294                         PRE_EMPHASIS_LEVEL_0, lane);
 295
 296         /* Set training pattern 1 */
 297         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 298
 299         /* Set RX training pattern */
 300         ret = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
 301                 DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1);
 302         if (ret)
 303                 return ret;
 304
 305         for (lane = 0; lane < lane_count; lane++)
 306                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 307                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 308         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
 309                 lane_count, buf);
 310         if (ret)
 311                 return ret;
 312
 313         return ret;
 314 }
 315
 316 static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
 317 {
 318         int shift = (lane & 1) * 4;
 319         u8 link_value = link_status[lane>>1];
 320
 321         return (link_value >> shift) & 0xf;
 322 }
 323
 324 static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
 325 {
 326         int lane;
 327         u8 lane_status;
 328
 329         for (lane = 0; lane < lane_count; lane++) {
 330                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 331                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 332                         return -EINVAL;
 333         }
 334         return 0;
 335 }
 336
 337 static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count)
 338 {
 339         int lane;
 340         u8 lane_align;
 341         u8 lane_status;
 342
 343         lane_align = link_status[2];
 344         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 345                 return -EINVAL;
 346
 347         for (lane = 0; lane < lane_count; lane++) {
 348                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 349                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 350                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 351                         return -EINVAL;
 352         }
 353         return 0;
 354 }
 355
 356 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 357                                                         int lane)
 358 {
 359         int shift = (lane & 1) * 4;
 360         u8 link_value = adjust_request[lane>>1];
 361
 362         return (link_value >> shift) & 0x3;
 363 }
 364
 365 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 366                                         u8 adjust_request[2],
 367                                         int lane)
 368 {
 369         int shift = (lane & 1) * 4;
 370         u8 link_value = adjust_request[lane>>1];
 371
 372         return ((link_value >> shift) & 0xc) >> 2;
 373 }
 374
 375 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 376                                         u8 training_lane_set, int lane)
 377 {
 378         switch (lane) {
 379         case 0:
 380                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
 381                 break;
 382         case 1:
 383                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
 384                 break;
 385
 386         case 2:
 387                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
 388                 break;
 389
 390         case 3:
 391                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
 392                 break;
 393         }
 394 }
 395
 396 static unsigned int exynos_dp_get_lane_link_training(
 397                                 struct exynos_dp_device *dp,
 398                                 int lane)
 399 {
 400         u32 reg = 0;
 401
 402         switch (lane) {
 403         case 0:
 404                 reg = exynos_dp_get_lane0_link_training(dp);
 405                 break;
 406         case 1:
 407                 reg = exynos_dp_get_lane1_link_training(dp);
 408                 break;
 409         case 2:
 410                 reg = exynos_dp_get_lane2_link_training(dp);
 411                 break;
 412         case 3:
 413                 reg = exynos_dp_get_lane3_link_training(dp);
 414                 break;
 415         }
 416
 417         return reg;
 418 }
 419
 420 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 421 {
 422         if (dp->link_train.link_rate == LINK_RATE_2_70GBPS) {
 423                 /* set to reduced bit rate */
 424                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 425                 dev_err(dp->dev, "set to bandwidth %.2x\n",
 426                         dp->link_train.link_rate);
 427                 dp->link_train.lt_state = START;
 428         } else {
 429                 exynos_dp_training_pattern_dis(dp);
 430                 /* set enhanced mode if available */
 431                 exynos_dp_set_enhanced_mode(dp);
 432                 dp->link_train.lt_state = FAILED;
 433         }
 434 }
 435
 436 static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp,
 437                                 u8 adjust_request[2])
 438 {
 439         int lane;
 440         int lane_count;
 441         u8 voltage_swing;
 442         u8 pre_emphasis;
 443         u8 training_lane;
 444
 445         lane_count = dp->link_train.lane_count;
 446         for (lane = 0; lane < lane_count; lane++) {
 447                 voltage_swing = exynos_dp_get_adjust_request_voltage(
 448                                                 adjust_request, lane);
 449                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 450                                                 adjust_request, lane);
 451                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 452                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 453
 454                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 455                    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 456                         training_lane |= DPCD_MAX_SWING_REACHED;
 457                         training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 458                 }
 459                 dp->link_train.training_lane[lane] = training_lane;
 460         }
 461 }
 462
 463 static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
 464                                         u8 voltage_swing)
 465 {
 466         int lane;
 467         int lane_count;
 468
 469         lane_count = dp->link_train.lane_count;
 470         for (lane = 0; lane < lane_count; lane++) {
 471                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 472                         dp->link_train.cr_loop[lane] == MAX_CR_LOOP)
 473                         return -EINVAL;
 474         }
 475         return 0;
 476 }
 477
 478 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 479 {
 480         int ret, lane, lane_count;
 481         u8 voltage_swing, pre_emphasis, training_lane, link_status[6];
 482         u8 *adjust_request;
 483
 484         udelay(100);
 485
 486         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 6,
 487                         link_status);
 488         if (ret)
 489                 return ret;
 490
 491         lane_count = dp->link_train.lane_count;
 492         adjust_request = link_status + 4;
 493
 494         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 495                 /* set training pattern 2 for EQ */
 496                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 497
 498                 ret = exynos_dp_write_byte_to_dpcd(dp,
 499                         DPCD_ADDR_TRAINING_PATTERN_SET,
 500                         DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2);
 501                 if (ret)
 502                         return ret;
 503
 504                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 505         } else {
 506                 for (lane = 0; lane < lane_count; lane++) {
 507                         training_lane = exynos_dp_get_lane_link_training(
 508                                                         dp, lane);
 509                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 510                                                         adjust_request, lane);
 511                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 512                                                         adjust_request, lane);
 513                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) &&
 514                             (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis))
 515                                 dp->link_train.cr_loop[lane]++;
 516                         dp->link_train.training_lane[lane] = training_lane;
 517                 }
 518
 519                 if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) {
 520                         exynos_dp_reduce_link_rate(dp);
 521                         return ret;
 522                 }
 523         }
 524
 525         exynos_dp_get_adjust_train(dp, adjust_request);
 526
 527         for (lane = 0; lane < lane_count; lane++) {
 528                 exynos_dp_set_lane_link_training(dp,
 529                         dp->link_train.training_lane[lane], lane);
 530                 ret = exynos_dp_write_byte_to_dpcd(dp,
 531                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 532                         dp->link_train.training_lane[lane]);
 533                 if (ret)
 534                         return ret;
 535         }
 536
 537         return ret;
 538 }
 539
 540 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 541 {
 542         int ret, lane, lane_count;
 543         u8 link_status[6];
 544         u32 reg;
 545         u8 *adjust_request;
 546
 547         udelay(400);
 548
 549         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
 550                                 6, link_status);
 551         if (ret)
 552                 return ret;
 553
 554         adjust_request = link_status + 4;
 555         lane_count = dp->link_train.lane_count;
 556
 557         if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
 558                 exynos_dp_reduce_link_rate(dp);
 559                 return ret;
 560         }
 561         if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
 562                 /* traing pattern Set to Normal */
 563                 exynos_dp_training_pattern_dis(dp);
 564
 565                 dev_info(dp->dev, "Link Training success!\n");
 566
 567                 exynos_dp_get_link_bandwidth(dp, &reg);
 568                 dp->link_train.link_rate = reg;
 569                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 570                         dp->link_train.link_rate);
 571
 572                 exynos_dp_get_lane_count(dp, &reg);
 573                 dp->link_train.lane_count = reg;
 574                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 575                         dp->link_train.lane_count);
 576                 /* set enhanced mode if available */
 577                 exynos_dp_set_enhanced_mode(dp);
 578
 579                 dp->link_train.lt_state = FINISHED;
 580         } else {
 581                 /* not all locked */
 582                 dp->link_train.eq_loop++;
 583
 584                 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 585                         exynos_dp_reduce_link_rate(dp);
 586                 } else {
 587                         exynos_dp_get_adjust_train(dp, adjust_request);
 588
 589                         for (lane = 0; lane < lane_count; lane++) {
 590                                 exynos_dp_set_lane_link_training(dp,
 591                                         dp->link_train.training_lane[lane],
 592                                         lane);
 593                                 ret = exynos_dp_write_byte_to_dpcd(dp,
 594                                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 595                                         dp->link_train.training_lane[lane]);
 596                                 if (ret)
 597                                         return ret;
 598                         }
 599                 }
 600         }
 601
 602         return ret;
 603 }
 604
 605 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 606                         u8 *bandwidth)
 607 {
 608         u8 data;
 609
 610         /*
 611          * For DP rev.1.1, Maximum link rate of Main Link lanes
 612          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 613          */
 614         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
 615         *bandwidth = data;
 616 }
 617
 618 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 619                         u8 *lane_count)
 620 {
 621         u8 data;
 622
 623         /*
 624          * For DP rev.1.1, Maximum number of Main Link lanes
 625          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 626          */
 627         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 628         *lane_count = DPCD_MAX_LANE_COUNT(data);
 629 }
 630
 631 static void exynos_dp_init_training(struct exynos_dp_device *dp,
 632                         enum link_lane_count_type max_lane,
 633                         enum link_rate_type max_rate)
 634 {
 635         /*
 636          * MACRO_RST must be applied after the PLL_LOCK to avoid
 637          * the DP inter pair skew issue for at least 10 us
 638          */
 639         exynos_dp_reset_macro(dp);
 640
 641         /* Initialize by reading RX's DPCD */
 642         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 643         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 644
 645         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 646            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 647                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 648                         dp->link_train.link_rate);
 649                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 650         }
 651
 652         if (dp->link_train.lane_count == 0) {
 653                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 654                         dp->link_train.lane_count);
 655                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 656         }
 657
 658         /* Setup TX lane count & rate */
 659         if (dp->link_train.lane_count > max_lane)
 660                 dp->link_train.lane_count = max_lane;
 661         if (dp->link_train.link_rate > max_rate)
 662                 dp->link_train.link_rate = max_rate;
 663
 664         /* All DP analog module power up */
 665         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 666 }
 667
 668 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 669 {
 670         int ret = 0, training_finished = 0;
 671
 672         /* Turn off unnecessary lanes */
 673         switch (dp->link_train.lane_count) {
 674         case LANE_COUNT1:
 675                 exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
 676         case LANE_COUNT2:
 677                 exynos_dp_set_analog_power_down(dp, CH2_BLOCK, 1);
 678                 exynos_dp_set_analog_power_down(dp, CH3_BLOCK, 1);
 679                 break;
 680         default:
 681                 break;
 682         }
 683
 684         dp->link_train.lt_state = START;
 685
 686         /* Process here */
 687         while (!ret && !training_finished) {
 688                 switch (dp->link_train.lt_state) {
 689                 case START:
 690                         ret = exynos_dp_link_start(dp);
 691                         break;
 692                 case CLOCK_RECOVERY:
 693                         ret = exynos_dp_process_clock_recovery(dp);
 694                         break;
 695                 case EQUALIZER_TRAINING:
 696                         ret = exynos_dp_process_equalizer_training(dp);
 697                         break;
 698                 case FINISHED:
 699                         training_finished = 1;
 700                         break;
 701                 case FAILED:
 702                         return -EREMOTEIO;
 703                 }
 704         }
 705         if (ret)
 706                 dev_err(dp->dev, "eDP link training failed (%d)\n", ret);
 707
 708         return ret;
 709 }
 710
 711 static int exynos_dp_set_hw_link_train(struct exynos_dp_device *dp,
 712                                 u32 max_lane,
 713                                 u32 max_rate)
 714 {
 715         u32 status;
 716         int lane;
 717
 718         exynos_dp_stop_video(dp);
 719
 720         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 721                 dev_err(dp->dev, "PLL is not locked yet.\n");
 722                 return -EINVAL;
 723         }
 724
 725         exynos_dp_reset_macro(dp);
 726
 727         /* Set TX pre-emphasis to minimum */
 728         for (lane = 0; lane < max_lane; lane++)
 729                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 730                                 PRE_EMPHASIS_LEVEL_0, lane);
 731
 732         /* All DP analog module power up */
 733         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 734
 735         /* Initialize by reading RX's DPCD */
 736         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 737         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 738
 739         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 740                 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 741                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 742                         dp->link_train.link_rate);
 743                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 744         }
 745
 746         if (dp->link_train.lane_count == 0) {
 747                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 748                         dp->link_train.lane_count);
 749                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 750         }
 751
 752         /* Setup TX lane count & rate */
 753         if (dp->link_train.lane_count > max_lane)
 754                 dp->link_train.lane_count = max_lane;
 755         if (dp->link_train.link_rate > max_rate)
 756                 dp->link_train.link_rate = max_rate;
 757
 758         /* Set link rate and count as you want to establish*/
 759         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 760         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 761
 762         /* Set sink to D0 (Sink Not Ready) mode. */
 763         exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
 764                                                 DPCD_SET_POWER_STATE_D0);
 765
 766         /* Enable H/W Link Training */
 767         status = exynos_dp_enable_hw_link_training(dp);
 768
 769         if (status != 0) {
 770                 dev_err(dp->dev, " H/W link training failure: 0x%x\n", status);
 771                 return -EINVAL;
 772         }
 773
 774         exynos_dp_get_link_bandwidth(dp, &status);
 775         dp->link_train.link_rate = status;
 776         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 777                                 dp->link_train.link_rate);
 778
 779         exynos_dp_get_lane_count(dp, &status);
 780         dp->link_train.lane_count = status;
 781         dev_dbg(dp->dev, "final lane count = %.2x\n",
 782                                 dp->link_train.lane_count);
 783
 784         return 0;
 785 }
 786
 787 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 788                                 u32 count,
 789                                 u32 bwtype)
 790 {
 791         int i;
 792         int retval;
 793
 794         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 795                 exynos_dp_init_training(dp, count, bwtype);
 796                 retval = exynos_dp_sw_link_training(dp);
 797                 if (retval == 0)
 798                         break;
 799
 800                 udelay(100);
 801         }
 802
 803         return retval;
 804 }
 805
 806 static int exynos_dp_config_video(struct exynos_dp_device *dp,
 807                         struct video_info *video_info)
 808 {
 809         int retval = 0;
 810         int timeout_loop = 0;
 811         int done_count = 0;
 812
 813         exynos_dp_config_video_slave_mode(dp, video_info);
 814
 815         exynos_dp_set_video_color_format(dp, video_info->color_depth,
 816                         video_info->color_space,
 817                         video_info->dynamic_range,
 818                         video_info->ycbcr_coeff);
 819
 820         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 821                 dev_err(dp->dev, "PLL is not locked yet.\n");
 822                 return -EINVAL;
 823         }
 824
 825         for (;;) {
 826                 timeout_loop++;
 827                 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
 828                         break;
 829                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 830                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 831                         return -ETIMEDOUT;
 832                 }
 833
 834                 mdelay(100);
 835         }
 836
 837         /* Set to use the register calculated M/N video */
 838         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 839
 840         /* For video bist, Video timing must be generated by register */
 841         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 842
 843         /* Disable video mute */
 844         exynos_dp_enable_video_mute(dp, 0);
 845
 846         /* Configure video slave mode */
 847         exynos_dp_enable_video_master(dp, 0);
 848
 849         /* Enable video */
 850         exynos_dp_start_video(dp);
 851
 852         timeout_loop = 0;
 853
 854         for (;;) {
 855                 timeout_loop++;
 856                 if (exynos_dp_is_video_stream_on(dp) == 0) {
 857                         done_count++;
 858                         if (done_count > 10)
 859                                 break;
 860                 } else if (done_count) {
 861                         done_count = 0;
 862                 }
 863                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 864                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 865                         return -ETIMEDOUT;
 866                 }
 867
 868                 mdelay(100);
 869         }
 870
 871         if (retval != 0)
 872                 dev_err(dp->dev, "Video stream is not detected!\n");
 873
 874         return retval;
 875 }
 876
 877 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 878 {
 879         u8 data;
 880
 881         if (enable) {
 882                 exynos_dp_enable_scrambling(dp);
 883
 884                 exynos_dp_read_byte_from_dpcd(dp,
 885                         DPCD_ADDR_TRAINING_PATTERN_SET,
 886                         &data);
 887                 exynos_dp_write_byte_to_dpcd(dp,
 888                         DPCD_ADDR_TRAINING_PATTERN_SET,
 889                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 890         } else {
 891                 exynos_dp_disable_scrambling(dp);
 892
 893                 exynos_dp_read_byte_from_dpcd(dp,
 894                         DPCD_ADDR_TRAINING_PATTERN_SET,
 895                         &data);
 896                 exynos_dp_write_byte_to_dpcd(dp,
 897                         DPCD_ADDR_TRAINING_PATTERN_SET,
 898                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
 899         }
 900 }
 901
 902 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 903 {
 904         struct exynos_dp_device *dp = arg;
 905
 906         dev_err(dp->dev, "exynos_dp_irq_handler\n");
 907         return IRQ_HANDLED;
 908 }
 909
 910 static int __devinit exynos_dp_probe(struct platform_device *pdev)
 911 {
 912         struct resource *res;
 913         struct exynos_dp_device *dp;
 914         struct exynos_dp_platdata *pdata;
 915
 916         int ret = 0;
 917
 918         pdata = pdev->dev.platform_data;
 919         if (!pdata) {
 920                 dev_err(&pdev->dev, "no platform data\n");
 921                 return -EINVAL;
 922         }
 923
 924         dp = kzalloc(sizeof(struct exynos_dp_device), GFP_KERNEL);
 925         if (!dp) {
 926                 dev_err(&pdev->dev, "no memory for device data\n");
 927                 return -ENOMEM;
 928         }
 929
 930         dp->dev = &pdev->dev;
 931
 932         dp->clock = clk_get(&pdev->dev, "dp");
 933         if (IS_ERR(dp->clock)) {
 934                 dev_err(&pdev->dev, "failed to get clock\n");
 935                 ret = PTR_ERR(dp->clock);
 936                 goto err_dp;
 937         }
 938
 939         clk_enable(dp->clock);
 940
 941         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 942         if (!res) {
 943                 dev_err(&pdev->dev, "failed to get registers\n");
 944                 ret = -EINVAL;
 945                 goto err_clock;
 946         }
 947
 948         res = request_mem_region(res->start, resource_size(res),
 949                                 dev_name(&pdev->dev));
 950         if (!res) {
 951                 dev_err(&pdev->dev, "failed to request registers region\n");
 952                 ret = -EINVAL;
 953                 goto err_clock;
 954         }
 955
 956         dp->res = res;
 957
 958         dp->reg_base = ioremap(res->start, resource_size(res));
 959         if (!dp->reg_base) {
 960                 dev_err(&pdev->dev, "failed to ioremap\n");
 961                 ret = -ENOMEM;
 962                 goto err_req_region;
 963         }
 964
 965         dp->irq = platform_get_irq(pdev, 0);
 966         if (!dp->irq) {
 967                 dev_err(&pdev->dev, "failed to get irq\n");
 968                 ret = -ENODEV;
 969                 goto err_ioremap;
 970         }
 971
 972         dp->video_info = pdata->video_info;
 973         if (pdata->phy_init)
 974                 pdata->phy_init();
 975
 976         exynos_dp_init_dp(dp);
 977
 978         ret = request_irq(dp->irq, exynos_dp_irq_handler, 0,
 979                         "exynos-dp", dp);
 980         if (ret) {
 981                 dev_err(&pdev->dev, "failed to request irq\n");
 982                 goto err_ioremap;
 983         }
 984
 985         ret = exynos_dp_detect_hpd(dp);
 986         if (ret) {
 987                 dev_err(&pdev->dev, "unable to detect hpd\n");
 988                 goto err_irq;
 989         }
 990
 991         exynos_dp_handle_edid(dp);
 992
 993         if (pdata->training_type == SW_LINK_TRAINING)
 994                 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
 995                                                 dp->video_info->link_rate);
 996         else
 997                 ret = exynos_dp_set_hw_link_train(dp,
 998                         dp->video_info->lane_count, dp->video_info->link_rate);
 999         if (ret) {
1000                 dev_err(&pdev->dev, "unable to do link train\n");
1001                 goto err_irq;
1002         }
1003
1004         exynos_dp_enable_scramble(dp, 1);
1005         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
1006         exynos_dp_enable_enhanced_mode(dp, 1);
1007
1008         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
1009         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
1010
1011         exynos_dp_init_video(dp);
1012         ret = exynos_dp_config_video(dp, dp->video_info);
1013         if (ret) {
1014                 dev_err(&pdev->dev, "unable to config video\n");
1015                 goto err_irq;
1016         }
1017
1018         platform_set_drvdata(pdev, dp);
1019
1020         return 0;
1021
1022 err_irq:
1023         free_irq(dp->irq, dp);
1024 err_ioremap:
1025         iounmap(dp->reg_base);
1026 err_req_region:
1027         release_mem_region(res->start, resource_size(res));
1028 err_clock:
1029         clk_put(dp->clock);
1030 err_dp:
1031         kfree(dp);
1032
1033         return ret;
1034 }
1035
1036 static int __devexit exynos_dp_remove(struct platform_device *pdev)
1037 {
1038         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1039         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1040
1041         if (pdata && pdata->phy_exit)
1042                 pdata->phy_exit();
1043
1044         free_irq(dp->irq, dp);
1045         iounmap(dp->reg_base);
1046
1047         clk_disable(dp->clock);
1048         clk_put(dp->clock);
1049
1050         release_mem_region(dp->res->start, resource_size(dp->res));
1051
1052         kfree(dp);
1053
1054         return 0;
1055 }
1056
1057 #ifdef CONFIG_PM_SLEEP
1058 static int exynos_dp_suspend(struct device *dev)
1059 {
1060         struct platform_device *pdev = to_platform_device(dev);
1061         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1062         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1063
1064         if (pdata && pdata->phy_exit)
1065                 pdata->phy_exit();
1066
1067         clk_disable(dp->clock);
1068
1069         return 0;
1070 }
1071
1072 static int exynos_dp_resume(struct device *dev)
1073 {
1074         struct platform_device *pdev = to_platform_device(dev);
1075         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1076         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1077
1078         if (pdata && pdata->phy_init)
1079                 pdata->phy_init();
1080
1081         clk_enable(dp->clock);
1082
1083         exynos_dp_init_dp(dp);
1084
1085         exynos_dp_detect_hpd(dp);
1086         exynos_dp_handle_edid(dp);
1087
1088         if (pdata->training_type == SW_LINK_TRAINING)
1089                 exynos_dp_set_link_train(dp, dp->video_info->lane_count,
1090                                                 dp->video_info->link_rate);
1091         else
1092                 exynos_dp_set_hw_link_train(dp,
1093                         dp->video_info->lane_count, dp->video_info->link_rate);
1094
1095         exynos_dp_enable_scramble(dp, 1);
1096         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
1097         exynos_dp_enable_enhanced_mode(dp, 1);
1098
1099         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
1100         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
1101
1102         exynos_dp_init_video(dp);
1103         exynos_dp_config_video(dp, dp->video_info);
1104
1105         return 0;
1106 }
1107 #endif
1108
1109 static const struct dev_pm_ops exynos_dp_pm_ops = {
1110         SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1111 };
1112
1113 #ifdef CONFIG_OF
1114 static const struct of_device_id exynos_dp_match[] = {
1115         { .compatible = "samsung,exynos5-dp" },
1116         {},
1117 };
1118 MODULE_DEVICE_TABLE(of, exynos_dp_match);
1119 #endif
1120
1121 static struct platform_driver exynos_dp_driver = {
1122         .probe          = exynos_dp_probe,
1123         .remove         = __devexit_p(exynos_dp_remove),
1124         .driver         = {
1125                 .name   = "s5p-dp",
1126                 .owner  = THIS_MODULE,
1127                 .pm     = &exynos_dp_pm_ops,
1128                 .of_match_table = of_match_ptr(exynos_dp_match),
1129         },
1130 };
1131
1132 static int __init exynos_dp_init(void)
1133 {
1134         return platform_driver_probe(&exynos_dp_driver, exynos_dp_probe);
1135 }
1136
1137 static void __exit exynos_dp_exit(void)
1138 {
1139         platform_driver_unregister(&exynos_dp_driver);
1140 }
1141 /* TODO: Register as module_platform_driver */
1142 /* Currently, we make it late_initcall to make */
1143 /* sure that s3c-fb is probed before DP driver */
1144 late_initcall(exynos_dp_init);
1145 module_exit(exynos_dp_exit);
1146
1147 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1148 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1149 MODULE_LICENSE("GPL");