drivers/video/exynos/exynos_dp_core.c

   1 /*
   2  * Samsung SoC DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/io.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/delay.h>
  21 #include <linux/of.h>
  22
  23 #include <video/exynos_dp.h>
  24
  25 #include <plat/cpu.h>
  26
  27 #include "exynos_dp_core.h"
  28
  29 #define PLL_MAX_TRIES 100
  30
  31 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
  32 {
  33         exynos_dp_reset(dp);
  34
  35         /* SW defined function Normal operation */
  36         exynos_dp_enable_sw_function(dp);
  37
  38         exynos_dp_init_analog_func(dp);
  39
  40         exynos_dp_init_hpd(dp);
  41         exynos_dp_init_aux(dp);
  42
  43         return 0;
  44 }
  45
  46 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
  47 {
  48         int timeout_loop = 0;
  49
  50         exynos_dp_init_hpd(dp);
  51
  52         udelay(200);
  53
  54         while (exynos_dp_get_plug_in_status(dp) != 0) {
  55                 timeout_loop++;
  56                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
  57                         dev_err(dp->dev, "failed to get hpd plug status\n");
  58                         return -ETIMEDOUT;
  59                 }
  60                 udelay(10);
  61         }
  62
  63         return 0;
  64 }
  65
  66 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  67 {
  68         int i;
  69         unsigned char sum = 0;
  70
  71         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  72                 sum = sum + edid_data[i];
  73
  74         return sum;
  75 }
  76
  77 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
  78 {
  79         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  80         unsigned int extend_block = 0;
  81         unsigned char sum;
  82         unsigned char test_vector;
  83         int retval;
  84
  85         /*
  86          * EDID device address is 0x50.
  87          * However, if necessary, you must have set upper address
  88          * into E-EDID in I2C device, 0x30.
  89          */
  90
  91         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  92         exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
  93                                 EDID_EXTENSION_FLAG,
  94                                 &extend_block);
  95
  96         if (extend_block > 0) {
  97                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
  98
  99                 /* Read EDID data */
 100                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 101                                                 EDID_HEADER_PATTERN,
 102                                                 EDID_BLOCK_LENGTH,
 103                                                 &edid[EDID_HEADER_PATTERN]);
 104                 if (retval != 0) {
 105                         dev_err(dp->dev, "EDID Read failed!\n");
 106                         return -EIO;
 107                 }
 108                 sum = exynos_dp_calc_edid_check_sum(edid);
 109                 if (sum != 0) {
 110                         dev_err(dp->dev, "EDID bad checksum!\n");
 111                         return -EIO;
 112                 }
 113
 114                 /* Read additional EDID data */
 115                 retval = exynos_dp_read_bytes_from_i2c(dp,
 116                                 I2C_EDID_DEVICE_ADDR,
 117                                 EDID_BLOCK_LENGTH,
 118                                 EDID_BLOCK_LENGTH,
 119                                 &edid[EDID_BLOCK_LENGTH]);
 120                 if (retval != 0) {
 121                         dev_err(dp->dev, "EDID Read failed!\n");
 122                         return -EIO;
 123                 }
 124                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 125                 if (sum != 0) {
 126                         dev_err(dp->dev, "EDID bad checksum!\n");
 127                         return -EIO;
 128                 }
 129
 130                 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
 131                                         &test_vector);
 132                 if (test_vector & DPCD_TEST_EDID_READ) {
 133                         exynos_dp_write_byte_to_dpcd(dp,
 134                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 135                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 136                         exynos_dp_write_byte_to_dpcd(dp,
 137                                 DPCD_ADDR_TEST_RESPONSE,
 138                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 139                 }
 140         } else {
 141                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
 142
 143                 /* Read EDID data */
 144                 retval = exynos_dp_read_bytes_from_i2c(dp,
 145                                 I2C_EDID_DEVICE_ADDR,
 146                                 EDID_HEADER_PATTERN,
 147                                 EDID_BLOCK_LENGTH,
 148                                 &edid[EDID_HEADER_PATTERN]);
 149                 if (retval != 0) {
 150                         dev_err(dp->dev, "EDID Read failed!\n");
 151                         return -EIO;
 152                 }
 153                 sum = exynos_dp_calc_edid_check_sum(edid);
 154                 if (sum != 0) {
 155                         dev_err(dp->dev, "EDID bad checksum!\n");
 156                         return -EIO;
 157                 }
 158
 159                 exynos_dp_read_byte_from_dpcd(dp,
 160                         DPCD_ADDR_TEST_REQUEST,
 161                         &test_vector);
 162                 if (test_vector & DPCD_TEST_EDID_READ) {
 163                         exynos_dp_write_byte_to_dpcd(dp,
 164                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 165                                 edid[EDID_CHECKSUM]);
 166                         exynos_dp_write_byte_to_dpcd(dp,
 167                                 DPCD_ADDR_TEST_RESPONSE,
 168                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 169                 }
 170         }
 171
 172         dev_err(dp->dev, "EDID Read success!\n");
 173         return 0;
 174 }
 175
 176 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 177 {
 178         u8 buf[12];
 179         int i;
 180         int retval;
 181
 182         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 183         exynos_dp_read_bytes_from_dpcd(dp,
 184                 DPCD_ADDR_DPCD_REV,
 185                 12, buf);
 186
 187         /* Read EDID */
 188         for (i = 0; i < 3; i++) {
 189                 retval = exynos_dp_read_edid(dp);
 190                 if (retval == 0)
 191                         break;
 192         }
 193
 194         return retval;
 195 }
 196
 197 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 198                                                 bool enable)
 199 {
 200         u8 data;
 201
 202         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
 203
 204         if (enable)
 205                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 206                         DPCD_ENHANCED_FRAME_EN |
 207                         DPCD_LANE_COUNT_SET(data));
 208         else
 209                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 210                         DPCD_LANE_COUNT_SET(data));
 211 }
 212
 213 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
 214 {
 215         u8 data;
 216         int retval;
 217
 218         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 219         retval = DPCD_ENHANCED_FRAME_CAP(data);
 220
 221         return retval;
 222 }
 223
 224 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
 225 {
 226         u8 data;
 227
 228         data = exynos_dp_is_enhanced_mode_available(dp);
 229         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
 230         exynos_dp_enable_enhanced_mode(dp, data);
 231 }
 232
 233 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 234 {
 235         exynos_dp_set_training_pattern(dp, DP_NONE);
 236
 237         exynos_dp_write_byte_to_dpcd(dp,
 238                 DPCD_ADDR_TRAINING_PATTERN_SET,
 239                 DPCD_TRAINING_PATTERN_DISABLED);
 240 }
 241
 242 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
 243                                         int pre_emphasis, int lane)
 244 {
 245         switch (lane) {
 246         case 0:
 247                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 248                 break;
 249         case 1:
 250                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 251                 break;
 252
 253         case 2:
 254                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 255                 break;
 256
 257         case 3:
 258                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 259                 break;
 260         }
 261 }
 262
 263 static int exynos_dp_link_start(struct exynos_dp_device *dp)
 264 {
 265         int ret, lane, lane_count, pll_tries;
 266         u8 buf[4];
 267
 268         lane_count = dp->link_train.lane_count;
 269
 270         dp->link_train.lt_state = CLOCK_RECOVERY;
 271         dp->link_train.eq_loop = 0;
 272
 273         for (lane = 0; lane < lane_count; lane++)
 274                 dp->link_train.cr_loop[lane] = 0;
 275
 276         /* Set link rate and count as you want to establish*/
 277         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 278         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
 279
 280         /* Setup RX configuration */
 281         buf[0] = dp->link_train.link_rate;
 282         buf[1] = dp->link_train.lane_count;
 283         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, 2, buf);
 284         if (ret)
 285                 return ret;
 286
 287         /* Set TX pre-emphasis to minimum */
 288         for (lane = 0; lane < lane_count; lane++)
 289                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 290                         PRE_EMPHASIS_LEVEL_0, lane);
 291
 292         /* Wait for PLL lock */
 293         pll_tries = 0;
 294         while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 295                 if (pll_tries == PLL_MAX_TRIES)
 296                         return -ETIMEDOUT;
 297
 298                 pll_tries++;
 299                 udelay(100);
 300         }
 301
 302         /* Set training pattern 1 */
 303         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 304
 305         /* Set RX training pattern */
 306         ret = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
 307                 DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1);
 308         if (ret)
 309                 return ret;
 310
 311         for (lane = 0; lane < lane_count; lane++)
 312                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 313                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 314         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
 315                 lane_count, buf);
 316         if (ret)
 317                 return ret;
 318
 319         return ret;
 320 }
 321
 322 static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
 323 {
 324         int shift = (lane & 1) * 4;
 325         u8 link_value = link_status[lane>>1];
 326
 327         return (link_value >> shift) & 0xf;
 328 }
 329
 330 static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
 331 {
 332         int lane;
 333         u8 lane_status;
 334
 335         for (lane = 0; lane < lane_count; lane++) {
 336                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 337                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 338                         return -EINVAL;
 339         }
 340         return 0;
 341 }
 342
 343 static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count)
 344 {
 345         int lane;
 346         u8 lane_align;
 347         u8 lane_status;
 348
 349         lane_align = link_status[2];
 350         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 351                 return -EINVAL;
 352
 353         for (lane = 0; lane < lane_count; lane++) {
 354                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 355                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 356                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 357                         return -EINVAL;
 358         }
 359         return 0;
 360 }
 361
 362 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 363                                                         int lane)
 364 {
 365         int shift = (lane & 1) * 4;
 366         u8 link_value = adjust_request[lane>>1];
 367
 368         return (link_value >> shift) & 0x3;
 369 }
 370
 371 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 372                                         u8 adjust_request[2],
 373                                         int lane)
 374 {
 375         int shift = (lane & 1) * 4;
 376         u8 link_value = adjust_request[lane>>1];
 377
 378         return ((link_value >> shift) & 0xc) >> 2;
 379 }
 380
 381 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 382                                         u8 training_lane_set, int lane)
 383 {
 384         switch (lane) {
 385         case 0:
 386                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
 387                 break;
 388         case 1:
 389                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
 390                 break;
 391
 392         case 2:
 393                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
 394                 break;
 395
 396         case 3:
 397                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
 398                 break;
 399         }
 400 }
 401
 402 static unsigned int exynos_dp_get_lane_link_training(
 403                                 struct exynos_dp_device *dp,
 404                                 int lane)
 405 {
 406         u32 reg = 0;
 407
 408         switch (lane) {
 409         case 0:
 410                 reg = exynos_dp_get_lane0_link_training(dp);
 411                 break;
 412         case 1:
 413                 reg = exynos_dp_get_lane1_link_training(dp);
 414                 break;
 415         case 2:
 416                 reg = exynos_dp_get_lane2_link_training(dp);
 417                 break;
 418         case 3:
 419                 reg = exynos_dp_get_lane3_link_training(dp);
 420                 break;
 421         }
 422
 423         return reg;
 424 }
 425
 426 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 427 {
 428         if (dp->link_train.link_rate == LINK_RATE_2_70GBPS) {
 429                 /* set to reduced bit rate */
 430                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 431                 dev_err(dp->dev, "set to bandwidth %.2x\n",
 432                         dp->link_train.link_rate);
 433                 dp->link_train.lt_state = START;
 434         } else {
 435                 exynos_dp_training_pattern_dis(dp);
 436                 /* set enhanced mode if available */
 437                 exynos_dp_set_enhanced_mode(dp);
 438                 dp->link_train.lt_state = FAILED;
 439         }
 440 }
 441
 442 static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp,
 443                                 u8 adjust_request[2])
 444 {
 445         int lane;
 446         int lane_count;
 447         u8 voltage_swing;
 448         u8 pre_emphasis;
 449         u8 training_lane;
 450
 451         lane_count = dp->link_train.lane_count;
 452         for (lane = 0; lane < lane_count; lane++) {
 453                 voltage_swing = exynos_dp_get_adjust_request_voltage(
 454                                                 adjust_request, lane);
 455                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 456                                                 adjust_request, lane);
 457                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 458                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 459
 460                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 461                    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 462                         training_lane |= DPCD_MAX_SWING_REACHED;
 463                         training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 464                 }
 465                 dp->link_train.training_lane[lane] = training_lane;
 466         }
 467 }
 468
 469 static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
 470                                         u8 voltage_swing)
 471 {
 472         int lane;
 473         int lane_count;
 474
 475         lane_count = dp->link_train.lane_count;
 476         for (lane = 0; lane < lane_count; lane++) {
 477                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 478                         dp->link_train.cr_loop[lane] == MAX_CR_LOOP)
 479                         return -EINVAL;
 480         }
 481         return 0;
 482 }
 483
 484 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 485 {
 486         int ret, lane, lane_count;
 487         u8 voltage_swing, pre_emphasis, training_lane, link_status[6];
 488         u8 *adjust_request;
 489
 490         udelay(100);
 491
 492         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 6,
 493                         link_status);
 494         if (ret)
 495                 return ret;
 496
 497         lane_count = dp->link_train.lane_count;
 498         adjust_request = link_status + 4;
 499
 500         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 501                 /* set training pattern 2 for EQ */
 502                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 503
 504                 ret = exynos_dp_write_byte_to_dpcd(dp,
 505                         DPCD_ADDR_TRAINING_PATTERN_SET,
 506                         DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2);
 507                 if (ret)
 508                         return ret;
 509
 510                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 511         } else {
 512                 for (lane = 0; lane < lane_count; lane++) {
 513                         training_lane = exynos_dp_get_lane_link_training(
 514                                                         dp, lane);
 515                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 516                                                         adjust_request, lane);
 517                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 518                                                         adjust_request, lane);
 519                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) &&
 520                             (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis))
 521                                 dp->link_train.cr_loop[lane]++;
 522                         dp->link_train.training_lane[lane] = training_lane;
 523                 }
 524
 525                 if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) {
 526                         exynos_dp_reduce_link_rate(dp);
 527                         return ret;
 528                 }
 529         }
 530
 531         exynos_dp_get_adjust_train(dp, adjust_request);
 532
 533         for (lane = 0; lane < lane_count; lane++) {
 534                 exynos_dp_set_lane_link_training(dp,
 535                         dp->link_train.training_lane[lane], lane);
 536                 ret = exynos_dp_write_byte_to_dpcd(dp,
 537                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 538                         dp->link_train.training_lane[lane]);
 539                 if (ret)
 540                         return ret;
 541         }
 542
 543         return ret;
 544 }
 545
 546 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 547 {
 548         int ret, lane, lane_count;
 549         u8 link_status[6];
 550         u32 reg;
 551         u8 *adjust_request;
 552
 553         udelay(400);
 554
 555         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
 556                                 6, link_status);
 557         if (ret)
 558                 return ret;
 559
 560         adjust_request = link_status + 4;
 561         lane_count = dp->link_train.lane_count;
 562
 563         if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
 564                 exynos_dp_reduce_link_rate(dp);
 565                 return ret;
 566         }
 567         if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
 568                 /* traing pattern Set to Normal */
 569                 exynos_dp_training_pattern_dis(dp);
 570
 571                 dev_info(dp->dev, "Link Training success!\n");
 572
 573                 exynos_dp_get_link_bandwidth(dp, &reg);
 574                 dp->link_train.link_rate = reg;
 575                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 576                         dp->link_train.link_rate);
 577
 578                 exynos_dp_get_lane_count(dp, &reg);
 579                 dp->link_train.lane_count = reg;
 580                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 581                         dp->link_train.lane_count);
 582                 /* set enhanced mode if available */
 583                 exynos_dp_set_enhanced_mode(dp);
 584
 585                 dp->link_train.lt_state = FINISHED;
 586         } else {
 587                 /* not all locked */
 588                 dp->link_train.eq_loop++;
 589
 590                 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 591                         exynos_dp_reduce_link_rate(dp);
 592                 } else {
 593                         exynos_dp_get_adjust_train(dp, adjust_request);
 594
 595                         for (lane = 0; lane < lane_count; lane++) {
 596                                 exynos_dp_set_lane_link_training(dp,
 597                                         dp->link_train.training_lane[lane],
 598                                         lane);
 599                                 ret = exynos_dp_write_byte_to_dpcd(dp,
 600                                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 601                                         dp->link_train.training_lane[lane]);
 602                                 if (ret)
 603                                         return ret;
 604                         }
 605                 }
 606         }
 607
 608         return ret;
 609 }
 610
 611 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 612                         u8 *bandwidth)
 613 {
 614         u8 data;
 615
 616         /*
 617          * For DP rev.1.1, Maximum link rate of Main Link lanes
 618          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 619          */
 620         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
 621         *bandwidth = data;
 622 }
 623
 624 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 625                         u8 *lane_count)
 626 {
 627         u8 data;
 628
 629         /*
 630          * For DP rev.1.1, Maximum number of Main Link lanes
 631          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 632          */
 633         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 634         *lane_count = DPCD_MAX_LANE_COUNT(data);
 635 }
 636
 637 static void exynos_dp_init_training(struct exynos_dp_device *dp,
 638                         enum link_lane_count_type max_lane,
 639                         enum link_rate_type max_rate)
 640 {
 641         /*
 642          * MACRO_RST must be applied after the PLL_LOCK to avoid
 643          * the DP inter pair skew issue for at least 10 us
 644          */
 645         exynos_dp_reset_macro(dp);
 646
 647         /* Initialize by reading RX's DPCD */
 648         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 649         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 650
 651         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 652            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 653                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 654                         dp->link_train.link_rate);
 655                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 656         }
 657
 658         if (dp->link_train.lane_count == 0) {
 659                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 660                         dp->link_train.lane_count);
 661                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 662         }
 663
 664         /* Setup TX lane count & rate */
 665         if (dp->link_train.lane_count > max_lane)
 666                 dp->link_train.lane_count = max_lane;
 667         if (dp->link_train.link_rate > max_rate)
 668                 dp->link_train.link_rate = max_rate;
 669
 670         /* All DP analog module power up */
 671         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 672 }
 673
 674 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 675 {
 676         int ret = 0, training_finished = 0;
 677
 678         /* Turn off unnecessary lanes */
 679         switch (dp->link_train.lane_count) {
 680         case LANE_COUNT1:
 681                 exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
 682         case LANE_COUNT2:
 683                 exynos_dp_set_analog_power_down(dp, CH2_BLOCK, 1);
 684                 exynos_dp_set_analog_power_down(dp, CH3_BLOCK, 1);
 685                 break;
 686         default:
 687                 break;
 688         }
 689
 690         dp->link_train.lt_state = START;
 691
 692         /* Process here */
 693         while (!ret && !training_finished) {
 694                 switch (dp->link_train.lt_state) {
 695                 case START:
 696                         ret = exynos_dp_link_start(dp);
 697                         break;
 698                 case CLOCK_RECOVERY:
 699                         ret = exynos_dp_process_clock_recovery(dp);
 700                         break;
 701                 case EQUALIZER_TRAINING:
 702                         ret = exynos_dp_process_equalizer_training(dp);
 703                         break;
 704                 case FINISHED:
 705                         training_finished = 1;
 706                         break;
 707                 case FAILED:
 708                         return -EREMOTEIO;
 709                 }
 710         }
 711         if (ret)
 712                 dev_err(dp->dev, "eDP link training failed (%d)\n", ret);
 713
 714         return ret;
 715 }
 716
 717 static int exynos_dp_set_hw_link_train(struct exynos_dp_device *dp,
 718                                 u32 max_lane,
 719                                 u32 max_rate)
 720 {
 721         u32 status;
 722         int lane;
 723
 724         exynos_dp_stop_video(dp);
 725
 726         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 727                 dev_err(dp->dev, "PLL is not locked yet.\n");
 728                 return -EINVAL;
 729         }
 730
 731         exynos_dp_reset_macro(dp);
 732
 733         /* Set TX pre-emphasis to minimum */
 734         for (lane = 0; lane < max_lane; lane++)
 735                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 736                                 PRE_EMPHASIS_LEVEL_0, lane);
 737
 738         /* All DP analog module power up */
 739         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 740
 741         /* Initialize by reading RX's DPCD */
 742         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 743         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 744
 745         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 746                 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 747                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 748                         dp->link_train.link_rate);
 749                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 750         }
 751
 752         if (dp->link_train.lane_count == 0) {
 753                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 754                         dp->link_train.lane_count);
 755                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 756         }
 757
 758         /* Setup TX lane count & rate */
 759         if (dp->link_train.lane_count > max_lane)
 760                 dp->link_train.lane_count = max_lane;
 761         if (dp->link_train.link_rate > max_rate)
 762                 dp->link_train.link_rate = max_rate;
 763
 764         /* Set link rate and count as you want to establish*/
 765         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 766         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 767
 768         /* Set sink to D0 (Sink Not Ready) mode. */
 769         exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
 770                                                 DPCD_SET_POWER_STATE_D0);
 771
 772         /* Enable H/W Link Training */
 773         status = exynos_dp_enable_hw_link_training(dp);
 774
 775         if (status != 0) {
 776                 dev_err(dp->dev, " H/W link training failure: 0x%x\n", status);
 777                 return -EINVAL;
 778         }
 779
 780         exynos_dp_get_link_bandwidth(dp, &status);
 781         dp->link_train.link_rate = status;
 782         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 783                                 dp->link_train.link_rate);
 784
 785         exynos_dp_get_lane_count(dp, &status);
 786         dp->link_train.lane_count = status;
 787         dev_dbg(dp->dev, "final lane count = %.2x\n",
 788                                 dp->link_train.lane_count);
 789
 790         return 0;
 791 }
 792
 793 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 794                                 u32 count,
 795                                 u32 bwtype)
 796 {
 797         int i;
 798         int retval;
 799
 800         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 801                 exynos_dp_init_training(dp, count, bwtype);
 802                 retval = exynos_dp_sw_link_training(dp);
 803                 if (retval == 0)
 804                         break;
 805
 806                 udelay(100);
 807         }
 808
 809         return retval;
 810 }
 811
 812 static int exynos_dp_config_video(struct exynos_dp_device *dp,
 813                         struct video_info *video_info)
 814 {
 815         int retval = 0;
 816         int timeout_loop = 0;
 817         int done_count = 0;
 818
 819         exynos_dp_config_video_slave_mode(dp, video_info);
 820
 821         exynos_dp_set_video_color_format(dp, video_info->color_depth,
 822                         video_info->color_space,
 823                         video_info->dynamic_range,
 824                         video_info->ycbcr_coeff);
 825
 826         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 827                 dev_err(dp->dev, "PLL is not locked yet.\n");
 828                 return -EINVAL;
 829         }
 830
 831         for (;;) {
 832                 timeout_loop++;
 833                 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
 834                         break;
 835                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 836                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 837                         return -ETIMEDOUT;
 838                 }
 839
 840                 mdelay(100);
 841         }
 842
 843         /* Set to use the register calculated M/N video */
 844         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 845
 846         /* For video bist, Video timing must be generated by register */
 847         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 848
 849         /* Disable video mute */
 850         exynos_dp_enable_video_mute(dp, 0);
 851
 852         /* Configure video slave mode */
 853         exynos_dp_enable_video_master(dp, 0);
 854
 855         /* Enable video */
 856         exynos_dp_start_video(dp);
 857
 858         timeout_loop = 0;
 859
 860         for (;;) {
 861                 timeout_loop++;
 862                 if (exynos_dp_is_video_stream_on(dp) == 0) {
 863                         done_count++;
 864                         if (done_count > 10)
 865                                 break;
 866                 } else if (done_count) {
 867                         done_count = 0;
 868                 }
 869                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 870                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 871                         return -ETIMEDOUT;
 872                 }
 873
 874                 mdelay(100);
 875         }
 876
 877         if (retval != 0)
 878                 dev_err(dp->dev, "Video stream is not detected!\n");
 879
 880         return retval;
 881 }
 882
 883 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 884 {
 885         u8 data;
 886
 887         if (enable) {
 888                 exynos_dp_enable_scrambling(dp);
 889
 890                 exynos_dp_read_byte_from_dpcd(dp,
 891                         DPCD_ADDR_TRAINING_PATTERN_SET,
 892                         &data);
 893                 exynos_dp_write_byte_to_dpcd(dp,
 894                         DPCD_ADDR_TRAINING_PATTERN_SET,
 895                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 896         } else {
 897                 exynos_dp_disable_scrambling(dp);
 898
 899                 exynos_dp_read_byte_from_dpcd(dp,
 900                         DPCD_ADDR_TRAINING_PATTERN_SET,
 901                         &data);
 902                 exynos_dp_write_byte_to_dpcd(dp,
 903                         DPCD_ADDR_TRAINING_PATTERN_SET,
 904                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
 905         }
 906 }
 907
 908 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 909 {
 910         struct exynos_dp_device *dp = arg;
 911
 912         dev_err(dp->dev, "exynos_dp_irq_handler\n");
 913         return IRQ_HANDLED;
 914 }
 915
 916 static int __devinit exynos_dp_probe(struct platform_device *pdev)
 917 {
 918         struct resource *res;
 919         struct exynos_dp_device *dp;
 920         struct exynos_dp_platdata *pdata;
 921
 922         int ret = 0;
 923
 924         pdata = pdev->dev.platform_data;
 925         if (!pdata) {
 926                 dev_err(&pdev->dev, "no platform data\n");
 927                 return -EINVAL;
 928         }
 929
 930         dp = kzalloc(sizeof(struct exynos_dp_device), GFP_KERNEL);
 931         if (!dp) {
 932                 dev_err(&pdev->dev, "no memory for device data\n");
 933                 return -ENOMEM;
 934         }
 935
 936         dp->dev = &pdev->dev;
 937
 938         dp->clock = clk_get(&pdev->dev, "dp");
 939         if (IS_ERR(dp->clock)) {
 940                 dev_err(&pdev->dev, "failed to get clock\n");
 941                 ret = PTR_ERR(dp->clock);
 942                 goto err_dp;
 943         }
 944
 945         clk_enable(dp->clock);
 946
 947         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 948         if (!res) {
 949                 dev_err(&pdev->dev, "failed to get registers\n");
 950                 ret = -EINVAL;
 951                 goto err_clock;
 952         }
 953
 954         res = request_mem_region(res->start, resource_size(res),
 955                                 dev_name(&pdev->dev));
 956         if (!res) {
 957                 dev_err(&pdev->dev, "failed to request registers region\n");
 958                 ret = -EINVAL;
 959                 goto err_clock;
 960         }
 961
 962         dp->res = res;
 963
 964         dp->reg_base = ioremap(res->start, resource_size(res));
 965         if (!dp->reg_base) {
 966                 dev_err(&pdev->dev, "failed to ioremap\n");
 967                 ret = -ENOMEM;
 968                 goto err_req_region;
 969         }
 970
 971         dp->irq = platform_get_irq(pdev, 0);
 972         if (!dp->irq) {
 973                 dev_err(&pdev->dev, "failed to get irq\n");
 974                 ret = -ENODEV;
 975                 goto err_ioremap;
 976         }
 977
 978         dp->video_info = pdata->video_info;
 979         if (pdata->phy_init)
 980                 pdata->phy_init();
 981
 982         exynos_dp_init_dp(dp);
 983
 984         ret = request_irq(dp->irq, exynos_dp_irq_handler, 0,
 985                         "exynos-dp", dp);
 986         if (ret) {
 987                 dev_err(&pdev->dev, "failed to request irq\n");
 988                 goto err_ioremap;
 989         }
 990
 991         ret = exynos_dp_detect_hpd(dp);
 992         if (ret) {
 993                 dev_err(&pdev->dev, "unable to detect hpd\n");
 994                 goto err_irq;
 995         }
 996
 997         exynos_dp_handle_edid(dp);
 998
 999         if (pdata->training_type == SW_LINK_TRAINING)
1000                 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
1001                                                 dp->video_info->link_rate);
1002         else
1003                 ret = exynos_dp_set_hw_link_train(dp,
1004                         dp->video_info->lane_count, dp->video_info->link_rate);
1005         if (ret) {
1006                 dev_err(&pdev->dev, "unable to do link train\n");
1007                 goto err_irq;
1008         }
1009
1010         exynos_dp_enable_scramble(dp, 1);
1011         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
1012         exynos_dp_enable_enhanced_mode(dp, 1);
1013
1014         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
1015         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
1016
1017         exynos_dp_init_video(dp);
1018         ret = exynos_dp_config_video(dp, dp->video_info);
1019         if (ret) {
1020                 dev_err(&pdev->dev, "unable to config video\n");
1021                 goto err_irq;
1022         }
1023
1024         platform_set_drvdata(pdev, dp);
1025
1026         return 0;
1027
1028 err_irq:
1029         free_irq(dp->irq, dp);
1030 err_ioremap:
1031         iounmap(dp->reg_base);
1032 err_req_region:
1033         release_mem_region(res->start, resource_size(res));
1034 err_clock:
1035         clk_put(dp->clock);
1036 err_dp:
1037         kfree(dp);
1038
1039         return ret;
1040 }
1041
1042 static int __devexit exynos_dp_remove(struct platform_device *pdev)
1043 {
1044         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1045         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1046
1047         if (pdata && pdata->phy_exit)
1048                 pdata->phy_exit();
1049
1050         free_irq(dp->irq, dp);
1051         iounmap(dp->reg_base);
1052
1053         clk_disable(dp->clock);
1054         clk_put(dp->clock);
1055
1056         release_mem_region(dp->res->start, resource_size(dp->res));
1057
1058         kfree(dp);
1059
1060         return 0;
1061 }
1062
1063 #ifdef CONFIG_PM_SLEEP
1064 static int exynos_dp_suspend(struct device *dev)
1065 {
1066         struct platform_device *pdev = to_platform_device(dev);
1067         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1068         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1069
1070         if (pdata && pdata->phy_exit)
1071                 pdata->phy_exit();
1072
1073         clk_disable(dp->clock);
1074
1075         return 0;
1076 }
1077
1078 static int exynos_dp_resume(struct device *dev)
1079 {
1080         struct platform_device *pdev = to_platform_device(dev);
1081         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1082         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1083
1084         if (pdata && pdata->phy_init)
1085                 pdata->phy_init();
1086
1087         clk_enable(dp->clock);
1088
1089         exynos_dp_init_dp(dp);
1090
1091         exynos_dp_detect_hpd(dp);
1092         exynos_dp_handle_edid(dp);
1093
1094         if (pdata->training_type == SW_LINK_TRAINING)
1095                 exynos_dp_set_link_train(dp, dp->video_info->lane_count,
1096                                                 dp->video_info->link_rate);
1097         else
1098                 exynos_dp_set_hw_link_train(dp,
1099                         dp->video_info->lane_count, dp->video_info->link_rate);
1100
1101         exynos_dp_enable_scramble(dp, 1);
1102         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
1103         exynos_dp_enable_enhanced_mode(dp, 1);
1104
1105         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
1106         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
1107
1108         exynos_dp_init_video(dp);
1109         exynos_dp_config_video(dp, dp->video_info);
1110
1111         return 0;
1112 }
1113 #endif
1114
1115 static const struct dev_pm_ops exynos_dp_pm_ops = {
1116         SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1117 };
1118
1119 #ifdef CONFIG_OF
1120 static const struct of_device_id exynos_dp_match[] = {
1121         { .compatible = "samsung,exynos5-dp" },
1122         {},
1123 };
1124 MODULE_DEVICE_TABLE(of, exynos_dp_match);
1125 #endif
1126
1127 static struct platform_driver exynos_dp_driver = {
1128         .probe          = exynos_dp_probe,
1129         .remove         = __devexit_p(exynos_dp_remove),
1130         .driver         = {
1131                 .name   = "s5p-dp",
1132                 .owner  = THIS_MODULE,
1133                 .pm     = &exynos_dp_pm_ops,
1134                 .of_match_table = of_match_ptr(exynos_dp_match),
1135         },
1136 };
1137
1138 static int __init exynos_dp_init(void)
1139 {
1140         return platform_driver_probe(&exynos_dp_driver, exynos_dp_probe);
1141 }
1142
1143 static void __exit exynos_dp_exit(void)
1144 {
1145         platform_driver_unregister(&exynos_dp_driver);
1146 }
1147 /* TODO: Register as module_platform_driver */
1148 /* Currently, we make it late_initcall to make */
1149 /* sure that s3c-fb is probed before DP driver */
1150 late_initcall(exynos_dp_init);
1151 module_exit(exynos_dp_exit);
1152
1153 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1154 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1155 MODULE_LICENSE("GPL");