drivers/video/exynos/exynos_dp_reg.c

   1 /*
   2  * Samsung DP (Display port) register interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/jiffies.h>
  17
  18 #include <video/exynos_dp.h>
  19
  20 #include <plat/cpu.h>
  21
  22 #include "exynos_dp_core.h"
  23 #include "exynos_dp_reg.h"
  24
  25 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
  26 {
  27         u32 reg;
  28
  29         if (enable) {
  30                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  31                 reg |= HDCP_VIDEO_MUTE;
  32                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  33         } else {
  34                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  35                 reg &= ~HDCP_VIDEO_MUTE;
  36                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  37         }
  38 }
  39
  40 void exynos_dp_stop_video(struct exynos_dp_device *dp)
  41 {
  42         u32 reg;
  43
  44         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  45         reg &= ~VIDEO_EN;
  46         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  47 }
  48
  49 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
  50 {
  51         u32 reg;
  52
  53         if (enable)
  54                 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
  55                         LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
  56         else
  57                 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
  58                         LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
  59
  60         writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
  61 }
  62
  63 void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
  64 {
  65         /* Set analog parameters for Tx */
  66         /* Set power source and terminal resistor values */
  67         writel(0x10, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
  68         writel(0x0C, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
  69         writel(0x85, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
  70         writel(0x66, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
  71         writel(0x0, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
  72 }
  73
  74 void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
  75 {
  76         /* Set interrupt pin assertion polarity as high */
  77         writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL);
  78
  79         /* Clear pending regisers */
  80         writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
  81         writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
  82         writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
  83         writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
  84         writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
  85
  86         /* 0:mask,1: unmask */
  87         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
  88         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
  89         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
  90         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
  91         writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
  92 }
  93
  94 void exynos_dp_reset(struct exynos_dp_device *dp)
  95 {
  96         u32 reg;
  97
  98         writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
  99
 100         exynos_dp_stop_video(dp);
 101         exynos_dp_enable_video_mute(dp, 0);
 102
 103         reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 104                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 105                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 106         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 107
 108         reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 109                 SERDES_FIFO_FUNC_EN_N |
 110                 LS_CLK_DOMAIN_FUNC_EN_N;
 111         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 112
 113         udelay(20);
 114
 115         exynos_dp_lane_swap(dp, 0);
 116
 117         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
 118         writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
 119         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 120         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 121
 122         writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
 123         writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
 124
 125         writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
 126         writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
 127
 128         writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
 129
 130         writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
 131
 132         writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
 133         writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
 134
 135         writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
 136         writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
 137
 138         writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
 139
 140         exynos_dp_init_analog_param(dp);
 141         exynos_dp_init_interrupt(dp);
 142 }
 143
 144 u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
 145 {
 146         u32 reg;
 147
 148         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 149         if (reg & PLL_LOCK)
 150                 return PLL_LOCKED;
 151         else
 152                 return PLL_UNLOCKED;
 153 }
 154
 155 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
 156 {
 157         u32 reg;
 158
 159         if (enable) {
 160                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 161                 reg |= DP_PLL_PD;
 162                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 163         } else {
 164                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 165                 reg &= ~DP_PLL_PD;
 166                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 167         }
 168 }
 169
 170 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
 171                                 enum analog_power_block block,
 172                                 bool enable)
 173 {
 174         u32 reg;
 175
 176         switch (block) {
 177         case AUX_BLOCK:
 178                 if (enable) {
 179                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 180                         reg |= AUX_PD;
 181                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 182                 } else {
 183                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 184                         reg &= ~AUX_PD;
 185                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 186                 }
 187                 break;
 188         case CH0_BLOCK:
 189                 if (enable) {
 190                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 191                         reg |= CH0_PD;
 192                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 193                 } else {
 194                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 195                         reg &= ~CH0_PD;
 196                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 197                 }
 198                 break;
 199         case CH1_BLOCK:
 200                 if (enable) {
 201                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 202                         reg |= CH1_PD;
 203                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 204                 } else {
 205                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 206                         reg &= ~CH1_PD;
 207                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 208                 }
 209                 break;
 210         case CH2_BLOCK:
 211                 if (enable) {
 212                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 213                         reg |= CH2_PD;
 214                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 215                 } else {
 216                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 217                         reg &= ~CH2_PD;
 218                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 219                 }
 220                 break;
 221         case CH3_BLOCK:
 222                 if (enable) {
 223                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 224                         reg |= CH3_PD;
 225                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 226                 } else {
 227                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 228                         reg &= ~CH3_PD;
 229                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 230                 }
 231                 break;
 232         case ANALOG_TOTAL:
 233                 if (enable) {
 234                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 235                         reg |= DP_PHY_PD;
 236                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 237                 } else {
 238                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 239                         reg &= ~DP_PHY_PD;
 240                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 241                 }
 242                 break;
 243         case POWER_ALL:
 244                 if (enable) {
 245                         reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 246                                 CH1_PD | CH0_PD;
 247                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 248                 } else {
 249                         writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
 250                 }
 251                 break;
 252         default:
 253                 break;
 254         }
 255 }
 256
 257 void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
 258 {
 259         u32 reg;
 260         int timeout_loop = 0;
 261
 262         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 263
 264         reg = PLL_LOCK_CHG;
 265         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
 266
 267         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 268         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 269         writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 270
 271         /* Power up PLL */
 272         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 273                 exynos_dp_set_pll_power_down(dp, 0);
 274
 275                 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 276                         timeout_loop++;
 277                         if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 278                                 dev_err(dp->dev, "failed to get pll lock status\n");
 279                                 return;
 280                         }
 281                         udelay(10);
 282                 }
 283         }
 284
 285         /* Enable Serdes FIFO function and Link symbol clock domain module */
 286         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 287         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 288                 | AUX_FUNC_EN_N);
 289         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 290 }
 291
 292 void exynos_dp_init_hpd(struct exynos_dp_device *dp)
 293 {
 294         u32 reg;
 295
 296         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 297         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
 298
 299         reg = INT_HPD;
 300         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 301
 302         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 303         reg &= ~(F_HPD | HPD_CTRL);
 304         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 305 }
 306
 307 void exynos_dp_reset_aux(struct exynos_dp_device *dp)
 308 {
 309         u32 reg;
 310
 311         /* Disable AUX channel module */
 312         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 313         reg |= AUX_FUNC_EN_N;
 314         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 315 }
 316
 317 void exynos_dp_init_aux(struct exynos_dp_device *dp)
 318 {
 319         u32 reg;
 320
 321         /* Clear inerrupts related to AUX channel */
 322         reg = RPLY_RECEIV | AUX_ERR;
 323         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 324
 325         exynos_dp_reset_aux(dp);
 326
 327         /* Disable AUX transaction H/W retry */
 328         reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
 329                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 330         writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ;
 331
 332         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 333         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 334         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
 335
 336         /* Enable AUX channel module */
 337         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 338         reg &= ~AUX_FUNC_EN_N;
 339         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 340 }
 341
 342 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
 343 {
 344         u32 reg;
 345
 346         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 347         if (reg & HPD_STATUS)
 348                 return 0;
 349
 350         return -EINVAL;
 351 }
 352
 353 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
 354 {
 355         u32 reg;
 356
 357         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 358         reg &= ~SW_FUNC_EN_N;
 359         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 360 }
 361
 362 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
 363 {
 364         int reg;
 365         int retval = 0;
 366
 367         /* Enable AUX CH operation */
 368         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 369         reg |= AUX_EN;
 370         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 371
 372         /* Is AUX CH command reply received? */
 373         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 374         while (!(reg & RPLY_RECEIV))
 375                 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 376
 377         /* Clear interrupt source for AUX CH command reply */
 378         writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
 379
 380         /* Clear interrupt source for AUX CH access error */
 381         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 382         if (reg & AUX_ERR) {
 383                 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
 384                 return -EREMOTEIO;
 385         }
 386
 387         /* Check AUX CH error access status */
 388         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
 389         if ((reg & AUX_STATUS_MASK) != 0) {
 390                 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
 391                         reg & AUX_STATUS_MASK);
 392                 return -EREMOTEIO;
 393         }
 394
 395         return retval;
 396 }
 397
 398 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 399                                 unsigned int reg_addr,
 400                                 unsigned char data)
 401 {
 402         u32 reg;
 403         int i;
 404         int retval;
 405
 406         for (i = 0; i < 3; i++) {
 407                 /* Clear AUX CH data buffer */
 408                 reg = BUF_CLR;
 409                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 410
 411                 /* Select DPCD device address */
 412                 reg = AUX_ADDR_7_0(reg_addr);
 413                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 414                 reg = AUX_ADDR_15_8(reg_addr);
 415                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 416                 reg = AUX_ADDR_19_16(reg_addr);
 417                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 418
 419                 /* Write data buffer */
 420                 reg = (unsigned int)data;
 421                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 422
 423                 /*
 424                  * Set DisplayPort transaction and write 1 byte
 425                  * If bit 3 is 1, DisplayPort transaction.
 426                  * If Bit 3 is 0, I2C transaction.
 427                  */
 428                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 429                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 430
 431                 /* Start AUX transaction */
 432                 retval = exynos_dp_start_aux_transaction(dp);
 433                 if (retval == 0)
 434                         break;
 435                 else
 436                         dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 437                                 __func__);
 438         }
 439
 440         return retval;
 441 }
 442
 443 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 444                                 unsigned int reg_addr,
 445                                 unsigned char *data)
 446 {
 447         u32 reg;
 448         int i;
 449         int retval;
 450
 451         for (i = 0; i < 10; i++) {
 452                 /* Clear AUX CH data buffer */
 453                 reg = BUF_CLR;
 454                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 455
 456                 /* Select DPCD device address */
 457                 reg = AUX_ADDR_7_0(reg_addr);
 458                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 459                 reg = AUX_ADDR_15_8(reg_addr);
 460                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 461                 reg = AUX_ADDR_19_16(reg_addr);
 462                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 463
 464                 /*
 465                  * Set DisplayPort transaction and read 1 byte
 466                  * If bit 3 is 1, DisplayPort transaction.
 467                  * If Bit 3 is 0, I2C transaction.
 468                  */
 469                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 470                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 471
 472                 /* Start AUX transaction */
 473                 retval = exynos_dp_start_aux_transaction(dp);
 474                 if (retval == 0)
 475                         break;
 476                 else
 477                         dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 478                                 __func__);
 479         }
 480
 481         /* Read data buffer */
 482         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 483         *data = (unsigned char)(reg & 0xff);
 484
 485         return retval;
 486 }
 487
 488 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 489                                 unsigned int reg_addr,
 490                                 unsigned int count,
 491                                 unsigned char data[])
 492 {
 493         u32 reg;
 494         unsigned int start_offset;
 495         unsigned int cur_data_count;
 496         unsigned int cur_data_idx;
 497         int i;
 498         int retval = 0;
 499
 500         /* Clear AUX CH data buffer */
 501         reg = BUF_CLR;
 502         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 503
 504         start_offset = 0;
 505         while (start_offset < count) {
 506                 /* Buffer size of AUX CH is 16 * 4bytes */
 507                 if ((count - start_offset) > 16)
 508                         cur_data_count = 16;
 509                 else
 510                         cur_data_count = count - start_offset;
 511
 512                 for (i = 0; i < 10; i++) {
 513                         /* Select DPCD device address */
 514                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 515                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 516                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 517                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 518                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 519                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 520
 521                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 522                              cur_data_idx++) {
 523                                 reg = data[start_offset + cur_data_idx];
 524                                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
 525                                                           + 4 * cur_data_idx);
 526                         }
 527
 528                         /*
 529                          * Set DisplayPort transaction and write
 530                          * If bit 3 is 1, DisplayPort transaction.
 531                          * If Bit 3 is 0, I2C transaction.
 532                          */
 533                         reg = AUX_LENGTH(cur_data_count) |
 534                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 535                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 536
 537                         /* Start AUX transaction */
 538                         retval = exynos_dp_start_aux_transaction(dp);
 539                         if (retval == 0)
 540                                 break;
 541                         else
 542                                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 543                                         __func__);
 544                 }
 545
 546                 start_offset += cur_data_count;
 547         }
 548
 549         return retval;
 550 }
 551
 552 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 553                                 unsigned int reg_addr,
 554                                 unsigned int count,
 555                                 unsigned char data[])
 556 {
 557         u32 reg;
 558         unsigned int start_offset;
 559         unsigned int cur_data_count;
 560         unsigned int cur_data_idx;
 561         int i;
 562         int retval = 0;
 563
 564         /* Clear AUX CH data buffer */
 565         reg = BUF_CLR;
 566         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 567
 568         start_offset = 0;
 569         while (start_offset < count) {
 570                 /* Buffer size of AUX CH is 16 * 4bytes */
 571                 if ((count - start_offset) > 16)
 572                         cur_data_count = 16;
 573                 else
 574                         cur_data_count = count - start_offset;
 575
 576                 /* AUX CH Request Transaction process */
 577                 for (i = 0; i < 10; i++) {
 578                         /* Select DPCD device address */
 579                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 580                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 581                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 582                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 583                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 584                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 585
 586                         /*
 587                          * Set DisplayPort transaction and read
 588                          * If bit 3 is 1, DisplayPort transaction.
 589                          * If Bit 3 is 0, I2C transaction.
 590                          */
 591                         reg = AUX_LENGTH(cur_data_count) |
 592                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 593                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 594
 595                         /* Start AUX transaction */
 596                         retval = exynos_dp_start_aux_transaction(dp);
 597                         if (retval == 0)
 598                                 break;
 599                         else
 600                                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 601                                         __func__);
 602                 }
 603
 604                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 605                     cur_data_idx++) {
 606                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 607                                                  + 4 * cur_data_idx);
 608                         data[start_offset + cur_data_idx] =
 609                                 (unsigned char)reg;
 610                 }
 611
 612                 start_offset += cur_data_count;
 613         }
 614
 615         return retval;
 616 }
 617
 618 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 619                                 unsigned int device_addr,
 620                                 unsigned int reg_addr)
 621 {
 622         u32 reg;
 623         int retval;
 624
 625         /* Set EDID device address */
 626         reg = device_addr;
 627         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 628         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 629         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 630
 631         /* Set offset from base address of EDID device */
 632         writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 633
 634         /*
 635          * Set I2C transaction and write address
 636          * If bit 3 is 1, DisplayPort transaction.
 637          * If Bit 3 is 0, I2C transaction.
 638          */
 639         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 640                 AUX_TX_COMM_WRITE;
 641         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 642
 643         /* Start AUX transaction */
 644         retval = exynos_dp_start_aux_transaction(dp);
 645         if (retval != 0)
 646                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 647
 648         return retval;
 649 }
 650
 651 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 652                                 unsigned int device_addr,
 653                                 unsigned int reg_addr,
 654                                 unsigned int *data)
 655 {
 656         u32 reg;
 657         int i;
 658         int retval;
 659
 660         for (i = 0; i < 10; i++) {
 661                 /* Clear AUX CH data buffer */
 662                 reg = BUF_CLR;
 663                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 664
 665                 /* Select EDID device */
 666                 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
 667                 if (retval != 0) {
 668                         dev_err(dp->dev, "Select EDID device fail!\n");
 669                         continue;
 670                 }
 671
 672                 /*
 673                  * Set I2C transaction and read data
 674                  * If bit 3 is 1, DisplayPort transaction.
 675                  * If Bit 3 is 0, I2C transaction.
 676                  */
 677                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 678                         AUX_TX_COMM_READ;
 679                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 680
 681                 /* Start AUX transaction */
 682                 retval = exynos_dp_start_aux_transaction(dp);
 683                 if (retval == 0)
 684                         break;
 685                 else
 686                         dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 687                                 __func__);
 688         }
 689
 690         /* Read data */
 691         if (retval == 0)
 692                 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 693
 694         return retval;
 695 }
 696
 697 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 698                                 unsigned int device_addr,
 699                                 unsigned int reg_addr,
 700                                 unsigned int count,
 701                                 unsigned char edid[])
 702 {
 703         u32 reg;
 704         unsigned int i, j;
 705         unsigned int cur_data_idx;
 706         unsigned int defer = 0;
 707         int retval = 0;
 708
 709         for (i = 0; i < count; i += 16) {
 710                 for (j = 0; j < 100; j++) {
 711                         /* Clear AUX CH data buffer */
 712                         reg = BUF_CLR;
 713                         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 714
 715                         /* Set normal AUX CH command */
 716                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 717                         reg &= ~ADDR_ONLY;
 718                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 719
 720                         /*
 721                          * If Rx sends defer, Tx sends only reads
 722                          * request without sending addres
 723                          */
 724                         if (!defer)
 725                                 retval = exynos_dp_select_i2c_device(dp,
 726                                                 device_addr, reg_addr + i);
 727                         else
 728                                 defer = 0;
 729
 730                         if (retval == 0) {
 731                                 /*
 732                                  * Set I2C transaction and write data
 733                                  * If bit 3 is 1, DisplayPort transaction.
 734                                  * If Bit 3 is 0, I2C transaction.
 735                                  */
 736                                 reg = AUX_LENGTH(16) |
 737                                         AUX_TX_COMM_I2C_TRANSACTION |
 738                                         AUX_TX_COMM_READ;
 739                                 writel(reg, dp->reg_base +
 740                                         EXYNOS_DP_AUX_CH_CTL_1);
 741
 742                                 /* Start AUX transaction */
 743                                 retval = exynos_dp_start_aux_transaction(dp);
 744                                 if (retval == 0)
 745                                         break;
 746                                 else
 747                                         dev_dbg(dp->dev,
 748                                                 "%s: Aux Transaction fail!\n",
 749                                                 __func__);
 750                         }
 751                         /* Check if Rx sends defer */
 752                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
 753                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 754                                 reg == AUX_RX_COMM_I2C_DEFER) {
 755                                 dev_err(dp->dev, "Defer: %d\n\n", reg);
 756                                 defer = 1;
 757                         }
 758                 }
 759
 760                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 761                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 762                                                  + 4 * cur_data_idx);
 763                         edid[i + cur_data_idx] = (unsigned char)reg;
 764                 }
 765         }
 766
 767         return retval;
 768 }
 769
 770 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
 771 {
 772         u32 reg;
 773
 774         reg = bwtype;
 775         if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
 776                 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 777 }
 778
 779 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
 780 {
 781         u32 reg;
 782
 783         reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 784         *bwtype = reg;
 785 }
 786
 787 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
 788 {
 789         u32 reg;
 790
 791         reg = count;
 792         writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 793 }
 794
 795 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
 796 {
 797         u32 reg;
 798
 799         reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 800         *count = reg;
 801 }
 802
 803 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
 804 {
 805         u32 reg;
 806
 807         if (enable) {
 808                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 809                 reg |= ENHANCED;
 810                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 811         } else {
 812                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 813                 reg &= ~ENHANCED;
 814                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 815         }
 816 }
 817
 818 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
 819                                  enum pattern_set pattern)
 820 {
 821         u32 reg;
 822
 823         switch (pattern) {
 824         case PRBS7:
 825                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 826                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 827                 break;
 828         case D10_2:
 829                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 830                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 831                 break;
 832         case TRAINING_PTN1:
 833                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 834                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 835                 break;
 836         case TRAINING_PTN2:
 837                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 838                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 839                 break;
 840         case DP_NONE:
 841                 reg = SCRAMBLING_ENABLE |
 842                         LINK_QUAL_PATTERN_SET_DISABLE |
 843                         SW_TRAINING_PATTERN_SET_NORMAL;
 844                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 845                 break;
 846         default:
 847                 break;
 848         }
 849 }
 850
 851 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 852 {
 853         u32 reg;
 854
 855         reg = level << PRE_EMPHASIS_SET_SHIFT;
 856         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 857 }
 858
 859 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 860 {
 861         u32 reg;
 862
 863         reg = level << PRE_EMPHASIS_SET_SHIFT;
 864         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 865 }
 866
 867 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 868 {
 869         u32 reg;
 870
 871         reg = level << PRE_EMPHASIS_SET_SHIFT;
 872         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 873 }
 874
 875 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 876 {
 877         u32 reg;
 878
 879         reg = level << PRE_EMPHASIS_SET_SHIFT;
 880         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 881 }
 882
 883 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 884                                         u32 training_lane)
 885 {
 886         u32 reg;
 887
 888         reg = training_lane;
 889         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 890 }
 891
 892 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 893                                         u32 training_lane)
 894 {
 895         u32 reg;
 896
 897         reg = training_lane;
 898         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 899 }
 900
 901 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 902                                         u32 training_lane)
 903 {
 904         u32 reg;
 905
 906         reg = training_lane;
 907         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 908 }
 909
 910 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
 911                                         u32 training_lane)
 912 {
 913         u32 reg;
 914
 915         reg = training_lane;
 916         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 917 }
 918
 919 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
 920 {
 921         u32 reg;
 922
 923         reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 924         return reg;
 925 }
 926
 927 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
 928 {
 929         u32 reg;
 930
 931         reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 932         return reg;
 933 }
 934
 935 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
 936 {
 937         u32 reg;
 938
 939         reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 940         return reg;
 941 }
 942
 943 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
 944 {
 945         u32 reg;
 946
 947         reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 948         return reg;
 949 }
 950
 951 void exynos_dp_reset_macro(struct exynos_dp_device *dp)
 952 {
 953         u32 reg;
 954
 955         reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
 956         reg |= MACRO_RST;
 957         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
 958
 959         /* 10 us is the minimum reset time. */
 960         udelay(10);
 961
 962         reg &= ~MACRO_RST;
 963         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
 964 }
 965
 966 int exynos_dp_init_video(struct exynos_dp_device *dp)
 967 {
 968         u32 reg;
 969
 970         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
 971         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
 972
 973         reg = 0x0;
 974         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
 975
 976         reg = CHA_CRI(4) | CHA_CTRL;
 977         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
 978
 979         reg = 0x0;
 980         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 981
 982         reg = VID_HRES_TH(2) | VID_VRES_TH(0);
 983         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
 984
 985         return 0;
 986 }
 987
 988 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
 989                         u32 color_depth,
 990                         u32 color_space,
 991                         u32 dynamic_range,
 992                         u32 ycbcr_coeff)
 993 {
 994         u32 reg;
 995
 996         /* Configure the input color depth, color space, dynamic range */
 997         reg = (dynamic_range << IN_D_RANGE_SHIFT) |
 998                 (color_depth << IN_BPC_SHIFT) |
 999                 (color_space << IN_COLOR_F_SHIFT);
1000         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
1001
1002         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1003         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1004         reg &= ~IN_YC_COEFFI_MASK;
1005         if (ycbcr_coeff)
1006                 reg |= IN_YC_COEFFI_ITU709;
1007         else
1008                 reg |= IN_YC_COEFFI_ITU601;
1009         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1010 }
1011
1012 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
1013 {
1014         u32 reg;
1015
1016         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1017         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1018
1019         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1020
1021         if (!(reg & DET_STA)) {
1022                 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1023                 return -EINVAL;
1024         }
1025
1026         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1027         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1028
1029         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1030         dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1031
1032         if (reg & CHA_STA) {
1033                 dev_dbg(dp->dev, "Input stream clk is changing\n");
1034                 return -EINVAL;
1035         }
1036
1037         return 0;
1038 }
1039
1040 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
1041                 enum clock_recovery_m_value_type type,
1042                 u32 m_value,
1043                 u32 n_value)
1044 {
1045         u32 reg;
1046
1047         if (type == REGISTER_M) {
1048                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1049                 reg |= FIX_M_VID;
1050                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1051                 reg = m_value & 0xff;
1052                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
1053                 reg = (m_value >> 8) & 0xff;
1054                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
1055                 reg = (m_value >> 16) & 0xff;
1056                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
1057
1058                 reg = n_value & 0xff;
1059                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
1060                 reg = (n_value >> 8) & 0xff;
1061                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
1062                 reg = (n_value >> 16) & 0xff;
1063                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
1064         } else  {
1065                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1066                 reg &= ~FIX_M_VID;
1067                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1068
1069                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
1070                 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
1071                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
1072         }
1073 }
1074
1075 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
1076 {
1077         u32 reg;
1078
1079         if (type == VIDEO_TIMING_FROM_CAPTURE) {
1080                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1081                 reg &= ~FORMAT_SEL;
1082                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1083         } else {
1084                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1085                 reg |= FORMAT_SEL;
1086                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1087         }
1088 }
1089
1090 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
1091 {
1092         u32 reg;
1093
1094         if (enable) {
1095                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1096                 reg &= ~VIDEO_MODE_MASK;
1097                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1098                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1099         } else {
1100                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1101                 reg &= ~VIDEO_MODE_MASK;
1102                 reg |= VIDEO_MODE_SLAVE_MODE;
1103                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1104         }
1105 }
1106
1107 void exynos_dp_start_video(struct exynos_dp_device *dp)
1108 {
1109         u32 reg;
1110
1111         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1112         reg |= VIDEO_EN;
1113         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1114 }
1115
1116 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
1117 {
1118         u32 reg;
1119
1120         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1121         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1122
1123         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1124         if (!(reg & STRM_VALID)) {
1125                 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1126                 return -EINVAL;
1127         }
1128
1129         return 0;
1130 }
1131
1132 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
1133                         struct video_info *video_info)
1134 {
1135         u32 reg;
1136
1137         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1138         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1139         reg |= MASTER_VID_FUNC_EN_N;
1140         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1141
1142         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1143         reg &= ~INTERACE_SCAN_CFG;
1144         reg |= (video_info->interlaced << 2);
1145         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1146
1147         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1148         reg &= ~VSYNC_POLARITY_CFG;
1149         reg |= (video_info->v_sync_polarity << 1);
1150         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1151
1152         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1153         reg &= ~HSYNC_POLARITY_CFG;
1154         reg |= (video_info->h_sync_polarity << 0);
1155         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1156
1157         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1158         writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1159 }
1160
1161 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
1162 {
1163         u32 reg;
1164
1165         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1166         reg &= ~SCRAMBLING_DISABLE;
1167         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1168 }
1169
1170 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
1171 {
1172         u32 reg;
1173
1174         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1175         reg |= SCRAMBLING_DISABLE;
1176         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1177 }
1178
1179 u32 exynos_dp_enable_hw_link_training(struct exynos_dp_device *dp)
1180 {
1181         u32 reg;
1182         unsigned long timeout;
1183
1184         reg = HW_TRAINING_EN;
1185         writel(reg, dp->reg_base + EXYNOS_DP_HW_LINK_TRAINING_CTL);
1186
1187         /* wait for maximum of 100 msec */
1188         timeout = jiffies + msecs_to_jiffies(100);
1189         do {
1190                 reg = readl(dp->reg_base + EXYNOS_DP_HW_LINK_TRAINING_CTL);
1191                 if (!(reg & HW_TRAINING_EN))
1192                         return 0;
1193                 udelay(10);
1194         } while (time_before(jiffies, timeout));
1195
1196         dev_warn(dp->dev, "H/W Link training failed\n");
1197         return -ETIMEDOUT;
1198 }