drivers/video/exynos/exynos_dp_reg.c

   1 /*
   2  * Samsung DP (Display port) register interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/jiffies.h>
  17
  18 #include <video/exynos_dp.h>
  19
  20 #include <plat/cpu.h>
  21
  22 #include "exynos_dp_core.h"
  23 #include "exynos_dp_reg.h"
  24
  25 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
  26 {
  27         u32 reg;
  28
  29         if (enable) {
  30                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  31                 reg |= HDCP_VIDEO_MUTE;
  32                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  33         } else {
  34                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  35                 reg &= ~HDCP_VIDEO_MUTE;
  36                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  37         }
  38 }
  39
  40 void exynos_dp_stop_video(struct exynos_dp_device *dp)
  41 {
  42         u32 reg;
  43
  44         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  45         reg &= ~VIDEO_EN;
  46         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  47 }
  48
  49 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
  50 {
  51         u32 reg;
  52
  53         if (enable)
  54                 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
  55                         LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
  56         else
  57                 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
  58                         LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
  59
  60         writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
  61 }
  62
  63 void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
  64 {
  65         /* Set analog parameters for Tx */
  66         /* Set power source and terminal resistor values */
  67         writel(0x10, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
  68         writel(0x0C, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
  69         writel(0x85, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
  70         writel(0x66, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
  71         writel(0x0, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
  72 }
  73
  74 void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
  75 {
  76         /* Set interrupt pin assertion polarity as high */
  77         writel(INT_POL0 | INT_POL1, dp->reg_base + EXYNOS_DP_INT_CTL);
  78
  79         /* Clear pending regisers */
  80         writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
  81         writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
  82         writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
  83         writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
  84         writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
  85
  86         /* 0:mask,1: unmask */
  87         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
  88         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
  89         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
  90         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
  91         writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
  92 }
  93
  94 void exynos_dp_reset(struct exynos_dp_device *dp)
  95 {
  96         u32 reg;
  97
  98         writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
  99
 100         exynos_dp_stop_video(dp);
 101         exynos_dp_enable_video_mute(dp, 0);
 102
 103         reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 104                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 105                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 106         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 107
 108         reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 109                 SERDES_FIFO_FUNC_EN_N |
 110                 LS_CLK_DOMAIN_FUNC_EN_N;
 111         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 112
 113         udelay(20);
 114
 115         exynos_dp_lane_swap(dp, 0);
 116
 117         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
 118         writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
 119         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 120         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 121
 122         writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
 123         writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
 124
 125         writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
 126         writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
 127
 128         writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
 129
 130         writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
 131
 132         writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
 133         writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
 134
 135         writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
 136         writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
 137
 138         writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
 139
 140         exynos_dp_init_analog_param(dp);
 141         exynos_dp_init_interrupt(dp);
 142 }
 143
 144 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
 145 {
 146         u32 reg;
 147
 148         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 149         if (reg & PLL_LOCK)
 150                 return PLL_LOCKED;
 151         else
 152                 return PLL_UNLOCKED;
 153 }
 154
 155 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
 156 {
 157         u32 reg;
 158
 159         if (enable) {
 160                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 161                 reg |= DP_PLL_PD;
 162                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 163         } else {
 164                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 165                 reg &= ~DP_PLL_PD;
 166                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 167         }
 168 }
 169
 170 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
 171                                 enum analog_power_block block,
 172                                 bool enable)
 173 {
 174         u32 reg;
 175
 176         switch (block) {
 177         case AUX_BLOCK:
 178                 if (enable) {
 179                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 180                         reg |= AUX_PD;
 181                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 182                 } else {
 183                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 184                         reg &= ~AUX_PD;
 185                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 186                 }
 187                 break;
 188         case CH0_BLOCK:
 189                 if (enable) {
 190                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 191                         reg |= CH0_PD;
 192                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 193                 } else {
 194                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 195                         reg &= ~CH0_PD;
 196                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 197                 }
 198                 break;
 199         case CH1_BLOCK:
 200                 if (enable) {
 201                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 202                         reg |= CH1_PD;
 203                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 204                 } else {
 205                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 206                         reg &= ~CH1_PD;
 207                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 208                 }
 209                 break;
 210         case CH2_BLOCK:
 211                 if (enable) {
 212                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 213                         reg |= CH2_PD;
 214                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 215                 } else {
 216                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 217                         reg &= ~CH2_PD;
 218                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 219                 }
 220                 break;
 221         case CH3_BLOCK:
 222                 if (enable) {
 223                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 224                         reg |= CH3_PD;
 225                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 226                 } else {
 227                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 228                         reg &= ~CH3_PD;
 229                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 230                 }
 231                 break;
 232         case ANALOG_TOTAL:
 233                 if (enable) {
 234                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 235                         reg |= DP_PHY_PD;
 236                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 237                 } else {
 238                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 239                         reg &= ~DP_PHY_PD;
 240                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 241                 }
 242                 break;
 243         case POWER_ALL:
 244                 if (enable) {
 245                         reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 246                                 CH1_PD | CH0_PD;
 247                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 248                 } else {
 249                         writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
 250                 }
 251                 break;
 252         default:
 253                 break;
 254         }
 255 }
 256
 257 void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
 258 {
 259         u32 reg;
 260         int timeout_loop = 0;
 261
 262         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 263
 264         reg = PLL_LOCK_CHG;
 265         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
 266
 267         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 268         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 269         writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 270
 271         /* Power up PLL */
 272         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 273                 exynos_dp_set_pll_power_down(dp, 0);
 274
 275                 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 276                         timeout_loop++;
 277                         if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 278                                 dev_err(dp->dev, "failed to get pll lock status\n");
 279                                 return;
 280                         }
 281                         udelay(10);
 282                 }
 283         }
 284
 285         /* Enable Serdes FIFO function and Link symbol clock domain module */
 286         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 287         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 288                 | AUX_FUNC_EN_N);
 289         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 290 }
 291
 292 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
 293 {
 294         u32 reg;
 295
 296         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 297         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
 298
 299         reg = INT_HPD;
 300         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 301 }
 302
 303 void exynos_dp_init_hpd(struct exynos_dp_device *dp)
 304 {
 305         u32 reg;
 306
 307         exynos_dp_clear_hotplug_interrupts(dp);
 308
 309         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 310         reg &= ~(F_HPD | HPD_CTRL);
 311         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 312
 313         /* Unmask hotplug interrupts */
 314         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 315         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
 316
 317         reg = INT_HPD;
 318         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
 319 }
 320
 321 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
 322 {
 323         u32 reg;
 324
 325         /* Parse hotplug interrupt status register */
 326         reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
 327
 328         if (reg & PLUG)
 329                 return DP_IRQ_TYPE_HP_CABLE_IN;
 330
 331         if (reg & HPD_LOST)
 332                 return DP_IRQ_TYPE_HP_CABLE_OUT;
 333
 334         if (reg & HOTPLUG_CHG)
 335                 return DP_IRQ_TYPE_HP_CHANGE;
 336
 337         return DP_IRQ_TYPE_UNKNOWN;
 338 }
 339
 340 void exynos_dp_reset_aux(struct exynos_dp_device *dp)
 341 {
 342         u32 reg;
 343
 344         /* Disable AUX channel module */
 345         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 346         reg |= AUX_FUNC_EN_N;
 347         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 348 }
 349
 350 void exynos_dp_init_aux(struct exynos_dp_device *dp)
 351 {
 352         u32 reg;
 353
 354         /* Clear inerrupts related to AUX channel */
 355         reg = RPLY_RECEIV | AUX_ERR;
 356         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 357
 358         exynos_dp_reset_aux(dp);
 359
 360         /* Disable AUX transaction H/W retry */
 361         reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
 362                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 363         writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ;
 364
 365         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 366         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 367         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
 368
 369         /* Enable AUX channel module */
 370         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 371         reg &= ~AUX_FUNC_EN_N;
 372         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 373 }
 374
 375 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
 376 {
 377         u32 reg;
 378
 379         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 380         if (reg & HPD_STATUS)
 381                 return 0;
 382
 383         return -EINVAL;
 384 }
 385
 386 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
 387 {
 388         u32 reg;
 389
 390         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 391         reg &= ~SW_FUNC_EN_N;
 392         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 393 }
 394
 395 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
 396 {
 397         int reg;
 398         int retval = 0;
 399
 400         /* Enable AUX CH operation */
 401         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 402         reg |= AUX_EN;
 403         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 404
 405         /* Is AUX CH command reply received? */
 406         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 407         while (!(reg & RPLY_RECEIV))
 408                 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 409
 410         /* Clear interrupt source for AUX CH command reply */
 411         writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
 412
 413         /* Clear interrupt source for AUX CH access error */
 414         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 415         if (reg & AUX_ERR) {
 416                 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
 417                 return -EREMOTEIO;
 418         }
 419
 420         /* Check AUX CH error access status */
 421         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
 422         if ((reg & AUX_STATUS_MASK) != 0) {
 423                 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
 424                         reg & AUX_STATUS_MASK);
 425                 return -EREMOTEIO;
 426         }
 427
 428         return retval;
 429 }
 430
 431 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 432                                 unsigned int reg_addr,
 433                                 unsigned char data)
 434 {
 435         u32 reg;
 436         int i;
 437         int retval;
 438
 439         for (i = 0; i < 3; i++) {
 440                 /* Clear AUX CH data buffer */
 441                 reg = BUF_CLR;
 442                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 443
 444                 /* Select DPCD device address */
 445                 reg = AUX_ADDR_7_0(reg_addr);
 446                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 447                 reg = AUX_ADDR_15_8(reg_addr);
 448                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 449                 reg = AUX_ADDR_19_16(reg_addr);
 450                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 451
 452                 /* Write data buffer */
 453                 reg = (unsigned int)data;
 454                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 455
 456                 /*
 457                  * Set DisplayPort transaction and write 1 byte
 458                  * If bit 3 is 1, DisplayPort transaction.
 459                  * If Bit 3 is 0, I2C transaction.
 460                  */
 461                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 462                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 463
 464                 /* Start AUX transaction */
 465                 retval = exynos_dp_start_aux_transaction(dp);
 466                 if (retval == 0)
 467                         break;
 468                 else
 469                         dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 470                                 __func__);
 471         }
 472
 473         return retval;
 474 }
 475
 476 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 477                                 unsigned int reg_addr,
 478                                 unsigned char *data)
 479 {
 480         u32 reg;
 481         int i;
 482         int retval;
 483
 484         for (i = 0; i < 10; i++) {
 485                 /* Clear AUX CH data buffer */
 486                 reg = BUF_CLR;
 487                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 488
 489                 /* Select DPCD device address */
 490                 reg = AUX_ADDR_7_0(reg_addr);
 491                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 492                 reg = AUX_ADDR_15_8(reg_addr);
 493                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 494                 reg = AUX_ADDR_19_16(reg_addr);
 495                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 496
 497                 /*
 498                  * Set DisplayPort transaction and read 1 byte
 499                  * If bit 3 is 1, DisplayPort transaction.
 500                  * If Bit 3 is 0, I2C transaction.
 501                  */
 502                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 503                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 504
 505                 /* Start AUX transaction */
 506                 retval = exynos_dp_start_aux_transaction(dp);
 507                 if (retval == 0)
 508                         break;
 509                 else
 510                         dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 511                                 __func__);
 512         }
 513
 514         /* Read data buffer */
 515         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 516         *data = (unsigned char)(reg & 0xff);
 517
 518         return retval;
 519 }
 520
 521 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 522                                 unsigned int reg_addr,
 523                                 unsigned int count,
 524                                 unsigned char data[])
 525 {
 526         u32 reg;
 527         unsigned int start_offset;
 528         unsigned int cur_data_count;
 529         unsigned int cur_data_idx;
 530         int i;
 531         int retval = 0;
 532
 533         /* Clear AUX CH data buffer */
 534         reg = BUF_CLR;
 535         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 536
 537         start_offset = 0;
 538         while (start_offset < count) {
 539                 /* Buffer size of AUX CH is 16 * 4bytes */
 540                 if ((count - start_offset) > 16)
 541                         cur_data_count = 16;
 542                 else
 543                         cur_data_count = count - start_offset;
 544
 545                 for (i = 0; i < 3; i++) {
 546                         /* Select DPCD device address */
 547                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 548                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 549                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 550                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 551                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 552                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 553
 554                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 555                              cur_data_idx++) {
 556                                 reg = data[start_offset + cur_data_idx];
 557                                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
 558                                                           + 4 * cur_data_idx);
 559                         }
 560
 561                         /*
 562                          * Set DisplayPort transaction and write
 563                          * If bit 3 is 1, DisplayPort transaction.
 564                          * If Bit 3 is 0, I2C transaction.
 565                          */
 566                         reg = AUX_LENGTH(cur_data_count) |
 567                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 568                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 569
 570                         /* Start AUX transaction */
 571                         retval = exynos_dp_start_aux_transaction(dp);
 572                         if (retval == 0)
 573                                 break;
 574                         else
 575                                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 576                                         __func__);
 577                 }
 578
 579                 start_offset += cur_data_count;
 580         }
 581
 582         return retval;
 583 }
 584
 585 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 586                                 unsigned int reg_addr,
 587                                 unsigned int count,
 588                                 unsigned char data[])
 589 {
 590         u32 reg;
 591         unsigned int start_offset;
 592         unsigned int cur_data_count;
 593         unsigned int cur_data_idx;
 594         int i;
 595         int retval = 0;
 596
 597         /* Clear AUX CH data buffer */
 598         reg = BUF_CLR;
 599         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 600
 601         start_offset = 0;
 602         while (start_offset < count) {
 603                 /* Buffer size of AUX CH is 16 * 4bytes */
 604                 if ((count - start_offset) > 16)
 605                         cur_data_count = 16;
 606                 else
 607                         cur_data_count = count - start_offset;
 608
 609                 /* AUX CH Request Transaction process */
 610                 for (i = 0; i < 3; i++) {
 611                         /* Select DPCD device address */
 612                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 613                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 614                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 615                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 616                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 617                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 618
 619                         /*
 620                          * Set DisplayPort transaction and read
 621                          * If bit 3 is 1, DisplayPort transaction.
 622                          * If Bit 3 is 0, I2C transaction.
 623                          */
 624                         reg = AUX_LENGTH(cur_data_count) |
 625                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 626                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 627
 628                         /* Start AUX transaction */
 629                         retval = exynos_dp_start_aux_transaction(dp);
 630                         if (retval == 0)
 631                                 break;
 632                         else
 633                                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 634                                         __func__);
 635                 }
 636
 637                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 638                     cur_data_idx++) {
 639                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 640                                                  + 4 * cur_data_idx);
 641                         data[start_offset + cur_data_idx] =
 642                                 (unsigned char)reg;
 643                 }
 644
 645                 start_offset += cur_data_count;
 646         }
 647
 648         return retval;
 649 }
 650
 651 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 652                                 unsigned int device_addr,
 653                                 unsigned int reg_addr)
 654 {
 655         u32 reg;
 656         int retval;
 657
 658         /* Set EDID device address */
 659         reg = device_addr;
 660         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 661         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 662         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 663
 664         /* Set offset from base address of EDID device */
 665         writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 666
 667         /*
 668          * Set I2C transaction and write address
 669          * If bit 3 is 1, DisplayPort transaction.
 670          * If Bit 3 is 0, I2C transaction.
 671          */
 672         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 673                 AUX_TX_COMM_WRITE;
 674         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 675
 676         /* Start AUX transaction */
 677         retval = exynos_dp_start_aux_transaction(dp);
 678         if (retval != 0)
 679                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 680
 681         return retval;
 682 }
 683
 684 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 685                                 unsigned int device_addr,
 686                                 unsigned int reg_addr,
 687                                 unsigned int *data)
 688 {
 689         u32 reg;
 690         int i;
 691         int retval;
 692
 693         for (i = 0; i < 3; i++) {
 694                 /* Clear AUX CH data buffer */
 695                 reg = BUF_CLR;
 696                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 697
 698                 /* Select EDID device */
 699                 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
 700                 if (retval != 0) {
 701                         continue;
 702                 }
 703
 704                 /*
 705                  * Set I2C transaction and read data
 706                  * If bit 3 is 1, DisplayPort transaction.
 707                  * If Bit 3 is 0, I2C transaction.
 708                  */
 709                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 710                         AUX_TX_COMM_READ;
 711                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 712
 713                 /* Start AUX transaction */
 714                 retval = exynos_dp_start_aux_transaction(dp);
 715                 if (retval == 0)
 716                         break;
 717                 else
 718                         dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 719                                 __func__);
 720         }
 721
 722         /* Read data */
 723         if (retval == 0)
 724                 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 725
 726         return retval;
 727 }
 728
 729 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 730                                 unsigned int device_addr,
 731                                 unsigned int reg_addr,
 732                                 unsigned int count,
 733                                 unsigned char edid[])
 734 {
 735         u32 reg;
 736         unsigned int i, j;
 737         unsigned int cur_data_idx;
 738         unsigned int defer = 0;
 739         int retval = 0;
 740
 741         for (i = 0; i < count; i += 16) {
 742                 for (j = 0; j < 3; j++) {
 743                         /* Clear AUX CH data buffer */
 744                         reg = BUF_CLR;
 745                         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 746
 747                         /* Set normal AUX CH command */
 748                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 749                         reg &= ~ADDR_ONLY;
 750                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 751
 752                         /*
 753                          * If Rx sends defer, Tx sends only reads
 754                          * request without sending addres
 755                          */
 756                         if (!defer)
 757                                 retval = exynos_dp_select_i2c_device(dp,
 758                                                 device_addr, reg_addr + i);
 759                         else
 760                                 defer = 0;
 761
 762                         if (retval == 0) {
 763                                 /*
 764                                  * Set I2C transaction and write data
 765                                  * If bit 3 is 1, DisplayPort transaction.
 766                                  * If Bit 3 is 0, I2C transaction.
 767                                  */
 768                                 reg = AUX_LENGTH(16) |
 769                                         AUX_TX_COMM_I2C_TRANSACTION |
 770                                         AUX_TX_COMM_READ;
 771                                 writel(reg, dp->reg_base +
 772                                         EXYNOS_DP_AUX_CH_CTL_1);
 773
 774                                 /* Start AUX transaction */
 775                                 retval = exynos_dp_start_aux_transaction(dp);
 776                                 if (retval == 0)
 777                                         break;
 778                                 else
 779                                         dev_dbg(dp->dev,
 780                                                 "%s: Aux Transaction fail!\n",
 781                                                 __func__);
 782                         }
 783                         /* Check if Rx sends defer */
 784                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
 785                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 786                                 reg == AUX_RX_COMM_I2C_DEFER) {
 787                                 dev_err(dp->dev, "Defer: %d\n\n", reg);
 788                                 defer = 1;
 789                         }
 790                 }
 791
 792                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 793                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 794                                                  + 4 * cur_data_idx);
 795                         edid[i + cur_data_idx] = (unsigned char)reg;
 796                 }
 797         }
 798
 799         return retval;
 800 }
 801
 802 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
 803 {
 804         u32 reg;
 805
 806         reg = bwtype;
 807         if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
 808                 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 809 }
 810
 811 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
 812 {
 813         u32 reg;
 814
 815         reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 816         *bwtype = reg;
 817 }
 818
 819 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
 820 {
 821         u32 reg;
 822
 823         reg = count;
 824         writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 825 }
 826
 827 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
 828 {
 829         u32 reg;
 830
 831         reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 832         *count = reg;
 833 }
 834
 835 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
 836 {
 837         u32 reg;
 838
 839         if (enable) {
 840                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 841                 reg |= ENHANCED;
 842                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 843         } else {
 844                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 845                 reg &= ~ENHANCED;
 846                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 847         }
 848 }
 849
 850 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
 851                                  enum pattern_set pattern)
 852 {
 853         u32 reg;
 854
 855         switch (pattern) {
 856         case PRBS7:
 857                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 858                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 859                 break;
 860         case D10_2:
 861                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 862                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 863                 break;
 864         case TRAINING_PTN1:
 865                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 866                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 867                 break;
 868         case TRAINING_PTN2:
 869                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 870                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 871                 break;
 872         case DP_NONE:
 873                 reg = SCRAMBLING_ENABLE |
 874                         LINK_QUAL_PATTERN_SET_DISABLE |
 875                         SW_TRAINING_PATTERN_SET_NORMAL;
 876                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 877                 break;
 878         default:
 879                 break;
 880         }
 881 }
 882
 883 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 884 {
 885         u32 reg;
 886
 887         reg = level << PRE_EMPHASIS_SET_SHIFT;
 888         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 889 }
 890
 891 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 892 {
 893         u32 reg;
 894
 895         reg = level << PRE_EMPHASIS_SET_SHIFT;
 896         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 897 }
 898
 899 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 900 {
 901         u32 reg;
 902
 903         reg = level << PRE_EMPHASIS_SET_SHIFT;
 904         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 905 }
 906
 907 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 908 {
 909         u32 reg;
 910
 911         reg = level << PRE_EMPHASIS_SET_SHIFT;
 912         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 913 }
 914
 915 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 916                                         u32 training_lane)
 917 {
 918         u32 reg;
 919
 920         reg = training_lane;
 921         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 922 }
 923
 924 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 925                                         u32 training_lane)
 926 {
 927         u32 reg;
 928
 929         reg = training_lane;
 930         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 931 }
 932
 933 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 934                                         u32 training_lane)
 935 {
 936         u32 reg;
 937
 938         reg = training_lane;
 939         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 940 }
 941
 942 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
 943                                         u32 training_lane)
 944 {
 945         u32 reg;
 946
 947         reg = training_lane;
 948         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 949 }
 950
 951 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
 952 {
 953         u32 reg;
 954
 955         reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 956         return reg;
 957 }
 958
 959 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
 960 {
 961         u32 reg;
 962
 963         reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 964         return reg;
 965 }
 966
 967 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
 968 {
 969         u32 reg;
 970
 971         reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 972         return reg;
 973 }
 974
 975 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
 976 {
 977         u32 reg;
 978
 979         reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 980         return reg;
 981 }
 982
 983 void exynos_dp_reset_macro(struct exynos_dp_device *dp)
 984 {
 985         u32 reg;
 986
 987         reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
 988         reg |= MACRO_RST;
 989         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
 990
 991         /* 10 us is the minimum reset time. */
 992         udelay(10);
 993
 994         reg &= ~MACRO_RST;
 995         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
 996 }
 997
 998 int exynos_dp_init_video(struct exynos_dp_device *dp)
 999 {
1000         u32 reg;
1001
1002         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1003         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
1004
1005         reg = 0x0;
1006         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1007
1008         reg = CHA_CRI(4) | CHA_CTRL;
1009         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1010
1011         reg = 0x0;
1012         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1013
1014         reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1015         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
1016
1017         return 0;
1018 }
1019
1020 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
1021 {
1022         u32 reg;
1023
1024         /* Configure the input color depth, color space, dynamic range */
1025         reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
1026                 (dp->video_info->color_depth << IN_BPC_SHIFT) |
1027                 (dp->video_info->color_space << IN_COLOR_F_SHIFT);
1028         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
1029
1030         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1031         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1032         reg &= ~IN_YC_COEFFI_MASK;
1033         if (dp->video_info->ycbcr_coeff)
1034                 reg |= IN_YC_COEFFI_ITU709;
1035         else
1036                 reg |= IN_YC_COEFFI_ITU601;
1037         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1038 }
1039
1040 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
1041 {
1042         u32 reg;
1043
1044         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1045         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1046
1047         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1048
1049         if (!(reg & DET_STA)) {
1050                 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1051                 return -EINVAL;
1052         }
1053
1054         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1055         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1056
1057         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1058         dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1059
1060         if (reg & CHA_STA) {
1061                 dev_dbg(dp->dev, "Input stream clk is changing\n");
1062                 return -EINVAL;
1063         }
1064
1065         return 0;
1066 }
1067
1068 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
1069                 enum clock_recovery_m_value_type type,
1070                 u32 m_value,
1071                 u32 n_value)
1072 {
1073         u32 reg;
1074
1075         if (type == REGISTER_M) {
1076                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1077                 reg |= FIX_M_VID;
1078                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1079                 reg = m_value & 0xff;
1080                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
1081                 reg = (m_value >> 8) & 0xff;
1082                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
1083                 reg = (m_value >> 16) & 0xff;
1084                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
1085
1086                 reg = n_value & 0xff;
1087                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
1088                 reg = (n_value >> 8) & 0xff;
1089                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
1090                 reg = (n_value >> 16) & 0xff;
1091                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
1092         } else  {
1093                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1094                 reg &= ~FIX_M_VID;
1095                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1096
1097                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
1098                 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
1099                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
1100         }
1101 }
1102
1103 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
1104 {
1105         u32 reg;
1106
1107         if (type == VIDEO_TIMING_FROM_CAPTURE) {
1108                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1109                 reg &= ~FORMAT_SEL;
1110                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1111         } else {
1112                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1113                 reg |= FORMAT_SEL;
1114                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1115         }
1116 }
1117
1118 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
1119 {
1120         u32 reg;
1121
1122         if (enable) {
1123                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1124                 reg &= ~VIDEO_MODE_MASK;
1125                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1126                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1127         } else {
1128                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1129                 reg &= ~VIDEO_MODE_MASK;
1130                 reg |= VIDEO_MODE_SLAVE_MODE;
1131                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1132         }
1133 }
1134
1135 void exynos_dp_start_video(struct exynos_dp_device *dp)
1136 {
1137         u32 reg;
1138
1139         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1140         reg |= VIDEO_EN;
1141         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1142 }
1143
1144 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
1145 {
1146         u32 reg;
1147
1148         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1149         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1150
1151         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1152         if (!(reg & STRM_VALID)) {
1153                 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1154                 return -EINVAL;
1155         }
1156
1157         return 0;
1158 }
1159
1160 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
1161 {
1162         u32 reg;
1163
1164         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1165         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1166         reg |= MASTER_VID_FUNC_EN_N;
1167         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1168
1169         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1170         reg &= ~INTERACE_SCAN_CFG;
1171         reg |= (dp->video_info->interlaced << 2);
1172         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1173
1174         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1175         reg &= ~VSYNC_POLARITY_CFG;
1176         reg |= (dp->video_info->v_sync_polarity << 1);
1177         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1178
1179         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1180         reg &= ~HSYNC_POLARITY_CFG;
1181         reg |= (dp->video_info->h_sync_polarity << 0);
1182         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1183
1184         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1185         writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1186 }
1187
1188 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
1189 {
1190         u32 reg;
1191
1192         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1193         reg &= ~SCRAMBLING_DISABLE;
1194         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1195 }
1196
1197 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
1198 {
1199         u32 reg;
1200
1201         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1202         reg |= SCRAMBLING_DISABLE;
1203         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1204 }
1205
1206 int exynos_dp_enable_hw_link_training(struct exynos_dp_device *dp)
1207 {
1208         u32 reg;
1209         unsigned long timeout;
1210
1211         reg = HW_TRAINING_EN;
1212         writel(reg, dp->reg_base + EXYNOS_DP_HW_LINK_TRAINING_CTL);
1213
1214         /* wait for maximum of 100 msec */
1215         timeout = jiffies + msecs_to_jiffies(100);
1216         do {
1217                 reg = readl(dp->reg_base + EXYNOS_DP_HW_LINK_TRAINING_CTL);
1218                 if (!(reg & HW_TRAINING_EN))
1219                         return 0;
1220                 udelay(10);
1221         } while (time_before(jiffies, timeout));
1222
1223         dev_warn(dp->dev, "H/W Link training failed\n");
1224         return -ETIMEDOUT;
1225 }