drivers/video/exynos/exynos_dp_reg.c

   1 /*
   2  * Samsung DP (Display port) register interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/jiffies.h>
  17
  18 #include <video/exynos_dp.h>
  19
  20 #include <plat/cpu.h>
  21
  22 #include "exynos_dp_core.h"
  23 #include "exynos_dp_reg.h"
  24
  25 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
  26 {
  27         u32 reg;
  28
  29         if (enable) {
  30                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  31                 reg |= HDCP_VIDEO_MUTE;
  32                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  33         } else {
  34                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  35                 reg &= ~HDCP_VIDEO_MUTE;
  36                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  37         }
  38 }
  39
  40 void exynos_dp_stop_video(struct exynos_dp_device *dp)
  41 {
  42         u32 reg;
  43
  44         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  45         reg &= ~VIDEO_EN;
  46         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  47 }
  48
  49 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
  50 {
  51         u32 reg;
  52
  53         if (enable)
  54                 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
  55                         LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
  56         else
  57                 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
  58                         LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
  59
  60         writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
  61 }
  62
  63 void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
  64 {
  65         /* Set analog parameters for Tx */
  66         /* Set power source and terminal resistor values */
  67         writel(0x10, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
  68         writel(0x0C, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
  69         writel(0x85, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
  70         writel(0x66, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
  71         writel(0x0, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
  72 }
  73
  74 void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
  75 {
  76         /* Set interrupt pin assertion polarity as high */
  77         writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL);
  78
  79         /* Clear pending regisers */
  80         writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
  81         writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
  82         writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
  83         writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
  84         writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
  85
  86         /* 0:mask,1: unmask */
  87         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
  88         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
  89         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
  90         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
  91         writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
  92 }
  93
  94 void exynos_dp_reset(struct exynos_dp_device *dp)
  95 {
  96         u32 reg;
  97
  98         writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
  99
 100         exynos_dp_stop_video(dp);
 101         exynos_dp_enable_video_mute(dp, 0);
 102
 103         reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 104                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 105                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 106         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 107
 108         reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 109                 SERDES_FIFO_FUNC_EN_N |
 110                 LS_CLK_DOMAIN_FUNC_EN_N;
 111         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 112
 113         udelay(20);
 114
 115         exynos_dp_lane_swap(dp, 0);
 116
 117         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
 118         writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
 119         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 120         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 121
 122         writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
 123         writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
 124
 125         writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
 126         writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
 127
 128         writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
 129
 130         writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
 131
 132         writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
 133         writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
 134
 135         writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
 136         writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
 137
 138         writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
 139
 140         exynos_dp_init_analog_param(dp);
 141         exynos_dp_init_interrupt(dp);
 142 }
 143
 144 u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
 145 {
 146         u32 reg;
 147
 148         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 149         if (reg & PLL_LOCK)
 150                 return PLL_LOCKED;
 151         else
 152                 return PLL_UNLOCKED;
 153 }
 154
 155 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
 156 {
 157         u32 reg;
 158
 159         if (enable) {
 160                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 161                 reg |= DP_PLL_PD;
 162                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 163         } else {
 164                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 165                 reg &= ~DP_PLL_PD;
 166                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 167         }
 168 }
 169
 170 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
 171                                 enum analog_power_block block,
 172                                 bool enable)
 173 {
 174         u32 reg;
 175
 176         switch (block) {
 177         case AUX_BLOCK:
 178                 if (enable) {
 179                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 180                         reg |= AUX_PD;
 181                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 182                 } else {
 183                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 184                         reg &= ~AUX_PD;
 185                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 186                 }
 187                 break;
 188         case CH0_BLOCK:
 189                 if (enable) {
 190                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 191                         reg |= CH0_PD;
 192                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 193                 } else {
 194                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 195                         reg &= ~CH0_PD;
 196                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 197                 }
 198                 break;
 199         case CH1_BLOCK:
 200                 if (enable) {
 201                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 202                         reg |= CH1_PD;
 203                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 204                 } else {
 205                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 206                         reg &= ~CH1_PD;
 207                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 208                 }
 209                 break;
 210         case CH2_BLOCK:
 211                 if (enable) {
 212                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 213                         reg |= CH2_PD;
 214                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 215                 } else {
 216                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 217                         reg &= ~CH2_PD;
 218                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 219                 }
 220                 break;
 221         case CH3_BLOCK:
 222                 if (enable) {
 223                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 224                         reg |= CH3_PD;
 225                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 226                 } else {
 227                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 228                         reg &= ~CH3_PD;
 229                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 230                 }
 231                 break;
 232         case ANALOG_TOTAL:
 233                 if (enable) {
 234                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 235                         reg |= DP_PHY_PD;
 236                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 237                 } else {
 238                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 239                         reg &= ~DP_PHY_PD;
 240                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 241                 }
 242                 break;
 243         case POWER_ALL:
 244                 if (enable) {
 245                         reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 246                                 CH1_PD | CH0_PD;
 247                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 248                 } else {
 249                         writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
 250                 }
 251                 break;
 252         default:
 253                 break;
 254         }
 255 }
 256
 257 void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
 258 {
 259         u32 reg;
 260         int timeout_loop = 0;
 261
 262         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 263
 264         reg = PLL_LOCK_CHG;
 265         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
 266
 267         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 268         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 269         writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 270
 271         /* Power up PLL */
 272         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 273                 exynos_dp_set_pll_power_down(dp, 0);
 274
 275                 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 276                         timeout_loop++;
 277                         if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 278                                 dev_err(dp->dev, "failed to get pll lock status\n");
 279                                 return;
 280                         }
 281                         udelay(10);
 282                 }
 283         }
 284
 285         /* Enable Serdes FIFO function and Link symbol clock domain module */
 286         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 287         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 288                 | AUX_FUNC_EN_N);
 289         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 290 }
 291
 292 void exynos_dp_init_hpd(struct exynos_dp_device *dp)
 293 {
 294         u32 reg;
 295
 296         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 297         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
 298
 299         reg = INT_HPD;
 300         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 301
 302         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 303         reg &= ~(F_HPD | HPD_CTRL);
 304         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 305 }
 306
 307 void exynos_dp_reset_aux(struct exynos_dp_device *dp)
 308 {
 309         u32 reg;
 310
 311         /* Disable AUX channel module */
 312         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 313         reg |= AUX_FUNC_EN_N;
 314         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 315 }
 316
 317 void exynos_dp_init_aux(struct exynos_dp_device *dp)
 318 {
 319         u32 reg;
 320
 321         /* Clear inerrupts related to AUX channel */
 322         reg = RPLY_RECEIV | AUX_ERR;
 323         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 324
 325         exynos_dp_reset_aux(dp);
 326
 327         /* Disable AUX transaction H/W retry */
 328         reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
 329                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 330         writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ;
 331
 332         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 333         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 334         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
 335
 336         /* Enable AUX channel module */
 337         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 338         reg &= ~AUX_FUNC_EN_N;
 339         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 340 }
 341
 342 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
 343 {
 344         u32 reg;
 345
 346         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 347         if (reg & HPD_STATUS)
 348                 return 0;
 349
 350         return -EINVAL;
 351 }
 352
 353 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
 354 {
 355         u32 reg;
 356
 357         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 358         reg &= ~SW_FUNC_EN_N;
 359         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 360 }
 361
 362 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
 363 {
 364         int reg;
 365         int retval = 0;
 366
 367         /* Enable AUX CH operation */
 368         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 369         reg |= AUX_EN;
 370         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 371
 372         /* Is AUX CH command reply received? */
 373         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 374         while (!(reg & RPLY_RECEIV))
 375                 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 376
 377         /* Clear interrupt source for AUX CH command reply */
 378         writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
 379
 380         /* Clear interrupt source for AUX CH access error */
 381         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 382         if (reg & AUX_ERR) {
 383                 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
 384                 return -EREMOTEIO;
 385         }
 386
 387         /* Check AUX CH error access status */
 388         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
 389         if ((reg & AUX_STATUS_MASK) != 0) {
 390                 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
 391                         reg & AUX_STATUS_MASK);
 392                 return -EREMOTEIO;
 393         }
 394
 395         return retval;
 396 }
 397
 398 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 399                                 unsigned int reg_addr,
 400                                 unsigned char data)
 401 {
 402         u32 reg;
 403         int i;
 404         int retval;
 405
 406         for (i = 0; i < 3; i++) {
 407                 /* Clear AUX CH data buffer */
 408                 reg = BUF_CLR;
 409                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 410
 411                 /* Select DPCD device address */
 412                 reg = AUX_ADDR_7_0(reg_addr);
 413                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 414                 reg = AUX_ADDR_15_8(reg_addr);
 415                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 416                 reg = AUX_ADDR_19_16(reg_addr);
 417                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 418
 419                 /* Write data buffer */
 420                 reg = (unsigned int)data;
 421                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 422
 423                 /*
 424                  * Set DisplayPort transaction and write 1 byte
 425                  * If bit 3 is 1, DisplayPort transaction.
 426                  * If Bit 3 is 0, I2C transaction.
 427                  */
 428                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 429                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 430
 431                 /* Start AUX transaction */
 432                 retval = exynos_dp_start_aux_transaction(dp);
 433                 if (retval == 0)
 434                         break;
 435                 else
 436                         dev_err(dp->dev, "Aux Transaction fail!\n");
 437         }
 438
 439         return retval;
 440 }
 441
 442 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 443                                 unsigned int reg_addr,
 444                                 unsigned char *data)
 445 {
 446         u32 reg;
 447         int i;
 448         int retval;
 449
 450         for (i = 0; i < 10; i++) {
 451                 /* Clear AUX CH data buffer */
 452                 reg = BUF_CLR;
 453                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 454
 455                 /* Select DPCD device address */
 456                 reg = AUX_ADDR_7_0(reg_addr);
 457                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 458                 reg = AUX_ADDR_15_8(reg_addr);
 459                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 460                 reg = AUX_ADDR_19_16(reg_addr);
 461                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 462
 463                 /*
 464                  * Set DisplayPort transaction and read 1 byte
 465                  * If bit 3 is 1, DisplayPort transaction.
 466                  * If Bit 3 is 0, I2C transaction.
 467                  */
 468                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 469                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 470
 471                 /* Start AUX transaction */
 472                 retval = exynos_dp_start_aux_transaction(dp);
 473                 if (retval == 0)
 474                         break;
 475                 else
 476                         dev_err(dp->dev, "Aux Transaction fail!\n");
 477         }
 478
 479         /* Read data buffer */
 480         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 481         *data = (unsigned char)(reg & 0xff);
 482
 483         return retval;
 484 }
 485
 486 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 487                                 unsigned int reg_addr,
 488                                 unsigned int count,
 489                                 unsigned char data[])
 490 {
 491         u32 reg;
 492         unsigned int start_offset;
 493         unsigned int cur_data_count;
 494         unsigned int cur_data_idx;
 495         int i;
 496         int retval = 0;
 497
 498         /* Clear AUX CH data buffer */
 499         reg = BUF_CLR;
 500         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 501
 502         start_offset = 0;
 503         while (start_offset < count) {
 504                 /* Buffer size of AUX CH is 16 * 4bytes */
 505                 if ((count - start_offset) > 16)
 506                         cur_data_count = 16;
 507                 else
 508                         cur_data_count = count - start_offset;
 509
 510                 for (i = 0; i < 10; i++) {
 511                         /* Select DPCD device address */
 512                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 513                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 514                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 515                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 516                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 517                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 518
 519                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 520                              cur_data_idx++) {
 521                                 reg = data[start_offset + cur_data_idx];
 522                                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
 523                                                           + 4 * cur_data_idx);
 524                         }
 525
 526                         /*
 527                          * Set DisplayPort transaction and write
 528                          * If bit 3 is 1, DisplayPort transaction.
 529                          * If Bit 3 is 0, I2C transaction.
 530                          */
 531                         reg = AUX_LENGTH(cur_data_count) |
 532                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 533                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 534
 535                         /* Start AUX transaction */
 536                         retval = exynos_dp_start_aux_transaction(dp);
 537                         if (retval == 0)
 538                                 break;
 539                         else
 540                                 dev_err(dp->dev, "Aux Transaction fail!\n");
 541                 }
 542
 543                 start_offset += cur_data_count;
 544         }
 545
 546         return retval;
 547 }
 548
 549 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 550                                 unsigned int reg_addr,
 551                                 unsigned int count,
 552                                 unsigned char data[])
 553 {
 554         u32 reg;
 555         unsigned int start_offset;
 556         unsigned int cur_data_count;
 557         unsigned int cur_data_idx;
 558         int i;
 559         int retval = 0;
 560
 561         /* Clear AUX CH data buffer */
 562         reg = BUF_CLR;
 563         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 564
 565         start_offset = 0;
 566         while (start_offset < count) {
 567                 /* Buffer size of AUX CH is 16 * 4bytes */
 568                 if ((count - start_offset) > 16)
 569                         cur_data_count = 16;
 570                 else
 571                         cur_data_count = count - start_offset;
 572
 573                 /* AUX CH Request Transaction process */
 574                 for (i = 0; i < 10; i++) {
 575                         /* Select DPCD device address */
 576                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 577                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 578                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 579                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 580                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 581                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 582
 583                         /*
 584                          * Set DisplayPort transaction and read
 585                          * If bit 3 is 1, DisplayPort transaction.
 586                          * If Bit 3 is 0, I2C transaction.
 587                          */
 588                         reg = AUX_LENGTH(cur_data_count) |
 589                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 590                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 591
 592                         /* Start AUX transaction */
 593                         retval = exynos_dp_start_aux_transaction(dp);
 594                         if (retval == 0)
 595                                 break;
 596                         else
 597                                 dev_err(dp->dev, "Aux Transaction fail!\n");
 598                 }
 599
 600                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 601                     cur_data_idx++) {
 602                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 603                                                  + 4 * cur_data_idx);
 604                         data[start_offset + cur_data_idx] =
 605                                 (unsigned char)reg;
 606                 }
 607
 608                 start_offset += cur_data_count;
 609         }
 610
 611         return retval;
 612 }
 613
 614 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 615                                 unsigned int device_addr,
 616                                 unsigned int reg_addr)
 617 {
 618         u32 reg;
 619         int retval;
 620
 621         /* Set EDID device address */
 622         reg = device_addr;
 623         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 624         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 625         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 626
 627         /* Set offset from base address of EDID device */
 628         writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 629
 630         /*
 631          * Set I2C transaction and write address
 632          * If bit 3 is 1, DisplayPort transaction.
 633          * If Bit 3 is 0, I2C transaction.
 634          */
 635         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 636                 AUX_TX_COMM_WRITE;
 637         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 638
 639         /* Start AUX transaction */
 640         retval = exynos_dp_start_aux_transaction(dp);
 641         if (retval != 0)
 642                 dev_err(dp->dev, "Aux Transaction fail!\n");
 643
 644         return retval;
 645 }
 646
 647 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 648                                 unsigned int device_addr,
 649                                 unsigned int reg_addr,
 650                                 unsigned int *data)
 651 {
 652         u32 reg;
 653         int i;
 654         int retval;
 655
 656         for (i = 0; i < 10; i++) {
 657                 /* Clear AUX CH data buffer */
 658                 reg = BUF_CLR;
 659                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 660
 661                 /* Select EDID device */
 662                 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
 663                 if (retval != 0) {
 664                         dev_err(dp->dev, "Select EDID device fail!\n");
 665                         continue;
 666                 }
 667
 668                 /*
 669                  * Set I2C transaction and read data
 670                  * If bit 3 is 1, DisplayPort transaction.
 671                  * If Bit 3 is 0, I2C transaction.
 672                  */
 673                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 674                         AUX_TX_COMM_READ;
 675                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 676
 677                 /* Start AUX transaction */
 678                 retval = exynos_dp_start_aux_transaction(dp);
 679                 if (retval == 0)
 680                         break;
 681                 else
 682                         dev_err(dp->dev, "Aux Transaction fail!\n");
 683         }
 684
 685         /* Read data */
 686         if (retval == 0)
 687                 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 688
 689         return retval;
 690 }
 691
 692 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 693                                 unsigned int device_addr,
 694                                 unsigned int reg_addr,
 695                                 unsigned int count,
 696                                 unsigned char edid[])
 697 {
 698         u32 reg;
 699         unsigned int i, j;
 700         unsigned int cur_data_idx;
 701         unsigned int defer = 0;
 702         int retval = 0;
 703
 704         for (i = 0; i < count; i += 16) {
 705                 for (j = 0; j < 100; j++) {
 706                         /* Clear AUX CH data buffer */
 707                         reg = BUF_CLR;
 708                         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 709
 710                         /* Set normal AUX CH command */
 711                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 712                         reg &= ~ADDR_ONLY;
 713                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 714
 715                         /*
 716                          * If Rx sends defer, Tx sends only reads
 717                          * request without sending addres
 718                          */
 719                         if (!defer)
 720                                 retval = exynos_dp_select_i2c_device(dp,
 721                                                 device_addr, reg_addr + i);
 722                         else
 723                                 defer = 0;
 724
 725                         if (retval == 0) {
 726                                 /*
 727                                  * Set I2C transaction and write data
 728                                  * If bit 3 is 1, DisplayPort transaction.
 729                                  * If Bit 3 is 0, I2C transaction.
 730                                  */
 731                                 reg = AUX_LENGTH(16) |
 732                                         AUX_TX_COMM_I2C_TRANSACTION |
 733                                         AUX_TX_COMM_READ;
 734                                 writel(reg, dp->reg_base +
 735                                         EXYNOS_DP_AUX_CH_CTL_1);
 736
 737                                 /* Start AUX transaction */
 738                                 retval = exynos_dp_start_aux_transaction(dp);
 739                                 if (retval == 0)
 740                                         break;
 741                                 else
 742                                         dev_err(dp->dev, "Aux Transaction fail!\n");
 743                         }
 744                         /* Check if Rx sends defer */
 745                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
 746                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 747                                 reg == AUX_RX_COMM_I2C_DEFER) {
 748                                 dev_err(dp->dev, "Defer: %d\n\n", reg);
 749                                 defer = 1;
 750                         }
 751                 }
 752
 753                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 754                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 755                                                  + 4 * cur_data_idx);
 756                         edid[i + cur_data_idx] = (unsigned char)reg;
 757                 }
 758         }
 759
 760         return retval;
 761 }
 762
 763 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
 764 {
 765         u32 reg;
 766
 767         reg = bwtype;
 768         if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
 769                 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 770 }
 771
 772 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
 773 {
 774         u32 reg;
 775
 776         reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 777         *bwtype = reg;
 778 }
 779
 780 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
 781 {
 782         u32 reg;
 783
 784         reg = count;
 785         writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 786 }
 787
 788 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
 789 {
 790         u32 reg;
 791
 792         reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 793         *count = reg;
 794 }
 795
 796 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
 797 {
 798         u32 reg;
 799
 800         if (enable) {
 801                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 802                 reg |= ENHANCED;
 803                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 804         } else {
 805                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 806                 reg &= ~ENHANCED;
 807                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 808         }
 809 }
 810
 811 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
 812                                  enum pattern_set pattern)
 813 {
 814         u32 reg;
 815
 816         switch (pattern) {
 817         case PRBS7:
 818                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 819                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 820                 break;
 821         case D10_2:
 822                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 823                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 824                 break;
 825         case TRAINING_PTN1:
 826                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 827                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 828                 break;
 829         case TRAINING_PTN2:
 830                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 831                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 832                 break;
 833         case DP_NONE:
 834                 reg = SCRAMBLING_ENABLE |
 835                         LINK_QUAL_PATTERN_SET_DISABLE |
 836                         SW_TRAINING_PATTERN_SET_NORMAL;
 837                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 838                 break;
 839         default:
 840                 break;
 841         }
 842 }
 843
 844 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 845 {
 846         u32 reg;
 847
 848         reg = level << PRE_EMPHASIS_SET_SHIFT;
 849         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 850 }
 851
 852 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 853 {
 854         u32 reg;
 855
 856         reg = level << PRE_EMPHASIS_SET_SHIFT;
 857         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 858 }
 859
 860 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 861 {
 862         u32 reg;
 863
 864         reg = level << PRE_EMPHASIS_SET_SHIFT;
 865         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 866 }
 867
 868 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 869 {
 870         u32 reg;
 871
 872         reg = level << PRE_EMPHASIS_SET_SHIFT;
 873         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 874 }
 875
 876 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 877                                         u32 training_lane)
 878 {
 879         u32 reg;
 880
 881         reg = training_lane;
 882         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 883 }
 884
 885 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 886                                         u32 training_lane)
 887 {
 888         u32 reg;
 889
 890         reg = training_lane;
 891         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 892 }
 893
 894 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 895                                         u32 training_lane)
 896 {
 897         u32 reg;
 898
 899         reg = training_lane;
 900         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 901 }
 902
 903 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
 904                                         u32 training_lane)
 905 {
 906         u32 reg;
 907
 908         reg = training_lane;
 909         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 910 }
 911
 912 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
 913 {
 914         u32 reg;
 915
 916         reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 917         return reg;
 918 }
 919
 920 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
 921 {
 922         u32 reg;
 923
 924         reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 925         return reg;
 926 }
 927
 928 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
 929 {
 930         u32 reg;
 931
 932         reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 933         return reg;
 934 }
 935
 936 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
 937 {
 938         u32 reg;
 939
 940         reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 941         return reg;
 942 }
 943
 944 void exynos_dp_reset_macro(struct exynos_dp_device *dp)
 945 {
 946         u32 reg;
 947
 948         reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
 949         reg |= MACRO_RST;
 950         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
 951
 952         /* 10 us is the minimum reset time. */
 953         udelay(10);
 954
 955         reg &= ~MACRO_RST;
 956         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
 957 }
 958
 959 int exynos_dp_init_video(struct exynos_dp_device *dp)
 960 {
 961         u32 reg;
 962
 963         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
 964         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
 965
 966         reg = 0x0;
 967         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
 968
 969         reg = CHA_CRI(4) | CHA_CTRL;
 970         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
 971
 972         reg = 0x0;
 973         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 974
 975         reg = VID_HRES_TH(2) | VID_VRES_TH(0);
 976         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
 977
 978         return 0;
 979 }
 980
 981 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
 982                         u32 color_depth,
 983                         u32 color_space,
 984                         u32 dynamic_range,
 985                         u32 ycbcr_coeff)
 986 {
 987         u32 reg;
 988
 989         /* Configure the input color depth, color space, dynamic range */
 990         reg = (dynamic_range << IN_D_RANGE_SHIFT) |
 991                 (color_depth << IN_BPC_SHIFT) |
 992                 (color_space << IN_COLOR_F_SHIFT);
 993         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
 994
 995         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 996         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
 997         reg &= ~IN_YC_COEFFI_MASK;
 998         if (ycbcr_coeff)
 999                 reg |= IN_YC_COEFFI_ITU709;
1000         else
1001                 reg |= IN_YC_COEFFI_ITU601;
1002         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1003 }
1004
1005 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
1006 {
1007         u32 reg;
1008
1009         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1010         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1011
1012         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1013
1014         if (!(reg & DET_STA)) {
1015                 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1016                 return -EINVAL;
1017         }
1018
1019         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1020         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1021
1022         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1023         dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1024
1025         if (reg & CHA_STA) {
1026                 dev_dbg(dp->dev, "Input stream clk is changing\n");
1027                 return -EINVAL;
1028         }
1029
1030         return 0;
1031 }
1032
1033 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
1034                 enum clock_recovery_m_value_type type,
1035                 u32 m_value,
1036                 u32 n_value)
1037 {
1038         u32 reg;
1039
1040         if (type == REGISTER_M) {
1041                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1042                 reg |= FIX_M_VID;
1043                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1044                 reg = m_value & 0xff;
1045                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
1046                 reg = (m_value >> 8) & 0xff;
1047                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
1048                 reg = (m_value >> 16) & 0xff;
1049                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
1050
1051                 reg = n_value & 0xff;
1052                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
1053                 reg = (n_value >> 8) & 0xff;
1054                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
1055                 reg = (n_value >> 16) & 0xff;
1056                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
1057         } else  {
1058                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1059                 reg &= ~FIX_M_VID;
1060                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1061
1062                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
1063                 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
1064                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
1065         }
1066 }
1067
1068 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
1069 {
1070         u32 reg;
1071
1072         if (type == VIDEO_TIMING_FROM_CAPTURE) {
1073                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1074                 reg &= ~FORMAT_SEL;
1075                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1076         } else {
1077                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1078                 reg |= FORMAT_SEL;
1079                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1080         }
1081 }
1082
1083 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
1084 {
1085         u32 reg;
1086
1087         if (enable) {
1088                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1089                 reg &= ~VIDEO_MODE_MASK;
1090                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1091                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1092         } else {
1093                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1094                 reg &= ~VIDEO_MODE_MASK;
1095                 reg |= VIDEO_MODE_SLAVE_MODE;
1096                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1097         }
1098 }
1099
1100 void exynos_dp_start_video(struct exynos_dp_device *dp)
1101 {
1102         u32 reg;
1103
1104         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1105         reg |= VIDEO_EN;
1106         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1107 }
1108
1109 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
1110 {
1111         u32 reg;
1112
1113         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1114         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1115
1116         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1117         if (!(reg & STRM_VALID)) {
1118                 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1119                 return -EINVAL;
1120         }
1121
1122         return 0;
1123 }
1124
1125 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
1126                         struct video_info *video_info)
1127 {
1128         u32 reg;
1129
1130         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1131         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1132         reg |= MASTER_VID_FUNC_EN_N;
1133         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1134
1135         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1136         reg &= ~INTERACE_SCAN_CFG;
1137         reg |= (video_info->interlaced << 2);
1138         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1139
1140         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1141         reg &= ~VSYNC_POLARITY_CFG;
1142         reg |= (video_info->v_sync_polarity << 1);
1143         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1144
1145         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1146         reg &= ~HSYNC_POLARITY_CFG;
1147         reg |= (video_info->h_sync_polarity << 0);
1148         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1149
1150         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1151         writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1152 }
1153
1154 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
1155 {
1156         u32 reg;
1157
1158         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1159         reg &= ~SCRAMBLING_DISABLE;
1160         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1161 }
1162
1163 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
1164 {
1165         u32 reg;
1166
1167         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1168         reg |= SCRAMBLING_DISABLE;
1169         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1170 }
1171
1172 u32 exynos_dp_enable_hw_link_training(struct exynos_dp_device *dp)
1173 {
1174         u32 reg;
1175         unsigned long timeout;
1176
1177         reg = HW_TRAINING_EN;
1178         writel(reg, dp->reg_base + EXYNOS_DP_HW_LINK_TRAINING_CTL);
1179
1180         /* wait for maximum of 100 msec */
1181         timeout = jiffies + msecs_to_jiffies(100);
1182         do {
1183                 reg = readl(dp->reg_base + EXYNOS_DP_HW_LINK_TRAINING_CTL);
1184                 if (!(reg & HW_TRAINING_EN))
1185                         return 0;
1186                 udelay(10);
1187         } while (time_before(jiffies, timeout));
1188
1189         dev_warn(dp->dev, "H/W Link training failed\n");
1190         return -ETIMEDOUT;
1191 }