2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/interrupt.h>
37 #include <linux/platform_device.h>
38 #include <linux/pm_runtime.h>
42 #include <video/omapdss.h>
45 #include "dss_features.h"
49 #define DISPC_SZ_REGS SZ_4K
51 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
58 #define DISPC_MAX_NR_ISRS 8
60 struct omap_dispc_isr_data {
66 enum omap_burst_size {
72 #define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
75 #define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
78 struct dispc_irq_stats {
79 unsigned long last_reset;
84 struct dispc_features {
91 int (*calc_scaling) (enum omap_plane plane,
92 const struct omap_video_timings *mgr_timings,
93 u16 width, u16 height, u16 out_width, u16 out_height,
94 enum omap_color_mode color_mode, bool *five_taps,
95 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
96 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
97 unsigned long (*calc_core_clk) (enum omap_plane plane,
98 u16 width, u16 height, u16 out_width, u16 out_height,
102 /* swap GFX & WB fifos */
103 bool gfx_fifo_workaround:1;
106 #define DISPC_MAX_NR_FIFOS 5
109 struct platform_device *pdev;
117 u32 fifo_size[DISPC_MAX_NR_FIFOS];
118 /* maps which plane is using a fifo. fifo-id -> plane-id */
119 int fifo_assignment[DISPC_MAX_NR_FIFOS];
123 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
125 struct work_struct error_work;
128 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
130 const struct dispc_features *feat;
132 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
133 spinlock_t irq_stats_lock;
134 struct dispc_irq_stats irq_stats;
138 enum omap_color_component {
139 /* used for all color formats for OMAP3 and earlier
140 * and for RGB and Y color component on OMAP4
142 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
143 /* used for UV component for
144 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
145 * color formats on OMAP4
147 DISPC_COLOR_COMPONENT_UV = 1 << 1,
150 enum mgr_reg_fields {
151 DISPC_MGR_FLD_ENABLE,
152 DISPC_MGR_FLD_STNTFT,
154 DISPC_MGR_FLD_TFTDATALINES,
155 DISPC_MGR_FLD_STALLMODE,
156 DISPC_MGR_FLD_TCKENABLE,
157 DISPC_MGR_FLD_TCKSELECTION,
159 DISPC_MGR_FLD_FIFOHANDCHECK,
160 /* used to maintain a count of the above fields */
164 static const struct {
169 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
171 [OMAP_DSS_CHANNEL_LCD] = {
173 .vsync_irq = DISPC_IRQ_VSYNC,
174 .framedone_irq = DISPC_IRQ_FRAMEDONE,
175 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
177 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
178 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
179 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
180 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
181 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
182 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
183 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
184 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
185 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
188 [OMAP_DSS_CHANNEL_DIGIT] = {
190 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
192 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
194 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
195 [DISPC_MGR_FLD_STNTFT] = { },
196 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
197 [DISPC_MGR_FLD_TFTDATALINES] = { },
198 [DISPC_MGR_FLD_STALLMODE] = { },
199 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
200 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
201 [DISPC_MGR_FLD_CPR] = { },
202 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
205 [OMAP_DSS_CHANNEL_LCD2] = {
207 .vsync_irq = DISPC_IRQ_VSYNC2,
208 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
209 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
211 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
212 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
213 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
214 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
215 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
216 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
217 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
218 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
219 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
222 [OMAP_DSS_CHANNEL_LCD3] = {
224 .vsync_irq = DISPC_IRQ_VSYNC3,
225 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
226 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
228 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
229 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
230 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
231 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
232 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
233 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
234 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
235 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
236 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
241 struct color_conv_coef {
242 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
246 static void _omap_dispc_set_irqs(void);
247 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
248 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
250 static inline void dispc_write_reg(const u16 idx, u32 val)
252 __raw_writel(val, dispc.base + idx);
255 static inline u32 dispc_read_reg(const u16 idx)
257 return __raw_readl(dispc.base + idx);
260 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
262 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
263 return REG_GET(rfld.reg, rfld.high, rfld.low);
266 static void mgr_fld_write(enum omap_channel channel,
267 enum mgr_reg_fields regfld, int val) {
268 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
269 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
273 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
275 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
277 static void dispc_save_context(void)
281 DSSDBG("dispc_save_context\n");
287 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
288 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
290 if (dss_has_feature(FEAT_MGR_LCD2)) {
294 if (dss_has_feature(FEAT_MGR_LCD3)) {
299 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
300 SR(DEFAULT_COLOR(i));
303 if (i == OMAP_DSS_CHANNEL_DIGIT)
314 if (dss_has_feature(FEAT_CPR)) {
321 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
326 SR(OVL_ATTRIBUTES(i));
327 SR(OVL_FIFO_THRESHOLD(i));
329 SR(OVL_PIXEL_INC(i));
330 if (dss_has_feature(FEAT_PRELOAD))
332 if (i == OMAP_DSS_GFX) {
333 SR(OVL_WINDOW_SKIP(i));
338 SR(OVL_PICTURE_SIZE(i));
342 for (j = 0; j < 8; j++)
343 SR(OVL_FIR_COEF_H(i, j));
345 for (j = 0; j < 8; j++)
346 SR(OVL_FIR_COEF_HV(i, j));
348 for (j = 0; j < 5; j++)
349 SR(OVL_CONV_COEF(i, j));
351 if (dss_has_feature(FEAT_FIR_COEF_V)) {
352 for (j = 0; j < 8; j++)
353 SR(OVL_FIR_COEF_V(i, j));
356 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
363 for (j = 0; j < 8; j++)
364 SR(OVL_FIR_COEF_H2(i, j));
366 for (j = 0; j < 8; j++)
367 SR(OVL_FIR_COEF_HV2(i, j));
369 for (j = 0; j < 8; j++)
370 SR(OVL_FIR_COEF_V2(i, j));
372 if (dss_has_feature(FEAT_ATTR2))
373 SR(OVL_ATTRIBUTES2(i));
376 if (dss_has_feature(FEAT_CORE_CLK_DIV))
379 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
380 dispc.ctx_valid = true;
382 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
385 static void dispc_restore_context(void)
389 DSSDBG("dispc_restore_context\n");
391 if (!dispc.ctx_valid)
394 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
396 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
399 DSSDBG("ctx_loss_count: saved %d, current %d\n",
400 dispc.ctx_loss_cnt, ctx);
406 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
407 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
409 if (dss_has_feature(FEAT_MGR_LCD2))
411 if (dss_has_feature(FEAT_MGR_LCD3))
414 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
415 RR(DEFAULT_COLOR(i));
418 if (i == OMAP_DSS_CHANNEL_DIGIT)
429 if (dss_has_feature(FEAT_CPR)) {
436 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
441 RR(OVL_ATTRIBUTES(i));
442 RR(OVL_FIFO_THRESHOLD(i));
444 RR(OVL_PIXEL_INC(i));
445 if (dss_has_feature(FEAT_PRELOAD))
447 if (i == OMAP_DSS_GFX) {
448 RR(OVL_WINDOW_SKIP(i));
453 RR(OVL_PICTURE_SIZE(i));
457 for (j = 0; j < 8; j++)
458 RR(OVL_FIR_COEF_H(i, j));
460 for (j = 0; j < 8; j++)
461 RR(OVL_FIR_COEF_HV(i, j));
463 for (j = 0; j < 5; j++)
464 RR(OVL_CONV_COEF(i, j));
466 if (dss_has_feature(FEAT_FIR_COEF_V)) {
467 for (j = 0; j < 8; j++)
468 RR(OVL_FIR_COEF_V(i, j));
471 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
478 for (j = 0; j < 8; j++)
479 RR(OVL_FIR_COEF_H2(i, j));
481 for (j = 0; j < 8; j++)
482 RR(OVL_FIR_COEF_HV2(i, j));
484 for (j = 0; j < 8; j++)
485 RR(OVL_FIR_COEF_V2(i, j));
487 if (dss_has_feature(FEAT_ATTR2))
488 RR(OVL_ATTRIBUTES2(i));
491 if (dss_has_feature(FEAT_CORE_CLK_DIV))
494 /* enable last, because LCD & DIGIT enable are here */
496 if (dss_has_feature(FEAT_MGR_LCD2))
498 if (dss_has_feature(FEAT_MGR_LCD3))
500 /* clear spurious SYNC_LOST_DIGIT interrupts */
501 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
504 * enable last so IRQs won't trigger before
505 * the context is fully restored
509 DSSDBG("context restored\n");
515 int dispc_runtime_get(void)
519 DSSDBG("dispc_runtime_get\n");
521 r = pm_runtime_get_sync(&dispc.pdev->dev);
523 return r < 0 ? r : 0;
526 void dispc_runtime_put(void)
530 DSSDBG("dispc_runtime_put\n");
532 r = pm_runtime_put_sync(&dispc.pdev->dev);
533 WARN_ON(r < 0 && r != -ENOSYS);
536 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
538 return mgr_desc[channel].vsync_irq;
541 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
543 return mgr_desc[channel].framedone_irq;
546 u32 dispc_wb_get_framedone_irq(void)
548 return DISPC_IRQ_FRAMEDONEWB;
551 bool dispc_mgr_go_busy(enum omap_channel channel)
553 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
556 void dispc_mgr_go(enum omap_channel channel)
558 bool enable_bit, go_bit;
560 /* if the channel is not enabled, we don't need GO */
561 enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
566 go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
569 DSSERR("GO bit not down for channel %d\n", channel);
573 DSSDBG("GO %s\n", mgr_desc[channel].name);
575 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
578 bool dispc_wb_go_busy(void)
580 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
583 void dispc_wb_go(void)
585 enum omap_plane plane = OMAP_DSS_WB;
588 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
593 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
595 DSSERR("GO bit not down for WB\n");
599 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
602 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
604 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
607 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
609 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
612 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
614 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
617 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
619 BUG_ON(plane == OMAP_DSS_GFX);
621 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
624 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
627 BUG_ON(plane == OMAP_DSS_GFX);
629 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
632 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
634 BUG_ON(plane == OMAP_DSS_GFX);
636 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
639 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
640 int fir_vinc, int five_taps,
641 enum omap_color_component color_comp)
643 const struct dispc_coef *h_coef, *v_coef;
646 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
647 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
649 for (i = 0; i < 8; i++) {
652 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
653 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
654 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
655 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
656 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
657 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
658 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
659 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
661 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
662 dispc_ovl_write_firh_reg(plane, i, h);
663 dispc_ovl_write_firhv_reg(plane, i, hv);
665 dispc_ovl_write_firh2_reg(plane, i, h);
666 dispc_ovl_write_firhv2_reg(plane, i, hv);
672 for (i = 0; i < 8; i++) {
674 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
675 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
676 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
677 dispc_ovl_write_firv_reg(plane, i, v);
679 dispc_ovl_write_firv2_reg(plane, i, v);
685 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
686 const struct color_conv_coef *ct)
688 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
690 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
691 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
692 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
693 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
694 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
696 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
701 static void dispc_setup_color_conv_coef(void)
704 int num_ovl = dss_feat_get_num_ovls();
705 int num_wb = dss_feat_get_num_wbs();
706 const struct color_conv_coef ctbl_bt601_5_ovl = {
707 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
709 const struct color_conv_coef ctbl_bt601_5_wb = {
710 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
713 for (i = 1; i < num_ovl; i++)
714 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
716 for (; i < num_wb; i++)
717 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
720 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
722 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
725 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
727 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
730 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
732 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
735 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
737 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
740 static void dispc_ovl_set_pos(enum omap_plane plane,
741 enum omap_overlay_caps caps, int x, int y)
745 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
748 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
750 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
753 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
756 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
758 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
759 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
761 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
764 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
769 BUG_ON(plane == OMAP_DSS_GFX);
771 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
773 if (plane == OMAP_DSS_WB)
774 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
776 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
779 static void dispc_ovl_set_zorder(enum omap_plane plane,
780 enum omap_overlay_caps caps, u8 zorder)
782 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
785 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
788 static void dispc_ovl_enable_zorder_planes(void)
792 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
795 for (i = 0; i < dss_feat_get_num_ovls(); i++)
796 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
799 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
800 enum omap_overlay_caps caps, bool enable)
802 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
805 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
808 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
809 enum omap_overlay_caps caps, u8 global_alpha)
811 static const unsigned shifts[] = { 0, 8, 16, 24, };
814 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
817 shift = shifts[plane];
818 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
821 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
823 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
826 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
828 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
831 static void dispc_ovl_set_color_mode(enum omap_plane plane,
832 enum omap_color_mode color_mode)
835 if (plane != OMAP_DSS_GFX) {
836 switch (color_mode) {
837 case OMAP_DSS_COLOR_NV12:
839 case OMAP_DSS_COLOR_RGBX16:
841 case OMAP_DSS_COLOR_RGBA16:
843 case OMAP_DSS_COLOR_RGB12U:
845 case OMAP_DSS_COLOR_ARGB16:
847 case OMAP_DSS_COLOR_RGB16:
849 case OMAP_DSS_COLOR_ARGB16_1555:
851 case OMAP_DSS_COLOR_RGB24U:
853 case OMAP_DSS_COLOR_RGB24P:
855 case OMAP_DSS_COLOR_YUV2:
857 case OMAP_DSS_COLOR_UYVY:
859 case OMAP_DSS_COLOR_ARGB32:
861 case OMAP_DSS_COLOR_RGBA32:
863 case OMAP_DSS_COLOR_RGBX32:
865 case OMAP_DSS_COLOR_XRGB16_1555:
871 switch (color_mode) {
872 case OMAP_DSS_COLOR_CLUT1:
874 case OMAP_DSS_COLOR_CLUT2:
876 case OMAP_DSS_COLOR_CLUT4:
878 case OMAP_DSS_COLOR_CLUT8:
880 case OMAP_DSS_COLOR_RGB12U:
882 case OMAP_DSS_COLOR_ARGB16:
884 case OMAP_DSS_COLOR_RGB16:
886 case OMAP_DSS_COLOR_ARGB16_1555:
888 case OMAP_DSS_COLOR_RGB24U:
890 case OMAP_DSS_COLOR_RGB24P:
892 case OMAP_DSS_COLOR_RGBX16:
894 case OMAP_DSS_COLOR_RGBA16:
896 case OMAP_DSS_COLOR_ARGB32:
898 case OMAP_DSS_COLOR_RGBA32:
900 case OMAP_DSS_COLOR_RGBX32:
902 case OMAP_DSS_COLOR_XRGB16_1555:
909 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
912 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
913 enum omap_dss_rotation_type rotation_type)
915 if (dss_has_feature(FEAT_BURST_2D) == 0)
918 if (rotation_type == OMAP_DSS_ROT_TILER)
919 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
921 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
924 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
928 int chan = 0, chan2 = 0;
934 case OMAP_DSS_VIDEO1:
935 case OMAP_DSS_VIDEO2:
936 case OMAP_DSS_VIDEO3:
944 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
945 if (dss_has_feature(FEAT_MGR_LCD2)) {
947 case OMAP_DSS_CHANNEL_LCD:
951 case OMAP_DSS_CHANNEL_DIGIT:
955 case OMAP_DSS_CHANNEL_LCD2:
959 case OMAP_DSS_CHANNEL_LCD3:
960 if (dss_has_feature(FEAT_MGR_LCD3)) {
973 val = FLD_MOD(val, chan, shift, shift);
974 val = FLD_MOD(val, chan2, 31, 30);
976 val = FLD_MOD(val, channel, shift, shift);
978 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
981 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
985 enum omap_channel channel;
991 case OMAP_DSS_VIDEO1:
992 case OMAP_DSS_VIDEO2:
993 case OMAP_DSS_VIDEO3:
1001 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1003 if (dss_has_feature(FEAT_MGR_LCD3)) {
1004 if (FLD_GET(val, 31, 30) == 0)
1005 channel = FLD_GET(val, shift, shift);
1006 else if (FLD_GET(val, 31, 30) == 1)
1007 channel = OMAP_DSS_CHANNEL_LCD2;
1009 channel = OMAP_DSS_CHANNEL_LCD3;
1010 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
1011 if (FLD_GET(val, 31, 30) == 0)
1012 channel = FLD_GET(val, shift, shift);
1014 channel = OMAP_DSS_CHANNEL_LCD2;
1016 channel = FLD_GET(val, shift, shift);
1022 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1024 enum omap_plane plane = OMAP_DSS_WB;
1026 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1029 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1030 enum omap_burst_size burst_size)
1032 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1035 shift = shifts[plane];
1036 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1039 static void dispc_configure_burst_sizes(void)
1042 const int burst_size = BURST_SIZE_X8;
1044 /* Configure burst size always to maximum size */
1045 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1046 dispc_ovl_set_burst_size(i, burst_size);
1049 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1051 unsigned unit = dss_feat_get_burst_size_unit();
1052 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1056 void dispc_enable_gamma_table(bool enable)
1059 * This is partially implemented to support only disabling of
1063 DSSWARN("Gamma table enabling for TV not yet supported");
1067 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1070 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1072 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1075 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1078 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1079 struct omap_dss_cpr_coefs *coefs)
1081 u32 coef_r, coef_g, coef_b;
1083 if (!dss_mgr_is_lcd(channel))
1086 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1087 FLD_VAL(coefs->rb, 9, 0);
1088 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1089 FLD_VAL(coefs->gb, 9, 0);
1090 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1091 FLD_VAL(coefs->bb, 9, 0);
1093 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1094 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1095 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1098 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1102 BUG_ON(plane == OMAP_DSS_GFX);
1104 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1105 val = FLD_MOD(val, enable, 9, 9);
1106 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1109 static void dispc_ovl_enable_replication(enum omap_plane plane,
1110 enum omap_overlay_caps caps, bool enable)
1112 static const unsigned shifts[] = { 5, 10, 10, 10 };
1115 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1118 shift = shifts[plane];
1119 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1122 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1127 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1128 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1131 static void dispc_init_fifos(void)
1138 unit = dss_feat_get_buffer_size_unit();
1140 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1142 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1143 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1145 dispc.fifo_size[fifo] = size;
1148 * By default fifos are mapped directly to overlays, fifo 0 to
1149 * ovl 0, fifo 1 to ovl 1, etc.
1151 dispc.fifo_assignment[fifo] = fifo;
1155 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1156 * causes problems with certain use cases, like using the tiler in 2D
1157 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1158 * giving GFX plane a larger fifo. WB but should work fine with a
1161 if (dispc.feat->gfx_fifo_workaround) {
1164 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1166 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1167 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1168 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1169 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1171 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1173 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1174 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1178 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1183 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1184 if (dispc.fifo_assignment[fifo] == plane)
1185 size += dispc.fifo_size[fifo];
1191 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1193 u8 hi_start, hi_end, lo_start, lo_end;
1196 unit = dss_feat_get_buffer_size_unit();
1198 WARN_ON(low % unit != 0);
1199 WARN_ON(high % unit != 0);
1204 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1205 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1207 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1209 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1210 lo_start, lo_end) * unit,
1211 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1212 hi_start, hi_end) * unit,
1213 low * unit, high * unit);
1215 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1216 FLD_VAL(high, hi_start, hi_end) |
1217 FLD_VAL(low, lo_start, lo_end));
1220 void dispc_enable_fifomerge(bool enable)
1222 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1227 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1228 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1231 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1232 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1236 * All sizes are in bytes. Both the buffer and burst are made of
1237 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1240 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1241 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1244 burst_size = dispc_ovl_get_burst_size(plane);
1245 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1247 if (use_fifomerge) {
1248 total_fifo_size = 0;
1249 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1250 total_fifo_size += dispc_ovl_get_fifo_size(i);
1252 total_fifo_size = ovl_fifo_size;
1256 * We use the same low threshold for both fifomerge and non-fifomerge
1257 * cases, but for fifomerge we calculate the high threshold using the
1258 * combined fifo size
1261 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1262 *fifo_low = ovl_fifo_size - burst_size * 2;
1263 *fifo_high = total_fifo_size - burst_size;
1264 } else if (plane == OMAP_DSS_WB) {
1266 * Most optimal configuration for writeback is to push out data
1267 * to the interconnect the moment writeback pushes enough pixels
1268 * in the FIFO to form a burst
1271 *fifo_high = burst_size;
1273 *fifo_low = ovl_fifo_size - burst_size;
1274 *fifo_high = total_fifo_size - buf_unit;
1278 static void dispc_ovl_set_fir(enum omap_plane plane,
1280 enum omap_color_component color_comp)
1284 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1285 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1287 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1288 &hinc_start, &hinc_end);
1289 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1290 &vinc_start, &vinc_end);
1291 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1292 FLD_VAL(hinc, hinc_start, hinc_end);
1294 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1296 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1297 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1301 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1304 u8 hor_start, hor_end, vert_start, vert_end;
1306 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1307 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1309 val = FLD_VAL(vaccu, vert_start, vert_end) |
1310 FLD_VAL(haccu, hor_start, hor_end);
1312 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1315 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1318 u8 hor_start, hor_end, vert_start, vert_end;
1320 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1321 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1323 val = FLD_VAL(vaccu, vert_start, vert_end) |
1324 FLD_VAL(haccu, hor_start, hor_end);
1326 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1329 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1334 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1335 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1338 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1343 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1344 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1347 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1348 u16 orig_width, u16 orig_height,
1349 u16 out_width, u16 out_height,
1350 bool five_taps, u8 rotation,
1351 enum omap_color_component color_comp)
1353 int fir_hinc, fir_vinc;
1355 fir_hinc = 1024 * orig_width / out_width;
1356 fir_vinc = 1024 * orig_height / out_height;
1358 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1360 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1363 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1364 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1365 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1367 int h_accu2_0, h_accu2_1;
1368 int v_accu2_0, v_accu2_1;
1369 int chroma_hinc, chroma_vinc;
1379 const struct accu *accu_table;
1380 const struct accu *accu_val;
1382 static const struct accu accu_nv12[4] = {
1383 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1384 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1385 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1386 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1389 static const struct accu accu_nv12_ilace[4] = {
1390 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1391 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1392 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1393 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1396 static const struct accu accu_yuv[4] = {
1397 { 0, 1, 0, 1, 0, 1, 0, 1 },
1398 { 0, 1, 0, 1, 0, 1, 0, 1 },
1399 { -1, 1, 0, 1, 0, 1, 0, 1 },
1400 { 0, 1, 0, 1, -1, 1, 0, 1 },
1404 case OMAP_DSS_ROT_0:
1407 case OMAP_DSS_ROT_90:
1410 case OMAP_DSS_ROT_180:
1413 case OMAP_DSS_ROT_270:
1421 switch (color_mode) {
1422 case OMAP_DSS_COLOR_NV12:
1424 accu_table = accu_nv12_ilace;
1426 accu_table = accu_nv12;
1428 case OMAP_DSS_COLOR_YUV2:
1429 case OMAP_DSS_COLOR_UYVY:
1430 accu_table = accu_yuv;
1437 accu_val = &accu_table[idx];
1439 chroma_hinc = 1024 * orig_width / out_width;
1440 chroma_vinc = 1024 * orig_height / out_height;
1442 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1443 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1444 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1445 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1447 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1448 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1451 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1452 u16 orig_width, u16 orig_height,
1453 u16 out_width, u16 out_height,
1454 bool ilace, bool five_taps,
1455 bool fieldmode, enum omap_color_mode color_mode,
1462 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1463 out_width, out_height, five_taps,
1464 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1465 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1467 /* RESIZEENABLE and VERTICALTAPS */
1468 l &= ~((0x3 << 5) | (0x1 << 21));
1469 l |= (orig_width != out_width) ? (1 << 5) : 0;
1470 l |= (orig_height != out_height) ? (1 << 6) : 0;
1471 l |= five_taps ? (1 << 21) : 0;
1473 /* VRESIZECONF and HRESIZECONF */
1474 if (dss_has_feature(FEAT_RESIZECONF)) {
1476 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1477 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1480 /* LINEBUFFERSPLIT */
1481 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1483 l |= five_taps ? (1 << 22) : 0;
1486 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1489 * field 0 = even field = bottom field
1490 * field 1 = odd field = top field
1492 if (ilace && !fieldmode) {
1494 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1495 if (accu0 >= 1024/2) {
1501 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1502 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1505 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1506 u16 orig_width, u16 orig_height,
1507 u16 out_width, u16 out_height,
1508 bool ilace, bool five_taps,
1509 bool fieldmode, enum omap_color_mode color_mode,
1512 int scale_x = out_width != orig_width;
1513 int scale_y = out_height != orig_height;
1514 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1516 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1518 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1519 color_mode != OMAP_DSS_COLOR_UYVY &&
1520 color_mode != OMAP_DSS_COLOR_NV12)) {
1521 /* reset chroma resampling for RGB formats */
1522 if (plane != OMAP_DSS_WB)
1523 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1527 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1528 out_height, ilace, color_mode, rotation);
1530 switch (color_mode) {
1531 case OMAP_DSS_COLOR_NV12:
1532 if (chroma_upscale) {
1533 /* UV is subsampled by 2 horizontally and vertically */
1537 /* UV is downsampled by 2 horizontally and vertically */
1543 case OMAP_DSS_COLOR_YUV2:
1544 case OMAP_DSS_COLOR_UYVY:
1545 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1546 if (rotation == OMAP_DSS_ROT_0 ||
1547 rotation == OMAP_DSS_ROT_180) {
1549 /* UV is subsampled by 2 horizontally */
1552 /* UV is downsampled by 2 horizontally */
1556 /* must use FIR for YUV422 if rotated */
1557 if (rotation != OMAP_DSS_ROT_0)
1558 scale_x = scale_y = true;
1566 if (out_width != orig_width)
1568 if (out_height != orig_height)
1571 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1572 out_width, out_height, five_taps,
1573 rotation, DISPC_COLOR_COMPONENT_UV);
1575 if (plane != OMAP_DSS_WB)
1576 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1577 (scale_x || scale_y) ? 1 : 0, 8, 8);
1580 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1582 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1585 static void dispc_ovl_set_scaling(enum omap_plane plane,
1586 u16 orig_width, u16 orig_height,
1587 u16 out_width, u16 out_height,
1588 bool ilace, bool five_taps,
1589 bool fieldmode, enum omap_color_mode color_mode,
1592 BUG_ON(plane == OMAP_DSS_GFX);
1594 dispc_ovl_set_scaling_common(plane,
1595 orig_width, orig_height,
1596 out_width, out_height,
1598 fieldmode, color_mode,
1601 dispc_ovl_set_scaling_uv(plane,
1602 orig_width, orig_height,
1603 out_width, out_height,
1605 fieldmode, color_mode,
1609 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1610 bool mirroring, enum omap_color_mode color_mode)
1612 bool row_repeat = false;
1615 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1616 color_mode == OMAP_DSS_COLOR_UYVY) {
1620 case OMAP_DSS_ROT_0:
1623 case OMAP_DSS_ROT_90:
1626 case OMAP_DSS_ROT_180:
1629 case OMAP_DSS_ROT_270:
1635 case OMAP_DSS_ROT_0:
1638 case OMAP_DSS_ROT_90:
1641 case OMAP_DSS_ROT_180:
1644 case OMAP_DSS_ROT_270:
1650 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1656 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1657 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1658 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1659 row_repeat ? 1 : 0, 18, 18);
1662 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1664 switch (color_mode) {
1665 case OMAP_DSS_COLOR_CLUT1:
1667 case OMAP_DSS_COLOR_CLUT2:
1669 case OMAP_DSS_COLOR_CLUT4:
1671 case OMAP_DSS_COLOR_CLUT8:
1672 case OMAP_DSS_COLOR_NV12:
1674 case OMAP_DSS_COLOR_RGB12U:
1675 case OMAP_DSS_COLOR_RGB16:
1676 case OMAP_DSS_COLOR_ARGB16:
1677 case OMAP_DSS_COLOR_YUV2:
1678 case OMAP_DSS_COLOR_UYVY:
1679 case OMAP_DSS_COLOR_RGBA16:
1680 case OMAP_DSS_COLOR_RGBX16:
1681 case OMAP_DSS_COLOR_ARGB16_1555:
1682 case OMAP_DSS_COLOR_XRGB16_1555:
1684 case OMAP_DSS_COLOR_RGB24P:
1686 case OMAP_DSS_COLOR_RGB24U:
1687 case OMAP_DSS_COLOR_ARGB32:
1688 case OMAP_DSS_COLOR_RGBA32:
1689 case OMAP_DSS_COLOR_RGBX32:
1697 static s32 pixinc(int pixels, u8 ps)
1701 else if (pixels > 1)
1702 return 1 + (pixels - 1) * ps;
1703 else if (pixels < 0)
1704 return 1 - (-pixels + 1) * ps;
1710 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1712 u16 width, u16 height,
1713 enum omap_color_mode color_mode, bool fieldmode,
1714 unsigned int field_offset,
1715 unsigned *offset0, unsigned *offset1,
1716 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1720 /* FIXME CLUT formats */
1721 switch (color_mode) {
1722 case OMAP_DSS_COLOR_CLUT1:
1723 case OMAP_DSS_COLOR_CLUT2:
1724 case OMAP_DSS_COLOR_CLUT4:
1725 case OMAP_DSS_COLOR_CLUT8:
1728 case OMAP_DSS_COLOR_YUV2:
1729 case OMAP_DSS_COLOR_UYVY:
1733 ps = color_mode_to_bpp(color_mode) / 8;
1737 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1741 * field 0 = even field = bottom field
1742 * field 1 = odd field = top field
1744 switch (rotation + mirror * 4) {
1745 case OMAP_DSS_ROT_0:
1746 case OMAP_DSS_ROT_180:
1748 * If the pixel format is YUV or UYVY divide the width
1749 * of the image by 2 for 0 and 180 degree rotation.
1751 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1752 color_mode == OMAP_DSS_COLOR_UYVY)
1754 case OMAP_DSS_ROT_90:
1755 case OMAP_DSS_ROT_270:
1758 *offset0 = field_offset * screen_width * ps;
1762 *row_inc = pixinc(1 +
1763 (y_predecim * screen_width - x_predecim * width) +
1764 (fieldmode ? screen_width : 0), ps);
1765 *pix_inc = pixinc(x_predecim, ps);
1768 case OMAP_DSS_ROT_0 + 4:
1769 case OMAP_DSS_ROT_180 + 4:
1770 /* If the pixel format is YUV or UYVY divide the width
1771 * of the image by 2 for 0 degree and 180 degree
1773 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1774 color_mode == OMAP_DSS_COLOR_UYVY)
1776 case OMAP_DSS_ROT_90 + 4:
1777 case OMAP_DSS_ROT_270 + 4:
1780 *offset0 = field_offset * screen_width * ps;
1783 *row_inc = pixinc(1 -
1784 (y_predecim * screen_width + x_predecim * width) -
1785 (fieldmode ? screen_width : 0), ps);
1786 *pix_inc = pixinc(x_predecim, ps);
1795 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1797 u16 width, u16 height,
1798 enum omap_color_mode color_mode, bool fieldmode,
1799 unsigned int field_offset,
1800 unsigned *offset0, unsigned *offset1,
1801 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1806 /* FIXME CLUT formats */
1807 switch (color_mode) {
1808 case OMAP_DSS_COLOR_CLUT1:
1809 case OMAP_DSS_COLOR_CLUT2:
1810 case OMAP_DSS_COLOR_CLUT4:
1811 case OMAP_DSS_COLOR_CLUT8:
1815 ps = color_mode_to_bpp(color_mode) / 8;
1819 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1822 /* width & height are overlay sizes, convert to fb sizes */
1824 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1833 * field 0 = even field = bottom field
1834 * field 1 = odd field = top field
1836 switch (rotation + mirror * 4) {
1837 case OMAP_DSS_ROT_0:
1840 *offset0 = *offset1 + field_offset * screen_width * ps;
1842 *offset0 = *offset1;
1843 *row_inc = pixinc(1 +
1844 (y_predecim * screen_width - fbw * x_predecim) +
1845 (fieldmode ? screen_width : 0), ps);
1846 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1847 color_mode == OMAP_DSS_COLOR_UYVY)
1848 *pix_inc = pixinc(x_predecim, 2 * ps);
1850 *pix_inc = pixinc(x_predecim, ps);
1852 case OMAP_DSS_ROT_90:
1853 *offset1 = screen_width * (fbh - 1) * ps;
1855 *offset0 = *offset1 + field_offset * ps;
1857 *offset0 = *offset1;
1858 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1859 y_predecim + (fieldmode ? 1 : 0), ps);
1860 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1862 case OMAP_DSS_ROT_180:
1863 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1865 *offset0 = *offset1 - field_offset * screen_width * ps;
1867 *offset0 = *offset1;
1868 *row_inc = pixinc(-1 -
1869 (y_predecim * screen_width - fbw * x_predecim) -
1870 (fieldmode ? screen_width : 0), ps);
1871 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1872 color_mode == OMAP_DSS_COLOR_UYVY)
1873 *pix_inc = pixinc(-x_predecim, 2 * ps);
1875 *pix_inc = pixinc(-x_predecim, ps);
1877 case OMAP_DSS_ROT_270:
1878 *offset1 = (fbw - 1) * ps;
1880 *offset0 = *offset1 - field_offset * ps;
1882 *offset0 = *offset1;
1883 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1884 y_predecim - (fieldmode ? 1 : 0), ps);
1885 *pix_inc = pixinc(x_predecim * screen_width, ps);
1889 case OMAP_DSS_ROT_0 + 4:
1890 *offset1 = (fbw - 1) * ps;
1892 *offset0 = *offset1 + field_offset * screen_width * ps;
1894 *offset0 = *offset1;
1895 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1896 (fieldmode ? screen_width : 0),
1898 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1899 color_mode == OMAP_DSS_COLOR_UYVY)
1900 *pix_inc = pixinc(-x_predecim, 2 * ps);
1902 *pix_inc = pixinc(-x_predecim, ps);
1905 case OMAP_DSS_ROT_90 + 4:
1908 *offset0 = *offset1 + field_offset * ps;
1910 *offset0 = *offset1;
1911 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1912 y_predecim + (fieldmode ? 1 : 0),
1914 *pix_inc = pixinc(x_predecim * screen_width, ps);
1917 case OMAP_DSS_ROT_180 + 4:
1918 *offset1 = screen_width * (fbh - 1) * ps;
1920 *offset0 = *offset1 - field_offset * screen_width * ps;
1922 *offset0 = *offset1;
1923 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
1924 (fieldmode ? screen_width : 0),
1926 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1927 color_mode == OMAP_DSS_COLOR_UYVY)
1928 *pix_inc = pixinc(x_predecim, 2 * ps);
1930 *pix_inc = pixinc(x_predecim, ps);
1933 case OMAP_DSS_ROT_270 + 4:
1934 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1936 *offset0 = *offset1 - field_offset * ps;
1938 *offset0 = *offset1;
1939 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1940 y_predecim - (fieldmode ? 1 : 0),
1942 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1951 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1952 enum omap_color_mode color_mode, bool fieldmode,
1953 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1954 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1958 switch (color_mode) {
1959 case OMAP_DSS_COLOR_CLUT1:
1960 case OMAP_DSS_COLOR_CLUT2:
1961 case OMAP_DSS_COLOR_CLUT4:
1962 case OMAP_DSS_COLOR_CLUT8:
1966 ps = color_mode_to_bpp(color_mode) / 8;
1970 DSSDBG("scrw %d, width %d\n", screen_width, width);
1973 * field 0 = even field = bottom field
1974 * field 1 = odd field = top field
1978 *offset0 = *offset1 + field_offset * screen_width * ps;
1980 *offset0 = *offset1;
1981 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1982 (fieldmode ? screen_width : 0), ps);
1983 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1984 color_mode == OMAP_DSS_COLOR_UYVY)
1985 *pix_inc = pixinc(x_predecim, 2 * ps);
1987 *pix_inc = pixinc(x_predecim, ps);
1991 * This function is used to avoid synclosts in OMAP3, because of some
1992 * undocumented horizontal position and timing related limitations.
1994 static int check_horiz_timing_omap3(enum omap_plane plane,
1995 const struct omap_video_timings *t, u16 pos_x,
1996 u16 width, u16 height, u16 out_width, u16 out_height)
1998 int DS = DIV_ROUND_UP(height, out_height);
1999 unsigned long nonactive;
2000 static const u8 limits[3] = { 8, 10, 20 };
2002 unsigned long pclk = dispc_plane_pclk_rate(plane);
2003 unsigned long lclk = dispc_plane_lclk_rate(plane);
2006 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2009 if (out_height < height)
2011 if (out_width < width)
2013 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2014 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2015 if (blank <= limits[i])
2019 * Pixel data should be prepared before visible display point starts.
2020 * So, atleast DS-2 lines must have already been fetched by DISPC
2021 * during nonactive - pos_x period.
2023 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2024 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2025 val, max(0, DS - 2) * width);
2026 if (val < max(0, DS - 2) * width)
2030 * All lines need to be refilled during the nonactive period of which
2031 * only one line can be loaded during the active period. So, atleast
2032 * DS - 1 lines should be loaded during nonactive period.
2034 val = div_u64((u64)nonactive * lclk, pclk);
2035 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2036 val, max(0, DS - 1) * width);
2037 if (val < max(0, DS - 1) * width)
2043 static unsigned long calc_core_clk_five_taps(enum omap_plane plane,
2044 const struct omap_video_timings *mgr_timings, u16 width,
2045 u16 height, u16 out_width, u16 out_height,
2046 enum omap_color_mode color_mode)
2050 unsigned long pclk = dispc_plane_pclk_rate(plane);
2052 if (height <= out_height && width <= out_width)
2053 return (unsigned long) pclk;
2055 if (height > out_height) {
2056 unsigned int ppl = mgr_timings->x_res;
2058 tmp = pclk * height * out_width;
2059 do_div(tmp, 2 * out_height * ppl);
2062 if (height > 2 * out_height) {
2063 if (ppl == out_width)
2066 tmp = pclk * (height - 2 * out_height) * out_width;
2067 do_div(tmp, 2 * out_height * (ppl - out_width));
2068 core_clk = max_t(u32, core_clk, tmp);
2072 if (width > out_width) {
2074 do_div(tmp, out_width);
2075 core_clk = max_t(u32, core_clk, tmp);
2077 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2084 static unsigned long calc_core_clk_24xx(enum omap_plane plane, u16 width,
2085 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2087 unsigned long pclk = dispc_plane_pclk_rate(plane);
2089 if (height > out_height && width > out_width)
2095 static unsigned long calc_core_clk_34xx(enum omap_plane plane, u16 width,
2096 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2098 unsigned int hf, vf;
2099 unsigned long pclk = dispc_plane_pclk_rate(plane);
2102 * FIXME how to determine the 'A' factor
2103 * for the no downscaling case ?
2106 if (width > 3 * out_width)
2108 else if (width > 2 * out_width)
2110 else if (width > out_width)
2114 if (height > out_height)
2119 return pclk * vf * hf;
2122 static unsigned long calc_core_clk_44xx(enum omap_plane plane, u16 width,
2123 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2128 * If the overlay/writeback is in mem to mem mode, there are no
2129 * downscaling limitations with respect to pixel clock, return 1 as
2130 * required core clock to represent that we have sufficient enough
2131 * core clock to do maximum downscaling
2136 pclk = dispc_plane_pclk_rate(plane);
2138 if (width > out_width)
2139 return DIV_ROUND_UP(pclk, out_width) * width;
2144 static int dispc_ovl_calc_scaling_24xx(enum omap_plane plane,
2145 const struct omap_video_timings *mgr_timings,
2146 u16 width, u16 height, u16 out_width, u16 out_height,
2147 enum omap_color_mode color_mode, bool *five_taps,
2148 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2149 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2152 u16 in_width, in_height;
2153 int min_factor = min(*decim_x, *decim_y);
2154 const int maxsinglelinewidth =
2155 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2160 in_height = DIV_ROUND_UP(height, *decim_y);
2161 in_width = DIV_ROUND_UP(width, *decim_x);
2162 *core_clk = dispc.feat->calc_core_clk(plane, in_width,
2163 in_height, out_width, out_height, mem_to_mem);
2164 error = (in_width > maxsinglelinewidth || !*core_clk ||
2165 *core_clk > dispc_core_clk_rate());
2167 if (*decim_x == *decim_y) {
2168 *decim_x = min_factor;
2171 swap(*decim_x, *decim_y);
2172 if (*decim_x < *decim_y)
2176 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2178 if (in_width > maxsinglelinewidth) {
2179 DSSERR("Cannot scale max input width exceeded");
2185 static int dispc_ovl_calc_scaling_34xx(enum omap_plane plane,
2186 const struct omap_video_timings *mgr_timings,
2187 u16 width, u16 height, u16 out_width, u16 out_height,
2188 enum omap_color_mode color_mode, bool *five_taps,
2189 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2190 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2193 u16 in_width, in_height;
2194 int min_factor = min(*decim_x, *decim_y);
2195 const int maxsinglelinewidth =
2196 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2199 in_height = DIV_ROUND_UP(height, *decim_y);
2200 in_width = DIV_ROUND_UP(width, *decim_x);
2201 *core_clk = calc_core_clk_five_taps(plane, mgr_timings,
2202 in_width, in_height, out_width, out_height, color_mode);
2204 error = check_horiz_timing_omap3(plane, mgr_timings,
2205 pos_x, in_width, in_height, out_width,
2208 if (in_width > maxsinglelinewidth)
2209 if (in_height > out_height &&
2210 in_height < out_height * 2)
2213 *core_clk = dispc.feat->calc_core_clk(plane, in_width,
2214 in_height, out_width, out_height,
2217 error = (error || in_width > maxsinglelinewidth * 2 ||
2218 (in_width > maxsinglelinewidth && *five_taps) ||
2219 !*core_clk || *core_clk > dispc_core_clk_rate());
2221 if (*decim_x == *decim_y) {
2222 *decim_x = min_factor;
2225 swap(*decim_x, *decim_y);
2226 if (*decim_x < *decim_y)
2230 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2232 if (check_horiz_timing_omap3(plane, mgr_timings, pos_x, width, height,
2233 out_width, out_height)){
2234 DSSERR("horizontal timing too tight\n");
2238 if (in_width > (maxsinglelinewidth * 2)) {
2239 DSSERR("Cannot setup scaling");
2240 DSSERR("width exceeds maximum width possible");
2244 if (in_width > maxsinglelinewidth && *five_taps) {
2245 DSSERR("cannot setup scaling with five taps");
2251 static int dispc_ovl_calc_scaling_44xx(enum omap_plane plane,
2252 const struct omap_video_timings *mgr_timings,
2253 u16 width, u16 height, u16 out_width, u16 out_height,
2254 enum omap_color_mode color_mode, bool *five_taps,
2255 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2256 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2258 u16 in_width, in_width_max;
2259 int decim_x_min = *decim_x;
2260 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2261 const int maxsinglelinewidth =
2262 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2263 unsigned long pclk = dispc_plane_pclk_rate(plane);
2264 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2267 in_width_max = DIV_ROUND_UP(out_width, maxdownscale);
2269 in_width_max = dispc_core_clk_rate() /
2270 DIV_ROUND_UP(pclk, out_width);
2272 *decim_x = DIV_ROUND_UP(width, in_width_max);
2274 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2275 if (*decim_x > *x_predecim)
2279 in_width = DIV_ROUND_UP(width, *decim_x);
2280 } while (*decim_x <= *x_predecim &&
2281 in_width > maxsinglelinewidth && ++*decim_x);
2283 if (in_width > maxsinglelinewidth) {
2284 DSSERR("Cannot scale width exceeds max line width");
2288 *core_clk = dispc.feat->calc_core_clk(plane, in_width, in_height,
2289 out_width, out_height, mem_to_mem);
2293 static int dispc_ovl_calc_scaling(enum omap_plane plane,
2294 enum omap_overlay_caps caps,
2295 const struct omap_video_timings *mgr_timings,
2296 u16 width, u16 height, u16 out_width, u16 out_height,
2297 enum omap_color_mode color_mode, bool *five_taps,
2298 int *x_predecim, int *y_predecim, u16 pos_x,
2299 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2301 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2302 const int max_decim_limit = 16;
2303 unsigned long core_clk = 0;
2304 int decim_x, decim_y, ret;
2306 if (width == out_width && height == out_height)
2309 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2312 *x_predecim = max_decim_limit;
2313 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2314 dss_has_feature(FEAT_BURST_2D)) ? 2 : max_decim_limit;
2316 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2317 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2318 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2319 color_mode == OMAP_DSS_COLOR_CLUT8) {
2326 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2327 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2329 if (decim_x > *x_predecim || out_width > width * 8)
2332 if (decim_y > *y_predecim || out_height > height * 8)
2335 ret = dispc.feat->calc_scaling(plane, mgr_timings, width, height,
2336 out_width, out_height, color_mode, five_taps,
2337 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2342 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2343 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2345 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2346 DSSERR("failed to set up scaling, "
2347 "required core clk rate = %lu Hz, "
2348 "current core clk rate = %lu Hz\n",
2349 core_clk, dispc_core_clk_rate());
2353 *x_predecim = decim_x;
2354 *y_predecim = decim_y;
2358 static int dispc_ovl_setup_common(enum omap_plane plane,
2359 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2360 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2361 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2362 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2363 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2364 bool replication, const struct omap_video_timings *mgr_timings,
2367 bool five_taps = true;
2370 unsigned offset0, offset1;
2373 u16 frame_height = height;
2374 unsigned int field_offset = 0;
2375 u16 in_height = height;
2376 u16 in_width = width;
2377 int x_predecim = 1, y_predecim = 1;
2378 bool ilace = mgr_timings->interlace;
2383 out_width = out_width == 0 ? width : out_width;
2384 out_height = out_height == 0 ? height : out_height;
2386 if (ilace && height == out_height)
2395 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2396 "out_height %d\n", in_height, pos_y,
2400 if (!dss_feat_color_mode_supported(plane, color_mode))
2403 r = dispc_ovl_calc_scaling(plane, caps, mgr_timings, in_width,
2404 in_height, out_width, out_height, color_mode,
2405 &five_taps, &x_predecim, &y_predecim, pos_x,
2406 rotation_type, mem_to_mem);
2410 in_width = DIV_ROUND_UP(in_width, x_predecim);
2411 in_height = DIV_ROUND_UP(in_height, y_predecim);
2413 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2414 color_mode == OMAP_DSS_COLOR_UYVY ||
2415 color_mode == OMAP_DSS_COLOR_NV12)
2418 if (ilace && !fieldmode) {
2420 * when downscaling the bottom field may have to start several
2421 * source lines below the top field. Unfortunately ACCUI
2422 * registers will only hold the fractional part of the offset
2423 * so the integer part must be added to the base address of the
2426 if (!in_height || in_height == out_height)
2429 field_offset = in_height / out_height / 2;
2432 /* Fields are independent but interleaved in memory. */
2441 if (rotation_type == OMAP_DSS_ROT_TILER)
2442 calc_tiler_rotation_offset(screen_width, in_width,
2443 color_mode, fieldmode, field_offset,
2444 &offset0, &offset1, &row_inc, &pix_inc,
2445 x_predecim, y_predecim);
2446 else if (rotation_type == OMAP_DSS_ROT_DMA)
2447 calc_dma_rotation_offset(rotation, mirror,
2448 screen_width, in_width, frame_height,
2449 color_mode, fieldmode, field_offset,
2450 &offset0, &offset1, &row_inc, &pix_inc,
2451 x_predecim, y_predecim);
2453 calc_vrfb_rotation_offset(rotation, mirror,
2454 screen_width, in_width, frame_height,
2455 color_mode, fieldmode, field_offset,
2456 &offset0, &offset1, &row_inc, &pix_inc,
2457 x_predecim, y_predecim);
2459 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2460 offset0, offset1, row_inc, pix_inc);
2462 dispc_ovl_set_color_mode(plane, color_mode);
2464 dispc_ovl_configure_burst_type(plane, rotation_type);
2466 dispc_ovl_set_ba0(plane, paddr + offset0);
2467 dispc_ovl_set_ba1(plane, paddr + offset1);
2469 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2470 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2471 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2474 dispc_ovl_set_row_inc(plane, row_inc);
2475 dispc_ovl_set_pix_inc(plane, pix_inc);
2477 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2478 in_height, out_width, out_height);
2480 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2482 dispc_ovl_set_input_size(plane, in_width, in_height);
2484 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2485 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2486 out_height, ilace, five_taps, fieldmode,
2487 color_mode, rotation);
2488 dispc_ovl_set_output_size(plane, out_width, out_height);
2489 dispc_ovl_set_vid_color_conv(plane, cconv);
2492 dispc_ovl_set_rotation_attrs(plane, rotation, mirror, color_mode);
2494 dispc_ovl_set_zorder(plane, caps, zorder);
2495 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2496 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2498 dispc_ovl_enable_replication(plane, caps, replication);
2503 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2504 bool replication, const struct omap_video_timings *mgr_timings,
2508 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
2509 enum omap_channel channel;
2511 channel = dispc_ovl_get_channel_out(plane);
2513 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2514 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2515 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2516 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2517 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2519 r = dispc_ovl_setup_common(plane, ovl->caps, oi->paddr, oi->p_uv_addr,
2520 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2521 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2522 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2523 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2528 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2529 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2533 enum omap_plane plane = OMAP_DSS_WB;
2534 const int pos_x = 0, pos_y = 0;
2535 const u8 zorder = 0, global_alpha = 0;
2536 const bool replication = false;
2538 int in_width = mgr_timings->x_res;
2539 int in_height = mgr_timings->y_res;
2540 enum omap_overlay_caps caps =
2541 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2543 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2544 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2545 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2548 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2549 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2550 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2551 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2552 replication, mgr_timings, mem_to_mem);
2554 switch (wi->color_mode) {
2555 case OMAP_DSS_COLOR_RGB16:
2556 case OMAP_DSS_COLOR_RGB24P:
2557 case OMAP_DSS_COLOR_ARGB16:
2558 case OMAP_DSS_COLOR_RGBA16:
2559 case OMAP_DSS_COLOR_RGB12U:
2560 case OMAP_DSS_COLOR_ARGB16_1555:
2561 case OMAP_DSS_COLOR_XRGB16_1555:
2562 case OMAP_DSS_COLOR_RGBX16:
2570 /* setup extra DISPC_WB_ATTRIBUTES */
2571 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2572 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2573 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2574 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2579 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2581 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2583 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2588 static void dispc_disable_isr(void *data, u32 mask)
2590 struct completion *compl = data;
2594 static void _enable_lcd_out(enum omap_channel channel, bool enable)
2596 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2597 /* flush posted write */
2598 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2601 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
2603 struct completion frame_done_completion;
2608 /* When we disable LCD output, we need to wait until frame is done.
2609 * Otherwise the DSS is still working, and turning off the clocks
2610 * prevents DSS from going to OFF mode */
2611 is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2613 irq = mgr_desc[channel].framedone_irq;
2615 if (!enable && is_on) {
2616 init_completion(&frame_done_completion);
2618 r = omap_dispc_register_isr(dispc_disable_isr,
2619 &frame_done_completion, irq);
2622 DSSERR("failed to register FRAMEDONE isr\n");
2625 _enable_lcd_out(channel, enable);
2627 if (!enable && is_on) {
2628 if (!wait_for_completion_timeout(&frame_done_completion,
2629 msecs_to_jiffies(100)))
2630 DSSERR("timeout waiting for FRAME DONE\n");
2632 r = omap_dispc_unregister_isr(dispc_disable_isr,
2633 &frame_done_completion, irq);
2636 DSSERR("failed to unregister FRAMEDONE isr\n");
2640 static void _enable_digit_out(bool enable)
2642 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2643 /* flush posted write */
2644 dispc_read_reg(DISPC_CONTROL);
2647 static void dispc_mgr_enable_digit_out(bool enable)
2649 struct completion frame_done_completion;
2650 enum dss_hdmi_venc_clk_source_select src;
2655 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
2658 src = dss_get_hdmi_venc_clk_source();
2661 unsigned long flags;
2662 /* When we enable digit output, we'll get an extra digit
2663 * sync lost interrupt, that we need to ignore */
2664 spin_lock_irqsave(&dispc.irq_lock, flags);
2665 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2666 _omap_dispc_set_irqs();
2667 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2670 /* When we disable digit output, we need to wait until fields are done.
2671 * Otherwise the DSS is still working, and turning off the clocks
2672 * prevents DSS from going to OFF mode. And when enabling, we need to
2673 * wait for the extra sync losts */
2674 init_completion(&frame_done_completion);
2676 if (src == DSS_HDMI_M_PCLK && enable == false) {
2677 irq_mask = DISPC_IRQ_FRAMEDONETV;
2680 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2681 /* XXX I understand from TRM that we should only wait for the
2682 * current field to complete. But it seems we have to wait for
2687 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2690 DSSERR("failed to register %x isr\n", irq_mask);
2692 _enable_digit_out(enable);
2694 for (i = 0; i < num_irqs; ++i) {
2695 if (!wait_for_completion_timeout(&frame_done_completion,
2696 msecs_to_jiffies(100)))
2697 DSSERR("timeout waiting for digit out to %s\n",
2698 enable ? "start" : "stop");
2701 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2704 DSSERR("failed to unregister %x isr\n", irq_mask);
2707 unsigned long flags;
2708 spin_lock_irqsave(&dispc.irq_lock, flags);
2709 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2710 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2711 _omap_dispc_set_irqs();
2712 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2716 bool dispc_mgr_is_enabled(enum omap_channel channel)
2718 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2721 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2723 if (dss_mgr_is_lcd(channel))
2724 dispc_mgr_enable_lcd_out(channel, enable);
2725 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2726 dispc_mgr_enable_digit_out(enable);
2731 void dispc_wb_enable(bool enable)
2733 enum omap_plane plane = OMAP_DSS_WB;
2734 struct completion frame_done_completion;
2739 is_on = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2740 irq = DISPC_IRQ_FRAMEDONEWB;
2742 if (!enable && is_on) {
2743 init_completion(&frame_done_completion);
2745 r = omap_dispc_register_isr(dispc_disable_isr,
2746 &frame_done_completion, irq);
2748 DSSERR("failed to register FRAMEDONEWB isr\n");
2751 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2753 if (!enable && is_on) {
2754 if (!wait_for_completion_timeout(&frame_done_completion,
2755 msecs_to_jiffies(100)))
2756 DSSERR("timeout waiting for FRAMEDONEWB\n");
2758 r = omap_dispc_unregister_isr(dispc_disable_isr,
2759 &frame_done_completion, irq);
2761 DSSERR("failed to unregister FRAMEDONEWB isr\n");
2765 bool dispc_wb_is_enabled(void)
2767 enum omap_plane plane = OMAP_DSS_WB;
2769 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2772 void dispc_lcd_enable_signal_polarity(bool act_high)
2774 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2777 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2780 void dispc_lcd_enable_signal(bool enable)
2782 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2785 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2788 void dispc_pck_free_enable(bool enable)
2790 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2793 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2796 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2798 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2802 void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2804 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2807 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2809 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2813 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2815 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2818 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2819 enum omap_dss_trans_key_type type,
2822 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2824 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2827 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2829 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2832 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2835 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2838 if (ch == OMAP_DSS_CHANNEL_LCD)
2839 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2840 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2841 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2844 void dispc_mgr_setup(enum omap_channel channel,
2845 struct omap_overlay_manager_info *info)
2847 dispc_mgr_set_default_color(channel, info->default_color);
2848 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2849 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2850 dispc_mgr_enable_alpha_fixed_zorder(channel,
2851 info->partial_alpha_enabled);
2852 if (dss_has_feature(FEAT_CPR)) {
2853 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2854 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2858 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2862 switch (data_lines) {
2880 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2883 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2889 case DSS_IO_PAD_MODE_RESET:
2893 case DSS_IO_PAD_MODE_RFBI:
2897 case DSS_IO_PAD_MODE_BYPASS:
2906 l = dispc_read_reg(DISPC_CONTROL);
2907 l = FLD_MOD(l, gpout0, 15, 15);
2908 l = FLD_MOD(l, gpout1, 16, 16);
2909 dispc_write_reg(DISPC_CONTROL, l);
2912 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2914 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2917 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2919 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2920 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2923 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2924 int vsw, int vfp, int vbp)
2926 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2927 hfp < 1 || hfp > dispc.feat->hp_max ||
2928 hbp < 1 || hbp > dispc.feat->hp_max ||
2929 vsw < 1 || vsw > dispc.feat->sw_max ||
2930 vfp < 0 || vfp > dispc.feat->vp_max ||
2931 vbp < 0 || vbp > dispc.feat->vp_max)
2936 bool dispc_mgr_timings_ok(enum omap_channel channel,
2937 const struct omap_video_timings *timings)
2941 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2943 if (dss_mgr_is_lcd(channel))
2944 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2945 timings->hfp, timings->hbp,
2946 timings->vsw, timings->vfp,
2952 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2953 int hfp, int hbp, int vsw, int vfp, int vbp,
2954 enum omap_dss_signal_level vsync_level,
2955 enum omap_dss_signal_level hsync_level,
2956 enum omap_dss_signal_edge data_pclk_edge,
2957 enum omap_dss_signal_level de_level,
2958 enum omap_dss_signal_edge sync_pclk_edge)
2961 u32 timing_h, timing_v, l;
2962 bool onoff, rf, ipc;
2964 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2965 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2966 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2967 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2968 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2969 FLD_VAL(vbp, dispc.feat->bp_start, 20);
2971 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2972 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2974 switch (data_pclk_edge) {
2975 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2978 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2981 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2986 switch (sync_pclk_edge) {
2987 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2991 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2995 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3003 l = dispc_read_reg(DISPC_POL_FREQ(channel));
3004 l |= FLD_VAL(onoff, 17, 17);
3005 l |= FLD_VAL(rf, 16, 16);
3006 l |= FLD_VAL(de_level, 15, 15);
3007 l |= FLD_VAL(ipc, 14, 14);
3008 l |= FLD_VAL(hsync_level, 13, 13);
3009 l |= FLD_VAL(vsync_level, 12, 12);
3010 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3013 /* change name to mode? */
3014 void dispc_mgr_set_timings(enum omap_channel channel,
3015 struct omap_video_timings *timings)
3017 unsigned xtot, ytot;
3018 unsigned long ht, vt;
3019 struct omap_video_timings t = *timings;
3021 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3023 if (!dispc_mgr_timings_ok(channel, &t)) {
3028 if (dss_mgr_is_lcd(channel)) {
3029 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3030 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3031 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3033 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3034 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3036 ht = (timings->pixel_clock * 1000) / xtot;
3037 vt = (timings->pixel_clock * 1000) / xtot / ytot;
3039 DSSDBG("pck %u\n", timings->pixel_clock);
3040 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3041 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3042 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3043 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3044 t.de_level, t.sync_pclk_edge);
3046 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3048 if (t.interlace == true)
3052 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3055 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3058 BUG_ON(lck_div < 1);
3059 BUG_ON(pck_div < 1);
3061 dispc_write_reg(DISPC_DIVISORo(channel),
3062 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3065 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3069 l = dispc_read_reg(DISPC_DIVISORo(channel));
3070 *lck_div = FLD_GET(l, 23, 16);
3071 *pck_div = FLD_GET(l, 7, 0);
3074 unsigned long dispc_fclk_rate(void)
3076 struct platform_device *dsidev;
3077 unsigned long r = 0;
3079 switch (dss_get_dispc_clk_source()) {
3080 case OMAP_DSS_CLK_SRC_FCK:
3081 r = clk_get_rate(dispc.dss_clk);
3083 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3084 dsidev = dsi_get_dsidev_from_id(0);
3085 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3087 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3088 dsidev = dsi_get_dsidev_from_id(1);
3089 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3099 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3101 struct platform_device *dsidev;
3106 l = dispc_read_reg(DISPC_DIVISORo(channel));
3108 lcd = FLD_GET(l, 23, 16);
3110 switch (dss_get_lcd_clk_source(channel)) {
3111 case OMAP_DSS_CLK_SRC_FCK:
3112 r = clk_get_rate(dispc.dss_clk);
3114 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3115 dsidev = dsi_get_dsidev_from_id(0);
3116 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3118 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3119 dsidev = dsi_get_dsidev_from_id(1);
3120 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3130 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3134 if (dss_mgr_is_lcd(channel)) {
3138 l = dispc_read_reg(DISPC_DIVISORo(channel));
3140 pcd = FLD_GET(l, 7, 0);
3142 r = dispc_mgr_lclk_rate(channel);
3146 enum dss_hdmi_venc_clk_source_select source;
3148 source = dss_get_hdmi_venc_clk_source();
3151 case DSS_VENC_TV_CLK:
3152 return venc_get_pixel_clock();
3153 case DSS_HDMI_M_PCLK:
3154 return hdmi_get_pixel_clock();
3162 unsigned long dispc_core_clk_rate(void)
3165 unsigned long fclk = dispc_fclk_rate();
3167 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3168 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
3170 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
3175 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3177 enum omap_channel channel = dispc_ovl_get_channel_out(plane);
3179 return dispc_mgr_pclk_rate(channel);
3182 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3184 enum omap_channel channel = dispc_ovl_get_channel_out(plane);
3186 if (dss_mgr_is_lcd(channel))
3187 return dispc_mgr_lclk_rate(channel);
3189 return dispc_fclk_rate();
3192 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3195 enum omap_dss_clk_source lcd_clk_src;
3197 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3199 lcd_clk_src = dss_get_lcd_clk_source(channel);
3201 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3202 dss_get_generic_clk_source_name(lcd_clk_src),
3203 dss_feat_get_clk_source_name(lcd_clk_src));
3205 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3207 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3208 dispc_mgr_lclk_rate(channel), lcd);
3209 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3210 dispc_mgr_pclk_rate(channel), pcd);
3213 void dispc_dump_clocks(struct seq_file *s)
3217 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3219 if (dispc_runtime_get())
3222 seq_printf(s, "- DISPC -\n");
3224 seq_printf(s, "dispc fclk source = %s (%s)\n",
3225 dss_get_generic_clk_source_name(dispc_clk_src),
3226 dss_feat_get_clk_source_name(dispc_clk_src));
3228 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3230 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3231 seq_printf(s, "- DISPC-CORE-CLK -\n");
3232 l = dispc_read_reg(DISPC_DIVISOR);
3233 lcd = FLD_GET(l, 23, 16);
3235 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3236 (dispc_fclk_rate()/lcd), lcd);
3239 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3241 if (dss_has_feature(FEAT_MGR_LCD2))
3242 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3243 if (dss_has_feature(FEAT_MGR_LCD3))
3244 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3246 dispc_runtime_put();
3249 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3250 void dispc_dump_irqs(struct seq_file *s)
3252 unsigned long flags;
3253 struct dispc_irq_stats stats;
3255 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
3257 stats = dispc.irq_stats;
3258 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
3259 dispc.irq_stats.last_reset = jiffies;
3261 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
3263 seq_printf(s, "period %u ms\n",
3264 jiffies_to_msecs(jiffies - stats.last_reset));
3266 seq_printf(s, "irqs %d\n", stats.irq_count);
3268 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
3274 PIS(ACBIAS_COUNT_STAT);
3276 PIS(GFX_FIFO_UNDERFLOW);
3278 PIS(PAL_GAMMA_MASK);
3280 PIS(VID1_FIFO_UNDERFLOW);
3282 PIS(VID2_FIFO_UNDERFLOW);
3284 if (dss_feat_get_num_ovls() > 3) {
3285 PIS(VID3_FIFO_UNDERFLOW);
3289 PIS(SYNC_LOST_DIGIT);
3291 if (dss_has_feature(FEAT_MGR_LCD2)) {
3294 PIS(ACBIAS_COUNT_STAT2);
3297 if (dss_has_feature(FEAT_MGR_LCD3)) {
3300 PIS(ACBIAS_COUNT_STAT3);
3307 static void dispc_dump_regs(struct seq_file *s)
3310 const char *mgr_names[] = {
3311 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3312 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3313 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3314 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3316 const char *ovl_names[] = {
3317 [OMAP_DSS_GFX] = "GFX",
3318 [OMAP_DSS_VIDEO1] = "VID1",
3319 [OMAP_DSS_VIDEO2] = "VID2",
3320 [OMAP_DSS_VIDEO3] = "VID3",
3322 const char **p_names;
3324 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3326 if (dispc_runtime_get())
3329 /* DISPC common registers */
3330 DUMPREG(DISPC_REVISION);
3331 DUMPREG(DISPC_SYSCONFIG);
3332 DUMPREG(DISPC_SYSSTATUS);
3333 DUMPREG(DISPC_IRQSTATUS);
3334 DUMPREG(DISPC_IRQENABLE);
3335 DUMPREG(DISPC_CONTROL);
3336 DUMPREG(DISPC_CONFIG);
3337 DUMPREG(DISPC_CAPABLE);
3338 DUMPREG(DISPC_LINE_STATUS);
3339 DUMPREG(DISPC_LINE_NUMBER);
3340 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3341 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3342 DUMPREG(DISPC_GLOBAL_ALPHA);
3343 if (dss_has_feature(FEAT_MGR_LCD2)) {
3344 DUMPREG(DISPC_CONTROL2);
3345 DUMPREG(DISPC_CONFIG2);
3347 if (dss_has_feature(FEAT_MGR_LCD3)) {
3348 DUMPREG(DISPC_CONTROL3);
3349 DUMPREG(DISPC_CONFIG3);
3354 #define DISPC_REG(i, name) name(i)
3355 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3356 48 - strlen(#r) - strlen(p_names[i]), " ", \
3357 dispc_read_reg(DISPC_REG(i, r)))
3359 p_names = mgr_names;
3361 /* DISPC channel specific registers */
3362 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3363 DUMPREG(i, DISPC_DEFAULT_COLOR);
3364 DUMPREG(i, DISPC_TRANS_COLOR);
3365 DUMPREG(i, DISPC_SIZE_MGR);
3367 if (i == OMAP_DSS_CHANNEL_DIGIT)
3370 DUMPREG(i, DISPC_DEFAULT_COLOR);
3371 DUMPREG(i, DISPC_TRANS_COLOR);
3372 DUMPREG(i, DISPC_TIMING_H);
3373 DUMPREG(i, DISPC_TIMING_V);
3374 DUMPREG(i, DISPC_POL_FREQ);
3375 DUMPREG(i, DISPC_DIVISORo);
3376 DUMPREG(i, DISPC_SIZE_MGR);
3378 DUMPREG(i, DISPC_DATA_CYCLE1);
3379 DUMPREG(i, DISPC_DATA_CYCLE2);
3380 DUMPREG(i, DISPC_DATA_CYCLE3);
3382 if (dss_has_feature(FEAT_CPR)) {
3383 DUMPREG(i, DISPC_CPR_COEF_R);
3384 DUMPREG(i, DISPC_CPR_COEF_G);
3385 DUMPREG(i, DISPC_CPR_COEF_B);
3389 p_names = ovl_names;
3391 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3392 DUMPREG(i, DISPC_OVL_BA0);
3393 DUMPREG(i, DISPC_OVL_BA1);
3394 DUMPREG(i, DISPC_OVL_POSITION);
3395 DUMPREG(i, DISPC_OVL_SIZE);
3396 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3397 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3398 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3399 DUMPREG(i, DISPC_OVL_ROW_INC);
3400 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3401 if (dss_has_feature(FEAT_PRELOAD))
3402 DUMPREG(i, DISPC_OVL_PRELOAD);
3404 if (i == OMAP_DSS_GFX) {
3405 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3406 DUMPREG(i, DISPC_OVL_TABLE_BA);
3410 DUMPREG(i, DISPC_OVL_FIR);
3411 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3412 DUMPREG(i, DISPC_OVL_ACCU0);
3413 DUMPREG(i, DISPC_OVL_ACCU1);
3414 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3415 DUMPREG(i, DISPC_OVL_BA0_UV);
3416 DUMPREG(i, DISPC_OVL_BA1_UV);
3417 DUMPREG(i, DISPC_OVL_FIR2);
3418 DUMPREG(i, DISPC_OVL_ACCU2_0);
3419 DUMPREG(i, DISPC_OVL_ACCU2_1);
3421 if (dss_has_feature(FEAT_ATTR2))
3422 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3423 if (dss_has_feature(FEAT_PRELOAD))
3424 DUMPREG(i, DISPC_OVL_PRELOAD);
3430 #define DISPC_REG(plane, name, i) name(plane, i)
3431 #define DUMPREG(plane, name, i) \
3432 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3433 46 - strlen(#name) - strlen(p_names[plane]), " ", \
3434 dispc_read_reg(DISPC_REG(plane, name, i)))
3436 /* Video pipeline coefficient registers */
3438 /* start from OMAP_DSS_VIDEO1 */
3439 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3440 for (j = 0; j < 8; j++)
3441 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3443 for (j = 0; j < 8; j++)
3444 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3446 for (j = 0; j < 5; j++)
3447 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3449 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3450 for (j = 0; j < 8; j++)
3451 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3454 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3455 for (j = 0; j < 8; j++)
3456 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3458 for (j = 0; j < 8; j++)
3459 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3461 for (j = 0; j < 8; j++)
3462 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3466 dispc_runtime_put();
3472 /* with fck as input clock rate, find dispc dividers that produce req_pck */
3473 void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
3474 struct dispc_clock_info *cinfo)
3476 u16 pcd_min, pcd_max;
3477 unsigned long best_pck;
3478 u16 best_ld, cur_ld;
3479 u16 best_pd, cur_pd;
3481 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3482 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3488 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3489 unsigned long lck = fck / cur_ld;
3491 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
3492 unsigned long pck = lck / cur_pd;
3493 long old_delta = abs(best_pck - req_pck);
3494 long new_delta = abs(pck - req_pck);
3496 if (best_pck == 0 || new_delta < old_delta) {
3509 if (lck / pcd_min < req_pck)
3514 cinfo->lck_div = best_ld;
3515 cinfo->pck_div = best_pd;
3516 cinfo->lck = fck / cinfo->lck_div;
3517 cinfo->pck = cinfo->lck / cinfo->pck_div;
3520 /* calculate clock rates using dividers in cinfo */
3521 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3522 struct dispc_clock_info *cinfo)
3524 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3526 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3529 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3530 cinfo->pck = cinfo->lck / cinfo->pck_div;
3535 void dispc_mgr_set_clock_div(enum omap_channel channel,
3536 struct dispc_clock_info *cinfo)
3538 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3539 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3541 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3544 int dispc_mgr_get_clock_div(enum omap_channel channel,
3545 struct dispc_clock_info *cinfo)
3549 fck = dispc_fclk_rate();
3551 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3552 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3554 cinfo->lck = fck / cinfo->lck_div;
3555 cinfo->pck = cinfo->lck / cinfo->pck_div;
3560 /* dispc.irq_lock has to be locked by the caller */
3561 static void _omap_dispc_set_irqs(void)
3566 struct omap_dispc_isr_data *isr_data;
3568 mask = dispc.irq_error_mask;
3570 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3571 isr_data = &dispc.registered_isr[i];
3573 if (isr_data->isr == NULL)
3576 mask |= isr_data->mask;
3579 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3580 /* clear the irqstatus for newly enabled irqs */
3581 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3583 dispc_write_reg(DISPC_IRQENABLE, mask);
3586 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3590 unsigned long flags;
3591 struct omap_dispc_isr_data *isr_data;
3596 spin_lock_irqsave(&dispc.irq_lock, flags);
3598 /* check for duplicate entry */
3599 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3600 isr_data = &dispc.registered_isr[i];
3601 if (isr_data->isr == isr && isr_data->arg == arg &&
3602 isr_data->mask == mask) {
3611 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3612 isr_data = &dispc.registered_isr[i];
3614 if (isr_data->isr != NULL)
3617 isr_data->isr = isr;
3618 isr_data->arg = arg;
3619 isr_data->mask = mask;
3628 _omap_dispc_set_irqs();
3630 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3634 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3638 EXPORT_SYMBOL(omap_dispc_register_isr);
3640 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3643 unsigned long flags;
3645 struct omap_dispc_isr_data *isr_data;
3647 spin_lock_irqsave(&dispc.irq_lock, flags);
3649 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3650 isr_data = &dispc.registered_isr[i];
3651 if (isr_data->isr != isr || isr_data->arg != arg ||
3652 isr_data->mask != mask)
3655 /* found the correct isr */
3657 isr_data->isr = NULL;
3658 isr_data->arg = NULL;
3666 _omap_dispc_set_irqs();
3668 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3672 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3675 static void print_irq_status(u32 status)
3677 if ((status & dispc.irq_error_mask) == 0)
3680 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3683 if (status & DISPC_IRQ_##x) \
3685 PIS(GFX_FIFO_UNDERFLOW);
3687 PIS(VID1_FIFO_UNDERFLOW);
3688 PIS(VID2_FIFO_UNDERFLOW);
3689 if (dss_feat_get_num_ovls() > 3)
3690 PIS(VID3_FIFO_UNDERFLOW);
3692 PIS(SYNC_LOST_DIGIT);
3693 if (dss_has_feature(FEAT_MGR_LCD2))
3695 if (dss_has_feature(FEAT_MGR_LCD3))
3703 /* Called from dss.c. Note that we don't touch clocks here,
3704 * but we presume they are on because we got an IRQ. However,
3705 * an irq handler may turn the clocks off, so we may not have
3706 * clock later in the function. */
3707 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3710 u32 irqstatus, irqenable;
3711 u32 handledirqs = 0;
3712 u32 unhandled_errors;
3713 struct omap_dispc_isr_data *isr_data;
3714 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3716 spin_lock(&dispc.irq_lock);
3718 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3719 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3721 /* IRQ is not for us */
3722 if (!(irqstatus & irqenable)) {
3723 spin_unlock(&dispc.irq_lock);
3727 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3728 spin_lock(&dispc.irq_stats_lock);
3729 dispc.irq_stats.irq_count++;
3730 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3731 spin_unlock(&dispc.irq_stats_lock);
3736 print_irq_status(irqstatus);
3738 /* Ack the interrupt. Do it here before clocks are possibly turned
3740 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3741 /* flush posted write */
3742 dispc_read_reg(DISPC_IRQSTATUS);
3744 /* make a copy and unlock, so that isrs can unregister
3746 memcpy(registered_isr, dispc.registered_isr,
3747 sizeof(registered_isr));
3749 spin_unlock(&dispc.irq_lock);
3751 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3752 isr_data = ®istered_isr[i];
3757 if (isr_data->mask & irqstatus) {
3758 isr_data->isr(isr_data->arg, irqstatus);
3759 handledirqs |= isr_data->mask;
3763 spin_lock(&dispc.irq_lock);
3765 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3767 if (unhandled_errors) {
3768 dispc.error_irqs |= unhandled_errors;
3770 dispc.irq_error_mask &= ~unhandled_errors;
3771 _omap_dispc_set_irqs();
3773 schedule_work(&dispc.error_work);
3776 spin_unlock(&dispc.irq_lock);
3781 static void dispc_error_worker(struct work_struct *work)
3785 unsigned long flags;
3786 static const unsigned fifo_underflow_bits[] = {
3787 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3788 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3789 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3790 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3793 spin_lock_irqsave(&dispc.irq_lock, flags);
3794 errors = dispc.error_irqs;
3795 dispc.error_irqs = 0;
3796 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3798 dispc_runtime_get();
3800 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3801 struct omap_overlay *ovl;
3804 ovl = omap_dss_get_overlay(i);
3805 bit = fifo_underflow_bits[i];
3808 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3810 dispc_ovl_enable(ovl->id, false);
3811 dispc_mgr_go(ovl->manager->id);
3816 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3817 struct omap_overlay_manager *mgr;
3820 mgr = omap_dss_get_overlay_manager(i);
3821 bit = mgr_desc[i].sync_lost_irq;
3824 struct omap_dss_device *dssdev = mgr->get_device(mgr);
3827 DSSERR("SYNC_LOST on channel %s, restarting the output "
3828 "with video overlays disabled\n",
3831 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3832 dssdev->driver->disable(dssdev);
3834 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3835 struct omap_overlay *ovl;
3836 ovl = omap_dss_get_overlay(i);
3838 if (ovl->id != OMAP_DSS_GFX &&
3839 ovl->manager == mgr)
3840 dispc_ovl_enable(ovl->id, false);
3843 dispc_mgr_go(mgr->id);
3847 dssdev->driver->enable(dssdev);
3851 if (errors & DISPC_IRQ_OCP_ERR) {
3852 DSSERR("OCP_ERR\n");
3853 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3854 struct omap_overlay_manager *mgr;
3855 struct omap_dss_device *dssdev;
3857 mgr = omap_dss_get_overlay_manager(i);
3858 dssdev = mgr->get_device(mgr);
3860 if (dssdev && dssdev->driver)
3861 dssdev->driver->disable(dssdev);
3865 spin_lock_irqsave(&dispc.irq_lock, flags);
3866 dispc.irq_error_mask |= errors;
3867 _omap_dispc_set_irqs();
3868 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3870 dispc_runtime_put();
3873 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3875 void dispc_irq_wait_handler(void *data, u32 mask)
3877 complete((struct completion *)data);
3881 DECLARE_COMPLETION_ONSTACK(completion);
3883 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3889 timeout = wait_for_completion_timeout(&completion, timeout);
3891 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3896 if (timeout == -ERESTARTSYS)
3897 return -ERESTARTSYS;
3902 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3903 unsigned long timeout)
3905 void dispc_irq_wait_handler(void *data, u32 mask)
3907 complete((struct completion *)data);
3911 DECLARE_COMPLETION_ONSTACK(completion);
3913 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3919 timeout = wait_for_completion_interruptible_timeout(&completion,
3922 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3927 if (timeout == -ERESTARTSYS)
3928 return -ERESTARTSYS;
3933 static void _omap_dispc_initialize_irq(void)
3935 unsigned long flags;
3937 spin_lock_irqsave(&dispc.irq_lock, flags);
3939 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3941 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3942 if (dss_has_feature(FEAT_MGR_LCD2))
3943 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3944 if (dss_has_feature(FEAT_MGR_LCD3))
3945 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
3946 if (dss_feat_get_num_ovls() > 3)
3947 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3949 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3951 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3953 _omap_dispc_set_irqs();
3955 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3958 void dispc_enable_sidle(void)
3960 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3963 void dispc_disable_sidle(void)
3965 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3968 static void _omap_dispc_initial_config(void)
3972 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3973 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3974 l = dispc_read_reg(DISPC_DIVISOR);
3975 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3976 l = FLD_MOD(l, 1, 0, 0);
3977 l = FLD_MOD(l, 1, 23, 16);
3978 dispc_write_reg(DISPC_DIVISOR, l);
3982 if (dss_has_feature(FEAT_FUNCGATED))
3983 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3985 dispc_setup_color_conv_coef();
3987 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3991 dispc_configure_burst_sizes();
3993 dispc_ovl_enable_zorder_planes();
3996 static const struct dispc_features omap24xx_dispc_feats __initconst = {
4003 .calc_scaling = dispc_ovl_calc_scaling_24xx,
4004 .calc_core_clk = calc_core_clk_24xx,
4008 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
4015 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4016 .calc_core_clk = calc_core_clk_34xx,
4020 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
4027 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4028 .calc_core_clk = calc_core_clk_34xx,
4032 static const struct dispc_features omap44xx_dispc_feats __initconst = {
4039 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4040 .calc_core_clk = calc_core_clk_44xx,
4042 .gfx_fifo_workaround = true,
4045 static int __init dispc_init_features(struct device *dev)
4047 const struct dispc_features *src;
4048 struct dispc_features *dst;
4050 dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
4052 dev_err(dev, "Failed to allocate DISPC Features\n");
4056 if (cpu_is_omap24xx()) {
4057 src = &omap24xx_dispc_feats;
4058 } else if (cpu_is_omap34xx()) {
4059 if (omap_rev() < OMAP3430_REV_ES3_0)
4060 src = &omap34xx_rev1_0_dispc_feats;
4062 src = &omap34xx_rev3_0_dispc_feats;
4063 } else if (cpu_is_omap44xx()) {
4064 src = &omap44xx_dispc_feats;
4065 } else if (soc_is_omap54xx()) {
4066 src = &omap44xx_dispc_feats;
4071 memcpy(dst, src, sizeof(*dst));
4077 /* DISPC HW IP initialisation */
4078 static int __init omap_dispchw_probe(struct platform_device *pdev)
4082 struct resource *dispc_mem;
4087 r = dispc_init_features(&dispc.pdev->dev);
4091 spin_lock_init(&dispc.irq_lock);
4093 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4094 spin_lock_init(&dispc.irq_stats_lock);
4095 dispc.irq_stats.last_reset = jiffies;
4098 INIT_WORK(&dispc.error_work, dispc_error_worker);
4100 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4102 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4106 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4107 resource_size(dispc_mem));
4109 DSSERR("can't ioremap DISPC\n");
4113 dispc.irq = platform_get_irq(dispc.pdev, 0);
4114 if (dispc.irq < 0) {
4115 DSSERR("platform_get_irq failed\n");
4119 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
4120 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
4122 DSSERR("request_irq failed\n");
4126 clk = clk_get(&pdev->dev, "fck");
4128 DSSERR("can't get fck\n");
4133 dispc.dss_clk = clk;
4135 pm_runtime_enable(&pdev->dev);
4137 r = dispc_runtime_get();
4139 goto err_runtime_get;
4141 _omap_dispc_initial_config();
4143 _omap_dispc_initialize_irq();
4145 rev = dispc_read_reg(DISPC_REVISION);
4146 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4147 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4149 dispc_runtime_put();
4151 dss_debugfs_create_file("dispc", dispc_dump_regs);
4153 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4154 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
4159 pm_runtime_disable(&pdev->dev);
4160 clk_put(dispc.dss_clk);
4164 static int __exit omap_dispchw_remove(struct platform_device *pdev)
4166 pm_runtime_disable(&pdev->dev);
4168 clk_put(dispc.dss_clk);
4173 static int dispc_runtime_suspend(struct device *dev)
4175 dispc_save_context();
4180 static int dispc_runtime_resume(struct device *dev)
4182 dispc_restore_context();
4187 static const struct dev_pm_ops dispc_pm_ops = {
4188 .runtime_suspend = dispc_runtime_suspend,
4189 .runtime_resume = dispc_runtime_resume,
4192 static struct platform_driver omap_dispchw_driver = {
4193 .remove = __exit_p(omap_dispchw_remove),
4195 .name = "omapdss_dispc",
4196 .owner = THIS_MODULE,
4197 .pm = &dispc_pm_ops,
4201 int __init dispc_init_platform_driver(void)
4203 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
4206 void __exit dispc_uninit_platform_driver(void)
4208 platform_driver_unregister(&omap_dispchw_driver);