drivers/video/s5p_mipi_dsi.c

   1 /* linux/drivers/video/s5p_mipi_dsi.c
   2  *
   3  * Samsung SoC MIPI-DSIM driver.
   4  *
   5  * Copyright (c) 2011 Samsung Electronics
   6  *
   7  * InKi Dae, <inki.dae@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/errno.h>
  17 #include <linux/clk.h>
  18 #include <linux/mutex.h>
  19 #include <linux/wait.h>
  20 #include <linux/fs.h>
  21 #include <linux/mm.h>
  22 #include <linux/fb.h>
  23 #include <linux/ctype.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/memory.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/kthread.h>
  31 #include <linux/regulator/consumer.h>
  32 #include <linux/notifier.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include <linux/gpio.h>
  36
  37 #include <video/mipi_display.h>
  38
  39 #include <plat/fb.h>
  40 #include <plat/regs-mipidsim.h>
  41 #include <plat/dsim.h>
  42
  43 #include <mach/map.h>
  44
  45 #include "s5p_mipi_dsi_lowlevel.h"
  46 #include "s5p_mipi_dsi.h"
  47
  48 #ifdef CONFIG_HAS_EARLYSUSPEND
  49 #include <linux/earlysuspend.h>
  50 #endif
  51
  52 static unsigned int dpll_table[15] = {
  53         100, 120, 170, 220, 270,
  54         320, 390, 450, 510, 560,
  55         640, 690, 770, 870, 950 };
  56
  57 int s5p_mipi_dsi_wait_int_status(struct mipi_dsim_device *dsim,
  58                                                         unsigned int intSrc)
  59 {
  60         while (1) {
  61                 if ((s5p_mipi_dsi_get_int_status(dsim) & intSrc)) {
  62                         s5p_mipi_dsi_clear_int_status(dsim, intSrc);
  63                         return 1;
  64                 } else if ((s5p_mipi_dsi_get_FIFOCTRL_status(dsim)
  65                                                         & 0xf00000) == 0)
  66                         return 0;
  67         }
  68 }
  69
  70 static int s5p_mipi_dsi_fb_notifier_callback(struct notifier_block *self,
  71         unsigned long event, void *data)
  72 {
  73         struct mipi_dsim_device *dsim;
  74
  75         if (event != FB_EVENT_RESUME)
  76                 return 0;
  77
  78         dsim = container_of(self, struct mipi_dsim_device, fb_notif);
  79         s5p_mipi_dsi_func_reset(dsim);
  80
  81         return 0;
  82 }
  83
  84 static int s5p_mipi_dsi_register_fb(struct mipi_dsim_device *dsim)
  85 {
  86         memset(&dsim->fb_notif, 0, sizeof(dsim->fb_notif));
  87         dsim->fb_notif.notifier_call = s5p_mipi_dsi_fb_notifier_callback;
  88
  89         return fb_register_client(&dsim->fb_notif);
  90 }
  91
  92 static void s5p_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
  93                                         unsigned int data0, unsigned int data1)
  94 {
  95         unsigned int data_cnt = 0, payload = 0;
  96
  97         /* in case that data count is more then 4 */
  98         for (data_cnt = 0; data_cnt < data1; data_cnt += 4) {
  99                 /*
 100                  * after sending 4bytes per one time,
 101                  * send remainder data less then 4.
 102                  */
 103                 if ((data1 - data_cnt) < 4) {
 104                         if ((data1 - data_cnt) == 3) {
 105                                 payload = *(u8 *)(data0 + data_cnt) |
 106                                     (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
 107                                         (*(u8 *)(data0 + (data_cnt + 2))) << 16;
 108                         dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",
 109                                 payload, *(u8 *)(data0 + data_cnt),
 110                                 *(u8 *)(data0 + (data_cnt + 1)),
 111                                 *(u8 *)(data0 + (data_cnt + 2)));
 112                         } else if ((data1 - data_cnt) == 2) {
 113                                 payload = *(u8 *)(data0 + data_cnt) |
 114                                         (*(u8 *)(data0 + (data_cnt + 1))) << 8;
 115                         dev_dbg(dsim->dev,
 116                                 "count = 2 payload = %x, %x %x\n", payload,
 117                                 *(u8 *)(data0 + data_cnt),
 118                                 *(u8 *)(data0 + (data_cnt + 1)));
 119                         } else if ((data1 - data_cnt) == 1) {
 120                                 payload = *(u8 *)(data0 + data_cnt);
 121                         }
 122
 123                         s5p_mipi_dsi_wr_tx_data(dsim, payload);
 124                 /* send 4bytes per one time. */
 125                 } else {
 126                         payload = *(u8 *)(data0 + data_cnt) |
 127                                 (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
 128                                 (*(u8 *)(data0 + (data_cnt + 2))) << 16 |
 129                                 (*(u8 *)(data0 + (data_cnt + 3))) << 24;
 130
 131                         dev_dbg(dsim->dev,
 132                                 "count = 4 payload = %x, %x %x %x %x\n",
 133                                 payload, *(u8 *)(data0 + data_cnt),
 134                                 *(u8 *)(data0 + (data_cnt + 1)),
 135                                 *(u8 *)(data0 + (data_cnt + 2)),
 136                                 *(u8 *)(data0 + (data_cnt + 3)));
 137
 138                         s5p_mipi_dsi_wr_tx_data(dsim, payload);
 139                 }
 140         }
 141 }
 142
 143 int s5p_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
 144         unsigned int data0, unsigned int data1)
 145 {
 146         unsigned long delay_val, udelay;
 147         unsigned int check_rx_ack = 0;
 148
 149         if (dsim->state == DSIM_STATE_ULPS) {
 150                 dev_err(dsim->dev, "state is ULPS.\n");
 151
 152                 return -EINVAL;
 153         }
 154
 155         delay_val = MHZ / dsim->dsim_config->esc_clk;
 156         udelay = 10 * delay_val;
 157
 158         mdelay(udelay);
 159
 160         switch (data_id) {
 161         /* short packet types of packet types for command. */
 162         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 163         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 164         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 165         case MIPI_DSI_DCS_SHORT_WRITE:
 166         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 167         case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
 168                 s5p_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
 169                 if (check_rx_ack)
 170                         /* process response func should be implemented */
 171                         return 0;
 172                 else
 173                         return -EINVAL;
 174
 175         /* general command */
 176         case MIPI_DSI_COLOR_MODE_OFF:
 177         case MIPI_DSI_COLOR_MODE_ON:
 178         case MIPI_DSI_SHUTDOWN_PERIPHERAL:
 179         case MIPI_DSI_TURN_ON_PERIPHERAL:
 180                 s5p_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
 181                 if (check_rx_ack)
 182                         /* process response func should be implemented. */
 183                         return 0;
 184                 else
 185                         return -EINVAL;
 186
 187         /* packet types for video data */
 188         case MIPI_DSI_V_SYNC_START:
 189         case MIPI_DSI_V_SYNC_END:
 190         case MIPI_DSI_H_SYNC_START:
 191         case MIPI_DSI_H_SYNC_END:
 192         case MIPI_DSI_END_OF_TRANSMISSION:
 193                 return 0;
 194
 195         /* short and response packet types for command */
 196         case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
 197         case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
 198         case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
 199         case MIPI_DSI_DCS_READ:
 200                 s5p_mipi_dsi_clear_all_interrupt(dsim);
 201                 s5p_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
 202                 /* process response func should be implemented. */
 203                 return 0;
 204
 205         /* long packet type and null packet */
 206         case MIPI_DSI_NULL_PACKET:
 207         case MIPI_DSI_BLANKING_PACKET:
 208                 return 0;
 209         case MIPI_DSI_GENERIC_LONG_WRITE:
 210         case MIPI_DSI_DCS_LONG_WRITE:
 211         {
 212                 unsigned int size, data_cnt = 0, payload = 0;
 213
 214                 size = data1 * 4;
 215
 216                 /* if data count is less then 4, then send 3bytes data.  */
 217                 if (data1 < 4) {
 218                         payload = *(u8 *)(data0) |
 219                                 *(u8 *)(data0 + 1) << 8 |
 220                                 *(u8 *)(data0 + 2) << 16;
 221
 222                         s5p_mipi_dsi_wr_tx_data(dsim, payload);
 223
 224                         dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",
 225                                 data1, payload,
 226                                 *(u8 *)(data0 + data_cnt),
 227                                 *(u8 *)(data0 + (data_cnt + 1)),
 228                                 *(u8 *)(data0 + (data_cnt + 2)));
 229                 /* in case that data count is more then 4 */
 230                 } else
 231                         s5p_mipi_dsi_long_data_wr(dsim, data0, data1);
 232
 233                 /* put data into header fifo */
 234                 s5p_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff,
 235                         (data1 & 0xff00) >> 8);
 236         }
 237         if (s5p_mipi_dsi_wait_int_status(dsim, INTSRC_SFR_FIFO_EMPTY) == 0)
 238                 return -1;
 239
 240         if (check_rx_ack)
 241                 /* process response func should be implemented. */
 242                 return 0;
 243         else
 244                 return -EINVAL;
 245
 246         /* packet typo for video data */
 247         case MIPI_DSI_PACKED_PIXEL_STREAM_16:
 248         case MIPI_DSI_PACKED_PIXEL_STREAM_18:
 249         case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
 250         case MIPI_DSI_PACKED_PIXEL_STREAM_24:
 251                 if (check_rx_ack)
 252                         /* process response func should be implemented. */
 253                         return 0;
 254                 else
 255                         return -EINVAL;
 256         default:
 257                 dev_warn(dsim->dev,
 258                         "data id %x is not supported current DSI spec.\n",
 259                         data_id);
 260
 261                 return -EINVAL;
 262         }
 263
 264         return 0;
 265 }
 266
 267 int s5p_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable)
 268 {
 269         int sw_timeout;
 270
 271         if (enable) {
 272                 sw_timeout = 1000;
 273
 274                 s5p_mipi_dsi_clear_interrupt(dsim, INTSRC_PLL_STABLE);
 275                 s5p_mipi_dsi_enable_pll(dsim, 1);
 276                 while (1) {
 277                         sw_timeout--;
 278                         if (s5p_mipi_dsi_is_pll_stable(dsim))
 279                                 return 0;
 280                         if (sw_timeout == 0)
 281                                 return -EINVAL;
 282                 }
 283         } else
 284                 s5p_mipi_dsi_enable_pll(dsim, 0);
 285
 286         return 0;
 287 }
 288
 289 unsigned long s5p_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
 290         unsigned int pre_divider, unsigned int main_divider,
 291         unsigned int scaler)
 292 {
 293         unsigned long dfin_pll, dfvco, dpll_out;
 294         unsigned int i, freq_band = 0xf;
 295
 296         dfin_pll = (FIN_HZ / pre_divider);
 297
 298         if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
 299                 dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n");
 300                 s5p_mipi_dsi_enable_afc(dsim, 0, 0);
 301         } else {
 302                 if (dfin_pll < 7 * MHZ)
 303                         s5p_mipi_dsi_enable_afc(dsim, 1, 0x1);
 304                 else if (dfin_pll < 8 * MHZ)
 305                         s5p_mipi_dsi_enable_afc(dsim, 1, 0x0);
 306                 else if (dfin_pll < 9 * MHZ)
 307                         s5p_mipi_dsi_enable_afc(dsim, 1, 0x3);
 308                 else if (dfin_pll < 10 * MHZ)
 309                         s5p_mipi_dsi_enable_afc(dsim, 1, 0x2);
 310                 else if (dfin_pll < 11 * MHZ)
 311                         s5p_mipi_dsi_enable_afc(dsim, 1, 0x5);
 312                 else
 313                         s5p_mipi_dsi_enable_afc(dsim, 1, 0x4);
 314         }
 315
 316         dfvco = dfin_pll * main_divider;
 317         dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
 318                                 dfvco, dfin_pll, main_divider);
 319         if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
 320                 dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n");
 321
 322         dpll_out = dfvco / (1 << scaler);
 323         dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
 324                 dpll_out, dfvco, scaler);
 325
 326         for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
 327                 if (dpll_out < dpll_table[i] * MHZ) {
 328                         freq_band = i;
 329                         break;
 330                 }
 331         }
 332
 333         dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
 334
 335         s5p_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
 336
 337         s5p_mipi_dsi_hs_zero_ctrl(dsim, 0);
 338         s5p_mipi_dsi_prep_ctrl(dsim, 0);
 339
 340         /* Freq Band */
 341         s5p_mipi_dsi_pll_freq_band(dsim, freq_band);
 342
 343         /* Stable time */
 344         s5p_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time);
 345
 346         /* Enable PLL */
 347         dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",
 348                 (dpll_out / MHZ));
 349
 350         return dpll_out;
 351 }
 352
 353 int s5p_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
 354         unsigned int byte_clk_sel, unsigned int enable)
 355 {
 356         unsigned int esc_div;
 357         unsigned long esc_clk_error_rate;
 358
 359         if (enable) {
 360                 dsim->e_clk_src = byte_clk_sel;
 361
 362                 /* Escape mode clock and byte clock source */
 363                 s5p_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
 364
 365                 /* DPHY, DSIM Link : D-PHY clock out */
 366                 if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
 367                         dsim->hs_clk = s5p_mipi_dsi_change_pll(dsim,
 368                                 dsim->dsim_config->p, dsim->dsim_config->m,
 369                                 dsim->dsim_config->s);
 370                         if (dsim->hs_clk == 0) {
 371                                 dev_err(dsim->dev,
 372                                         "failed to get hs clock.\n");
 373                                 return -EINVAL;
 374                         }
 375
 376                         dsim->byte_clk = dsim->hs_clk / 8;
 377                         s5p_mipi_dsi_enable_pll_bypass(dsim, 0);
 378                         s5p_mipi_dsi_pll_on(dsim, 1);
 379                 /* DPHY : D-PHY clock out, DSIM link : external clock out */
 380                 } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)
 381                         dev_warn(dsim->dev,
 382                                 "this project is not support \
 383                                 external clock source for MIPI DSIM\n");
 384                 else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)
 385                         dev_warn(dsim->dev,
 386                                 "this project is not support \
 387                                 external clock source for MIPI DSIM\n");
 388
 389                 /* escape clock divider */
 390                 esc_div = dsim->byte_clk / (dsim->dsim_config->esc_clk);
 391                 dev_dbg(dsim->dev,
 392                         "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
 393                         esc_div, dsim->byte_clk, dsim->dsim_config->esc_clk);
 394                 if ((dsim->byte_clk / esc_div) >= (20 * MHZ) ||
 395                                 (dsim->byte_clk / esc_div) >
 396                                         dsim->dsim_config->esc_clk)
 397                         esc_div += 1;
 398
 399                 dsim->escape_clk = dsim->byte_clk / esc_div;
 400                 dev_dbg(dsim->dev,
 401                         "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
 402                         dsim->escape_clk, dsim->byte_clk, esc_div);
 403
 404                 /* enable escape clock. */
 405                 s5p_mipi_dsi_enable_byte_clock(dsim, DSIM_ESCCLK_ON);
 406
 407                 /* enable byte clk and escape clock */
 408                 s5p_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
 409                 /* escape clock on lane */
 410                 s5p_mipi_dsi_enable_esc_clk_on_lane(dsim,
 411                         (DSIM_LANE_CLOCK | dsim->data_lane), 1);
 412
 413                 dev_dbg(dsim->dev, "byte clock is %luMHz\n",
 414                         (dsim->byte_clk / MHZ));
 415                 dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",
 416                         (dsim->dsim_config->esc_clk / MHZ));
 417                 dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
 418                 dev_dbg(dsim->dev, "escape clock is %luMHz\n",
 419                         ((dsim->byte_clk / esc_div) / MHZ));
 420
 421                 if ((dsim->byte_clk / esc_div) > dsim->escape_clk) {
 422                         esc_clk_error_rate = dsim->escape_clk /
 423                                 (dsim->byte_clk / esc_div);
 424                         dev_warn(dsim->dev, "error rate is %lu over.\n",
 425                                 (esc_clk_error_rate / 100));
 426                 } else if ((dsim->byte_clk / esc_div) < (dsim->escape_clk)) {
 427                         esc_clk_error_rate = (dsim->byte_clk / esc_div) /
 428                                 dsim->escape_clk;
 429                         dev_warn(dsim->dev, "error rate is %lu under.\n",
 430                                 (esc_clk_error_rate / 100));
 431                 }
 432         } else {
 433                 s5p_mipi_dsi_enable_esc_clk_on_lane(dsim,
 434                         (DSIM_LANE_CLOCK | dsim->data_lane), 0);
 435                 s5p_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
 436
 437                 /* disable escape clock. */
 438                 s5p_mipi_dsi_enable_byte_clock(dsim, DSIM_ESCCLK_OFF);
 439
 440                 if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
 441                         s5p_mipi_dsi_pll_on(dsim, 0);
 442         }
 443
 444         return 0;
 445 }
 446
 447 void s5p_mipi_dsi_d_phy_onoff(struct mipi_dsim_device *dsim,
 448         unsigned int enable)
 449 {
 450         if (dsim->pd->init_d_phy)
 451                 dsim->pd->init_d_phy(dsim, enable);
 452 }
 453
 454 int s5p_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
 455 {
 456         s5p_mipi_dsi_d_phy_onoff(dsim, 1);
 457
 458         dsim->state = DSIM_STATE_INIT;
 459
 460         switch (dsim->dsim_config->e_no_data_lane) {
 461         case DSIM_DATA_LANE_1:
 462                 dsim->data_lane = DSIM_LANE_DATA0;
 463                 break;
 464         case DSIM_DATA_LANE_2:
 465                 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
 466                 break;
 467         case DSIM_DATA_LANE_3:
 468                 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
 469                         DSIM_LANE_DATA2;
 470                 break;
 471         case DSIM_DATA_LANE_4:
 472                 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
 473                         DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
 474                 break;
 475         default:
 476                 dev_info(dsim->dev, "data lane is invalid.\n");
 477                 return -EINVAL;
 478         };
 479
 480         s5p_mipi_dsi_sw_reset(dsim);
 481         s5p_mipi_dsi_dp_dn_swap(dsim, 0);
 482
 483         return 0;
 484 }
 485
 486 int s5p_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
 487         unsigned int enable)
 488 {
 489         /* enable only frame done interrupt */
 490         s5p_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
 491
 492         return 0;
 493 }
 494
 495 int s5p_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
 496         struct mipi_dsim_config *dsim_config)
 497 {
 498         struct fb_videomode *lcd_video = NULL;
 499         struct s3c_fb_pd_win *pd;
 500         unsigned int width = 0, height = 0;
 501         pd = (struct s3c_fb_pd_win *)dsim->dsim_config->lcd_panel_info;
 502         lcd_video = (struct fb_videomode *)&pd->win_mode;
 503
 504         width = dsim->pd->dsim_lcd_config->lcd_size.width;
 505         height = dsim->pd->dsim_lcd_config->lcd_size.height;
 506
 507         /* in case of VIDEO MODE (RGB INTERFACE) */
 508         if (dsim->dsim_config->e_interface == (u32) DSIM_VIDEO) {
 509                         s5p_mipi_dsi_set_main_disp_vporch(dsim,
 510                                 DSIM_CMD_LEN,
 511                                 dsim->pd->dsim_lcd_config->rgb_timing.left_margin,
 512                                 dsim->pd->dsim_lcd_config->rgb_timing.right_margin);
 513                         s5p_mipi_dsi_set_main_disp_hporch(dsim,
 514                                 dsim->pd->dsim_lcd_config->rgb_timing.upper_margin,
 515                                 dsim->pd->dsim_lcd_config->rgb_timing.lower_margin);
 516                         s5p_mipi_dsi_set_main_disp_sync_area(dsim,
 517                                 dsim->pd->dsim_lcd_config->rgb_timing.vsync_len,
 518                                 dsim->pd->dsim_lcd_config->rgb_timing.hsync_len);
 519         }
 520         s5p_mipi_dsi_set_main_disp_resol(dsim, height, width);
 521         s5p_mipi_dsi_display_config(dsim);
 522         return 0;
 523 }
 524
 525 int s5p_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
 526 {
 527         unsigned int time_out = 100;
 528         unsigned int id;
 529         id = dsim->id;
 530         switch (dsim->state) {
 531         case DSIM_STATE_INIT:
 532                 s5p_mipi_dsi_sw_reset(dsim);
 533                 s5p_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
 534
 535                 /* dsi configuration */
 536                 s5p_mipi_dsi_init_config(dsim);
 537                 s5p_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
 538                 s5p_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
 539
 540                 /* set clock configuration */
 541                 s5p_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1);
 542
 543                 mdelay(100);
 544
 545                 /* check clock and data lane state are stop state */
 546                 while (!(s5p_mipi_dsi_is_lane_state(dsim))) {
 547                         time_out--;
 548                         if (time_out == 0) {
 549                                 dev_err(dsim->dev,
 550                                         "DSI Master is not stop state.\n");
 551                                 dev_err(dsim->dev,
 552                                         "Check initialization process\n");
 553
 554                                 return -EINVAL;
 555                         }
 556                 }
 557
 558                 if (time_out != 0) {
 559                         dev_info(dsim->dev,
 560                                 "DSI Master driver has been completed.\n");
 561                         dev_info(dsim->dev, "DSI Master state is stop state\n");
 562                 }
 563
 564                 dsim->state = DSIM_STATE_STOP;
 565
 566                 /* BTA sequence counters */
 567                 s5p_mipi_dsi_set_stop_state_counter(dsim,
 568                         dsim->dsim_config->stop_holding_cnt);
 569                 s5p_mipi_dsi_set_bta_timeout(dsim,
 570                         dsim->dsim_config->bta_timeout);
 571                 s5p_mipi_dsi_set_lpdr_timeout(dsim,
 572                         dsim->dsim_config->rx_timeout);
 573
 574                 return 0;
 575         default:
 576                 dev_info(dsim->dev, "DSI Master is already init.\n");
 577                 return 0;
 578         }
 579
 580         return 0;
 581 }
 582
 583 int s5p_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
 584 {
 585         if (dsim->state == DSIM_STATE_STOP) {
 586                 if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
 587                         dsim->state = DSIM_STATE_HSCLKEN;
 588
 589                          /* set LCDC and CPU transfer mode to HS. */
 590                         s5p_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
 591                         s5p_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
 592
 593                         s5p_mipi_dsi_enable_hs_clock(dsim, 1);
 594
 595                         return 0;
 596                 } else
 597                         dev_warn(dsim->dev,
 598                                 "clock source is external bypass.\n");
 599         } else
 600                 dev_warn(dsim->dev, "DSIM is not stop state.\n");
 601
 602         return 0;
 603 }
 604
 605 int s5p_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
 606                 unsigned int mode)
 607 {
 608         if (mode) {
 609                 if (dsim->state != DSIM_STATE_HSCLKEN) {
 610                         dev_err(dsim->dev, "HS Clock lane is not enabled.\n");
 611                         return -EINVAL;
 612                 }
 613
 614                 s5p_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
 615         } else {
 616                 if (dsim->state == DSIM_STATE_INIT || dsim->state ==
 617                         DSIM_STATE_ULPS) {
 618                         dev_err(dsim->dev,
 619                                 "DSI Master is not STOP or HSDT state.\n");
 620                         return -EINVAL;
 621                 }
 622
 623                 s5p_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
 624         }
 625         return 0;
 626 }
 627
 628 int s5p_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
 629 {
 630         return _s5p_mipi_dsi_get_frame_done_status(dsim);
 631 }
 632
 633 int s5p_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
 634 {
 635         _s5p_mipi_dsi_clear_frame_done(dsim);
 636
 637         return 0;
 638 }
 639
 640 static irqreturn_t s5p_mipi_dsi_interrupt_handler(int irq, void *dev_id)
 641 {
 642         unsigned int int_src;
 643         struct mipi_dsim_device *dsim = dev_id;
 644
 645         s5p_mipi_dsi_set_interrupt_mask(dsim, 0xffffffff, 1);
 646
 647         int_src = readl(dsim->reg_base + S5P_DSIM_INTSRC);
 648         s5p_mipi_dsi_clear_interrupt(dsim, int_src);
 649
 650         if (!(int_src & (INTSRC_PLL_STABLE | INTSRC_FRAME_DONE)))
 651                 printk(KERN_ERR "mipi dsi interrupt source (%x).\n", int_src);
 652
 653         s5p_mipi_dsi_set_interrupt_mask(dsim, 0xffffffff, 0);
 654         return IRQ_HANDLED;
 655 }
 656
 657 static inline void s5p_mipi_initialize_mipi_client(struct device *dev,
 658                                                 struct mipi_dsim_device *dsim)
 659 {
 660         int again = 1;
 661         while (again == 1) {
 662                 pm_runtime_get_sync(dev);
 663                 clk_enable(dsim->clock);
 664                 s5p_mipi_dsi_init_dsim(dsim);
 665                 s5p_mipi_dsi_init_link(dsim);
 666                 s5p_mipi_dsi_enable_hs_clock(dsim, 1);
 667                 s5p_mipi_dsi_set_cpu_transfer_mode(dsim, 1);
 668                 s5p_mipi_dsi_set_display_mode(dsim, dsim->dsim_config);
 669                 s5p_mipi_dsi_clear_int_status(dsim, INTSRC_SFR_FIFO_EMPTY);
 670                 if (dsim->dsim_lcd_drv->displayon(dsim) == 0)
 671                         again = 1;
 672                 else
 673                         again = 0;
 674                 s5p_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
 675                 if (again == 1)
 676                         s5p_mipi_dsi_sw_reset(dsim);
 677         }
 678 }
 679
 680 #ifdef CONFIG_PM
 681 #ifdef CONFIG_HAS_EARLYSUSPEND
 682 static void s5p_mipi_dsi_early_suspend(struct early_suspend *handler)
 683 {
 684         struct mipi_dsim_device *dsim =
 685                 container_of(handler, struct mipi_dsim_device, early_suspend);
 686         struct platform_device *pdev = to_platform_device(dsim->dev);
 687
 688         dsim->dsim_lcd_drv->suspend(dsim);
 689         s5p_mipi_dsi_d_phy_onoff(dsim, 0);
 690         clk_disable(dsim->clock);
 691         pm_runtime_put_sync(&pdev->dev);
 692 }
 693
 694 static void s5p_mipi_dsi_late_resume(struct early_suspend *handler)
 695 {
 696         struct mipi_dsim_device *dsim =
 697                 container_of(handler, struct mipi_dsim_device, early_suspend);
 698         struct platform_device *pdev = to_platform_device(dsim->dev);
 699         s5p_mipi_initialize_mipi_client(&pdev->dev, dsim);
 700 }
 701 #else
 702 static int s5p_mipi_dsi_suspend(struct device *dev)
 703 {
 704         struct platform_device *pdev = to_platform_device(dev);
 705         struct mipi_dsim_device *dsim = platform_get_drvdata(pdev);
 706
 707         dsim->dsim_lcd_drv->suspend(dsim);
 708         s5p_mipi_dsi_d_phy_onoff(dsim, 0);
 709         clk_disable(dsim->clock);
 710         pm_runtime_put_sync(dev);
 711         return 0;
 712 }
 713
 714 static int s5p_mipi_dsi_resume(struct device *dev)
 715 {
 716         struct platform_device *pdev = to_platform_device(dev);
 717         struct mipi_dsim_device *dsim = platform_get_drvdata(pdev);
 718
 719         return 0;
 720         s5p_mipi_initialize_mipi_client(dev, dsim);
 721 }
 722 #endif
 723 static int s5p_mipi_dsi_runtime_suspend(struct device *dev)
 724 {
 725         return 0;
 726 }
 727
 728 static int s5p_mipi_dsi_runtime_resume(struct device *dev)
 729 {
 730         return 0;
 731 }
 732 #else
 733 #define s5p_mipi_dsi_suspend NULL
 734 #define s5p_mipi_dsi_resume NULL
 735 #define s5p_mipi_dsi_runtime_suspend NULL
 736 #define s5p_mipi_dsi_runtime_resume NULL
 737 #endif
 738
 739
 740 static int s5p_mipi_dsi_probe(struct platform_device *pdev)
 741 {
 742         struct resource *res;
 743         struct mipi_dsim_device *dsim = NULL;
 744         struct mipi_dsim_config *dsim_config;
 745         struct s5p_platform_mipi_dsim *dsim_pd;
 746         int ret = -1;
 747
 748         if (!dsim)
 749                 dsim = kzalloc(sizeof(struct mipi_dsim_device),
 750                         GFP_KERNEL);
 751         if (!dsim) {
 752                 dev_err(&pdev->dev, "failed to allocate dsim object.\n");
 753                 return -EFAULT;
 754         }
 755
 756         dsim->pd = to_dsim_plat(&pdev->dev);
 757         dsim->dev = &pdev->dev;
 758         dsim->id = pdev->id;
 759
 760         ret = s5p_mipi_dsi_register_fb(dsim);
 761         if (ret) {
 762                 dev_err(&pdev->dev, "failed to register fb notifier chain\n");
 763                 return -EFAULT;
 764         }
 765
 766         pm_runtime_enable(&pdev->dev);
 767
 768         /* get s5p_platform_mipi_dsim. */
 769         dsim_pd = (struct s5p_platform_mipi_dsim *)dsim->pd;
 770         /* get mipi_dsim_config. */
 771         dsim_config = dsim_pd->dsim_config;
 772         dsim->dsim_config = dsim_config;
 773
 774         dsim->clock = clk_get(&pdev->dev, dsim->pd->clk_name);
 775         if (IS_ERR(dsim->clock)) {
 776                 dev_err(&pdev->dev, "failed to get dsim clock source\n");
 777                 goto err_clock_get;
 778         }
 779
 780         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 781         if (!res) {
 782                 dev_err(&pdev->dev, "failed to get io memory region\n");
 783                 ret = -EINVAL;
 784                 goto err_platform_get;
 785         }
 786         res = request_mem_region(res->start, resource_size(res),
 787                                         dev_name(&pdev->dev));
 788         if (!res) {
 789                 dev_err(&pdev->dev, "failed to request io memory region\n");
 790                 ret = -EINVAL;
 791                 goto err_mem_region;
 792         }
 793
 794         dsim->res = res;
 795         dsim->reg_base = ioremap(res->start, resource_size(res));
 796         if (!dsim->reg_base) {
 797                 dev_err(&pdev->dev, "failed to remap io region\n");
 798                 ret = -EINVAL;
 799                 goto err_mem_region;
 800         }
 801
 802         /*
 803          * it uses frame done interrupt handler
 804          * only in case of MIPI Video mode.
 805          */
 806         if (dsim->pd->dsim_config->e_interface == DSIM_VIDEO) {
 807                 dsim->irq = platform_get_irq(pdev, 0);
 808                 if (request_irq(dsim->irq, s5p_mipi_dsi_interrupt_handler,
 809                                 IRQF_DISABLED, "mipi-dsi", dsim)) {
 810                         dev_err(&pdev->dev, "request_irq failed.\n");
 811                         goto err_irq;
 812                 }
 813         }
 814
 815         dsim->dsim_lcd_drv = dsim->dsim_config->dsim_ddi_pd;
 816
 817         if (dsim->dsim_config == NULL) {
 818                 dev_err(&pdev->dev, "dsim_config is NULL.\n");
 819                 goto err_dsim_config;
 820         }
 821
 822         dsim->dsim_lcd_drv->probe(dsim);
 823
 824         s5p_mipi_initialize_mipi_client(&pdev->dev, dsim);
 825
 826         dev_info(&pdev->dev, "mipi-dsi driver(%s mode) has been probed.\n",
 827                 (dsim_config->e_interface == DSIM_COMMAND) ?
 828                         "CPU" : "RGB");
 829
 830 #ifdef CONFIG_HAS_EARLYSUSPEND
 831         dsim->early_suspend.suspend = s5p_mipi_dsi_early_suspend;
 832         dsim->early_suspend.resume = s5p_mipi_dsi_late_resume;
 833         dsim->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 1;
 834         register_early_suspend(&(dsim->early_suspend));
 835 #endif
 836         platform_set_drvdata(pdev, dsim);
 837
 838         return 0;
 839
 840 err_dsim_config:
 841 err_irq:
 842         release_resource(dsim->res);
 843         kfree(dsim->res);
 844
 845         iounmap((void __iomem *) dsim->reg_base);
 846
 847 err_mem_region:
 848 err_platform_get:
 849         clk_disable(dsim->clock);
 850         clk_put(dsim->clock);
 851
 852 err_clock_get:
 853         kfree(dsim);
 854         pm_runtime_put_sync(&pdev->dev);
 855         return ret;
 856
 857 }
 858
 859 static int __devexit s5p_mipi_dsi_remove(struct platform_device *pdev)
 860 {
 861         struct mipi_dsim_device *dsim = platform_get_drvdata(pdev);
 862
 863         if (dsim->dsim_config->e_interface == DSIM_VIDEO)
 864                 free_irq(dsim->irq, dsim);
 865
 866         iounmap(dsim->reg_base);
 867
 868         clk_disable(dsim->clock);
 869         clk_put(dsim->clock);
 870
 871         release_resource(dsim->res);
 872         kfree(dsim->res);
 873
 874         kfree(dsim);
 875
 876         return 0;
 877 }
 878
 879 static const struct dev_pm_ops mipi_dsi_pm_ops = {
 880 #ifndef CONFIG_HAS_EARLYSUSPEND
 881         .suspend = s5p_mipi_dsi_suspend,
 882         .resume = s5p_mipi_dsi_resume,
 883 #endif
 884         .runtime_suspend        = s5p_mipi_dsi_runtime_suspend,
 885         .runtime_resume         = s5p_mipi_dsi_runtime_resume,
 886 };
 887
 888 #ifdef CONFIG_OF
 889         static const struct of_device_id exynos_mipi_match[] = {
 890                 { .compatible = "samsung,exynos-mipi" },
 891                 {},
 892         };
 893         MODULE_DEVICE_TABLE(of, exynos_mipi_match);
 894 #endif
 895
 896 static struct platform_driver s5p_mipi_dsi_driver = {
 897         .probe = s5p_mipi_dsi_probe,
 898         .remove = __devexit_p(s5p_mipi_dsi_remove),
 899         .driver = {
 900                    .name = "s5p-mipi-dsim",
 901                    .owner = THIS_MODULE,
 902                    .pm = &mipi_dsi_pm_ops,
 903                    .of_match_table = of_match_ptr(exynos_mipi_match),
 904         },
 905 };
 906
 907 static int s5p_mipi_dsi_register(void)
 908 {
 909         platform_driver_register(&s5p_mipi_dsi_driver);
 910
 911         return 0;
 912 }
 913
 914 static void s5p_mipi_dsi_unregister(void)
 915 {
 916         platform_driver_unregister(&s5p_mipi_dsi_driver);
 917 }
 918 module_init(s5p_mipi_dsi_register);
 919 module_exit(s5p_mipi_dsi_unregister);
 920
 921 MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
 922 MODULE_DESCRIPTION("Samusung MIPI-DSI driver");
 923 MODULE_LICENSE("GPL");