include/asm-x86_64/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7
   8 /*
   9  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  10  *
  11  * Simple spin lock operations.  There are two variants, one clears IRQ's
  12  * on the local processor, one does not.
  13  *
  14  * We make no fairness assumptions. They have a cost.
  15  *
  16  * (the type definitions are in asm/spinlock_types.h)
  17  */
  18
  19 static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
  20 {
  21         return *(volatile signed int *)(&(lock)->slock) <= 0;
  22 }
  23
  24 static inline void __raw_spin_lock(raw_spinlock_t *lock)
  25 {
  26         asm volatile(
  27                 "\n1:\t"
  28                 LOCK_PREFIX " ; decl %0\n\t"
  29                 "jns 2f\n"
  30                 "3:\n"
  31                 "rep;nop\n\t"
  32                 "cmpl $0,%0\n\t"
  33                 "jle 3b\n\t"
  34                 "jmp 1b\n"
  35                 "2:\t" : "=m" (lock->slock) : : "memory");
  36 }
  37
  38 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
  39
  40 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
  41 {
  42         int oldval;
  43
  44         asm volatile(
  45                 "xchgl %0,%1"
  46                 :"=q" (oldval), "=m" (lock->slock)
  47                 :"0" (0) : "memory");
  48
  49         return oldval > 0;
  50 }
  51
  52 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  53 {
  54         asm volatile("movl $1,%0" :"=m" (lock->slock) :: "memory");
  55 }
  56
  57 static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
  58 {
  59         while (__raw_spin_is_locked(lock))
  60                 cpu_relax();
  61 }
  62
  63 /*
  64  * Read-write spinlocks, allowing multiple readers
  65  * but only one writer.
  66  *
  67  * NOTE! it is quite common to have readers in interrupts
  68  * but no interrupt writers. For those circumstances we
  69  * can "mix" irq-safe locks - any writer needs to get a
  70  * irq-safe write-lock, but readers can get non-irqsafe
  71  * read-locks.
  72  *
  73  * On x86, we implement read-write locks as a 32-bit counter
  74  * with the high bit (sign) being the "contended" bit.
  75  */
  76
  77 static inline int __raw_read_can_lock(raw_rwlock_t *lock)
  78 {
  79         return (int)(lock)->lock > 0;
  80 }
  81
  82 static inline int __raw_write_can_lock(raw_rwlock_t *lock)
  83 {
  84         return (lock)->lock == RW_LOCK_BIAS;
  85 }
  86
  87 static inline void __raw_read_lock(raw_rwlock_t *rw)
  88 {
  89         asm volatile(LOCK_PREFIX "subl $1,(%0)\n\t"
  90                      "jns 1f\n"
  91                      "call __read_lock_failed\n"
  92                      "1:\n"
  93                      ::"D" (rw), "i" (RW_LOCK_BIAS) : "memory");
  94 }
  95
  96 static inline void __raw_write_lock(raw_rwlock_t *rw)
  97 {
  98         asm volatile(LOCK_PREFIX "subl %1,(%0)\n\t"
  99                      "jz 1f\n"
 100                      "\tcall __write_lock_failed\n\t"
 101                      "1:\n"
 102                      ::"D" (rw), "i" (RW_LOCK_BIAS) : "memory");
 103 }
 104
 105 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 106 {
 107         atomic_t *count = (atomic_t *)lock;
 108         atomic_dec(count);
 109         if (atomic_read(count) >= 0)
 110                 return 1;
 111         atomic_inc(count);
 112         return 0;
 113 }
 114
 115 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 116 {
 117         atomic_t *count = (atomic_t *)lock;
 118         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 119                 return 1;
 120         atomic_add(RW_LOCK_BIAS, count);
 121         return 0;
 122 }
 123
 124 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 125 {
 126         asm volatile(LOCK_PREFIX " ; incl %0" :"=m" (rw->lock) : : "memory");
 127 }
 128
 129 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 130 {
 131         asm volatile(LOCK_PREFIX " ; addl $" RW_LOCK_BIAS_STR ",%0"
 132                                 : "=m" (rw->lock) : : "memory");
 133 }
 134
 135 #endif /* __ASM_SPINLOCK_H */