4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
14 #ifndef __LINUX_MFD_S5M_CORE_H
15 #define __LINUX_MFD_S5M_CORE_H
17 #define NUM_IRQ_REGS 4
19 enum s5m_device_type {
25 /* S5M8767 registers */
43 S5M8767_REG_DVSTIMER2 = 0x10,
44 S5M8767_REG_DVSTIMER3,
45 S5M8767_REG_DVSTIMER4,
59 S5M8767_REG_LDO14 = 0x20,
74 S5M8767_REG_UVLO = 0x31,
75 S5M8767_REG_BUCK1CTRL1,
76 S5M8767_REG_BUCK1CTRL2,
77 S5M8767_REG_BUCK2CTRL,
78 S5M8767_REG_BUCK2DVS1,
79 S5M8767_REG_BUCK2DVS2,
80 S5M8767_REG_BUCK2DVS3,
81 S5M8767_REG_BUCK2DVS4,
82 S5M8767_REG_BUCK2DVS5,
83 S5M8767_REG_BUCK2DVS6,
84 S5M8767_REG_BUCK2DVS7,
85 S5M8767_REG_BUCK2DVS8,
86 S5M8767_REG_BUCK3CTRL,
87 S5M8767_REG_BUCK3DVS1,
88 S5M8767_REG_BUCK3DVS2,
89 S5M8767_REG_BUCK3DVS3,
90 S5M8767_REG_BUCK3DVS4,
91 S5M8767_REG_BUCK3DVS5,
92 S5M8767_REG_BUCK3DVS6,
93 S5M8767_REG_BUCK3DVS7,
94 S5M8767_REG_BUCK3DVS8,
95 S5M8767_REG_BUCK4CTRL,
96 S5M8767_REG_BUCK4DVS1,
97 S5M8767_REG_BUCK4DVS2,
98 S5M8767_REG_BUCK4DVS3,
99 S5M8767_REG_BUCK4DVS4,
100 S5M8767_REG_BUCK4DVS5,
101 S5M8767_REG_BUCK4DVS6,
102 S5M8767_REG_BUCK4DVS7,
103 S5M8767_REG_BUCK4DVS8,
104 S5M8767_REG_BUCK5CTRL1,
105 S5M8767_REG_BUCK5CTRL2,
106 S5M8767_REG_BUCK5CTRL3,
107 S5M8767_REG_BUCK5CTRL4,
108 S5M8767_REG_BUCK5CTRL5,
109 S5M8767_REG_BUCK6CTRL1,
110 S5M8767_REG_BUCK6CTRL2,
111 S5M8767_REG_BUCK7CTRL1,
112 S5M8767_REG_BUCK7CTRL2,
113 S5M8767_REG_BUCK8CTRL1,
114 S5M8767_REG_BUCK8CTRL2,
115 S5M8767_REG_BUCK9CTRL1,
116 S5M8767_REG_BUCK9CTRL2,
117 S5M8767_REG_LDO1CTRL,
118 S5M8767_REG_LDO2_1CTRL,
119 S5M8767_REG_LDO2_2CTRL,
120 S5M8767_REG_LDO2_3CTRL,
121 S5M8767_REG_LDO2_4CTRL,
122 S5M8767_REG_LDO3CTRL,
123 S5M8767_REG_LDO4CTRL,
124 S5M8767_REG_LDO5CTRL,
125 S5M8767_REG_LDO6CTRL,
126 S5M8767_REG_LDO7CTRL,
127 S5M8767_REG_LDO8CTRL,
128 S5M8767_REG_LDO9CTRL,
129 S5M8767_REG_LDO10CTRL,
130 S5M8767_REG_LDO11CTRL,
131 S5M8767_REG_LDO12CTRL,
132 S5M8767_REG_LDO13CTRL,
133 S5M8767_REG_LDO14CTRL,
134 S5M8767_REG_LDO15CTRL,
135 S5M8767_REG_LDO16CTRL,
136 S5M8767_REG_LDO17CTRL,
137 S5M8767_REG_LDO18CTRL,
138 S5M8767_REG_LDO19CTRL,
139 S5M8767_REG_LDO20CTRL,
140 S5M8767_REG_LDO21CTRL,
141 S5M8767_REG_LDO22CTRL,
142 S5M8767_REG_LDO23CTRL,
143 S5M8767_REG_LDO24CTRL,
144 S5M8767_REG_LDO25CTRL,
145 S5M8767_REG_LDO26CTRL,
146 S5M8767_REG_LDO27CTRL,
147 S5M8767_REG_LDO28CTRL,
150 /* S5M8763 registers */
162 S5M8763_REG_STATUSM1,
163 S5M8763_REG_STATUSM2,
166 S5M8763_REG_LDO_ACTIVE_DISCHARGE1,
167 S5M8763_REG_LDO_ACTIVE_DISCHARGE2,
168 S5M8763_REG_BUCK_ACTIVE_DISCHARGE3,
173 S5M8763_REG_BUCK1_VOLTAGE1,
174 S5M8763_REG_BUCK1_VOLTAGE2,
175 S5M8763_REG_BUCK1_VOLTAGE3,
176 S5M8763_REG_BUCK1_VOLTAGE4,
177 S5M8763_REG_BUCK2_VOLTAGE1,
178 S5M8763_REG_BUCK2_VOLTAGE2,
181 S5M8763_REG_LDO1_LDO2,
187 S5M8763_REG_LDO7_LDO8,
188 S5M8763_REG_LDO9_LDO10,
224 #define S5M8767_IRQ_PWRR_MASK (1 << 0)
225 #define S5M8767_IRQ_PWRF_MASK (1 << 1)
226 #define S5M8767_IRQ_PWR1S_MASK (1 << 3)
227 #define S5M8767_IRQ_JIGR_MASK (1 << 4)
228 #define S5M8767_IRQ_JIGF_MASK (1 << 5)
229 #define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
230 #define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
232 #define S5M8767_IRQ_MRB_MASK (1 << 2)
233 #define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
234 #define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
235 #define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
237 #define S5M8767_IRQ_RTC60S_MASK (1 << 0)
238 #define S5M8767_IRQ_RTCA1_MASK (1 << 1)
239 #define S5M8767_IRQ_RTCA2_MASK (1 << 2)
240 #define S5M8767_IRQ_SMPL_MASK (1 << 3)
241 #define S5M8767_IRQ_RTC1S_MASK (1 << 4)
242 #define S5M8767_IRQ_WTSR_MASK (1 << 5)
252 S5M8763_IRQ_WTSREVNT,
253 S5M8763_IRQ_SMPLEVNT,
259 S5M8763_IRQ_DCINOVPR,
262 S5M8763_IRQ_CHGFAULT,
270 #define S5M8763_IRQ_DCINF_MASK (1 << 2)
271 #define S5M8763_IRQ_DCINR_MASK (1 << 3)
272 #define S5M8763_IRQ_JIGF_MASK (1 << 4)
273 #define S5M8763_IRQ_JIGR_MASK (1 << 5)
274 #define S5M8763_IRQ_PWRONF_MASK (1 << 6)
275 #define S5M8763_IRQ_PWRONR_MASK (1 << 7)
277 #define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
278 #define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
279 #define S5M8763_IRQ_ALARM1_MASK (1 << 2)
280 #define S5M8763_IRQ_ALARM0_MASK (1 << 3)
282 #define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
283 #define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
284 #define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
285 #define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
286 #define S5M8763_IRQ_DONER_MASK (1 << 5)
287 #define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
289 #define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
290 #define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
292 #define S5M8763_ENRAMP (1 << 4)
295 * struct s5m87xx_dev - s5m87xx master device for sub-drivers
296 * @dev: master device of the chip (can be used to access platform data)
297 * @i2c: i2c client private data for regulator
298 * @rtc: i2c client private data for rtc
299 * @iolock: mutex for serializing io access
300 * @irqlock: mutex for buslock
301 * @irq_base: base IRQ number for s5m87xx, required for IRQs
302 * @irq: generic IRQ number for s5m87xx
303 * @ono: power onoff IRQ number for s5m87xx
304 * @irq_masks_cur: currently active value
305 * @irq_masks_cache: cached hardware value
306 * @type: indicate which s5m87xx "variant" is used
307 * @pdata: platform data
311 struct regmap *regmap;
312 struct i2c_client *i2c;
313 struct i2c_client *rtc;
315 struct mutex irqlock;
321 u8 irq_masks_cur[NUM_IRQ_REGS];
322 u8 irq_masks_cache[NUM_IRQ_REGS];
325 struct s5m_platform_data *pdata;
328 int s5m_irq_init(struct s5m87xx_dev *s5m87xx);
329 void s5m_irq_exit(struct s5m87xx_dev *s5m87xx);
330 int s5m_irq_resume(struct s5m87xx_dev *s5m87xx);
332 extern int s5m_reg_read(struct s5m87xx_dev *s5m87xx, u8 reg, void *dest);
333 extern int s5m_bulk_read(struct s5m87xx_dev *s5m87xx, u8 reg, int count, u8 *buf);
334 extern int s5m_reg_write(struct s5m87xx_dev *s5m87xx, u8 reg, u8 value);
335 extern int s5m_bulk_write(struct s5m87xx_dev *s5m87xx, u8 reg, int count, u8 *buf);
336 extern int s5m_reg_update(struct s5m87xx_dev *s5m87xx, u8 reg, u8 val, u8 mask);
338 struct s5m_platform_data {
339 struct s5m_regulator_data *regulators;
344 int (*cfg_pmic_irq)(void);
348 bool buck_voltage_lock;
351 int buck2_voltage[8];
353 int buck3_voltage[8];
355 int buck4_voltage[8];
364 int buck_default_idx;
365 int buck2_default_idx;
366 int buck3_default_idx;
367 int buck4_default_idx;
370 bool buck2_ramp_enable;
371 bool buck3_ramp_enable;
372 bool buck4_ramp_enable;
375 #endif /* __LINUX_MFD_S5M_CORE_H */