2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
43 #include <linux/atomic.h>
45 #include <linux/clocksource.h>
47 #define MAX_MSIX_P_PORT 17
49 #define MSIX_LEGACY_SZ 4
50 #define MIN_MSIX_P_PORT 5
54 #define MLX4_MAX_100M_UNITS_VAL 255 /*
55 * work around: can't set values
56 * greater then this value when
57 * using 100 Mbps units.
59 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
60 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
61 #define MLX4_RATELIMIT_DEFAULT 0x00ff
63 #define MLX4_ROCE_MAX_GIDS 128
64 #define MLX4_ROCE_PF_GIDS 16
67 MLX4_FLAG_MSI_X = 1 << 0,
68 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
69 MLX4_FLAG_MASTER = 1 << 2,
70 MLX4_FLAG_SLAVE = 1 << 3,
71 MLX4_FLAG_SRIOV = 1 << 4,
72 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
76 MLX4_PORT_CAP_IS_SM = 1 << 1,
77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
82 MLX4_MAX_PORT_PKEYS = 128
85 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
86 * These qkeys must not be allowed for general use. This is a 64k range,
87 * and to test for violation, we use the mask (protect against future chg).
89 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
90 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
93 MLX4_BOARD_ID_LEN = 64
99 MLX4_MAX_NUM_VF_P_PORT = 64,
101 MLX4_MAX_EQ_NUM = 1024,
102 MLX4_MFUNC_EQ_NUM = 4,
103 MLX4_MFUNC_MAX_EQES = 8,
104 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
107 /* Driver supports 3 diffrent device methods to manage traffic steering:
108 * -device managed - High level API for ib and eth flow steering. FW is
109 * managing flow steering tables.
110 * - B0 steering mode - Common low level API for ib and (if supported) eth.
111 * - A0 steering mode - Limited low level API for eth. In case of IB,
115 MLX4_STEERING_MODE_A0,
116 MLX4_STEERING_MODE_B0,
117 MLX4_STEERING_MODE_DEVICE_MANAGED
120 static inline const char *mlx4_steering_mode_str(int steering_mode)
122 switch (steering_mode) {
123 case MLX4_STEERING_MODE_A0:
124 return "A0 steering";
126 case MLX4_STEERING_MODE_B0:
127 return "B0 steering";
129 case MLX4_STEERING_MODE_DEVICE_MANAGED:
130 return "Device managed flow steering";
133 return "Unrecognize steering mode";
138 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
139 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
143 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
144 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
145 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
146 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
147 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
148 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
149 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
150 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
151 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
152 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
153 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
154 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
155 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
156 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
157 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
158 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
159 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
160 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
161 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
162 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
163 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
164 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
165 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
166 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
167 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
168 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
169 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
170 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
171 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
172 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
176 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
177 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
178 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
179 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
180 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
181 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
182 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
183 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
184 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
185 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
186 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
187 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
188 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
189 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
190 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
191 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
192 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16
196 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
197 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
198 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
199 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
203 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
207 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
208 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1
212 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
215 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
216 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
217 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
218 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
219 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
220 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
221 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
225 MLX4_EVENT_TYPE_COMP = 0x00,
226 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
227 MLX4_EVENT_TYPE_COMM_EST = 0x02,
228 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
229 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
230 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
231 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
232 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
233 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
234 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
235 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
236 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
237 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
238 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
239 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
240 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
241 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
242 MLX4_EVENT_TYPE_CMD = 0x0a,
243 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
244 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
245 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
246 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
247 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
248 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
249 MLX4_EVENT_TYPE_NONE = 0xff,
253 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
254 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
258 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
261 enum slave_port_state {
267 enum slave_port_gen_event {
268 SLAVE_PORT_GEN_EVENT_DOWN = 0,
269 SLAVE_PORT_GEN_EVENT_UP,
270 SLAVE_PORT_GEN_EVENT_NONE,
273 enum slave_port_state_event {
274 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
275 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
276 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
277 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
281 MLX4_PERM_LOCAL_READ = 1 << 10,
282 MLX4_PERM_LOCAL_WRITE = 1 << 11,
283 MLX4_PERM_REMOTE_READ = 1 << 12,
284 MLX4_PERM_REMOTE_WRITE = 1 << 13,
285 MLX4_PERM_ATOMIC = 1 << 14,
286 MLX4_PERM_BIND_MW = 1 << 15,
287 MLX4_PERM_MASK = 0xFC00
291 MLX4_OPCODE_NOP = 0x00,
292 MLX4_OPCODE_SEND_INVAL = 0x01,
293 MLX4_OPCODE_RDMA_WRITE = 0x08,
294 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
295 MLX4_OPCODE_SEND = 0x0a,
296 MLX4_OPCODE_SEND_IMM = 0x0b,
297 MLX4_OPCODE_LSO = 0x0e,
298 MLX4_OPCODE_RDMA_READ = 0x10,
299 MLX4_OPCODE_ATOMIC_CS = 0x11,
300 MLX4_OPCODE_ATOMIC_FA = 0x12,
301 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
302 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
303 MLX4_OPCODE_BIND_MW = 0x18,
304 MLX4_OPCODE_FMR = 0x19,
305 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
306 MLX4_OPCODE_CONFIG_CMD = 0x1f,
308 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
309 MLX4_RECV_OPCODE_SEND = 0x01,
310 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
311 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
313 MLX4_CQE_OPCODE_ERROR = 0x1e,
314 MLX4_CQE_OPCODE_RESIZE = 0x16,
318 MLX4_STAT_RATE_OFFSET = 5
322 MLX4_PROT_IB_IPV6 = 0,
329 MLX4_MTT_FLAG_PRESENT = 1
332 enum mlx4_qp_region {
333 MLX4_QP_REGION_FW = 0,
334 MLX4_QP_REGION_ETH_ADDR,
335 MLX4_QP_REGION_FC_ADDR,
336 MLX4_QP_REGION_FC_EXCH,
340 enum mlx4_port_type {
341 MLX4_PORT_TYPE_NONE = 0,
342 MLX4_PORT_TYPE_IB = 1,
343 MLX4_PORT_TYPE_ETH = 2,
344 MLX4_PORT_TYPE_AUTO = 3
347 enum mlx4_special_vlan_idx {
348 MLX4_NO_VLAN_IDX = 0,
353 enum mlx4_steer_type {
360 MLX4_NUM_FEXCH = 64 * 1024,
364 MLX4_MAX_FAST_REG_PAGES = 511,
368 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
369 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
370 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
373 /* Port mgmt change event handling */
375 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
376 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
377 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
378 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
379 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
382 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
383 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
385 enum mlx4_module_id {
386 MLX4_MODULE_ID_SFP = 0x3,
387 MLX4_MODULE_ID_QSFP = 0xC,
388 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
389 MLX4_MODULE_ID_QSFP28 = 0x11,
392 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
394 return (major << 32) | (minor << 16) | subminor;
397 struct mlx4_phys_caps {
398 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
399 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
403 u32 base_tunnel_sqpn;
410 int vl_cap[MLX4_MAX_PORTS + 1];
411 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
412 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
413 u64 def_mac[MLX4_MAX_PORTS + 1];
414 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
415 int gid_table_len[MLX4_MAX_PORTS + 1];
416 int pkey_table_len[MLX4_MAX_PORTS + 1];
417 int trans_type[MLX4_MAX_PORTS + 1];
418 int vendor_oui[MLX4_MAX_PORTS + 1];
419 int wavelength[MLX4_MAX_PORTS + 1];
420 u64 trans_code[MLX4_MAX_PORTS + 1];
421 int local_ca_ack_delay;
425 int bf_regs_per_page;
432 int max_qp_init_rdma;
433 int max_qp_dest_rdma;
448 int num_comp_vectors;
453 int fmr_reserved_mtts;
462 int fs_log_max_ucast_qp_range_size;
474 u16 stat_rate_support;
475 u8 port_width_cap[MLX4_MAX_PORTS + 1];
478 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
480 int reserved_qps_base[MLX4_NUM_QP_REGION];
483 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
484 u8 supported_type[MLX4_MAX_PORTS + 1];
485 u8 suggested_type[MLX4_MAX_PORTS + 1];
486 u8 default_sense[MLX4_MAX_PORTS + 1];
487 u32 port_mask[MLX4_MAX_PORTS + 1];
488 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
490 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
495 u32 userspace_caps; /* userspace must be aware of these */
496 u32 function_caps; /* VFs must be aware of these */
498 u64 phys_port_id[MLX4_MAX_PORTS + 1];
499 int tunnel_offload_mode;
502 struct mlx4_buf_list {
508 struct mlx4_buf_list direct;
509 struct mlx4_buf_list *page_list;
522 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
525 struct mlx4_db_pgdir {
526 struct list_head list;
527 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
528 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
529 unsigned long *bits[2];
534 struct mlx4_ib_user_db_page;
539 struct mlx4_db_pgdir *pgdir;
540 struct mlx4_ib_user_db_page *user_page;
547 struct mlx4_hwq_resources {
571 enum mlx4_mw_type type;
577 struct mlx4_mpt_entry *mpt;
579 dma_addr_t dma_handle;
589 struct list_head bf_list;
590 unsigned free_bf_bmap;
592 void __iomem *bf_map;
598 struct mlx4_uar *uar;
603 void (*comp) (struct mlx4_cq *);
604 void (*event) (struct mlx4_cq *, enum mlx4_event);
606 struct mlx4_uar *uar;
619 struct completion free;
623 void (*event) (struct mlx4_qp *, enum mlx4_event);
628 struct completion free;
632 void (*event) (struct mlx4_srq *, enum mlx4_event);
640 struct completion free;
652 __be32 sl_tclass_flowlabel;
665 __be32 sl_tclass_flowlabel;
675 struct mlx4_eth_av eth;
678 struct mlx4_counter {
705 struct pci_dev *pdev;
707 unsigned long num_slaves;
708 struct mlx4_caps caps;
709 struct mlx4_phys_caps phys_caps;
710 struct mlx4_quotas quotas;
711 struct radix_tree_root qp_table_tree;
713 char board_id[MLX4_BOARD_ID_LEN];
716 int oper_log_mgm_entry_size;
717 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
718 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
719 struct mlx4_vf_dev *dev_vfs;
720 int nvfs[MLX4_MAX_PORTS + 1];
756 } __packed port_change;
758 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
760 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
761 } __packed comm_channel_arm;
766 } __packed mac_update;
769 } __packed flr_event;
771 __be16 current_temperature;
772 __be16 warning_threshold;
785 } __packed port_info;
788 __be32 tbl_entries_mask;
789 } __packed tbl_change_info;
791 } __packed port_mgmt_change;
798 struct mlx4_init_port_param {
812 #define MAD_IFC_DATA_SZ 192
813 /* MAD IFC Mailbox */
814 struct mlx4_mad_ifc {
820 __be16 class_specific;
829 u8 data[MAD_IFC_DATA_SZ];
832 #define mlx4_foreach_port(port, dev, type) \
833 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
834 if ((type) == (dev)->caps.port_mask[(port)])
836 #define mlx4_foreach_non_ib_transport_port(port, dev) \
837 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
838 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
840 #define mlx4_foreach_ib_transport_port(port, dev) \
841 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
842 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
843 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
845 #define MLX4_INVALID_SLAVE_ID 0xFF
847 void handle_port_mgmt_change_event(struct work_struct *work);
849 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
851 return dev->caps.function;
854 static inline int mlx4_is_master(struct mlx4_dev *dev)
856 return dev->flags & MLX4_FLAG_MASTER;
859 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
861 return dev->phys_caps.base_sqpn + 8 +
862 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
865 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
867 return (qpn < dev->phys_caps.base_sqpn + 8 +
868 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
871 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
873 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
875 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
881 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
883 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
886 static inline int mlx4_is_slave(struct mlx4_dev *dev)
888 return dev->flags & MLX4_FLAG_SLAVE;
891 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
892 struct mlx4_buf *buf, gfp_t gfp);
893 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
894 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
896 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
897 return buf->direct.buf + offset;
899 return buf->page_list[offset >> PAGE_SHIFT].buf +
900 (offset & (PAGE_SIZE - 1));
903 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
904 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
905 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
906 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
908 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
909 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
910 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
911 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
913 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
914 struct mlx4_mtt *mtt);
915 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
916 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
918 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
919 int npages, int page_shift, struct mlx4_mr *mr);
920 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
921 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
922 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
924 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
925 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
926 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
927 int start_index, int npages, u64 *page_list);
928 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
929 struct mlx4_buf *buf, gfp_t gfp);
931 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
933 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
935 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
936 int size, int max_direct);
937 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
940 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
941 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
942 unsigned vector, int collapsed, int timestamp_en);
943 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
945 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
946 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
948 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
950 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
952 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
953 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
954 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
955 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
956 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
958 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
959 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
961 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
962 int block_mcast_loopback, enum mlx4_protocol prot);
963 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
964 enum mlx4_protocol prot);
965 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
966 u8 port, int block_mcast_loopback,
967 enum mlx4_protocol protocol, u64 *reg_id);
968 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
969 enum mlx4_protocol protocol, u64 reg_id);
972 MLX4_DOMAIN_UVERBS = 0x1000,
973 MLX4_DOMAIN_ETHTOOL = 0x2000,
974 MLX4_DOMAIN_RFS = 0x3000,
975 MLX4_DOMAIN_NIC = 0x5000,
978 enum mlx4_net_trans_rule_id {
979 MLX4_NET_TRANS_RULE_ID_ETH = 0,
980 MLX4_NET_TRANS_RULE_ID_IB,
981 MLX4_NET_TRANS_RULE_ID_IPV6,
982 MLX4_NET_TRANS_RULE_ID_IPV4,
983 MLX4_NET_TRANS_RULE_ID_TCP,
984 MLX4_NET_TRANS_RULE_ID_UDP,
985 MLX4_NET_TRANS_RULE_ID_VXLAN,
986 MLX4_NET_TRANS_RULE_NUM, /* should be last */
989 extern const u16 __sw_id_hw[];
991 static inline int map_hw_to_sw_id(u16 header_id)
995 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
996 if (header_id == __sw_id_hw[i])
1002 enum mlx4_net_trans_promisc_mode {
1003 MLX4_FS_REGULAR = 1,
1004 MLX4_FS_ALL_DEFAULT,
1008 MLX4_FS_MODE_NUM, /* should be last */
1011 struct mlx4_spec_eth {
1012 u8 dst_mac[ETH_ALEN];
1013 u8 dst_mac_msk[ETH_ALEN];
1014 u8 src_mac[ETH_ALEN];
1015 u8 src_mac_msk[ETH_ALEN];
1016 u8 ether_type_enable;
1022 struct mlx4_spec_tcp_udp {
1024 __be16 dst_port_msk;
1026 __be16 src_port_msk;
1029 struct mlx4_spec_ipv4 {
1036 struct mlx4_spec_ib {
1043 struct mlx4_spec_vxlan {
1049 struct mlx4_spec_list {
1050 struct list_head list;
1051 enum mlx4_net_trans_rule_id id;
1053 struct mlx4_spec_eth eth;
1054 struct mlx4_spec_ib ib;
1055 struct mlx4_spec_ipv4 ipv4;
1056 struct mlx4_spec_tcp_udp tcp_udp;
1057 struct mlx4_spec_vxlan vxlan;
1061 enum mlx4_net_trans_hw_rule_queue {
1062 MLX4_NET_TRANS_Q_FIFO,
1063 MLX4_NET_TRANS_Q_LIFO,
1066 struct mlx4_net_trans_rule {
1067 struct list_head list;
1068 enum mlx4_net_trans_hw_rule_queue queue_mode;
1070 bool allow_loopback;
1071 enum mlx4_net_trans_promisc_mode promisc_mode;
1077 struct mlx4_net_trans_rule_hw_ctrl {
1089 struct mlx4_net_trans_rule_hw_ib {
1100 struct mlx4_net_trans_rule_hw_eth {
1113 u8 ether_type_enable;
1115 __be16 vlan_tag_msk;
1119 struct mlx4_net_trans_rule_hw_tcp_udp {
1126 __be16 dst_port_msk;
1130 __be16 src_port_msk;
1133 struct mlx4_net_trans_rule_hw_ipv4 {
1144 struct mlx4_net_trans_rule_hw_vxlan {
1160 struct mlx4_net_trans_rule_hw_eth eth;
1161 struct mlx4_net_trans_rule_hw_ib ib;
1162 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1163 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1164 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1169 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1170 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1171 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1172 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1173 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1177 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1178 enum mlx4_net_trans_promisc_mode mode);
1179 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1180 enum mlx4_net_trans_promisc_mode mode);
1181 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1182 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1183 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1184 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1185 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1187 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1188 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1189 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1190 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1191 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1192 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1193 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1194 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1196 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1197 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1198 u8 *pg, u16 *ratelimit);
1199 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1200 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1201 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1202 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1203 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1205 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1206 int npages, u64 iova, u32 *lkey, u32 *rkey);
1207 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1208 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1209 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1210 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1211 u32 *lkey, u32 *rkey);
1212 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1213 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1214 int mlx4_test_interrupts(struct mlx4_dev *dev);
1215 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1217 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1219 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1221 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1222 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1223 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1225 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1226 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1228 int mlx4_flow_attach(struct mlx4_dev *dev,
1229 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1230 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1231 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1232 enum mlx4_net_trans_promisc_mode flow_type);
1233 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1234 enum mlx4_net_trans_rule_id id);
1235 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1237 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1238 int port, int qpn, u16 prio, u64 *reg_id);
1240 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1243 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1245 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1246 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1247 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1248 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1249 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1250 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1251 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1253 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1254 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1256 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1258 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1261 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1264 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1266 struct mlx4_active_ports {
1267 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1269 /* Returns a bitmap of the physical ports which are assigned to slave */
1270 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1272 /* Returns the physical port that represents the virtual port of the slave, */
1273 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1274 /* mapping is returned. */
1275 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1277 struct mlx4_slaves_pport {
1278 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1280 /* Returns a bitmap of all slaves that are assigned to port. */
1281 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1284 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1285 /* the ports that are set in crit_ports. */
1286 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1287 struct mlx4_dev *dev,
1288 const struct mlx4_active_ports *crit_ports);
1290 /* Returns the slave's virtual port that represents the physical port. */
1291 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1293 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1295 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1296 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1297 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1298 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1300 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1301 struct mlx4_mpt_entry ***mpt_entry);
1302 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1303 struct mlx4_mpt_entry **mpt_entry);
1304 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1306 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1307 struct mlx4_mpt_entry *mpt_entry,
1309 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1310 struct mlx4_mpt_entry **mpt_entry);
1311 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1312 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1313 u64 iova, u64 size, int npages,
1314 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1316 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1317 u16 offset, u16 size, u8 *data);
1319 /* Returns true if running in low memory profile (kdump kernel) */
1320 static inline bool mlx4_low_memory_profile(void)
1322 return is_kdump_kernel();
1325 /* ACCESS REG commands */
1326 enum mlx4_access_reg_method {
1327 MLX4_ACCESS_REG_QUERY = 0x1,
1328 MLX4_ACCESS_REG_WRITE = 0x2,
1331 /* ACCESS PTYS Reg command */
1332 enum mlx4_ptys_proto {
1333 MLX4_PTYS_IB = 1<<0,
1334 MLX4_PTYS_EN = 1<<2,
1337 struct mlx4_ptys_reg {
1343 __be32 eth_proto_cap;
1344 __be16 ib_width_cap;
1345 __be16 ib_speed_cap;
1347 __be32 eth_proto_admin;
1348 __be16 ib_width_admin;
1349 __be16 ib_speed_admin;
1351 __be32 eth_proto_oper;
1352 __be16 ib_width_oper;
1353 __be16 ib_speed_oper;
1355 __be32 eth_proto_lp_adv;
1358 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1359 enum mlx4_access_reg_method method,
1360 struct mlx4_ptys_reg *ptys_reg);
1362 #endif /* MLX4_DEVICE_H */