include/linux/mlx5/device.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DEVICE_H
  34 #define MLX5_DEVICE_H
  35
  36 #include <linux/types.h>
  37 #include <rdma/ib_verbs.h>
  38 #include <linux/mlx5/mlx5_ifc.h>
  39
  40 #if defined(__LITTLE_ENDIAN)
  41 #define MLX5_SET_HOST_ENDIANNESS        0
  42 #elif defined(__BIG_ENDIAN)
  43 #define MLX5_SET_HOST_ENDIANNESS        0x80
  44 #else
  45 #error Host endianness not defined
  46 #endif
  47
  48 /* helper macros */
  49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
  50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
  51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
  52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
  53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
  54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
  55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
  57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
  58
  59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
  60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
  61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
  62 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
  63 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
  64 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
  65 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
  66
  67 /* insert a value to a struct */
  68 #define MLX5_SET(typ, p, fld, v) do { \
  69         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  70         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  71         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  72                      (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
  73                      << __mlx5_dw_bit_off(typ, fld))); \
  74 } while (0)
  75
  76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
  77         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  78         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  79         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  80                      (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
  81                      << __mlx5_dw_bit_off(typ, fld))); \
  82 } while (0)
  83
  84 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
  85 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
  86 __mlx5_mask(typ, fld))
  87
  88 #define MLX5_GET_PR(typ, p, fld) ({ \
  89         u32 ___t = MLX5_GET(typ, p, fld); \
  90         pr_debug(#fld " = 0x%x\n", ___t); \
  91         ___t; \
  92 })
  93
  94 #define MLX5_SET64(typ, p, fld, v) do { \
  95         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
  96         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
  97         *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
  98 } while (0)
  99
 100 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
 101
 102 #define MLX5_GET64_PR(typ, p, fld) ({ \
 103         u64 ___t = MLX5_GET64(typ, p, fld); \
 104         pr_debug(#fld " = 0x%llx\n", ___t); \
 105         ___t; \
 106 })
 107
 108 enum {
 109         MLX5_MAX_COMMANDS               = 32,
 110         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
 111         MLX5_PCI_CMD_XPORT              = 7,
 112         MLX5_MKEY_BSF_OCTO_SIZE         = 4,
 113         MLX5_MAX_PSVS                   = 4,
 114 };
 115
 116 enum {
 117         MLX5_EXTENDED_UD_AV             = 0x80000000,
 118 };
 119
 120 enum {
 121         MLX5_CQ_STATE_ARMED             = 9,
 122         MLX5_CQ_STATE_ALWAYS_ARMED      = 0xb,
 123         MLX5_CQ_STATE_FIRED             = 0xa,
 124 };
 125
 126 enum {
 127         MLX5_STAT_RATE_OFFSET   = 5,
 128 };
 129
 130 enum {
 131         MLX5_INLINE_SEG = 0x80000000,
 132 };
 133
 134 enum {
 135         MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
 136 };
 137
 138 enum {
 139         MLX5_MIN_PKEY_TABLE_SIZE = 128,
 140         MLX5_MAX_LOG_PKEY_TABLE  = 5,
 141 };
 142
 143 enum {
 144         MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
 145 };
 146
 147 enum {
 148         MLX5_PFAULT_SUBTYPE_WQE = 0,
 149         MLX5_PFAULT_SUBTYPE_RDMA = 1,
 150 };
 151
 152 enum {
 153         MLX5_PERM_LOCAL_READ    = 1 << 2,
 154         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
 155         MLX5_PERM_REMOTE_READ   = 1 << 4,
 156         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
 157         MLX5_PERM_ATOMIC        = 1 << 6,
 158         MLX5_PERM_UMR_EN        = 1 << 7,
 159 };
 160
 161 enum {
 162         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
 163         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
 164         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
 165         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
 166         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
 167 };
 168
 169 enum {
 170         MLX5_ACCESS_MODE_PA     = 0,
 171         MLX5_ACCESS_MODE_MTT    = 1,
 172         MLX5_ACCESS_MODE_KLM    = 2
 173 };
 174
 175 enum {
 176         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
 177         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
 178         MLX5_MKEY_BSF_EN        = 1 << 30,
 179         MLX5_MKEY_LEN64         = 1 << 31,
 180 };
 181
 182 enum {
 183         MLX5_EN_RD      = (u64)1,
 184         MLX5_EN_WR      = (u64)2
 185 };
 186
 187 enum {
 188         MLX5_BF_REGS_PER_PAGE           = 4,
 189         MLX5_MAX_UAR_PAGES              = 1 << 8,
 190         MLX5_NON_FP_BF_REGS_PER_PAGE    = 2,
 191         MLX5_MAX_UUARS  = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
 192 };
 193
 194 enum {
 195         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 196         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 197         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 198         MLX5_MKEY_MASK_PD               = 1ull << 7,
 199         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 200         MLX5_MKEY_MASK_EN_SIGERR        = 1ull << 9,
 201         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 202         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 203         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 204         MLX5_MKEY_MASK_LR               = 1ull << 17,
 205         MLX5_MKEY_MASK_LW               = 1ull << 18,
 206         MLX5_MKEY_MASK_RR               = 1ull << 19,
 207         MLX5_MKEY_MASK_RW               = 1ull << 20,
 208         MLX5_MKEY_MASK_A                = 1ull << 21,
 209         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 210         MLX5_MKEY_MASK_FREE             = 1ull << 29,
 211 };
 212
 213 enum {
 214         MLX5_UMR_TRANSLATION_OFFSET_EN  = (1 << 4),
 215
 216         MLX5_UMR_CHECK_NOT_FREE         = (1 << 5),
 217         MLX5_UMR_CHECK_FREE             = (2 << 5),
 218
 219         MLX5_UMR_INLINE                 = (1 << 7),
 220 };
 221
 222 #define MLX5_UMR_MTT_ALIGNMENT 0x40
 223 #define MLX5_UMR_MTT_MASK      (MLX5_UMR_MTT_ALIGNMENT - 1)
 224 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
 225
 226 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
 227
 228 enum {
 229         MLX5_EVENT_QUEUE_TYPE_QP = 0,
 230         MLX5_EVENT_QUEUE_TYPE_RQ = 1,
 231         MLX5_EVENT_QUEUE_TYPE_SQ = 2,
 232 };
 233
 234 enum mlx5_event {
 235         MLX5_EVENT_TYPE_COMP               = 0x0,
 236
 237         MLX5_EVENT_TYPE_PATH_MIG           = 0x01,
 238         MLX5_EVENT_TYPE_COMM_EST           = 0x02,
 239         MLX5_EVENT_TYPE_SQ_DRAINED         = 0x03,
 240         MLX5_EVENT_TYPE_SRQ_LAST_WQE       = 0x13,
 241         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT       = 0x14,
 242
 243         MLX5_EVENT_TYPE_CQ_ERROR           = 0x04,
 244         MLX5_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 245         MLX5_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 246         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 247         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 248         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 249
 250         MLX5_EVENT_TYPE_INTERNAL_ERROR     = 0x08,
 251         MLX5_EVENT_TYPE_PORT_CHANGE        = 0x09,
 252         MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
 253         MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
 254
 255         MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
 256         MLX5_EVENT_TYPE_STALL_EVENT        = 0x1b,
 257
 258         MLX5_EVENT_TYPE_CMD                = 0x0a,
 259         MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 260
 261         MLX5_EVENT_TYPE_PAGE_FAULT         = 0xc,
 262 };
 263
 264 enum {
 265         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 266         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 267         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 268         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 269         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 270         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 271         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 272 };
 273
 274 enum {
 275         MLX5_DEV_CAP_FLAG_XRC           = 1LL <<  3,
 276         MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
 277         MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
 278         MLX5_DEV_CAP_FLAG_APM           = 1LL << 17,
 279         MLX5_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
 280         MLX5_DEV_CAP_FLAG_BLOCK_MCAST   = 1LL << 23,
 281         MLX5_DEV_CAP_FLAG_ON_DMND_PG    = 1LL << 24,
 282         MLX5_DEV_CAP_FLAG_CQ_MODER      = 1LL << 29,
 283         MLX5_DEV_CAP_FLAG_RESIZE_CQ     = 1LL << 30,
 284         MLX5_DEV_CAP_FLAG_DCT           = 1LL << 37,
 285         MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
 286         MLX5_DEV_CAP_FLAG_CMDIF_CSUM    = 3LL << 46,
 287 };
 288
 289 enum {
 290         MLX5_ROCE_VERSION_1             = 0,
 291         MLX5_ROCE_VERSION_2             = 2,
 292 };
 293
 294 enum {
 295         MLX5_ROCE_VERSION_1_CAP         = 1 << MLX5_ROCE_VERSION_1,
 296         MLX5_ROCE_VERSION_2_CAP         = 1 << MLX5_ROCE_VERSION_2,
 297 };
 298
 299 enum {
 300         MLX5_ROCE_L3_TYPE_IPV4          = 0,
 301         MLX5_ROCE_L3_TYPE_IPV6          = 1,
 302 };
 303
 304 enum {
 305         MLX5_ROCE_L3_TYPE_IPV4_CAP      = 1 << 1,
 306         MLX5_ROCE_L3_TYPE_IPV6_CAP      = 1 << 2,
 307 };
 308
 309 enum {
 310         MLX5_OPCODE_NOP                 = 0x00,
 311         MLX5_OPCODE_SEND_INVAL          = 0x01,
 312         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 313         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 314         MLX5_OPCODE_SEND                = 0x0a,
 315         MLX5_OPCODE_SEND_IMM            = 0x0b,
 316         MLX5_OPCODE_LSO                 = 0x0e,
 317         MLX5_OPCODE_RDMA_READ           = 0x10,
 318         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 319         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 320         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 321         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 322         MLX5_OPCODE_BIND_MW             = 0x18,
 323         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 324
 325         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 326         MLX5_RECV_OPCODE_SEND           = 0x01,
 327         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 328         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 329
 330         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 331         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 332
 333         MLX5_OPCODE_SET_PSV             = 0x20,
 334         MLX5_OPCODE_GET_PSV             = 0x21,
 335         MLX5_OPCODE_CHECK_PSV           = 0x22,
 336         MLX5_OPCODE_RGET_PSV            = 0x26,
 337         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 338
 339         MLX5_OPCODE_UMR                 = 0x25,
 340
 341 };
 342
 343 enum {
 344         MLX5_SET_PORT_RESET_QKEY        = 0,
 345         MLX5_SET_PORT_GUID0             = 16,
 346         MLX5_SET_PORT_NODE_GUID         = 17,
 347         MLX5_SET_PORT_SYS_GUID          = 18,
 348         MLX5_SET_PORT_GID_TABLE         = 19,
 349         MLX5_SET_PORT_PKEY_TABLE        = 20,
 350 };
 351
 352 enum {
 353         MLX5_MAX_PAGE_SHIFT             = 31
 354 };
 355
 356 enum {
 357         MLX5_ADAPTER_PAGE_SHIFT         = 12,
 358         MLX5_ADAPTER_PAGE_SIZE          = 1 << MLX5_ADAPTER_PAGE_SHIFT,
 359 };
 360
 361 enum {
 362         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 363 };
 364
 365 struct mlx5_inbox_hdr {
 366         __be16          opcode;
 367         u8              rsvd[4];
 368         __be16          opmod;
 369 };
 370
 371 struct mlx5_outbox_hdr {
 372         u8              status;
 373         u8              rsvd[3];
 374         __be32          syndrome;
 375 };
 376
 377 struct mlx5_cmd_query_adapter_mbox_in {
 378         struct mlx5_inbox_hdr   hdr;
 379         u8                      rsvd[8];
 380 };
 381
 382 struct mlx5_cmd_query_adapter_mbox_out {
 383         struct mlx5_outbox_hdr  hdr;
 384         u8                      rsvd0[24];
 385         u8                      intapin;
 386         u8                      rsvd1[13];
 387         __be16                  vsd_vendor_id;
 388         u8                      vsd[208];
 389         u8                      vsd_psid[16];
 390 };
 391
 392 enum mlx5_odp_transport_cap_bits {
 393         MLX5_ODP_SUPPORT_SEND    = 1 << 31,
 394         MLX5_ODP_SUPPORT_RECV    = 1 << 30,
 395         MLX5_ODP_SUPPORT_WRITE   = 1 << 29,
 396         MLX5_ODP_SUPPORT_READ    = 1 << 28,
 397 };
 398
 399 struct mlx5_odp_caps {
 400         char reserved[0x10];
 401         struct {
 402                 __be32                  rc_odp_caps;
 403                 __be32                  uc_odp_caps;
 404                 __be32                  ud_odp_caps;
 405         } per_transport_caps;
 406         char reserved2[0xe4];
 407 };
 408
 409 struct mlx5_cmd_init_hca_mbox_in {
 410         struct mlx5_inbox_hdr   hdr;
 411         u8                      rsvd0[2];
 412         __be16                  profile;
 413         u8                      rsvd1[4];
 414 };
 415
 416 struct mlx5_cmd_init_hca_mbox_out {
 417         struct mlx5_outbox_hdr  hdr;
 418         u8                      rsvd[8];
 419 };
 420
 421 struct mlx5_cmd_teardown_hca_mbox_in {
 422         struct mlx5_inbox_hdr   hdr;
 423         u8                      rsvd0[2];
 424         __be16                  profile;
 425         u8                      rsvd1[4];
 426 };
 427
 428 struct mlx5_cmd_teardown_hca_mbox_out {
 429         struct mlx5_outbox_hdr  hdr;
 430         u8                      rsvd[8];
 431 };
 432
 433 struct mlx5_cmd_layout {
 434         u8              type;
 435         u8              rsvd0[3];
 436         __be32          inlen;
 437         __be64          in_ptr;
 438         __be32          in[4];
 439         __be32          out[4];
 440         __be64          out_ptr;
 441         __be32          outlen;
 442         u8              token;
 443         u8              sig;
 444         u8              rsvd1;
 445         u8              status_own;
 446 };
 447
 448
 449 struct health_buffer {
 450         __be32          assert_var[5];
 451         __be32          rsvd0[3];
 452         __be32          assert_exit_ptr;
 453         __be32          assert_callra;
 454         __be32          rsvd1[2];
 455         __be32          fw_ver;
 456         __be32          hw_id;
 457         __be32          rsvd2;
 458         u8              irisc_index;
 459         u8              synd;
 460         __be16          ext_synd;
 461 };
 462
 463 struct mlx5_init_seg {
 464         __be32                  fw_rev;
 465         __be32                  cmdif_rev_fw_sub;
 466         __be32                  rsvd0[2];
 467         __be32                  cmdq_addr_h;
 468         __be32                  cmdq_addr_l_sz;
 469         __be32                  cmd_dbell;
 470         __be32                  rsvd1[120];
 471         __be32                  initializing;
 472         struct health_buffer    health;
 473         __be32                  rsvd2[880];
 474         __be32                  internal_timer_h;
 475         __be32                  internal_timer_l;
 476         __be32                  rsvd3[2];
 477         __be32                  health_counter;
 478         __be32                  rsvd4[1019];
 479         __be64                  ieee1588_clk;
 480         __be32                  ieee1588_clk_type;
 481         __be32                  clr_intx;
 482 };
 483
 484 struct mlx5_eqe_comp {
 485         __be32  reserved[6];
 486         __be32  cqn;
 487 };
 488
 489 struct mlx5_eqe_qp_srq {
 490         __be32  reserved1[5];
 491         u8      type;
 492         u8      reserved2[3];
 493         __be32  qp_srq_n;
 494 };
 495
 496 struct mlx5_eqe_cq_err {
 497         __be32  cqn;
 498         u8      reserved1[7];
 499         u8      syndrome;
 500 };
 501
 502 struct mlx5_eqe_port_state {
 503         u8      reserved0[8];
 504         u8      port;
 505 };
 506
 507 struct mlx5_eqe_gpio {
 508         __be32  reserved0[2];
 509         __be64  gpio_event;
 510 };
 511
 512 struct mlx5_eqe_congestion {
 513         u8      type;
 514         u8      rsvd0;
 515         u8      congestion_level;
 516 };
 517
 518 struct mlx5_eqe_stall_vl {
 519         u8      rsvd0[3];
 520         u8      port_vl;
 521 };
 522
 523 struct mlx5_eqe_cmd {
 524         __be32  vector;
 525         __be32  rsvd[6];
 526 };
 527
 528 struct mlx5_eqe_page_req {
 529         u8              rsvd0[2];
 530         __be16          func_id;
 531         __be32          num_pages;
 532         __be32          rsvd1[5];
 533 };
 534
 535 struct mlx5_eqe_page_fault {
 536         __be32 bytes_committed;
 537         union {
 538                 struct {
 539                         u16     reserved1;
 540                         __be16  wqe_index;
 541                         u16     reserved2;
 542                         __be16  packet_length;
 543                         u8      reserved3[12];
 544                 } __packed wqe;
 545                 struct {
 546                         __be32  r_key;
 547                         u16     reserved1;
 548                         __be16  packet_length;
 549                         __be32  rdma_op_len;
 550                         __be64  rdma_va;
 551                 } __packed rdma;
 552         } __packed;
 553         __be32 flags_qpn;
 554 } __packed;
 555
 556 union ev_data {
 557         __be32                          raw[7];
 558         struct mlx5_eqe_cmd             cmd;
 559         struct mlx5_eqe_comp            comp;
 560         struct mlx5_eqe_qp_srq          qp_srq;
 561         struct mlx5_eqe_cq_err          cq_err;
 562         struct mlx5_eqe_port_state      port;
 563         struct mlx5_eqe_gpio            gpio;
 564         struct mlx5_eqe_congestion      cong;
 565         struct mlx5_eqe_stall_vl        stall_vl;
 566         struct mlx5_eqe_page_req        req_pages;
 567         struct mlx5_eqe_page_fault      page_fault;
 568 } __packed;
 569
 570 struct mlx5_eqe {
 571         u8              rsvd0;
 572         u8              type;
 573         u8              rsvd1;
 574         u8              sub_type;
 575         __be32          rsvd2[7];
 576         union ev_data   data;
 577         __be16          rsvd3;
 578         u8              signature;
 579         u8              owner;
 580 } __packed;
 581
 582 struct mlx5_cmd_prot_block {
 583         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 584         u8              rsvd0[48];
 585         __be64          next;
 586         __be32          block_num;
 587         u8              rsvd1;
 588         u8              token;
 589         u8              ctrl_sig;
 590         u8              sig;
 591 };
 592
 593 enum {
 594         MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
 595 };
 596
 597 struct mlx5_err_cqe {
 598         u8      rsvd0[32];
 599         __be32  srqn;
 600         u8      rsvd1[18];
 601         u8      vendor_err_synd;
 602         u8      syndrome;
 603         __be32  s_wqe_opcode_qpn;
 604         __be16  wqe_counter;
 605         u8      signature;
 606         u8      op_own;
 607 };
 608
 609 struct mlx5_cqe64 {
 610         u8              rsvd0[4];
 611         u8              lro_tcppsh_abort_dupack;
 612         u8              lro_min_ttl;
 613         __be16          lro_tcp_win;
 614         __be32          lro_ack_seq_num;
 615         __be32          rss_hash_result;
 616         u8              rss_hash_type;
 617         u8              ml_path;
 618         u8              rsvd20[2];
 619         __be16          check_sum;
 620         __be16          slid;
 621         __be32          flags_rqpn;
 622         u8              hds_ip_ext;
 623         u8              l4_hdr_type_etc;
 624         __be16          vlan_info;
 625         __be32          srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
 626         __be32          imm_inval_pkey;
 627         u8              rsvd40[4];
 628         __be32          byte_cnt;
 629         __be64          timestamp;
 630         __be32          sop_drop_qpn;
 631         __be16          wqe_counter;
 632         u8              signature;
 633         u8              op_own;
 634 };
 635
 636 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
 637 {
 638         return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
 639 }
 640
 641 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
 642 {
 643         return (cqe->l4_hdr_type_etc >> 4) & 0x7;
 644 }
 645
 646 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
 647 {
 648         return !!(cqe->l4_hdr_type_etc & 0x1);
 649 }
 650
 651 enum {
 652         CQE_L4_HDR_TYPE_NONE                    = 0x0,
 653         CQE_L4_HDR_TYPE_TCP_NO_ACK              = 0x1,
 654         CQE_L4_HDR_TYPE_UDP                     = 0x2,
 655         CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA         = 0x3,
 656         CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA        = 0x4,
 657 };
 658
 659 enum {
 660         CQE_RSS_HTYPE_IP        = 0x3 << 6,
 661         CQE_RSS_HTYPE_L4        = 0x3 << 2,
 662 };
 663
 664 enum {
 665         MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH        = 0x0,
 666         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6       = 0x1,
 667         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4       = 0x2,
 668 };
 669
 670 enum {
 671         CQE_L2_OK       = 1 << 0,
 672         CQE_L3_OK       = 1 << 1,
 673         CQE_L4_OK       = 1 << 2,
 674 };
 675
 676 struct mlx5_sig_err_cqe {
 677         u8              rsvd0[16];
 678         __be32          expected_trans_sig;
 679         __be32          actual_trans_sig;
 680         __be32          expected_reftag;
 681         __be32          actual_reftag;
 682         __be16          syndrome;
 683         u8              rsvd22[2];
 684         __be32          mkey;
 685         __be64          err_offset;
 686         u8              rsvd30[8];
 687         __be32          qpn;
 688         u8              rsvd38[2];
 689         u8              signature;
 690         u8              op_own;
 691 };
 692
 693 struct mlx5_wqe_srq_next_seg {
 694         u8                      rsvd0[2];
 695         __be16                  next_wqe_index;
 696         u8                      signature;
 697         u8                      rsvd1[11];
 698 };
 699
 700 union mlx5_ext_cqe {
 701         struct ib_grh   grh;
 702         u8              inl[64];
 703 };
 704
 705 struct mlx5_cqe128 {
 706         union mlx5_ext_cqe      inl_grh;
 707         struct mlx5_cqe64       cqe64;
 708 };
 709
 710 struct mlx5_srq_ctx {
 711         u8                      state_log_sz;
 712         u8                      rsvd0[3];
 713         __be32                  flags_xrcd;
 714         __be32                  pgoff_cqn;
 715         u8                      rsvd1[4];
 716         u8                      log_pg_sz;
 717         u8                      rsvd2[7];
 718         __be32                  pd;
 719         __be16                  lwm;
 720         __be16                  wqe_cnt;
 721         u8                      rsvd3[8];
 722         __be64                  db_record;
 723 };
 724
 725 struct mlx5_create_srq_mbox_in {
 726         struct mlx5_inbox_hdr   hdr;
 727         __be32                  input_srqn;
 728         u8                      rsvd0[4];
 729         struct mlx5_srq_ctx     ctx;
 730         u8                      rsvd1[208];
 731         __be64                  pas[0];
 732 };
 733
 734 struct mlx5_create_srq_mbox_out {
 735         struct mlx5_outbox_hdr  hdr;
 736         __be32                  srqn;
 737         u8                      rsvd[4];
 738 };
 739
 740 struct mlx5_destroy_srq_mbox_in {
 741         struct mlx5_inbox_hdr   hdr;
 742         __be32                  srqn;
 743         u8                      rsvd[4];
 744 };
 745
 746 struct mlx5_destroy_srq_mbox_out {
 747         struct mlx5_outbox_hdr  hdr;
 748         u8                      rsvd[8];
 749 };
 750
 751 struct mlx5_query_srq_mbox_in {
 752         struct mlx5_inbox_hdr   hdr;
 753         __be32                  srqn;
 754         u8                      rsvd0[4];
 755 };
 756
 757 struct mlx5_query_srq_mbox_out {
 758         struct mlx5_outbox_hdr  hdr;
 759         u8                      rsvd0[8];
 760         struct mlx5_srq_ctx     ctx;
 761         u8                      rsvd1[32];
 762         __be64                  pas[0];
 763 };
 764
 765 struct mlx5_arm_srq_mbox_in {
 766         struct mlx5_inbox_hdr   hdr;
 767         __be32                  srqn;
 768         __be16                  rsvd;
 769         __be16                  lwm;
 770 };
 771
 772 struct mlx5_arm_srq_mbox_out {
 773         struct mlx5_outbox_hdr  hdr;
 774         u8                      rsvd[8];
 775 };
 776
 777 struct mlx5_cq_context {
 778         u8                      status;
 779         u8                      cqe_sz_flags;
 780         u8                      st;
 781         u8                      rsvd3;
 782         u8                      rsvd4[6];
 783         __be16                  page_offset;
 784         __be32                  log_sz_usr_page;
 785         __be16                  cq_period;
 786         __be16                  cq_max_count;
 787         __be16                  rsvd20;
 788         __be16                  c_eqn;
 789         u8                      log_pg_sz;
 790         u8                      rsvd25[7];
 791         __be32                  last_notified_index;
 792         __be32                  solicit_producer_index;
 793         __be32                  consumer_counter;
 794         __be32                  producer_counter;
 795         u8                      rsvd48[8];
 796         __be64                  db_record_addr;
 797 };
 798
 799 struct mlx5_create_cq_mbox_in {
 800         struct mlx5_inbox_hdr   hdr;
 801         __be32                  input_cqn;
 802         u8                      rsvdx[4];
 803         struct mlx5_cq_context  ctx;
 804         u8                      rsvd6[192];
 805         __be64                  pas[0];
 806 };
 807
 808 struct mlx5_create_cq_mbox_out {
 809         struct mlx5_outbox_hdr  hdr;
 810         __be32                  cqn;
 811         u8                      rsvd0[4];
 812 };
 813
 814 struct mlx5_destroy_cq_mbox_in {
 815         struct mlx5_inbox_hdr   hdr;
 816         __be32                  cqn;
 817         u8                      rsvd0[4];
 818 };
 819
 820 struct mlx5_destroy_cq_mbox_out {
 821         struct mlx5_outbox_hdr  hdr;
 822         u8                      rsvd0[8];
 823 };
 824
 825 struct mlx5_query_cq_mbox_in {
 826         struct mlx5_inbox_hdr   hdr;
 827         __be32                  cqn;
 828         u8                      rsvd0[4];
 829 };
 830
 831 struct mlx5_query_cq_mbox_out {
 832         struct mlx5_outbox_hdr  hdr;
 833         u8                      rsvd0[8];
 834         struct mlx5_cq_context  ctx;
 835         u8                      rsvd6[16];
 836         __be64                  pas[0];
 837 };
 838
 839 struct mlx5_modify_cq_mbox_in {
 840         struct mlx5_inbox_hdr   hdr;
 841         __be32                  cqn;
 842         __be32                  field_select;
 843         struct mlx5_cq_context  ctx;
 844         u8                      rsvd[192];
 845         __be64                  pas[0];
 846 };
 847
 848 struct mlx5_modify_cq_mbox_out {
 849         struct mlx5_outbox_hdr  hdr;
 850         u8                      rsvd[8];
 851 };
 852
 853 struct mlx5_enable_hca_mbox_in {
 854         struct mlx5_inbox_hdr   hdr;
 855         u8                      rsvd[8];
 856 };
 857
 858 struct mlx5_enable_hca_mbox_out {
 859         struct mlx5_outbox_hdr  hdr;
 860         u8                      rsvd[8];
 861 };
 862
 863 struct mlx5_disable_hca_mbox_in {
 864         struct mlx5_inbox_hdr   hdr;
 865         u8                      rsvd[8];
 866 };
 867
 868 struct mlx5_disable_hca_mbox_out {
 869         struct mlx5_outbox_hdr  hdr;
 870         u8                      rsvd[8];
 871 };
 872
 873 struct mlx5_eq_context {
 874         u8                      status;
 875         u8                      ec_oi;
 876         u8                      st;
 877         u8                      rsvd2[7];
 878         __be16                  page_pffset;
 879         __be32                  log_sz_usr_page;
 880         u8                      rsvd3[7];
 881         u8                      intr;
 882         u8                      log_page_size;
 883         u8                      rsvd4[15];
 884         __be32                  consumer_counter;
 885         __be32                  produser_counter;
 886         u8                      rsvd5[16];
 887 };
 888
 889 struct mlx5_create_eq_mbox_in {
 890         struct mlx5_inbox_hdr   hdr;
 891         u8                      rsvd0[3];
 892         u8                      input_eqn;
 893         u8                      rsvd1[4];
 894         struct mlx5_eq_context  ctx;
 895         u8                      rsvd2[8];
 896         __be64                  events_mask;
 897         u8                      rsvd3[176];
 898         __be64                  pas[0];
 899 };
 900
 901 struct mlx5_create_eq_mbox_out {
 902         struct mlx5_outbox_hdr  hdr;
 903         u8                      rsvd0[3];
 904         u8                      eq_number;
 905         u8                      rsvd1[4];
 906 };
 907
 908 struct mlx5_destroy_eq_mbox_in {
 909         struct mlx5_inbox_hdr   hdr;
 910         u8                      rsvd0[3];
 911         u8                      eqn;
 912         u8                      rsvd1[4];
 913 };
 914
 915 struct mlx5_destroy_eq_mbox_out {
 916         struct mlx5_outbox_hdr  hdr;
 917         u8                      rsvd[8];
 918 };
 919
 920 struct mlx5_map_eq_mbox_in {
 921         struct mlx5_inbox_hdr   hdr;
 922         __be64                  mask;
 923         u8                      mu;
 924         u8                      rsvd0[2];
 925         u8                      eqn;
 926         u8                      rsvd1[24];
 927 };
 928
 929 struct mlx5_map_eq_mbox_out {
 930         struct mlx5_outbox_hdr  hdr;
 931         u8                      rsvd[8];
 932 };
 933
 934 struct mlx5_query_eq_mbox_in {
 935         struct mlx5_inbox_hdr   hdr;
 936         u8                      rsvd0[3];
 937         u8                      eqn;
 938         u8                      rsvd1[4];
 939 };
 940
 941 struct mlx5_query_eq_mbox_out {
 942         struct mlx5_outbox_hdr  hdr;
 943         u8                      rsvd[8];
 944         struct mlx5_eq_context  ctx;
 945 };
 946
 947 enum {
 948         MLX5_MKEY_STATUS_FREE = 1 << 6,
 949 };
 950
 951 struct mlx5_mkey_seg {
 952         /* This is a two bit field occupying bits 31-30.
 953          * bit 31 is always 0,
 954          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
 955          */
 956         u8              status;
 957         u8              pcie_control;
 958         u8              flags;
 959         u8              version;
 960         __be32          qpn_mkey7_0;
 961         u8              rsvd1[4];
 962         __be32          flags_pd;
 963         __be64          start_addr;
 964         __be64          len;
 965         __be32          bsfs_octo_size;
 966         u8              rsvd2[16];
 967         __be32          xlt_oct_size;
 968         u8              rsvd3[3];
 969         u8              log2_page_size;
 970         u8              rsvd4[4];
 971 };
 972
 973 struct mlx5_query_special_ctxs_mbox_in {
 974         struct mlx5_inbox_hdr   hdr;
 975         u8                      rsvd[8];
 976 };
 977
 978 struct mlx5_query_special_ctxs_mbox_out {
 979         struct mlx5_outbox_hdr  hdr;
 980         __be32                  dump_fill_mkey;
 981         __be32                  reserved_lkey;
 982 };
 983
 984 struct mlx5_create_mkey_mbox_in {
 985         struct mlx5_inbox_hdr   hdr;
 986         __be32                  input_mkey_index;
 987         __be32                  flags;
 988         struct mlx5_mkey_seg    seg;
 989         u8                      rsvd1[16];
 990         __be32                  xlat_oct_act_size;
 991         __be32                  rsvd2;
 992         u8                      rsvd3[168];
 993         __be64                  pas[0];
 994 };
 995
 996 struct mlx5_create_mkey_mbox_out {
 997         struct mlx5_outbox_hdr  hdr;
 998         __be32                  mkey;
 999         u8                      rsvd[4];
1000 };
1001
1002 struct mlx5_destroy_mkey_mbox_in {
1003         struct mlx5_inbox_hdr   hdr;
1004         __be32                  mkey;
1005         u8                      rsvd[4];
1006 };
1007
1008 struct mlx5_destroy_mkey_mbox_out {
1009         struct mlx5_outbox_hdr  hdr;
1010         u8                      rsvd[8];
1011 };
1012
1013 struct mlx5_query_mkey_mbox_in {
1014         struct mlx5_inbox_hdr   hdr;
1015         __be32                  mkey;
1016 };
1017
1018 struct mlx5_query_mkey_mbox_out {
1019         struct mlx5_outbox_hdr  hdr;
1020         __be64                  pas[0];
1021 };
1022
1023 struct mlx5_modify_mkey_mbox_in {
1024         struct mlx5_inbox_hdr   hdr;
1025         __be32                  mkey;
1026         __be64                  pas[0];
1027 };
1028
1029 struct mlx5_modify_mkey_mbox_out {
1030         struct mlx5_outbox_hdr  hdr;
1031         u8                      rsvd[8];
1032 };
1033
1034 struct mlx5_dump_mkey_mbox_in {
1035         struct mlx5_inbox_hdr   hdr;
1036 };
1037
1038 struct mlx5_dump_mkey_mbox_out {
1039         struct mlx5_outbox_hdr  hdr;
1040         __be32                  mkey;
1041 };
1042
1043 struct mlx5_mad_ifc_mbox_in {
1044         struct mlx5_inbox_hdr   hdr;
1045         __be16                  remote_lid;
1046         u8                      rsvd0;
1047         u8                      port;
1048         u8                      rsvd1[4];
1049         u8                      data[256];
1050 };
1051
1052 struct mlx5_mad_ifc_mbox_out {
1053         struct mlx5_outbox_hdr  hdr;
1054         u8                      rsvd[8];
1055         u8                      data[256];
1056 };
1057
1058 struct mlx5_access_reg_mbox_in {
1059         struct mlx5_inbox_hdr           hdr;
1060         u8                              rsvd0[2];
1061         __be16                          register_id;
1062         __be32                          arg;
1063         __be32                          data[0];
1064 };
1065
1066 struct mlx5_access_reg_mbox_out {
1067         struct mlx5_outbox_hdr          hdr;
1068         u8                              rsvd[8];
1069         __be32                          data[0];
1070 };
1071
1072 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
1073
1074 enum {
1075         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
1076 };
1077
1078 struct mlx5_allocate_psv_in {
1079         struct mlx5_inbox_hdr   hdr;
1080         __be32                  npsv_pd;
1081         __be32                  rsvd_psv0;
1082 };
1083
1084 struct mlx5_allocate_psv_out {
1085         struct mlx5_outbox_hdr  hdr;
1086         u8                      rsvd[8];
1087         __be32                  psv_idx[4];
1088 };
1089
1090 struct mlx5_destroy_psv_in {
1091         struct mlx5_inbox_hdr   hdr;
1092         __be32                  psv_number;
1093         u8                      rsvd[4];
1094 };
1095
1096 struct mlx5_destroy_psv_out {
1097         struct mlx5_outbox_hdr  hdr;
1098         u8                      rsvd[8];
1099 };
1100
1101 #define MLX5_CMD_OP_MAX 0x920
1102
1103 enum {
1104         VPORT_STATE_DOWN                = 0x0,
1105         VPORT_STATE_UP                  = 0x1,
1106 };
1107
1108 enum {
1109         MLX5_L3_PROT_TYPE_IPV4          = 0,
1110         MLX5_L3_PROT_TYPE_IPV6          = 1,
1111 };
1112
1113 enum {
1114         MLX5_L4_PROT_TYPE_TCP           = 0,
1115         MLX5_L4_PROT_TYPE_UDP           = 1,
1116 };
1117
1118 enum {
1119         MLX5_HASH_FIELD_SEL_SRC_IP      = 1 << 0,
1120         MLX5_HASH_FIELD_SEL_DST_IP      = 1 << 1,
1121         MLX5_HASH_FIELD_SEL_L4_SPORT    = 1 << 2,
1122         MLX5_HASH_FIELD_SEL_L4_DPORT    = 1 << 3,
1123         MLX5_HASH_FIELD_SEL_IPSEC_SPI   = 1 << 4,
1124 };
1125
1126 enum {
1127         MLX5_MATCH_OUTER_HEADERS        = 1 << 0,
1128         MLX5_MATCH_MISC_PARAMETERS      = 1 << 1,
1129         MLX5_MATCH_INNER_HEADERS        = 1 << 2,
1130
1131 };
1132
1133 enum {
1134         MLX5_FLOW_TABLE_TYPE_NIC_RCV    = 0,
1135         MLX5_FLOW_TABLE_TYPE_ESWITCH    = 4,
1136 };
1137
1138 enum {
1139         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT       = 0,
1140         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE  = 1,
1141         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR         = 2,
1142 };
1143
1144 enum {
1145         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1146         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM    = 0x1,
1147 };
1148
1149 /* MLX5 DEV CAPs */
1150
1151 /* TODO: EAT.ME */
1152 enum mlx5_cap_mode {
1153         HCA_CAP_OPMOD_GET_MAX   = 0,
1154         HCA_CAP_OPMOD_GET_CUR   = 1,
1155 };
1156
1157 enum mlx5_cap_type {
1158         MLX5_CAP_GENERAL = 0,
1159         MLX5_CAP_ETHERNET_OFFLOADS,
1160         MLX5_CAP_ODP,
1161         MLX5_CAP_ATOMIC,
1162         MLX5_CAP_ROCE,
1163         MLX5_CAP_IPOIB_OFFLOADS,
1164         MLX5_CAP_EOIB_OFFLOADS,
1165         MLX5_CAP_FLOW_TABLE,
1166         /* NUM OF CAP Types */
1167         MLX5_CAP_NUM
1168 };
1169
1170 /* GET Dev Caps macros */
1171 #define MLX5_CAP_GEN(mdev, cap) \
1172         MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1173
1174 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1175         MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1176
1177 #define MLX5_CAP_ETH(mdev, cap) \
1178         MLX5_GET(per_protocol_networking_offload_caps,\
1179                  mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1180
1181 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1182         MLX5_GET(per_protocol_networking_offload_caps,\
1183                  mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1184
1185 #define MLX5_CAP_ROCE(mdev, cap) \
1186         MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1187
1188 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1189         MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1190
1191 #define MLX5_CAP_ATOMIC(mdev, cap) \
1192         MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1193
1194 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1195         MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1196
1197 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1198         MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1199
1200 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1201         MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1202
1203 #define MLX5_CAP_ODP(mdev, cap)\
1204         MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1205
1206 enum {
1207         MLX5_CMD_STAT_OK                        = 0x0,
1208         MLX5_CMD_STAT_INT_ERR                   = 0x1,
1209         MLX5_CMD_STAT_BAD_OP_ERR                = 0x2,
1210         MLX5_CMD_STAT_BAD_PARAM_ERR             = 0x3,
1211         MLX5_CMD_STAT_BAD_SYS_STATE_ERR         = 0x4,
1212         MLX5_CMD_STAT_BAD_RES_ERR               = 0x5,
1213         MLX5_CMD_STAT_RES_BUSY                  = 0x6,
1214         MLX5_CMD_STAT_LIM_ERR                   = 0x8,
1215         MLX5_CMD_STAT_BAD_RES_STATE_ERR         = 0x9,
1216         MLX5_CMD_STAT_IX_ERR                    = 0xa,
1217         MLX5_CMD_STAT_NO_RES_ERR                = 0xf,
1218         MLX5_CMD_STAT_BAD_INP_LEN_ERR           = 0x50,
1219         MLX5_CMD_STAT_BAD_OUTP_LEN_ERR          = 0x51,
1220         MLX5_CMD_STAT_BAD_QP_STATE_ERR          = 0x10,
1221         MLX5_CMD_STAT_BAD_PKT_ERR               = 0x30,
1222         MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR    = 0x40,
1223 };
1224
1225 enum {
1226         MLX5_IEEE_802_3_COUNTERS_GROUP        = 0x0,
1227         MLX5_RFC_2863_COUNTERS_GROUP          = 0x1,
1228         MLX5_RFC_2819_COUNTERS_GROUP          = 0x2,
1229         MLX5_RFC_3635_COUNTERS_GROUP          = 0x3,
1230         MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1231         MLX5_PER_PRIORITY_COUNTERS_GROUP      = 0x10,
1232         MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11
1233 };
1234
1235 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1236 {
1237         if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1238                 return 0;
1239         return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1240 }
1241
1242 #endif /* MLX5_DEVICE_H */