include/linux/mlx5/device.h

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DEVICE_H
  34 #define MLX5_DEVICE_H
  35
  36 #include <linux/types.h>
  37 #include <rdma/ib_verbs.h>
  38
  39 #if defined(__LITTLE_ENDIAN)
  40 #define MLX5_SET_HOST_ENDIANNESS        0
  41 #elif defined(__BIG_ENDIAN)
  42 #define MLX5_SET_HOST_ENDIANNESS        0x80
  43 #else
  44 #error Host endianness not defined
  45 #endif
  46
  47 enum {
  48         MLX5_MAX_COMMANDS               = 32,
  49         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
  50         MLX5_PCI_CMD_XPORT              = 7,
  51         MLX5_MKEY_BSF_OCTO_SIZE         = 4,
  52         MLX5_MAX_PSVS                   = 4,
  53 };
  54
  55 enum {
  56         MLX5_EXTENDED_UD_AV             = 0x80000000,
  57 };
  58
  59 enum {
  60         MLX5_CQ_STATE_ARMED             = 9,
  61         MLX5_CQ_STATE_ALWAYS_ARMED      = 0xb,
  62         MLX5_CQ_STATE_FIRED             = 0xa,
  63 };
  64
  65 enum {
  66         MLX5_STAT_RATE_OFFSET   = 5,
  67 };
  68
  69 enum {
  70         MLX5_INLINE_SEG = 0x80000000,
  71 };
  72
  73 enum {
  74         MLX5_MIN_PKEY_TABLE_SIZE = 128,
  75         MLX5_MAX_LOG_PKEY_TABLE  = 5,
  76 };
  77
  78 enum {
  79         MLX5_PERM_LOCAL_READ    = 1 << 2,
  80         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
  81         MLX5_PERM_REMOTE_READ   = 1 << 4,
  82         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
  83         MLX5_PERM_ATOMIC        = 1 << 6,
  84         MLX5_PERM_UMR_EN        = 1 << 7,
  85 };
  86
  87 enum {
  88         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
  89         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
  90         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
  91         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
  92         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
  93 };
  94
  95 enum {
  96         MLX5_ACCESS_MODE_PA     = 0,
  97         MLX5_ACCESS_MODE_MTT    = 1,
  98         MLX5_ACCESS_MODE_KLM    = 2
  99 };
 100
 101 enum {
 102         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
 103         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
 104         MLX5_MKEY_BSF_EN        = 1 << 30,
 105         MLX5_MKEY_LEN64         = 1 << 31,
 106 };
 107
 108 enum {
 109         MLX5_EN_RD      = (u64)1,
 110         MLX5_EN_WR      = (u64)2
 111 };
 112
 113 enum {
 114         MLX5_BF_REGS_PER_PAGE           = 4,
 115         MLX5_MAX_UAR_PAGES              = 1 << 8,
 116         MLX5_NON_FP_BF_REGS_PER_PAGE    = 2,
 117         MLX5_MAX_UUARS  = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
 118 };
 119
 120 enum {
 121         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 122         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 123         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 124         MLX5_MKEY_MASK_PD               = 1ull << 7,
 125         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 126         MLX5_MKEY_MASK_EN_SIGERR        = 1ull << 9,
 127         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 128         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 129         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 130         MLX5_MKEY_MASK_LR               = 1ull << 17,
 131         MLX5_MKEY_MASK_LW               = 1ull << 18,
 132         MLX5_MKEY_MASK_RR               = 1ull << 19,
 133         MLX5_MKEY_MASK_RW               = 1ull << 20,
 134         MLX5_MKEY_MASK_A                = 1ull << 21,
 135         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 136         MLX5_MKEY_MASK_FREE             = 1ull << 29,
 137 };
 138
 139 enum mlx5_event {
 140         MLX5_EVENT_TYPE_COMP               = 0x0,
 141
 142         MLX5_EVENT_TYPE_PATH_MIG           = 0x01,
 143         MLX5_EVENT_TYPE_COMM_EST           = 0x02,
 144         MLX5_EVENT_TYPE_SQ_DRAINED         = 0x03,
 145         MLX5_EVENT_TYPE_SRQ_LAST_WQE       = 0x13,
 146         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT       = 0x14,
 147
 148         MLX5_EVENT_TYPE_CQ_ERROR           = 0x04,
 149         MLX5_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 150         MLX5_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 151         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 152         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 153         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 154
 155         MLX5_EVENT_TYPE_INTERNAL_ERROR     = 0x08,
 156         MLX5_EVENT_TYPE_PORT_CHANGE        = 0x09,
 157         MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
 158         MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
 159
 160         MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
 161         MLX5_EVENT_TYPE_STALL_EVENT        = 0x1b,
 162
 163         MLX5_EVENT_TYPE_CMD                = 0x0a,
 164         MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 165 };
 166
 167 enum {
 168         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 169         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 170         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 171         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 172         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 173         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 174         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 175 };
 176
 177 enum {
 178         MLX5_DEV_CAP_FLAG_RC            = 1LL <<  0,
 179         MLX5_DEV_CAP_FLAG_UC            = 1LL <<  1,
 180         MLX5_DEV_CAP_FLAG_UD            = 1LL <<  2,
 181         MLX5_DEV_CAP_FLAG_XRC           = 1LL <<  3,
 182         MLX5_DEV_CAP_FLAG_SRQ           = 1LL <<  6,
 183         MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
 184         MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
 185         MLX5_DEV_CAP_FLAG_APM           = 1LL << 17,
 186         MLX5_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
 187         MLX5_DEV_CAP_FLAG_BLOCK_MCAST   = 1LL << 23,
 188         MLX5_DEV_CAP_FLAG_ON_DMND_PG    = 1LL << 24,
 189         MLX5_DEV_CAP_FLAG_CQ_MODER      = 1LL << 29,
 190         MLX5_DEV_CAP_FLAG_RESIZE_CQ     = 1LL << 30,
 191         MLX5_DEV_CAP_FLAG_RESIZE_SRQ    = 1LL << 32,
 192         MLX5_DEV_CAP_FLAG_DCT           = 1LL << 37,
 193         MLX5_DEV_CAP_FLAG_REMOTE_FENCE  = 1LL << 38,
 194         MLX5_DEV_CAP_FLAG_TLP_HINTS     = 1LL << 39,
 195         MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
 196         MLX5_DEV_CAP_FLAG_CMDIF_CSUM    = 3LL << 46,
 197 };
 198
 199 enum {
 200         MLX5_OPCODE_NOP                 = 0x00,
 201         MLX5_OPCODE_SEND_INVAL          = 0x01,
 202         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 203         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 204         MLX5_OPCODE_SEND                = 0x0a,
 205         MLX5_OPCODE_SEND_IMM            = 0x0b,
 206         MLX5_OPCODE_RDMA_READ           = 0x10,
 207         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 208         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 209         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 210         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 211         MLX5_OPCODE_BIND_MW             = 0x18,
 212         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 213
 214         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 215         MLX5_RECV_OPCODE_SEND           = 0x01,
 216         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 217         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 218
 219         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 220         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 221
 222         MLX5_OPCODE_SET_PSV             = 0x20,
 223         MLX5_OPCODE_GET_PSV             = 0x21,
 224         MLX5_OPCODE_CHECK_PSV           = 0x22,
 225         MLX5_OPCODE_RGET_PSV            = 0x26,
 226         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 227
 228         MLX5_OPCODE_UMR                 = 0x25,
 229
 230 };
 231
 232 enum {
 233         MLX5_SET_PORT_RESET_QKEY        = 0,
 234         MLX5_SET_PORT_GUID0             = 16,
 235         MLX5_SET_PORT_NODE_GUID         = 17,
 236         MLX5_SET_PORT_SYS_GUID          = 18,
 237         MLX5_SET_PORT_GID_TABLE         = 19,
 238         MLX5_SET_PORT_PKEY_TABLE        = 20,
 239 };
 240
 241 enum {
 242         MLX5_MAX_PAGE_SHIFT             = 31
 243 };
 244
 245 enum {
 246         MLX5_ADAPTER_PAGE_SHIFT         = 12,
 247         MLX5_ADAPTER_PAGE_SIZE          = 1 << MLX5_ADAPTER_PAGE_SHIFT,
 248 };
 249
 250 enum {
 251         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 252 };
 253
 254 enum {
 255         HCA_CAP_OPMOD_GET_MAX   = 0,
 256         HCA_CAP_OPMOD_GET_CUR   = 1,
 257 };
 258
 259 struct mlx5_inbox_hdr {
 260         __be16          opcode;
 261         u8              rsvd[4];
 262         __be16          opmod;
 263 };
 264
 265 struct mlx5_outbox_hdr {
 266         u8              status;
 267         u8              rsvd[3];
 268         __be32          syndrome;
 269 };
 270
 271 struct mlx5_cmd_query_adapter_mbox_in {
 272         struct mlx5_inbox_hdr   hdr;
 273         u8                      rsvd[8];
 274 };
 275
 276 struct mlx5_cmd_query_adapter_mbox_out {
 277         struct mlx5_outbox_hdr  hdr;
 278         u8                      rsvd0[24];
 279         u8                      intapin;
 280         u8                      rsvd1[13];
 281         __be16                  vsd_vendor_id;
 282         u8                      vsd[208];
 283         u8                      vsd_psid[16];
 284 };
 285
 286 struct mlx5_hca_cap {
 287         u8      rsvd1[16];
 288         u8      log_max_srq_sz;
 289         u8      log_max_qp_sz;
 290         u8      rsvd2;
 291         u8      log_max_qp;
 292         u8      log_max_strq_sz;
 293         u8      log_max_srqs;
 294         u8      rsvd4[2];
 295         u8      rsvd5;
 296         u8      log_max_cq_sz;
 297         u8      rsvd6;
 298         u8      log_max_cq;
 299         u8      log_max_eq_sz;
 300         u8      log_max_mkey;
 301         u8      rsvd7;
 302         u8      log_max_eq;
 303         u8      max_indirection;
 304         u8      log_max_mrw_sz;
 305         u8      log_max_bsf_list_sz;
 306         u8      log_max_klm_list_sz;
 307         u8      rsvd_8_0;
 308         u8      log_max_ra_req_dc;
 309         u8      rsvd_8_1;
 310         u8      log_max_ra_res_dc;
 311         u8      rsvd9;
 312         u8      log_max_ra_req_qp;
 313         u8      rsvd10;
 314         u8      log_max_ra_res_qp;
 315         u8      pad_cap;
 316         u8      rsvd11[3];
 317         __be16  max_qp_count;
 318         __be16  pkey_table_size;
 319         u8      rsvd13;
 320         u8      local_ca_ack_delay;
 321         u8      rsvd14;
 322         u8      num_ports;
 323         u8      log_max_msg;
 324         u8      rsvd15[3];
 325         __be16  stat_rate_support;
 326         u8      rsvd16[2];
 327         __be64  flags;
 328         u8      rsvd17;
 329         u8      uar_sz;
 330         u8      rsvd18;
 331         u8      log_pg_sz;
 332         __be16  bf_log_bf_reg_size;
 333         u8      rsvd19[4];
 334         __be16  max_desc_sz_sq;
 335         u8      rsvd20[2];
 336         __be16  max_desc_sz_rq;
 337         u8      rsvd21[2];
 338         __be16  max_desc_sz_sq_dc;
 339         __be32  max_qp_mcg;
 340         u8      rsvd22[3];
 341         u8      log_max_mcg;
 342         u8      rsvd23;
 343         u8      log_max_pd;
 344         u8      rsvd24;
 345         u8      log_max_xrcd;
 346         u8      rsvd25[42];
 347         __be16  log_uar_page_sz;
 348         u8      rsvd26[108];
 349 };
 350
 351
 352 struct mlx5_cmd_query_hca_cap_mbox_in {
 353         struct mlx5_inbox_hdr   hdr;
 354         u8                      rsvd[8];
 355 };
 356
 357
 358 struct mlx5_cmd_query_hca_cap_mbox_out {
 359         struct mlx5_outbox_hdr  hdr;
 360         u8                      rsvd0[8];
 361         struct mlx5_hca_cap     hca_cap;
 362 };
 363
 364
 365 struct mlx5_cmd_set_hca_cap_mbox_in {
 366         struct mlx5_inbox_hdr   hdr;
 367         u8                      rsvd[8];
 368         struct mlx5_hca_cap     hca_cap;
 369 };
 370
 371
 372 struct mlx5_cmd_set_hca_cap_mbox_out {
 373         struct mlx5_outbox_hdr  hdr;
 374         u8                      rsvd0[8];
 375 };
 376
 377
 378 struct mlx5_cmd_init_hca_mbox_in {
 379         struct mlx5_inbox_hdr   hdr;
 380         u8                      rsvd0[2];
 381         __be16                  profile;
 382         u8                      rsvd1[4];
 383 };
 384
 385 struct mlx5_cmd_init_hca_mbox_out {
 386         struct mlx5_outbox_hdr  hdr;
 387         u8                      rsvd[8];
 388 };
 389
 390 struct mlx5_cmd_teardown_hca_mbox_in {
 391         struct mlx5_inbox_hdr   hdr;
 392         u8                      rsvd0[2];
 393         __be16                  profile;
 394         u8                      rsvd1[4];
 395 };
 396
 397 struct mlx5_cmd_teardown_hca_mbox_out {
 398         struct mlx5_outbox_hdr  hdr;
 399         u8                      rsvd[8];
 400 };
 401
 402 struct mlx5_cmd_layout {
 403         u8              type;
 404         u8              rsvd0[3];
 405         __be32          inlen;
 406         __be64          in_ptr;
 407         __be32          in[4];
 408         __be32          out[4];
 409         __be64          out_ptr;
 410         __be32          outlen;
 411         u8              token;
 412         u8              sig;
 413         u8              rsvd1;
 414         u8              status_own;
 415 };
 416
 417
 418 struct health_buffer {
 419         __be32          assert_var[5];
 420         __be32          rsvd0[3];
 421         __be32          assert_exit_ptr;
 422         __be32          assert_callra;
 423         __be32          rsvd1[2];
 424         __be32          fw_ver;
 425         __be32          hw_id;
 426         __be32          rsvd2;
 427         u8              irisc_index;
 428         u8              synd;
 429         __be16          ext_sync;
 430 };
 431
 432 struct mlx5_init_seg {
 433         __be32                  fw_rev;
 434         __be32                  cmdif_rev_fw_sub;
 435         __be32                  rsvd0[2];
 436         __be32                  cmdq_addr_h;
 437         __be32                  cmdq_addr_l_sz;
 438         __be32                  cmd_dbell;
 439         __be32                  rsvd1[121];
 440         struct health_buffer    health;
 441         __be32                  rsvd2[884];
 442         __be32                  health_counter;
 443         __be32                  rsvd3[1019];
 444         __be64                  ieee1588_clk;
 445         __be32                  ieee1588_clk_type;
 446         __be32                  clr_intx;
 447 };
 448
 449 struct mlx5_eqe_comp {
 450         __be32  reserved[6];
 451         __be32  cqn;
 452 };
 453
 454 struct mlx5_eqe_qp_srq {
 455         __be32  reserved[6];
 456         __be32  qp_srq_n;
 457 };
 458
 459 struct mlx5_eqe_cq_err {
 460         __be32  cqn;
 461         u8      reserved1[7];
 462         u8      syndrome;
 463 };
 464
 465 struct mlx5_eqe_port_state {
 466         u8      reserved0[8];
 467         u8      port;
 468 };
 469
 470 struct mlx5_eqe_gpio {
 471         __be32  reserved0[2];
 472         __be64  gpio_event;
 473 };
 474
 475 struct mlx5_eqe_congestion {
 476         u8      type;
 477         u8      rsvd0;
 478         u8      congestion_level;
 479 };
 480
 481 struct mlx5_eqe_stall_vl {
 482         u8      rsvd0[3];
 483         u8      port_vl;
 484 };
 485
 486 struct mlx5_eqe_cmd {
 487         __be32  vector;
 488         __be32  rsvd[6];
 489 };
 490
 491 struct mlx5_eqe_page_req {
 492         u8              rsvd0[2];
 493         __be16          func_id;
 494         __be32          num_pages;
 495         __be32          rsvd1[5];
 496 };
 497
 498 union ev_data {
 499         __be32                          raw[7];
 500         struct mlx5_eqe_cmd             cmd;
 501         struct mlx5_eqe_comp            comp;
 502         struct mlx5_eqe_qp_srq          qp_srq;
 503         struct mlx5_eqe_cq_err          cq_err;
 504         struct mlx5_eqe_port_state      port;
 505         struct mlx5_eqe_gpio            gpio;
 506         struct mlx5_eqe_congestion      cong;
 507         struct mlx5_eqe_stall_vl        stall_vl;
 508         struct mlx5_eqe_page_req        req_pages;
 509 } __packed;
 510
 511 struct mlx5_eqe {
 512         u8              rsvd0;
 513         u8              type;
 514         u8              rsvd1;
 515         u8              sub_type;
 516         __be32          rsvd2[7];
 517         union ev_data   data;
 518         __be16          rsvd3;
 519         u8              signature;
 520         u8              owner;
 521 } __packed;
 522
 523 struct mlx5_cmd_prot_block {
 524         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 525         u8              rsvd0[48];
 526         __be64          next;
 527         __be32          block_num;
 528         u8              rsvd1;
 529         u8              token;
 530         u8              ctrl_sig;
 531         u8              sig;
 532 };
 533
 534 struct mlx5_err_cqe {
 535         u8      rsvd0[32];
 536         __be32  srqn;
 537         u8      rsvd1[18];
 538         u8      vendor_err_synd;
 539         u8      syndrome;
 540         __be32  s_wqe_opcode_qpn;
 541         __be16  wqe_counter;
 542         u8      signature;
 543         u8      op_own;
 544 };
 545
 546 struct mlx5_cqe64 {
 547         u8              rsvd0[17];
 548         u8              ml_path;
 549         u8              rsvd20[4];
 550         __be16          slid;
 551         __be32          flags_rqpn;
 552         u8              rsvd28[4];
 553         __be32          srqn;
 554         __be32          imm_inval_pkey;
 555         u8              rsvd40[4];
 556         __be32          byte_cnt;
 557         __be64          timestamp;
 558         __be32          sop_drop_qpn;
 559         __be16          wqe_counter;
 560         u8              signature;
 561         u8              op_own;
 562 };
 563
 564 struct mlx5_sig_err_cqe {
 565         u8              rsvd0[16];
 566         __be32          expected_trans_sig;
 567         __be32          actual_trans_sig;
 568         __be32          expected_reftag;
 569         __be32          actual_reftag;
 570         __be16          syndrome;
 571         u8              rsvd22[2];
 572         __be32          mkey;
 573         __be64          err_offset;
 574         u8              rsvd30[8];
 575         __be32          qpn;
 576         u8              rsvd38[2];
 577         u8              signature;
 578         u8              op_own;
 579 };
 580
 581 struct mlx5_wqe_srq_next_seg {
 582         u8                      rsvd0[2];
 583         __be16                  next_wqe_index;
 584         u8                      signature;
 585         u8                      rsvd1[11];
 586 };
 587
 588 union mlx5_ext_cqe {
 589         struct ib_grh   grh;
 590         u8              inl[64];
 591 };
 592
 593 struct mlx5_cqe128 {
 594         union mlx5_ext_cqe      inl_grh;
 595         struct mlx5_cqe64       cqe64;
 596 };
 597
 598 struct mlx5_srq_ctx {
 599         u8                      state_log_sz;
 600         u8                      rsvd0[3];
 601         __be32                  flags_xrcd;
 602         __be32                  pgoff_cqn;
 603         u8                      rsvd1[4];
 604         u8                      log_pg_sz;
 605         u8                      rsvd2[7];
 606         __be32                  pd;
 607         __be16                  lwm;
 608         __be16                  wqe_cnt;
 609         u8                      rsvd3[8];
 610         __be64                  db_record;
 611 };
 612
 613 struct mlx5_create_srq_mbox_in {
 614         struct mlx5_inbox_hdr   hdr;
 615         __be32                  input_srqn;
 616         u8                      rsvd0[4];
 617         struct mlx5_srq_ctx     ctx;
 618         u8                      rsvd1[208];
 619         __be64                  pas[0];
 620 };
 621
 622 struct mlx5_create_srq_mbox_out {
 623         struct mlx5_outbox_hdr  hdr;
 624         __be32                  srqn;
 625         u8                      rsvd[4];
 626 };
 627
 628 struct mlx5_destroy_srq_mbox_in {
 629         struct mlx5_inbox_hdr   hdr;
 630         __be32                  srqn;
 631         u8                      rsvd[4];
 632 };
 633
 634 struct mlx5_destroy_srq_mbox_out {
 635         struct mlx5_outbox_hdr  hdr;
 636         u8                      rsvd[8];
 637 };
 638
 639 struct mlx5_query_srq_mbox_in {
 640         struct mlx5_inbox_hdr   hdr;
 641         __be32                  srqn;
 642         u8                      rsvd0[4];
 643 };
 644
 645 struct mlx5_query_srq_mbox_out {
 646         struct mlx5_outbox_hdr  hdr;
 647         u8                      rsvd0[8];
 648         struct mlx5_srq_ctx     ctx;
 649         u8                      rsvd1[32];
 650         __be64                  pas[0];
 651 };
 652
 653 struct mlx5_arm_srq_mbox_in {
 654         struct mlx5_inbox_hdr   hdr;
 655         __be32                  srqn;
 656         __be16                  rsvd;
 657         __be16                  lwm;
 658 };
 659
 660 struct mlx5_arm_srq_mbox_out {
 661         struct mlx5_outbox_hdr  hdr;
 662         u8                      rsvd[8];
 663 };
 664
 665 struct mlx5_cq_context {
 666         u8                      status;
 667         u8                      cqe_sz_flags;
 668         u8                      st;
 669         u8                      rsvd3;
 670         u8                      rsvd4[6];
 671         __be16                  page_offset;
 672         __be32                  log_sz_usr_page;
 673         __be16                  cq_period;
 674         __be16                  cq_max_count;
 675         __be16                  rsvd20;
 676         __be16                  c_eqn;
 677         u8                      log_pg_sz;
 678         u8                      rsvd25[7];
 679         __be32                  last_notified_index;
 680         __be32                  solicit_producer_index;
 681         __be32                  consumer_counter;
 682         __be32                  producer_counter;
 683         u8                      rsvd48[8];
 684         __be64                  db_record_addr;
 685 };
 686
 687 struct mlx5_create_cq_mbox_in {
 688         struct mlx5_inbox_hdr   hdr;
 689         __be32                  input_cqn;
 690         u8                      rsvdx[4];
 691         struct mlx5_cq_context  ctx;
 692         u8                      rsvd6[192];
 693         __be64                  pas[0];
 694 };
 695
 696 struct mlx5_create_cq_mbox_out {
 697         struct mlx5_outbox_hdr  hdr;
 698         __be32                  cqn;
 699         u8                      rsvd0[4];
 700 };
 701
 702 struct mlx5_destroy_cq_mbox_in {
 703         struct mlx5_inbox_hdr   hdr;
 704         __be32                  cqn;
 705         u8                      rsvd0[4];
 706 };
 707
 708 struct mlx5_destroy_cq_mbox_out {
 709         struct mlx5_outbox_hdr  hdr;
 710         u8                      rsvd0[8];
 711 };
 712
 713 struct mlx5_query_cq_mbox_in {
 714         struct mlx5_inbox_hdr   hdr;
 715         __be32                  cqn;
 716         u8                      rsvd0[4];
 717 };
 718
 719 struct mlx5_query_cq_mbox_out {
 720         struct mlx5_outbox_hdr  hdr;
 721         u8                      rsvd0[8];
 722         struct mlx5_cq_context  ctx;
 723         u8                      rsvd6[16];
 724         __be64                  pas[0];
 725 };
 726
 727 struct mlx5_modify_cq_mbox_in {
 728         struct mlx5_inbox_hdr   hdr;
 729         __be32                  cqn;
 730         __be32                  field_select;
 731         struct mlx5_cq_context  ctx;
 732         u8                      rsvd[192];
 733         __be64                  pas[0];
 734 };
 735
 736 struct mlx5_modify_cq_mbox_out {
 737         struct mlx5_outbox_hdr  hdr;
 738         u8                      rsvd[8];
 739 };
 740
 741 struct mlx5_enable_hca_mbox_in {
 742         struct mlx5_inbox_hdr   hdr;
 743         u8                      rsvd[8];
 744 };
 745
 746 struct mlx5_enable_hca_mbox_out {
 747         struct mlx5_outbox_hdr  hdr;
 748         u8                      rsvd[8];
 749 };
 750
 751 struct mlx5_disable_hca_mbox_in {
 752         struct mlx5_inbox_hdr   hdr;
 753         u8                      rsvd[8];
 754 };
 755
 756 struct mlx5_disable_hca_mbox_out {
 757         struct mlx5_outbox_hdr  hdr;
 758         u8                      rsvd[8];
 759 };
 760
 761 struct mlx5_eq_context {
 762         u8                      status;
 763         u8                      ec_oi;
 764         u8                      st;
 765         u8                      rsvd2[7];
 766         __be16                  page_pffset;
 767         __be32                  log_sz_usr_page;
 768         u8                      rsvd3[7];
 769         u8                      intr;
 770         u8                      log_page_size;
 771         u8                      rsvd4[15];
 772         __be32                  consumer_counter;
 773         __be32                  produser_counter;
 774         u8                      rsvd5[16];
 775 };
 776
 777 struct mlx5_create_eq_mbox_in {
 778         struct mlx5_inbox_hdr   hdr;
 779         u8                      rsvd0[3];
 780         u8                      input_eqn;
 781         u8                      rsvd1[4];
 782         struct mlx5_eq_context  ctx;
 783         u8                      rsvd2[8];
 784         __be64                  events_mask;
 785         u8                      rsvd3[176];
 786         __be64                  pas[0];
 787 };
 788
 789 struct mlx5_create_eq_mbox_out {
 790         struct mlx5_outbox_hdr  hdr;
 791         u8                      rsvd0[3];
 792         u8                      eq_number;
 793         u8                      rsvd1[4];
 794 };
 795
 796 struct mlx5_destroy_eq_mbox_in {
 797         struct mlx5_inbox_hdr   hdr;
 798         u8                      rsvd0[3];
 799         u8                      eqn;
 800         u8                      rsvd1[4];
 801 };
 802
 803 struct mlx5_destroy_eq_mbox_out {
 804         struct mlx5_outbox_hdr  hdr;
 805         u8                      rsvd[8];
 806 };
 807
 808 struct mlx5_map_eq_mbox_in {
 809         struct mlx5_inbox_hdr   hdr;
 810         __be64                  mask;
 811         u8                      mu;
 812         u8                      rsvd0[2];
 813         u8                      eqn;
 814         u8                      rsvd1[24];
 815 };
 816
 817 struct mlx5_map_eq_mbox_out {
 818         struct mlx5_outbox_hdr  hdr;
 819         u8                      rsvd[8];
 820 };
 821
 822 struct mlx5_query_eq_mbox_in {
 823         struct mlx5_inbox_hdr   hdr;
 824         u8                      rsvd0[3];
 825         u8                      eqn;
 826         u8                      rsvd1[4];
 827 };
 828
 829 struct mlx5_query_eq_mbox_out {
 830         struct mlx5_outbox_hdr  hdr;
 831         u8                      rsvd[8];
 832         struct mlx5_eq_context  ctx;
 833 };
 834
 835 struct mlx5_mkey_seg {
 836         /* This is a two bit field occupying bits 31-30.
 837          * bit 31 is always 0,
 838          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
 839          */
 840         u8              status;
 841         u8              pcie_control;
 842         u8              flags;
 843         u8              version;
 844         __be32          qpn_mkey7_0;
 845         u8              rsvd1[4];
 846         __be32          flags_pd;
 847         __be64          start_addr;
 848         __be64          len;
 849         __be32          bsfs_octo_size;
 850         u8              rsvd2[16];
 851         __be32          xlt_oct_size;
 852         u8              rsvd3[3];
 853         u8              log2_page_size;
 854         u8              rsvd4[4];
 855 };
 856
 857 struct mlx5_query_special_ctxs_mbox_in {
 858         struct mlx5_inbox_hdr   hdr;
 859         u8                      rsvd[8];
 860 };
 861
 862 struct mlx5_query_special_ctxs_mbox_out {
 863         struct mlx5_outbox_hdr  hdr;
 864         __be32                  dump_fill_mkey;
 865         __be32                  reserved_lkey;
 866 };
 867
 868 struct mlx5_create_mkey_mbox_in {
 869         struct mlx5_inbox_hdr   hdr;
 870         __be32                  input_mkey_index;
 871         u8                      rsvd0[4];
 872         struct mlx5_mkey_seg    seg;
 873         u8                      rsvd1[16];
 874         __be32                  xlat_oct_act_size;
 875         __be32                  rsvd2;
 876         u8                      rsvd3[168];
 877         __be64                  pas[0];
 878 };
 879
 880 struct mlx5_create_mkey_mbox_out {
 881         struct mlx5_outbox_hdr  hdr;
 882         __be32                  mkey;
 883         u8                      rsvd[4];
 884 };
 885
 886 struct mlx5_destroy_mkey_mbox_in {
 887         struct mlx5_inbox_hdr   hdr;
 888         __be32                  mkey;
 889         u8                      rsvd[4];
 890 };
 891
 892 struct mlx5_destroy_mkey_mbox_out {
 893         struct mlx5_outbox_hdr  hdr;
 894         u8                      rsvd[8];
 895 };
 896
 897 struct mlx5_query_mkey_mbox_in {
 898         struct mlx5_inbox_hdr   hdr;
 899         __be32                  mkey;
 900 };
 901
 902 struct mlx5_query_mkey_mbox_out {
 903         struct mlx5_outbox_hdr  hdr;
 904         __be64                  pas[0];
 905 };
 906
 907 struct mlx5_modify_mkey_mbox_in {
 908         struct mlx5_inbox_hdr   hdr;
 909         __be32                  mkey;
 910         __be64                  pas[0];
 911 };
 912
 913 struct mlx5_modify_mkey_mbox_out {
 914         struct mlx5_outbox_hdr  hdr;
 915         u8                      rsvd[8];
 916 };
 917
 918 struct mlx5_dump_mkey_mbox_in {
 919         struct mlx5_inbox_hdr   hdr;
 920 };
 921
 922 struct mlx5_dump_mkey_mbox_out {
 923         struct mlx5_outbox_hdr  hdr;
 924         __be32                  mkey;
 925 };
 926
 927 struct mlx5_mad_ifc_mbox_in {
 928         struct mlx5_inbox_hdr   hdr;
 929         __be16                  remote_lid;
 930         u8                      rsvd0;
 931         u8                      port;
 932         u8                      rsvd1[4];
 933         u8                      data[256];
 934 };
 935
 936 struct mlx5_mad_ifc_mbox_out {
 937         struct mlx5_outbox_hdr  hdr;
 938         u8                      rsvd[8];
 939         u8                      data[256];
 940 };
 941
 942 struct mlx5_access_reg_mbox_in {
 943         struct mlx5_inbox_hdr           hdr;
 944         u8                              rsvd0[2];
 945         __be16                          register_id;
 946         __be32                          arg;
 947         __be32                          data[0];
 948 };
 949
 950 struct mlx5_access_reg_mbox_out {
 951         struct mlx5_outbox_hdr          hdr;
 952         u8                              rsvd[8];
 953         __be32                          data[0];
 954 };
 955
 956 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
 957
 958 enum {
 959         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
 960 };
 961
 962 struct mlx5_allocate_psv_in {
 963         struct mlx5_inbox_hdr   hdr;
 964         __be32                  npsv_pd;
 965         __be32                  rsvd_psv0;
 966 };
 967
 968 struct mlx5_allocate_psv_out {
 969         struct mlx5_outbox_hdr  hdr;
 970         u8                      rsvd[8];
 971         __be32                  psv_idx[4];
 972 };
 973
 974 struct mlx5_destroy_psv_in {
 975         struct mlx5_inbox_hdr   hdr;
 976         __be32                  psv_number;
 977         u8                      rsvd[4];
 978 };
 979
 980 struct mlx5_destroy_psv_out {
 981         struct mlx5_outbox_hdr  hdr;
 982         u8                      rsvd[8];
 983 };
 984
 985 #endif /* MLX5_DEVICE_H */