2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
45 #error Host endianness not defined
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
63 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
64 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
65 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
67 /* insert a value to a struct */
68 #define MLX5_SET(typ, p, fld, v) do { \
69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
81 << __mlx5_dw_bit_off(typ, fld))); \
84 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
85 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
86 __mlx5_mask(typ, fld))
88 #define MLX5_GET_PR(typ, p, fld) ({ \
89 u32 ___t = MLX5_GET(typ, p, fld); \
90 pr_debug(#fld " = 0x%x\n", ___t); \
94 #define MLX5_SET64(typ, p, fld, v) do { \
95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
100 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
102 #define MLX5_GET64_PR(typ, p, fld) ({ \
103 u64 ___t = MLX5_GET64(typ, p, fld); \
104 pr_debug(#fld " = 0x%llx\n", ___t); \
108 /* Big endian getters */
109 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
110 __mlx5_64_off(typ, fld)))
112 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
114 switch (sizeof(tmp)) { \
116 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
119 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
122 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
125 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
132 MLX5_MAX_COMMANDS = 32,
133 MLX5_CMD_DATA_BLOCK_SIZE = 512,
134 MLX5_PCI_CMD_XPORT = 7,
135 MLX5_MKEY_BSF_OCTO_SIZE = 4,
140 MLX5_EXTENDED_UD_AV = 0x80000000,
144 MLX5_CQ_STATE_ARMED = 9,
145 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
146 MLX5_CQ_STATE_FIRED = 0xa,
150 MLX5_STAT_RATE_OFFSET = 5,
154 MLX5_INLINE_SEG = 0x80000000,
158 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
162 MLX5_MIN_PKEY_TABLE_SIZE = 128,
163 MLX5_MAX_LOG_PKEY_TABLE = 5,
167 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
171 MLX5_PFAULT_SUBTYPE_WQE = 0,
172 MLX5_PFAULT_SUBTYPE_RDMA = 1,
176 MLX5_PERM_LOCAL_READ = 1 << 2,
177 MLX5_PERM_LOCAL_WRITE = 1 << 3,
178 MLX5_PERM_REMOTE_READ = 1 << 4,
179 MLX5_PERM_REMOTE_WRITE = 1 << 5,
180 MLX5_PERM_ATOMIC = 1 << 6,
181 MLX5_PERM_UMR_EN = 1 << 7,
185 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
186 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
187 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
188 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
189 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
193 MLX5_ACCESS_MODE_PA = 0,
194 MLX5_ACCESS_MODE_MTT = 1,
195 MLX5_ACCESS_MODE_KLM = 2
199 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
200 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
201 MLX5_MKEY_BSF_EN = 1 << 30,
202 MLX5_MKEY_LEN64 = 1 << 31,
211 MLX5_BF_REGS_PER_PAGE = 4,
212 MLX5_MAX_UAR_PAGES = 1 << 8,
213 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
214 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
218 MLX5_MKEY_MASK_LEN = 1ull << 0,
219 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
220 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
221 MLX5_MKEY_MASK_PD = 1ull << 7,
222 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
223 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
224 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
225 MLX5_MKEY_MASK_KEY = 1ull << 13,
226 MLX5_MKEY_MASK_QPN = 1ull << 14,
227 MLX5_MKEY_MASK_LR = 1ull << 17,
228 MLX5_MKEY_MASK_LW = 1ull << 18,
229 MLX5_MKEY_MASK_RR = 1ull << 19,
230 MLX5_MKEY_MASK_RW = 1ull << 20,
231 MLX5_MKEY_MASK_A = 1ull << 21,
232 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
233 MLX5_MKEY_MASK_FREE = 1ull << 29,
237 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
239 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
240 MLX5_UMR_CHECK_FREE = (2 << 5),
242 MLX5_UMR_INLINE = (1 << 7),
245 #define MLX5_UMR_MTT_ALIGNMENT 0x40
246 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
247 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
249 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
252 MLX5_EVENT_QUEUE_TYPE_QP = 0,
253 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
254 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
258 MLX5_EVENT_TYPE_COMP = 0x0,
260 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
261 MLX5_EVENT_TYPE_COMM_EST = 0x02,
262 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
263 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
264 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
266 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
267 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
268 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
269 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
270 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
271 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
273 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
274 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
275 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
276 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
278 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
279 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
281 MLX5_EVENT_TYPE_CMD = 0x0a,
282 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
284 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
285 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
289 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
290 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
291 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
292 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
293 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
294 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
295 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
299 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
300 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
301 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
302 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
303 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
304 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
305 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
306 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
307 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
308 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
309 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
310 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
314 MLX5_ROCE_VERSION_1 = 0,
315 MLX5_ROCE_VERSION_2 = 2,
319 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
320 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
324 MLX5_ROCE_L3_TYPE_IPV4 = 0,
325 MLX5_ROCE_L3_TYPE_IPV6 = 1,
329 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
330 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
334 MLX5_OPCODE_NOP = 0x00,
335 MLX5_OPCODE_SEND_INVAL = 0x01,
336 MLX5_OPCODE_RDMA_WRITE = 0x08,
337 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
338 MLX5_OPCODE_SEND = 0x0a,
339 MLX5_OPCODE_SEND_IMM = 0x0b,
340 MLX5_OPCODE_LSO = 0x0e,
341 MLX5_OPCODE_RDMA_READ = 0x10,
342 MLX5_OPCODE_ATOMIC_CS = 0x11,
343 MLX5_OPCODE_ATOMIC_FA = 0x12,
344 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
345 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
346 MLX5_OPCODE_BIND_MW = 0x18,
347 MLX5_OPCODE_CONFIG_CMD = 0x1f,
349 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
350 MLX5_RECV_OPCODE_SEND = 0x01,
351 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
352 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
354 MLX5_CQE_OPCODE_ERROR = 0x1e,
355 MLX5_CQE_OPCODE_RESIZE = 0x16,
357 MLX5_OPCODE_SET_PSV = 0x20,
358 MLX5_OPCODE_GET_PSV = 0x21,
359 MLX5_OPCODE_CHECK_PSV = 0x22,
360 MLX5_OPCODE_RGET_PSV = 0x26,
361 MLX5_OPCODE_RCHECK_PSV = 0x27,
363 MLX5_OPCODE_UMR = 0x25,
368 MLX5_SET_PORT_RESET_QKEY = 0,
369 MLX5_SET_PORT_GUID0 = 16,
370 MLX5_SET_PORT_NODE_GUID = 17,
371 MLX5_SET_PORT_SYS_GUID = 18,
372 MLX5_SET_PORT_GID_TABLE = 19,
373 MLX5_SET_PORT_PKEY_TABLE = 20,
377 MLX5_MAX_PAGE_SHIFT = 31
381 MLX5_ADAPTER_PAGE_SHIFT = 12,
382 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
386 MLX5_CAP_OFF_CMDIF_CSUM = 46,
389 struct mlx5_inbox_hdr {
395 struct mlx5_outbox_hdr {
401 struct mlx5_cmd_query_adapter_mbox_in {
402 struct mlx5_inbox_hdr hdr;
406 struct mlx5_cmd_query_adapter_mbox_out {
407 struct mlx5_outbox_hdr hdr;
411 __be16 vsd_vendor_id;
416 enum mlx5_odp_transport_cap_bits {
417 MLX5_ODP_SUPPORT_SEND = 1 << 31,
418 MLX5_ODP_SUPPORT_RECV = 1 << 30,
419 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
420 MLX5_ODP_SUPPORT_READ = 1 << 28,
423 struct mlx5_odp_caps {
429 } per_transport_caps;
430 char reserved2[0xe4];
433 struct mlx5_cmd_init_hca_mbox_in {
434 struct mlx5_inbox_hdr hdr;
440 struct mlx5_cmd_init_hca_mbox_out {
441 struct mlx5_outbox_hdr hdr;
445 struct mlx5_cmd_teardown_hca_mbox_in {
446 struct mlx5_inbox_hdr hdr;
452 struct mlx5_cmd_teardown_hca_mbox_out {
453 struct mlx5_outbox_hdr hdr;
457 struct mlx5_cmd_layout {
473 struct health_buffer {
474 __be32 assert_var[5];
476 __be32 assert_exit_ptr;
477 __be32 assert_callra;
487 struct mlx5_init_seg {
489 __be32 cmdif_rev_fw_sub;
492 __be32 cmdq_addr_l_sz;
496 struct health_buffer health;
498 __be32 internal_timer_h;
499 __be32 internal_timer_l;
501 __be32 health_counter;
504 __be32 ieee1588_clk_type;
508 struct mlx5_eqe_comp {
513 struct mlx5_eqe_qp_srq {
520 struct mlx5_eqe_cq_err {
526 struct mlx5_eqe_port_state {
531 struct mlx5_eqe_gpio {
536 struct mlx5_eqe_congestion {
542 struct mlx5_eqe_stall_vl {
547 struct mlx5_eqe_cmd {
552 struct mlx5_eqe_page_req {
559 struct mlx5_eqe_page_fault {
560 __be32 bytes_committed;
566 __be16 packet_length;
572 __be16 packet_length;
580 struct mlx5_eqe_vport_change {
588 struct mlx5_eqe_cmd cmd;
589 struct mlx5_eqe_comp comp;
590 struct mlx5_eqe_qp_srq qp_srq;
591 struct mlx5_eqe_cq_err cq_err;
592 struct mlx5_eqe_port_state port;
593 struct mlx5_eqe_gpio gpio;
594 struct mlx5_eqe_congestion cong;
595 struct mlx5_eqe_stall_vl stall_vl;
596 struct mlx5_eqe_page_req req_pages;
597 struct mlx5_eqe_page_fault page_fault;
598 struct mlx5_eqe_vport_change vport_change;
613 struct mlx5_cmd_prot_block {
614 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
625 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
628 struct mlx5_err_cqe {
634 __be32 s_wqe_opcode_qpn;
642 u8 lro_tcppsh_abort_dupack;
645 __be32 lro_ack_seq_num;
646 __be32 rss_hash_result;
656 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
657 __be32 imm_inval_pkey;
668 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
670 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
673 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
675 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
678 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
680 return !!(cqe->l4_hdr_type_etc & 0x1);
683 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
687 hi = be32_to_cpu(cqe->timestamp_h);
688 lo = be32_to_cpu(cqe->timestamp_l);
690 return (u64)lo | ((u64)hi << 32);
694 CQE_L4_HDR_TYPE_NONE = 0x0,
695 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
696 CQE_L4_HDR_TYPE_UDP = 0x2,
697 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
698 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
702 CQE_RSS_HTYPE_IP = 0x3 << 6,
703 CQE_RSS_HTYPE_L4 = 0x3 << 2,
707 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
708 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
709 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
718 struct mlx5_sig_err_cqe {
720 __be32 expected_trans_sig;
721 __be32 actual_trans_sig;
722 __be32 expected_reftag;
723 __be32 actual_reftag;
735 struct mlx5_wqe_srq_next_seg {
737 __be16 next_wqe_index;
748 union mlx5_ext_cqe inl_grh;
749 struct mlx5_cqe64 cqe64;
752 struct mlx5_srq_ctx {
767 struct mlx5_create_srq_mbox_in {
768 struct mlx5_inbox_hdr hdr;
771 struct mlx5_srq_ctx ctx;
776 struct mlx5_create_srq_mbox_out {
777 struct mlx5_outbox_hdr hdr;
782 struct mlx5_destroy_srq_mbox_in {
783 struct mlx5_inbox_hdr hdr;
788 struct mlx5_destroy_srq_mbox_out {
789 struct mlx5_outbox_hdr hdr;
793 struct mlx5_query_srq_mbox_in {
794 struct mlx5_inbox_hdr hdr;
799 struct mlx5_query_srq_mbox_out {
800 struct mlx5_outbox_hdr hdr;
802 struct mlx5_srq_ctx ctx;
807 struct mlx5_arm_srq_mbox_in {
808 struct mlx5_inbox_hdr hdr;
814 struct mlx5_arm_srq_mbox_out {
815 struct mlx5_outbox_hdr hdr;
819 struct mlx5_cq_context {
826 __be32 log_sz_usr_page;
833 __be32 last_notified_index;
834 __be32 solicit_producer_index;
835 __be32 consumer_counter;
836 __be32 producer_counter;
838 __be64 db_record_addr;
841 struct mlx5_create_cq_mbox_in {
842 struct mlx5_inbox_hdr hdr;
845 struct mlx5_cq_context ctx;
850 struct mlx5_create_cq_mbox_out {
851 struct mlx5_outbox_hdr hdr;
856 struct mlx5_destroy_cq_mbox_in {
857 struct mlx5_inbox_hdr hdr;
862 struct mlx5_destroy_cq_mbox_out {
863 struct mlx5_outbox_hdr hdr;
867 struct mlx5_query_cq_mbox_in {
868 struct mlx5_inbox_hdr hdr;
873 struct mlx5_query_cq_mbox_out {
874 struct mlx5_outbox_hdr hdr;
876 struct mlx5_cq_context ctx;
881 struct mlx5_modify_cq_mbox_in {
882 struct mlx5_inbox_hdr hdr;
885 struct mlx5_cq_context ctx;
890 struct mlx5_modify_cq_mbox_out {
891 struct mlx5_outbox_hdr hdr;
895 struct mlx5_enable_hca_mbox_in {
896 struct mlx5_inbox_hdr hdr;
900 struct mlx5_enable_hca_mbox_out {
901 struct mlx5_outbox_hdr hdr;
905 struct mlx5_disable_hca_mbox_in {
906 struct mlx5_inbox_hdr hdr;
910 struct mlx5_disable_hca_mbox_out {
911 struct mlx5_outbox_hdr hdr;
915 struct mlx5_eq_context {
921 __be32 log_sz_usr_page;
926 __be32 consumer_counter;
927 __be32 produser_counter;
931 struct mlx5_create_eq_mbox_in {
932 struct mlx5_inbox_hdr hdr;
936 struct mlx5_eq_context ctx;
943 struct mlx5_create_eq_mbox_out {
944 struct mlx5_outbox_hdr hdr;
950 struct mlx5_destroy_eq_mbox_in {
951 struct mlx5_inbox_hdr hdr;
957 struct mlx5_destroy_eq_mbox_out {
958 struct mlx5_outbox_hdr hdr;
962 struct mlx5_map_eq_mbox_in {
963 struct mlx5_inbox_hdr hdr;
971 struct mlx5_map_eq_mbox_out {
972 struct mlx5_outbox_hdr hdr;
976 struct mlx5_query_eq_mbox_in {
977 struct mlx5_inbox_hdr hdr;
983 struct mlx5_query_eq_mbox_out {
984 struct mlx5_outbox_hdr hdr;
986 struct mlx5_eq_context ctx;
990 MLX5_MKEY_STATUS_FREE = 1 << 6,
993 struct mlx5_mkey_seg {
994 /* This is a two bit field occupying bits 31-30.
995 * bit 31 is always 0,
996 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
1007 __be32 bsfs_octo_size;
1009 __be32 xlt_oct_size;
1015 struct mlx5_query_special_ctxs_mbox_in {
1016 struct mlx5_inbox_hdr hdr;
1020 struct mlx5_query_special_ctxs_mbox_out {
1021 struct mlx5_outbox_hdr hdr;
1022 __be32 dump_fill_mkey;
1023 __be32 reserved_lkey;
1026 struct mlx5_create_mkey_mbox_in {
1027 struct mlx5_inbox_hdr hdr;
1028 __be32 input_mkey_index;
1030 struct mlx5_mkey_seg seg;
1032 __be32 xlat_oct_act_size;
1038 struct mlx5_create_mkey_mbox_out {
1039 struct mlx5_outbox_hdr hdr;
1044 struct mlx5_destroy_mkey_mbox_in {
1045 struct mlx5_inbox_hdr hdr;
1050 struct mlx5_destroy_mkey_mbox_out {
1051 struct mlx5_outbox_hdr hdr;
1055 struct mlx5_query_mkey_mbox_in {
1056 struct mlx5_inbox_hdr hdr;
1060 struct mlx5_query_mkey_mbox_out {
1061 struct mlx5_outbox_hdr hdr;
1065 struct mlx5_modify_mkey_mbox_in {
1066 struct mlx5_inbox_hdr hdr;
1071 struct mlx5_modify_mkey_mbox_out {
1072 struct mlx5_outbox_hdr hdr;
1076 struct mlx5_dump_mkey_mbox_in {
1077 struct mlx5_inbox_hdr hdr;
1080 struct mlx5_dump_mkey_mbox_out {
1081 struct mlx5_outbox_hdr hdr;
1085 struct mlx5_mad_ifc_mbox_in {
1086 struct mlx5_inbox_hdr hdr;
1094 struct mlx5_mad_ifc_mbox_out {
1095 struct mlx5_outbox_hdr hdr;
1100 struct mlx5_access_reg_mbox_in {
1101 struct mlx5_inbox_hdr hdr;
1108 struct mlx5_access_reg_mbox_out {
1109 struct mlx5_outbox_hdr hdr;
1114 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1117 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1120 struct mlx5_allocate_psv_in {
1121 struct mlx5_inbox_hdr hdr;
1126 struct mlx5_allocate_psv_out {
1127 struct mlx5_outbox_hdr hdr;
1132 struct mlx5_destroy_psv_in {
1133 struct mlx5_inbox_hdr hdr;
1138 struct mlx5_destroy_psv_out {
1139 struct mlx5_outbox_hdr hdr;
1143 #define MLX5_CMD_OP_MAX 0x920
1146 VPORT_STATE_DOWN = 0x0,
1147 VPORT_STATE_UP = 0x1,
1151 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
1152 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
1153 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
1157 MLX5_L3_PROT_TYPE_IPV4 = 0,
1158 MLX5_L3_PROT_TYPE_IPV6 = 1,
1162 MLX5_L4_PROT_TYPE_TCP = 0,
1163 MLX5_L4_PROT_TYPE_UDP = 1,
1167 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1168 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1169 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1170 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1171 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1175 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1176 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1177 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1182 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1183 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1187 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1188 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1189 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1192 enum mlx5_list_type {
1193 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1194 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1195 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1199 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1200 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1206 enum mlx5_cap_mode {
1207 HCA_CAP_OPMOD_GET_MAX = 0,
1208 HCA_CAP_OPMOD_GET_CUR = 1,
1211 enum mlx5_cap_type {
1212 MLX5_CAP_GENERAL = 0,
1213 MLX5_CAP_ETHERNET_OFFLOADS,
1217 MLX5_CAP_IPOIB_OFFLOADS,
1218 MLX5_CAP_EOIB_OFFLOADS,
1219 MLX5_CAP_FLOW_TABLE,
1220 MLX5_CAP_ESWITCH_FLOW_TABLE,
1223 MLX5_CAP_VECTOR_CALC,
1224 /* NUM OF CAP Types */
1228 /* GET Dev Caps macros */
1229 #define MLX5_CAP_GEN(mdev, cap) \
1230 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1232 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1233 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1235 #define MLX5_CAP_ETH(mdev, cap) \
1236 MLX5_GET(per_protocol_networking_offload_caps,\
1237 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1239 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1240 MLX5_GET(per_protocol_networking_offload_caps,\
1241 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1243 #define MLX5_CAP_ROCE(mdev, cap) \
1244 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1246 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1247 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1249 #define MLX5_CAP_ATOMIC(mdev, cap) \
1250 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1252 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1253 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1255 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1256 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1258 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1259 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1261 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1262 MLX5_GET(flow_table_eswitch_cap, \
1263 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1265 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1266 MLX5_GET(flow_table_eswitch_cap, \
1267 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1269 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1270 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1272 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1273 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1275 #define MLX5_CAP_ESW(mdev, cap) \
1276 MLX5_GET(e_switch_cap, \
1277 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1279 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1280 MLX5_GET(e_switch_cap, \
1281 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1283 #define MLX5_CAP_ODP(mdev, cap)\
1284 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1286 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1287 MLX5_GET(vector_calc_cap, \
1288 mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1291 MLX5_CMD_STAT_OK = 0x0,
1292 MLX5_CMD_STAT_INT_ERR = 0x1,
1293 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1294 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1295 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1296 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1297 MLX5_CMD_STAT_RES_BUSY = 0x6,
1298 MLX5_CMD_STAT_LIM_ERR = 0x8,
1299 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1300 MLX5_CMD_STAT_IX_ERR = 0xa,
1301 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1302 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1303 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1304 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1305 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1306 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1310 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1311 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1312 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1313 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1314 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1315 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1316 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1317 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1320 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1322 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1324 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1327 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1328 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1329 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1330 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1331 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1332 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1334 #endif /* MLX5_DEVICE_H */