include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  87         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  88         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  89         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  90         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  91         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  92         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  93         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  94         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  95         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  96         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  97         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  98         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  99         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 100         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 101         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 102         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 103         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 104         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 105         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 106         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 107         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 108         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 109         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 110         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 111         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 112         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 113         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 114         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 115         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 116         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 117         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 118         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 119         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 120         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 121         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 122         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 123         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 124         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 125         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 126         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 127         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 128         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 129         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 130         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 131         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 132         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 133         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 134         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 135         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 136         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 137         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 138         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 139         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 140         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 141         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 142         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 143         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 144         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 145         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 146         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 147         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 148         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 149         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 150         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 151         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 152         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 153         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 154         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 155         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 156         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 157         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 158         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 159         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 160         MLX5_CMD_OP_NOP                           = 0x80d,
 161         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 162         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 163         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 164         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 165         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 166         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 167         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 168         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 169         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 170         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 171         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 172         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 173         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 174         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 175         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 176         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 177         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 178         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 179         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 180         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 181         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 182         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 183         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 184         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 185         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 186         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 187         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 188         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 189         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 190         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 191         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 192         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 193         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 194         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 195         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 196         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 197         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 198         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 199         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 200         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 201         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 202         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 203         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 204         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 205         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 206         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 207         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 208         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 209         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 210         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 211         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 212         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 213         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 214         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c
 215 };
 216
 217 struct mlx5_ifc_flow_table_fields_supported_bits {
 218         u8         outer_dmac[0x1];
 219         u8         outer_smac[0x1];
 220         u8         outer_ether_type[0x1];
 221         u8         reserved_at_3[0x1];
 222         u8         outer_first_prio[0x1];
 223         u8         outer_first_cfi[0x1];
 224         u8         outer_first_vid[0x1];
 225         u8         reserved_at_7[0x1];
 226         u8         outer_second_prio[0x1];
 227         u8         outer_second_cfi[0x1];
 228         u8         outer_second_vid[0x1];
 229         u8         reserved_at_b[0x1];
 230         u8         outer_sip[0x1];
 231         u8         outer_dip[0x1];
 232         u8         outer_frag[0x1];
 233         u8         outer_ip_protocol[0x1];
 234         u8         outer_ip_ecn[0x1];
 235         u8         outer_ip_dscp[0x1];
 236         u8         outer_udp_sport[0x1];
 237         u8         outer_udp_dport[0x1];
 238         u8         outer_tcp_sport[0x1];
 239         u8         outer_tcp_dport[0x1];
 240         u8         outer_tcp_flags[0x1];
 241         u8         outer_gre_protocol[0x1];
 242         u8         outer_gre_key[0x1];
 243         u8         outer_vxlan_vni[0x1];
 244         u8         reserved_at_1a[0x5];
 245         u8         source_eswitch_port[0x1];
 246
 247         u8         inner_dmac[0x1];
 248         u8         inner_smac[0x1];
 249         u8         inner_ether_type[0x1];
 250         u8         reserved_at_23[0x1];
 251         u8         inner_first_prio[0x1];
 252         u8         inner_first_cfi[0x1];
 253         u8         inner_first_vid[0x1];
 254         u8         reserved_at_27[0x1];
 255         u8         inner_second_prio[0x1];
 256         u8         inner_second_cfi[0x1];
 257         u8         inner_second_vid[0x1];
 258         u8         reserved_at_2b[0x1];
 259         u8         inner_sip[0x1];
 260         u8         inner_dip[0x1];
 261         u8         inner_frag[0x1];
 262         u8         inner_ip_protocol[0x1];
 263         u8         inner_ip_ecn[0x1];
 264         u8         inner_ip_dscp[0x1];
 265         u8         inner_udp_sport[0x1];
 266         u8         inner_udp_dport[0x1];
 267         u8         inner_tcp_sport[0x1];
 268         u8         inner_tcp_dport[0x1];
 269         u8         inner_tcp_flags[0x1];
 270         u8         reserved_at_37[0x9];
 271
 272         u8         reserved_at_40[0x40];
 273 };
 274
 275 struct mlx5_ifc_flow_table_prop_layout_bits {
 276         u8         ft_support[0x1];
 277         u8         reserved_at_1[0x1];
 278         u8         flow_counter[0x1];
 279         u8         flow_modify_en[0x1];
 280         u8         modify_root[0x1];
 281         u8         identified_miss_table_mode[0x1];
 282         u8         flow_table_modify[0x1];
 283         u8         reserved_at_7[0x19];
 284
 285         u8         reserved_at_20[0x2];
 286         u8         log_max_ft_size[0x6];
 287         u8         reserved_at_28[0x10];
 288         u8         max_ft_level[0x8];
 289
 290         u8         reserved_at_40[0x20];
 291
 292         u8         reserved_at_60[0x18];
 293         u8         log_max_ft_num[0x8];
 294
 295         u8         reserved_at_80[0x18];
 296         u8         log_max_destination[0x8];
 297
 298         u8         reserved_at_a0[0x18];
 299         u8         log_max_flow[0x8];
 300
 301         u8         reserved_at_c0[0x40];
 302
 303         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 304
 305         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 306 };
 307
 308 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 309         u8         send[0x1];
 310         u8         receive[0x1];
 311         u8         write[0x1];
 312         u8         read[0x1];
 313         u8         reserved_at_4[0x1];
 314         u8         srq_receive[0x1];
 315         u8         reserved_at_6[0x1a];
 316 };
 317
 318 struct mlx5_ifc_ipv4_layout_bits {
 319         u8         reserved_at_0[0x60];
 320
 321         u8         ipv4[0x20];
 322 };
 323
 324 struct mlx5_ifc_ipv6_layout_bits {
 325         u8         ipv6[16][0x8];
 326 };
 327
 328 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 329         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 330         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 331         u8         reserved_at_0[0x80];
 332 };
 333
 334 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 335         u8         smac_47_16[0x20];
 336
 337         u8         smac_15_0[0x10];
 338         u8         ethertype[0x10];
 339
 340         u8         dmac_47_16[0x20];
 341
 342         u8         dmac_15_0[0x10];
 343         u8         first_prio[0x3];
 344         u8         first_cfi[0x1];
 345         u8         first_vid[0xc];
 346
 347         u8         ip_protocol[0x8];
 348         u8         ip_dscp[0x6];
 349         u8         ip_ecn[0x2];
 350         u8         vlan_tag[0x1];
 351         u8         reserved_at_91[0x1];
 352         u8         frag[0x1];
 353         u8         reserved_at_93[0x4];
 354         u8         tcp_flags[0x9];
 355
 356         u8         tcp_sport[0x10];
 357         u8         tcp_dport[0x10];
 358
 359         u8         reserved_at_c0[0x20];
 360
 361         u8         udp_sport[0x10];
 362         u8         udp_dport[0x10];
 363
 364         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 365
 366         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 367 };
 368
 369 struct mlx5_ifc_fte_match_set_misc_bits {
 370         u8         reserved_at_0[0x8];
 371         u8         source_sqn[0x18];
 372
 373         u8         reserved_at_20[0x10];
 374         u8         source_port[0x10];
 375
 376         u8         outer_second_prio[0x3];
 377         u8         outer_second_cfi[0x1];
 378         u8         outer_second_vid[0xc];
 379         u8         inner_second_prio[0x3];
 380         u8         inner_second_cfi[0x1];
 381         u8         inner_second_vid[0xc];
 382
 383         u8         outer_second_vlan_tag[0x1];
 384         u8         inner_second_vlan_tag[0x1];
 385         u8         reserved_at_62[0xe];
 386         u8         gre_protocol[0x10];
 387
 388         u8         gre_key_h[0x18];
 389         u8         gre_key_l[0x8];
 390
 391         u8         vxlan_vni[0x18];
 392         u8         reserved_at_b8[0x8];
 393
 394         u8         reserved_at_c0[0x20];
 395
 396         u8         reserved_at_e0[0xc];
 397         u8         outer_ipv6_flow_label[0x14];
 398
 399         u8         reserved_at_100[0xc];
 400         u8         inner_ipv6_flow_label[0x14];
 401
 402         u8         reserved_at_120[0xe0];
 403 };
 404
 405 struct mlx5_ifc_cmd_pas_bits {
 406         u8         pa_h[0x20];
 407
 408         u8         pa_l[0x14];
 409         u8         reserved_at_34[0xc];
 410 };
 411
 412 struct mlx5_ifc_uint64_bits {
 413         u8         hi[0x20];
 414
 415         u8         lo[0x20];
 416 };
 417
 418 enum {
 419         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 420         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 421         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 422         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 423         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 424         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 425         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 426         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 427         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 428         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 429 };
 430
 431 struct mlx5_ifc_ads_bits {
 432         u8         fl[0x1];
 433         u8         free_ar[0x1];
 434         u8         reserved_at_2[0xe];
 435         u8         pkey_index[0x10];
 436
 437         u8         reserved_at_20[0x8];
 438         u8         grh[0x1];
 439         u8         mlid[0x7];
 440         u8         rlid[0x10];
 441
 442         u8         ack_timeout[0x5];
 443         u8         reserved_at_45[0x3];
 444         u8         src_addr_index[0x8];
 445         u8         reserved_at_50[0x4];
 446         u8         stat_rate[0x4];
 447         u8         hop_limit[0x8];
 448
 449         u8         reserved_at_60[0x4];
 450         u8         tclass[0x8];
 451         u8         flow_label[0x14];
 452
 453         u8         rgid_rip[16][0x8];
 454
 455         u8         reserved_at_100[0x4];
 456         u8         f_dscp[0x1];
 457         u8         f_ecn[0x1];
 458         u8         reserved_at_106[0x1];
 459         u8         f_eth_prio[0x1];
 460         u8         ecn[0x2];
 461         u8         dscp[0x6];
 462         u8         udp_sport[0x10];
 463
 464         u8         dei_cfi[0x1];
 465         u8         eth_prio[0x3];
 466         u8         sl[0x4];
 467         u8         port[0x8];
 468         u8         rmac_47_32[0x10];
 469
 470         u8         rmac_31_0[0x20];
 471 };
 472
 473 struct mlx5_ifc_flow_table_nic_cap_bits {
 474         u8         nic_rx_multi_path_tirs[0x1];
 475         u8         reserved_at_1[0x1ff];
 476
 477         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 478
 479         u8         reserved_at_400[0x200];
 480
 481         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 482
 483         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 484
 485         u8         reserved_at_a00[0x200];
 486
 487         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 488
 489         u8         reserved_at_e00[0x7200];
 490 };
 491
 492 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 493         u8     reserved_at_0[0x200];
 494
 495         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 496
 497         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 498
 499         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 500
 501         u8      reserved_at_800[0x7800];
 502 };
 503
 504 struct mlx5_ifc_e_switch_cap_bits {
 505         u8         vport_svlan_strip[0x1];
 506         u8         vport_cvlan_strip[0x1];
 507         u8         vport_svlan_insert[0x1];
 508         u8         vport_cvlan_insert_if_not_exist[0x1];
 509         u8         vport_cvlan_insert_overwrite[0x1];
 510         u8         reserved_at_5[0x1b];
 511
 512         u8         reserved_at_20[0x7e0];
 513 };
 514
 515 struct mlx5_ifc_qos_cap_bits {
 516         u8         packet_pacing[0x1];
 517         u8         reserved_0[0x1f];
 518         u8         reserved_1[0x20];
 519         u8         packet_pacing_max_rate[0x20];
 520         u8         packet_pacing_min_rate[0x20];
 521         u8         reserved_2[0x10];
 522         u8         packet_pacing_rate_table_size[0x10];
 523         u8         reserved_3[0x760];
 524 };
 525
 526 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 527         u8         csum_cap[0x1];
 528         u8         vlan_cap[0x1];
 529         u8         lro_cap[0x1];
 530         u8         lro_psh_flag[0x1];
 531         u8         lro_time_stamp[0x1];
 532         u8         reserved_at_5[0x3];
 533         u8         self_lb_en_modifiable[0x1];
 534         u8         reserved_at_9[0x2];
 535         u8         max_lso_cap[0x5];
 536         u8         reserved_at_10[0x4];
 537         u8         rss_ind_tbl_cap[0x4];
 538         u8         reg_umr_sq[0x1];
 539         u8         scatter_fcs[0x1];
 540         u8         reserved_at_1a[0x1];
 541         u8         tunnel_lso_const_out_ip_id[0x1];
 542         u8         reserved_at_1c[0x2];
 543         u8         tunnel_statless_gre[0x1];
 544         u8         tunnel_stateless_vxlan[0x1];
 545
 546         u8         reserved_at_20[0x20];
 547
 548         u8         reserved_at_40[0x10];
 549         u8         lro_min_mss_size[0x10];
 550
 551         u8         reserved_at_60[0x120];
 552
 553         u8         lro_timer_supported_periods[4][0x20];
 554
 555         u8         reserved_at_200[0x600];
 556 };
 557
 558 struct mlx5_ifc_roce_cap_bits {
 559         u8         roce_apm[0x1];
 560         u8         reserved_at_1[0x1f];
 561
 562         u8         reserved_at_20[0x60];
 563
 564         u8         reserved_at_80[0xc];
 565         u8         l3_type[0x4];
 566         u8         reserved_at_90[0x8];
 567         u8         roce_version[0x8];
 568
 569         u8         reserved_at_a0[0x10];
 570         u8         r_roce_dest_udp_port[0x10];
 571
 572         u8         r_roce_max_src_udp_port[0x10];
 573         u8         r_roce_min_src_udp_port[0x10];
 574
 575         u8         reserved_at_e0[0x10];
 576         u8         roce_address_table_size[0x10];
 577
 578         u8         reserved_at_100[0x700];
 579 };
 580
 581 enum {
 582         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 583         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 584         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 585         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 586         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 587         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 588         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 589         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 590         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 591 };
 592
 593 enum {
 594         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 595         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 596         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 597         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 598         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 599         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 600         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 601         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 602         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 603 };
 604
 605 struct mlx5_ifc_atomic_caps_bits {
 606         u8         reserved_at_0[0x40];
 607
 608         u8         atomic_req_8B_endianess_mode[0x2];
 609         u8         reserved_at_42[0x4];
 610         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 611
 612         u8         reserved_at_47[0x19];
 613
 614         u8         reserved_at_60[0x20];
 615
 616         u8         reserved_at_80[0x10];
 617         u8         atomic_operations[0x10];
 618
 619         u8         reserved_at_a0[0x10];
 620         u8         atomic_size_qp[0x10];
 621
 622         u8         reserved_at_c0[0x10];
 623         u8         atomic_size_dc[0x10];
 624
 625         u8         reserved_at_e0[0x720];
 626 };
 627
 628 struct mlx5_ifc_odp_cap_bits {
 629         u8         reserved_at_0[0x40];
 630
 631         u8         sig[0x1];
 632         u8         reserved_at_41[0x1f];
 633
 634         u8         reserved_at_60[0x20];
 635
 636         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 637
 638         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 639
 640         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 641
 642         u8         reserved_at_e0[0x720];
 643 };
 644
 645 struct mlx5_ifc_calc_op {
 646         u8        reserved_at_0[0x10];
 647         u8        reserved_at_10[0x9];
 648         u8        op_swap_endianness[0x1];
 649         u8        op_min[0x1];
 650         u8        op_xor[0x1];
 651         u8        op_or[0x1];
 652         u8        op_and[0x1];
 653         u8        op_max[0x1];
 654         u8        op_add[0x1];
 655 };
 656
 657 struct mlx5_ifc_vector_calc_cap_bits {
 658         u8         calc_matrix[0x1];
 659         u8         reserved_at_1[0x1f];
 660         u8         reserved_at_20[0x8];
 661         u8         max_vec_count[0x8];
 662         u8         reserved_at_30[0xd];
 663         u8         max_chunk_size[0x3];
 664         struct mlx5_ifc_calc_op calc0;
 665         struct mlx5_ifc_calc_op calc1;
 666         struct mlx5_ifc_calc_op calc2;
 667         struct mlx5_ifc_calc_op calc3;
 668
 669         u8         reserved_at_e0[0x720];
 670 };
 671
 672 enum {
 673         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 674         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 675         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 676 };
 677
 678 enum {
 679         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 680         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 681 };
 682
 683 enum {
 684         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 685         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 686         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 687         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 688         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 689 };
 690
 691 enum {
 692         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 693         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 694         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 695         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 696         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 697         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 698 };
 699
 700 enum {
 701         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 702         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 703 };
 704
 705 enum {
 706         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 707         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 708         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 709 };
 710
 711 enum {
 712         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 713         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 714 };
 715
 716 struct mlx5_ifc_cmd_hca_cap_bits {
 717         u8         reserved_at_0[0x80];
 718
 719         u8         log_max_srq_sz[0x8];
 720         u8         log_max_qp_sz[0x8];
 721         u8         reserved_at_90[0xb];
 722         u8         log_max_qp[0x5];
 723
 724         u8         reserved_at_a0[0xb];
 725         u8         log_max_srq[0x5];
 726         u8         reserved_at_b0[0x10];
 727
 728         u8         reserved_at_c0[0x8];
 729         u8         log_max_cq_sz[0x8];
 730         u8         reserved_at_d0[0xb];
 731         u8         log_max_cq[0x5];
 732
 733         u8         log_max_eq_sz[0x8];
 734         u8         reserved_at_e8[0x2];
 735         u8         log_max_mkey[0x6];
 736         u8         reserved_at_f0[0xc];
 737         u8         log_max_eq[0x4];
 738
 739         u8         max_indirection[0x8];
 740         u8         reserved_at_108[0x1];
 741         u8         log_max_mrw_sz[0x7];
 742         u8         reserved_at_110[0x2];
 743         u8         log_max_bsf_list_size[0x6];
 744         u8         reserved_at_118[0x2];
 745         u8         log_max_klm_list_size[0x6];
 746
 747         u8         reserved_at_120[0xa];
 748         u8         log_max_ra_req_dc[0x6];
 749         u8         reserved_at_130[0xa];
 750         u8         log_max_ra_res_dc[0x6];
 751
 752         u8         reserved_at_140[0xa];
 753         u8         log_max_ra_req_qp[0x6];
 754         u8         reserved_at_150[0xa];
 755         u8         log_max_ra_res_qp[0x6];
 756
 757         u8         pad_cap[0x1];
 758         u8         cc_query_allowed[0x1];
 759         u8         cc_modify_allowed[0x1];
 760         u8         reserved_at_163[0xd];
 761         u8         gid_table_size[0x10];
 762
 763         u8         out_of_seq_cnt[0x1];
 764         u8         vport_counters[0x1];
 765         u8         retransmission_q_counters[0x1];
 766         u8         reserved_at_183[0x3];
 767         u8         max_qp_cnt[0xa];
 768         u8         pkey_table_size[0x10];
 769
 770         u8         vport_group_manager[0x1];
 771         u8         vhca_group_manager[0x1];
 772         u8         ib_virt[0x1];
 773         u8         eth_virt[0x1];
 774         u8         reserved_at_1a4[0x1];
 775         u8         ets[0x1];
 776         u8         nic_flow_table[0x1];
 777         u8         eswitch_flow_table[0x1];
 778         u8         early_vf_enable[0x1];
 779         u8         reserved_at_1a9[0x2];
 780         u8         local_ca_ack_delay[0x5];
 781         u8         reserved_at_1af[0x2];
 782         u8         ports_check[0x1];
 783         u8         reserved_at_1b2[0x1];
 784         u8         disable_link_up[0x1];
 785         u8         beacon_led[0x1];
 786         u8         port_type[0x2];
 787         u8         num_ports[0x8];
 788
 789         u8         reserved_at_1c0[0x3];
 790         u8         log_max_msg[0x5];
 791         u8         reserved_at_1c8[0x4];
 792         u8         max_tc[0x4];
 793         u8         reserved_at_1d0[0x1];
 794         u8         dcbx[0x1];
 795         u8         reserved_at_1d2[0x4];
 796         u8         rol_s[0x1];
 797         u8         rol_g[0x1];
 798         u8         reserved_at_1d8[0x1];
 799         u8         wol_s[0x1];
 800         u8         wol_g[0x1];
 801         u8         wol_a[0x1];
 802         u8         wol_b[0x1];
 803         u8         wol_m[0x1];
 804         u8         wol_u[0x1];
 805         u8         wol_p[0x1];
 806
 807         u8         stat_rate_support[0x10];
 808         u8         reserved_at_1f0[0xc];
 809         u8         cqe_version[0x4];
 810
 811         u8         compact_address_vector[0x1];
 812         u8         striding_rq[0x1];
 813         u8         reserved_at_201[0x2];
 814         u8         ipoib_basic_offloads[0x1];
 815         u8         reserved_at_205[0xa];
 816         u8         drain_sigerr[0x1];
 817         u8         cmdif_checksum[0x2];
 818         u8         sigerr_cqe[0x1];
 819         u8         reserved_at_213[0x1];
 820         u8         wq_signature[0x1];
 821         u8         sctr_data_cqe[0x1];
 822         u8         reserved_at_216[0x1];
 823         u8         sho[0x1];
 824         u8         tph[0x1];
 825         u8         rf[0x1];
 826         u8         dct[0x1];
 827         u8         qos[0x1];
 828         u8         eth_net_offloads[0x1];
 829         u8         roce[0x1];
 830         u8         atomic[0x1];
 831         u8         reserved_at_21f[0x1];
 832
 833         u8         cq_oi[0x1];
 834         u8         cq_resize[0x1];
 835         u8         cq_moderation[0x1];
 836         u8         reserved_at_223[0x3];
 837         u8         cq_eq_remap[0x1];
 838         u8         pg[0x1];
 839         u8         block_lb_mc[0x1];
 840         u8         reserved_at_229[0x1];
 841         u8         scqe_break_moderation[0x1];
 842         u8         cq_period_start_from_cqe[0x1];
 843         u8         cd[0x1];
 844         u8         reserved_at_22d[0x1];
 845         u8         apm[0x1];
 846         u8         vector_calc[0x1];
 847         u8         umr_ptr_rlky[0x1];
 848         u8         imaicl[0x1];
 849         u8         reserved_at_232[0x4];
 850         u8         qkv[0x1];
 851         u8         pkv[0x1];
 852         u8         set_deth_sqpn[0x1];
 853         u8         reserved_at_239[0x3];
 854         u8         xrc[0x1];
 855         u8         ud[0x1];
 856         u8         uc[0x1];
 857         u8         rc[0x1];
 858
 859         u8         reserved_at_240[0xa];
 860         u8         uar_sz[0x6];
 861         u8         reserved_at_250[0x8];
 862         u8         log_pg_sz[0x8];
 863
 864         u8         bf[0x1];
 865         u8         reserved_at_261[0x1];
 866         u8         pad_tx_eth_packet[0x1];
 867         u8         reserved_at_263[0x8];
 868         u8         log_bf_reg_size[0x5];
 869         u8         reserved_at_270[0x10];
 870
 871         u8         reserved_at_280[0x10];
 872         u8         max_wqe_sz_sq[0x10];
 873
 874         u8         reserved_at_2a0[0x10];
 875         u8         max_wqe_sz_rq[0x10];
 876
 877         u8         reserved_at_2c0[0x10];
 878         u8         max_wqe_sz_sq_dc[0x10];
 879
 880         u8         reserved_at_2e0[0x7];
 881         u8         max_qp_mcg[0x19];
 882
 883         u8         reserved_at_300[0x18];
 884         u8         log_max_mcg[0x8];
 885
 886         u8         reserved_at_320[0x3];
 887         u8         log_max_transport_domain[0x5];
 888         u8         reserved_at_328[0x3];
 889         u8         log_max_pd[0x5];
 890         u8         reserved_at_330[0xb];
 891         u8         log_max_xrcd[0x5];
 892
 893         u8         reserved_at_340[0x20];
 894
 895         u8         reserved_at_360[0x3];
 896         u8         log_max_rq[0x5];
 897         u8         reserved_at_368[0x3];
 898         u8         log_max_sq[0x5];
 899         u8         reserved_at_370[0x3];
 900         u8         log_max_tir[0x5];
 901         u8         reserved_at_378[0x3];
 902         u8         log_max_tis[0x5];
 903
 904         u8         basic_cyclic_rcv_wqe[0x1];
 905         u8         reserved_at_381[0x2];
 906         u8         log_max_rmp[0x5];
 907         u8         reserved_at_388[0x3];
 908         u8         log_max_rqt[0x5];
 909         u8         reserved_at_390[0x3];
 910         u8         log_max_rqt_size[0x5];
 911         u8         reserved_at_398[0x3];
 912         u8         log_max_tis_per_sq[0x5];
 913
 914         u8         reserved_at_3a0[0x3];
 915         u8         log_max_stride_sz_rq[0x5];
 916         u8         reserved_at_3a8[0x3];
 917         u8         log_min_stride_sz_rq[0x5];
 918         u8         reserved_at_3b0[0x3];
 919         u8         log_max_stride_sz_sq[0x5];
 920         u8         reserved_at_3b8[0x3];
 921         u8         log_min_stride_sz_sq[0x5];
 922
 923         u8         reserved_at_3c0[0x1b];
 924         u8         log_max_wq_sz[0x5];
 925
 926         u8         nic_vport_change_event[0x1];
 927         u8         reserved_at_3e1[0xa];
 928         u8         log_max_vlan_list[0x5];
 929         u8         reserved_at_3f0[0x3];
 930         u8         log_max_current_mc_list[0x5];
 931         u8         reserved_at_3f8[0x3];
 932         u8         log_max_current_uc_list[0x5];
 933
 934         u8         reserved_at_400[0x80];
 935
 936         u8         reserved_at_480[0x3];
 937         u8         log_max_l2_table[0x5];
 938         u8         reserved_at_488[0x8];
 939         u8         log_uar_page_sz[0x10];
 940
 941         u8         reserved_at_4a0[0x20];
 942         u8         device_frequency_mhz[0x20];
 943         u8         device_frequency_khz[0x20];
 944
 945         u8         reserved_at_500[0x80];
 946
 947         u8         reserved_at_580[0x3f];
 948         u8         cqe_compression[0x1];
 949
 950         u8         cqe_compression_timeout[0x10];
 951         u8         cqe_compression_max_num[0x10];
 952
 953         u8         reserved_at_5e0[0x10];
 954         u8         tag_matching[0x1];
 955         u8         rndv_offload_rc[0x1];
 956         u8         rndv_offload_dc[0x1];
 957         u8         log_tag_matching_list_sz[0x5];
 958         u8         reserved_at_5e8[0x3];
 959         u8         log_max_xrq[0x5];
 960
 961         u8         reserved_at_5f0[0x200];
 962 };
 963
 964 enum mlx5_flow_destination_type {
 965         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 966         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 967         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 968
 969         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
 970 };
 971
 972 struct mlx5_ifc_dest_format_struct_bits {
 973         u8         destination_type[0x8];
 974         u8         destination_id[0x18];
 975
 976         u8         reserved_at_20[0x20];
 977 };
 978
 979 struct mlx5_ifc_flow_counter_list_bits {
 980         u8         reserved_at_0[0x10];
 981         u8         flow_counter_id[0x10];
 982
 983         u8         reserved_at_20[0x20];
 984 };
 985
 986 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
 987         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
 988         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
 989         u8         reserved_at_0[0x40];
 990 };
 991
 992 struct mlx5_ifc_fte_match_param_bits {
 993         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 994
 995         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 996
 997         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 998
 999         u8         reserved_at_600[0xa00];
1000 };
1001
1002 enum {
1003         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1004         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1005         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1006         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1007         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1008 };
1009
1010 struct mlx5_ifc_rx_hash_field_select_bits {
1011         u8         l3_prot_type[0x1];
1012         u8         l4_prot_type[0x1];
1013         u8         selected_fields[0x1e];
1014 };
1015
1016 enum {
1017         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1018         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1019 };
1020
1021 enum {
1022         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1023         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1024 };
1025
1026 struct mlx5_ifc_wq_bits {
1027         u8         wq_type[0x4];
1028         u8         wq_signature[0x1];
1029         u8         end_padding_mode[0x2];
1030         u8         cd_slave[0x1];
1031         u8         reserved_at_8[0x18];
1032
1033         u8         hds_skip_first_sge[0x1];
1034         u8         log2_hds_buf_size[0x3];
1035         u8         reserved_at_24[0x7];
1036         u8         page_offset[0x5];
1037         u8         lwm[0x10];
1038
1039         u8         reserved_at_40[0x8];
1040         u8         pd[0x18];
1041
1042         u8         reserved_at_60[0x8];
1043         u8         uar_page[0x18];
1044
1045         u8         dbr_addr[0x40];
1046
1047         u8         hw_counter[0x20];
1048
1049         u8         sw_counter[0x20];
1050
1051         u8         reserved_at_100[0xc];
1052         u8         log_wq_stride[0x4];
1053         u8         reserved_at_110[0x3];
1054         u8         log_wq_pg_sz[0x5];
1055         u8         reserved_at_118[0x3];
1056         u8         log_wq_sz[0x5];
1057
1058         u8         reserved_at_120[0x15];
1059         u8         log_wqe_num_of_strides[0x3];
1060         u8         two_byte_shift_en[0x1];
1061         u8         reserved_at_139[0x4];
1062         u8         log_wqe_stride_size[0x3];
1063
1064         u8         reserved_at_140[0x4c0];
1065
1066         struct mlx5_ifc_cmd_pas_bits pas[0];
1067 };
1068
1069 struct mlx5_ifc_rq_num_bits {
1070         u8         reserved_at_0[0x8];
1071         u8         rq_num[0x18];
1072 };
1073
1074 struct mlx5_ifc_mac_address_layout_bits {
1075         u8         reserved_at_0[0x10];
1076         u8         mac_addr_47_32[0x10];
1077
1078         u8         mac_addr_31_0[0x20];
1079 };
1080
1081 struct mlx5_ifc_vlan_layout_bits {
1082         u8         reserved_at_0[0x14];
1083         u8         vlan[0x0c];
1084
1085         u8         reserved_at_20[0x20];
1086 };
1087
1088 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1089         u8         reserved_at_0[0xa0];
1090
1091         u8         min_time_between_cnps[0x20];
1092
1093         u8         reserved_at_c0[0x12];
1094         u8         cnp_dscp[0x6];
1095         u8         reserved_at_d8[0x5];
1096         u8         cnp_802p_prio[0x3];
1097
1098         u8         reserved_at_e0[0x720];
1099 };
1100
1101 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1102         u8         reserved_at_0[0x60];
1103
1104         u8         reserved_at_60[0x4];
1105         u8         clamp_tgt_rate[0x1];
1106         u8         reserved_at_65[0x3];
1107         u8         clamp_tgt_rate_after_time_inc[0x1];
1108         u8         reserved_at_69[0x17];
1109
1110         u8         reserved_at_80[0x20];
1111
1112         u8         rpg_time_reset[0x20];
1113
1114         u8         rpg_byte_reset[0x20];
1115
1116         u8         rpg_threshold[0x20];
1117
1118         u8         rpg_max_rate[0x20];
1119
1120         u8         rpg_ai_rate[0x20];
1121
1122         u8         rpg_hai_rate[0x20];
1123
1124         u8         rpg_gd[0x20];
1125
1126         u8         rpg_min_dec_fac[0x20];
1127
1128         u8         rpg_min_rate[0x20];
1129
1130         u8         reserved_at_1c0[0xe0];
1131
1132         u8         rate_to_set_on_first_cnp[0x20];
1133
1134         u8         dce_tcp_g[0x20];
1135
1136         u8         dce_tcp_rtt[0x20];
1137
1138         u8         rate_reduce_monitor_period[0x20];
1139
1140         u8         reserved_at_320[0x20];
1141
1142         u8         initial_alpha_value[0x20];
1143
1144         u8         reserved_at_360[0x4a0];
1145 };
1146
1147 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1148         u8         reserved_at_0[0x80];
1149
1150         u8         rppp_max_rps[0x20];
1151
1152         u8         rpg_time_reset[0x20];
1153
1154         u8         rpg_byte_reset[0x20];
1155
1156         u8         rpg_threshold[0x20];
1157
1158         u8         rpg_max_rate[0x20];
1159
1160         u8         rpg_ai_rate[0x20];
1161
1162         u8         rpg_hai_rate[0x20];
1163
1164         u8         rpg_gd[0x20];
1165
1166         u8         rpg_min_dec_fac[0x20];
1167
1168         u8         rpg_min_rate[0x20];
1169
1170         u8         reserved_at_1c0[0x640];
1171 };
1172
1173 enum {
1174         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1175         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1176         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1177 };
1178
1179 struct mlx5_ifc_resize_field_select_bits {
1180         u8         resize_field_select[0x20];
1181 };
1182
1183 enum {
1184         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1185         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1186         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1187         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1188 };
1189
1190 struct mlx5_ifc_modify_field_select_bits {
1191         u8         modify_field_select[0x20];
1192 };
1193
1194 struct mlx5_ifc_field_select_r_roce_np_bits {
1195         u8         field_select_r_roce_np[0x20];
1196 };
1197
1198 struct mlx5_ifc_field_select_r_roce_rp_bits {
1199         u8         field_select_r_roce_rp[0x20];
1200 };
1201
1202 enum {
1203         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1204         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1205         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1206         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1207         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1208         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1209         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1210         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1211         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1212         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1213 };
1214
1215 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1216         u8         field_select_8021qaurp[0x20];
1217 };
1218
1219 struct mlx5_ifc_phys_layer_cntrs_bits {
1220         u8         time_since_last_clear_high[0x20];
1221
1222         u8         time_since_last_clear_low[0x20];
1223
1224         u8         symbol_errors_high[0x20];
1225
1226         u8         symbol_errors_low[0x20];
1227
1228         u8         sync_headers_errors_high[0x20];
1229
1230         u8         sync_headers_errors_low[0x20];
1231
1232         u8         edpl_bip_errors_lane0_high[0x20];
1233
1234         u8         edpl_bip_errors_lane0_low[0x20];
1235
1236         u8         edpl_bip_errors_lane1_high[0x20];
1237
1238         u8         edpl_bip_errors_lane1_low[0x20];
1239
1240         u8         edpl_bip_errors_lane2_high[0x20];
1241
1242         u8         edpl_bip_errors_lane2_low[0x20];
1243
1244         u8         edpl_bip_errors_lane3_high[0x20];
1245
1246         u8         edpl_bip_errors_lane3_low[0x20];
1247
1248         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1249
1250         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1251
1252         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1253
1254         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1255
1256         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1257
1258         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1259
1260         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1261
1262         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1263
1264         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1265
1266         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1267
1268         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1269
1270         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1271
1272         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1273
1274         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1275
1276         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1277
1278         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1279
1280         u8         rs_fec_corrected_blocks_high[0x20];
1281
1282         u8         rs_fec_corrected_blocks_low[0x20];
1283
1284         u8         rs_fec_uncorrectable_blocks_high[0x20];
1285
1286         u8         rs_fec_uncorrectable_blocks_low[0x20];
1287
1288         u8         rs_fec_no_errors_blocks_high[0x20];
1289
1290         u8         rs_fec_no_errors_blocks_low[0x20];
1291
1292         u8         rs_fec_single_error_blocks_high[0x20];
1293
1294         u8         rs_fec_single_error_blocks_low[0x20];
1295
1296         u8         rs_fec_corrected_symbols_total_high[0x20];
1297
1298         u8         rs_fec_corrected_symbols_total_low[0x20];
1299
1300         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1301
1302         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1303
1304         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1305
1306         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1307
1308         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1309
1310         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1311
1312         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1313
1314         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1315
1316         u8         link_down_events[0x20];
1317
1318         u8         successful_recovery_events[0x20];
1319
1320         u8         reserved_at_640[0x180];
1321 };
1322
1323 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1324         u8         symbol_error_counter[0x10];
1325
1326         u8         link_error_recovery_counter[0x8];
1327
1328         u8         link_downed_counter[0x8];
1329
1330         u8         port_rcv_errors[0x10];
1331
1332         u8         port_rcv_remote_physical_errors[0x10];
1333
1334         u8         port_rcv_switch_relay_errors[0x10];
1335
1336         u8         port_xmit_discards[0x10];
1337
1338         u8         port_xmit_constraint_errors[0x8];
1339
1340         u8         port_rcv_constraint_errors[0x8];
1341
1342         u8         reserved_at_70[0x8];
1343
1344         u8         link_overrun_errors[0x8];
1345
1346         u8         reserved_at_80[0x10];
1347
1348         u8         vl_15_dropped[0x10];
1349
1350         u8         reserved_at_a0[0xa0];
1351 };
1352
1353 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1354         u8         transmit_queue_high[0x20];
1355
1356         u8         transmit_queue_low[0x20];
1357
1358         u8         reserved_at_40[0x780];
1359 };
1360
1361 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1362         u8         rx_octets_high[0x20];
1363
1364         u8         rx_octets_low[0x20];
1365
1366         u8         reserved_at_40[0xc0];
1367
1368         u8         rx_frames_high[0x20];
1369
1370         u8         rx_frames_low[0x20];
1371
1372         u8         tx_octets_high[0x20];
1373
1374         u8         tx_octets_low[0x20];
1375
1376         u8         reserved_at_180[0xc0];
1377
1378         u8         tx_frames_high[0x20];
1379
1380         u8         tx_frames_low[0x20];
1381
1382         u8         rx_pause_high[0x20];
1383
1384         u8         rx_pause_low[0x20];
1385
1386         u8         rx_pause_duration_high[0x20];
1387
1388         u8         rx_pause_duration_low[0x20];
1389
1390         u8         tx_pause_high[0x20];
1391
1392         u8         tx_pause_low[0x20];
1393
1394         u8         tx_pause_duration_high[0x20];
1395
1396         u8         tx_pause_duration_low[0x20];
1397
1398         u8         rx_pause_transition_high[0x20];
1399
1400         u8         rx_pause_transition_low[0x20];
1401
1402         u8         reserved_at_3c0[0x400];
1403 };
1404
1405 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1406         u8         port_transmit_wait_high[0x20];
1407
1408         u8         port_transmit_wait_low[0x20];
1409
1410         u8         reserved_at_40[0x780];
1411 };
1412
1413 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1414         u8         dot3stats_alignment_errors_high[0x20];
1415
1416         u8         dot3stats_alignment_errors_low[0x20];
1417
1418         u8         dot3stats_fcs_errors_high[0x20];
1419
1420         u8         dot3stats_fcs_errors_low[0x20];
1421
1422         u8         dot3stats_single_collision_frames_high[0x20];
1423
1424         u8         dot3stats_single_collision_frames_low[0x20];
1425
1426         u8         dot3stats_multiple_collision_frames_high[0x20];
1427
1428         u8         dot3stats_multiple_collision_frames_low[0x20];
1429
1430         u8         dot3stats_sqe_test_errors_high[0x20];
1431
1432         u8         dot3stats_sqe_test_errors_low[0x20];
1433
1434         u8         dot3stats_deferred_transmissions_high[0x20];
1435
1436         u8         dot3stats_deferred_transmissions_low[0x20];
1437
1438         u8         dot3stats_late_collisions_high[0x20];
1439
1440         u8         dot3stats_late_collisions_low[0x20];
1441
1442         u8         dot3stats_excessive_collisions_high[0x20];
1443
1444         u8         dot3stats_excessive_collisions_low[0x20];
1445
1446         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1447
1448         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1449
1450         u8         dot3stats_carrier_sense_errors_high[0x20];
1451
1452         u8         dot3stats_carrier_sense_errors_low[0x20];
1453
1454         u8         dot3stats_frame_too_longs_high[0x20];
1455
1456         u8         dot3stats_frame_too_longs_low[0x20];
1457
1458         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1459
1460         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1461
1462         u8         dot3stats_symbol_errors_high[0x20];
1463
1464         u8         dot3stats_symbol_errors_low[0x20];
1465
1466         u8         dot3control_in_unknown_opcodes_high[0x20];
1467
1468         u8         dot3control_in_unknown_opcodes_low[0x20];
1469
1470         u8         dot3in_pause_frames_high[0x20];
1471
1472         u8         dot3in_pause_frames_low[0x20];
1473
1474         u8         dot3out_pause_frames_high[0x20];
1475
1476         u8         dot3out_pause_frames_low[0x20];
1477
1478         u8         reserved_at_400[0x3c0];
1479 };
1480
1481 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1482         u8         ether_stats_drop_events_high[0x20];
1483
1484         u8         ether_stats_drop_events_low[0x20];
1485
1486         u8         ether_stats_octets_high[0x20];
1487
1488         u8         ether_stats_octets_low[0x20];
1489
1490         u8         ether_stats_pkts_high[0x20];
1491
1492         u8         ether_stats_pkts_low[0x20];
1493
1494         u8         ether_stats_broadcast_pkts_high[0x20];
1495
1496         u8         ether_stats_broadcast_pkts_low[0x20];
1497
1498         u8         ether_stats_multicast_pkts_high[0x20];
1499
1500         u8         ether_stats_multicast_pkts_low[0x20];
1501
1502         u8         ether_stats_crc_align_errors_high[0x20];
1503
1504         u8         ether_stats_crc_align_errors_low[0x20];
1505
1506         u8         ether_stats_undersize_pkts_high[0x20];
1507
1508         u8         ether_stats_undersize_pkts_low[0x20];
1509
1510         u8         ether_stats_oversize_pkts_high[0x20];
1511
1512         u8         ether_stats_oversize_pkts_low[0x20];
1513
1514         u8         ether_stats_fragments_high[0x20];
1515
1516         u8         ether_stats_fragments_low[0x20];
1517
1518         u8         ether_stats_jabbers_high[0x20];
1519
1520         u8         ether_stats_jabbers_low[0x20];
1521
1522         u8         ether_stats_collisions_high[0x20];
1523
1524         u8         ether_stats_collisions_low[0x20];
1525
1526         u8         ether_stats_pkts64octets_high[0x20];
1527
1528         u8         ether_stats_pkts64octets_low[0x20];
1529
1530         u8         ether_stats_pkts65to127octets_high[0x20];
1531
1532         u8         ether_stats_pkts65to127octets_low[0x20];
1533
1534         u8         ether_stats_pkts128to255octets_high[0x20];
1535
1536         u8         ether_stats_pkts128to255octets_low[0x20];
1537
1538         u8         ether_stats_pkts256to511octets_high[0x20];
1539
1540         u8         ether_stats_pkts256to511octets_low[0x20];
1541
1542         u8         ether_stats_pkts512to1023octets_high[0x20];
1543
1544         u8         ether_stats_pkts512to1023octets_low[0x20];
1545
1546         u8         ether_stats_pkts1024to1518octets_high[0x20];
1547
1548         u8         ether_stats_pkts1024to1518octets_low[0x20];
1549
1550         u8         ether_stats_pkts1519to2047octets_high[0x20];
1551
1552         u8         ether_stats_pkts1519to2047octets_low[0x20];
1553
1554         u8         ether_stats_pkts2048to4095octets_high[0x20];
1555
1556         u8         ether_stats_pkts2048to4095octets_low[0x20];
1557
1558         u8         ether_stats_pkts4096to8191octets_high[0x20];
1559
1560         u8         ether_stats_pkts4096to8191octets_low[0x20];
1561
1562         u8         ether_stats_pkts8192to10239octets_high[0x20];
1563
1564         u8         ether_stats_pkts8192to10239octets_low[0x20];
1565
1566         u8         reserved_at_540[0x280];
1567 };
1568
1569 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1570         u8         if_in_octets_high[0x20];
1571
1572         u8         if_in_octets_low[0x20];
1573
1574         u8         if_in_ucast_pkts_high[0x20];
1575
1576         u8         if_in_ucast_pkts_low[0x20];
1577
1578         u8         if_in_discards_high[0x20];
1579
1580         u8         if_in_discards_low[0x20];
1581
1582         u8         if_in_errors_high[0x20];
1583
1584         u8         if_in_errors_low[0x20];
1585
1586         u8         if_in_unknown_protos_high[0x20];
1587
1588         u8         if_in_unknown_protos_low[0x20];
1589
1590         u8         if_out_octets_high[0x20];
1591
1592         u8         if_out_octets_low[0x20];
1593
1594         u8         if_out_ucast_pkts_high[0x20];
1595
1596         u8         if_out_ucast_pkts_low[0x20];
1597
1598         u8         if_out_discards_high[0x20];
1599
1600         u8         if_out_discards_low[0x20];
1601
1602         u8         if_out_errors_high[0x20];
1603
1604         u8         if_out_errors_low[0x20];
1605
1606         u8         if_in_multicast_pkts_high[0x20];
1607
1608         u8         if_in_multicast_pkts_low[0x20];
1609
1610         u8         if_in_broadcast_pkts_high[0x20];
1611
1612         u8         if_in_broadcast_pkts_low[0x20];
1613
1614         u8         if_out_multicast_pkts_high[0x20];
1615
1616         u8         if_out_multicast_pkts_low[0x20];
1617
1618         u8         if_out_broadcast_pkts_high[0x20];
1619
1620         u8         if_out_broadcast_pkts_low[0x20];
1621
1622         u8         reserved_at_340[0x480];
1623 };
1624
1625 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1626         u8         a_frames_transmitted_ok_high[0x20];
1627
1628         u8         a_frames_transmitted_ok_low[0x20];
1629
1630         u8         a_frames_received_ok_high[0x20];
1631
1632         u8         a_frames_received_ok_low[0x20];
1633
1634         u8         a_frame_check_sequence_errors_high[0x20];
1635
1636         u8         a_frame_check_sequence_errors_low[0x20];
1637
1638         u8         a_alignment_errors_high[0x20];
1639
1640         u8         a_alignment_errors_low[0x20];
1641
1642         u8         a_octets_transmitted_ok_high[0x20];
1643
1644         u8         a_octets_transmitted_ok_low[0x20];
1645
1646         u8         a_octets_received_ok_high[0x20];
1647
1648         u8         a_octets_received_ok_low[0x20];
1649
1650         u8         a_multicast_frames_xmitted_ok_high[0x20];
1651
1652         u8         a_multicast_frames_xmitted_ok_low[0x20];
1653
1654         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1655
1656         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1657
1658         u8         a_multicast_frames_received_ok_high[0x20];
1659
1660         u8         a_multicast_frames_received_ok_low[0x20];
1661
1662         u8         a_broadcast_frames_received_ok_high[0x20];
1663
1664         u8         a_broadcast_frames_received_ok_low[0x20];
1665
1666         u8         a_in_range_length_errors_high[0x20];
1667
1668         u8         a_in_range_length_errors_low[0x20];
1669
1670         u8         a_out_of_range_length_field_high[0x20];
1671
1672         u8         a_out_of_range_length_field_low[0x20];
1673
1674         u8         a_frame_too_long_errors_high[0x20];
1675
1676         u8         a_frame_too_long_errors_low[0x20];
1677
1678         u8         a_symbol_error_during_carrier_high[0x20];
1679
1680         u8         a_symbol_error_during_carrier_low[0x20];
1681
1682         u8         a_mac_control_frames_transmitted_high[0x20];
1683
1684         u8         a_mac_control_frames_transmitted_low[0x20];
1685
1686         u8         a_mac_control_frames_received_high[0x20];
1687
1688         u8         a_mac_control_frames_received_low[0x20];
1689
1690         u8         a_unsupported_opcodes_received_high[0x20];
1691
1692         u8         a_unsupported_opcodes_received_low[0x20];
1693
1694         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1695
1696         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1697
1698         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1699
1700         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1701
1702         u8         reserved_at_4c0[0x300];
1703 };
1704
1705 struct mlx5_ifc_cmd_inter_comp_event_bits {
1706         u8         command_completion_vector[0x20];
1707
1708         u8         reserved_at_20[0xc0];
1709 };
1710
1711 struct mlx5_ifc_stall_vl_event_bits {
1712         u8         reserved_at_0[0x18];
1713         u8         port_num[0x1];
1714         u8         reserved_at_19[0x3];
1715         u8         vl[0x4];
1716
1717         u8         reserved_at_20[0xa0];
1718 };
1719
1720 struct mlx5_ifc_db_bf_congestion_event_bits {
1721         u8         event_subtype[0x8];
1722         u8         reserved_at_8[0x8];
1723         u8         congestion_level[0x8];
1724         u8         reserved_at_18[0x8];
1725
1726         u8         reserved_at_20[0xa0];
1727 };
1728
1729 struct mlx5_ifc_gpio_event_bits {
1730         u8         reserved_at_0[0x60];
1731
1732         u8         gpio_event_hi[0x20];
1733
1734         u8         gpio_event_lo[0x20];
1735
1736         u8         reserved_at_a0[0x40];
1737 };
1738
1739 struct mlx5_ifc_port_state_change_event_bits {
1740         u8         reserved_at_0[0x40];
1741
1742         u8         port_num[0x4];
1743         u8         reserved_at_44[0x1c];
1744
1745         u8         reserved_at_60[0x80];
1746 };
1747
1748 struct mlx5_ifc_dropped_packet_logged_bits {
1749         u8         reserved_at_0[0xe0];
1750 };
1751
1752 enum {
1753         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1754         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1755 };
1756
1757 struct mlx5_ifc_cq_error_bits {
1758         u8         reserved_at_0[0x8];
1759         u8         cqn[0x18];
1760
1761         u8         reserved_at_20[0x20];
1762
1763         u8         reserved_at_40[0x18];
1764         u8         syndrome[0x8];
1765
1766         u8         reserved_at_60[0x80];
1767 };
1768
1769 struct mlx5_ifc_rdma_page_fault_event_bits {
1770         u8         bytes_committed[0x20];
1771
1772         u8         r_key[0x20];
1773
1774         u8         reserved_at_40[0x10];
1775         u8         packet_len[0x10];
1776
1777         u8         rdma_op_len[0x20];
1778
1779         u8         rdma_va[0x40];
1780
1781         u8         reserved_at_c0[0x5];
1782         u8         rdma[0x1];
1783         u8         write[0x1];
1784         u8         requestor[0x1];
1785         u8         qp_number[0x18];
1786 };
1787
1788 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1789         u8         bytes_committed[0x20];
1790
1791         u8         reserved_at_20[0x10];
1792         u8         wqe_index[0x10];
1793
1794         u8         reserved_at_40[0x10];
1795         u8         len[0x10];
1796
1797         u8         reserved_at_60[0x60];
1798
1799         u8         reserved_at_c0[0x5];
1800         u8         rdma[0x1];
1801         u8         write_read[0x1];
1802         u8         requestor[0x1];
1803         u8         qpn[0x18];
1804 };
1805
1806 struct mlx5_ifc_qp_events_bits {
1807         u8         reserved_at_0[0xa0];
1808
1809         u8         type[0x8];
1810         u8         reserved_at_a8[0x18];
1811
1812         u8         reserved_at_c0[0x8];
1813         u8         qpn_rqn_sqn[0x18];
1814 };
1815
1816 struct mlx5_ifc_dct_events_bits {
1817         u8         reserved_at_0[0xc0];
1818
1819         u8         reserved_at_c0[0x8];
1820         u8         dct_number[0x18];
1821 };
1822
1823 struct mlx5_ifc_comp_event_bits {
1824         u8         reserved_at_0[0xc0];
1825
1826         u8         reserved_at_c0[0x8];
1827         u8         cq_number[0x18];
1828 };
1829
1830 enum {
1831         MLX5_QPC_STATE_RST        = 0x0,
1832         MLX5_QPC_STATE_INIT       = 0x1,
1833         MLX5_QPC_STATE_RTR        = 0x2,
1834         MLX5_QPC_STATE_RTS        = 0x3,
1835         MLX5_QPC_STATE_SQER       = 0x4,
1836         MLX5_QPC_STATE_ERR        = 0x6,
1837         MLX5_QPC_STATE_SQD        = 0x7,
1838         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1839 };
1840
1841 enum {
1842         MLX5_QPC_ST_RC            = 0x0,
1843         MLX5_QPC_ST_UC            = 0x1,
1844         MLX5_QPC_ST_UD            = 0x2,
1845         MLX5_QPC_ST_XRC           = 0x3,
1846         MLX5_QPC_ST_DCI           = 0x5,
1847         MLX5_QPC_ST_QP0           = 0x7,
1848         MLX5_QPC_ST_QP1           = 0x8,
1849         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1850         MLX5_QPC_ST_REG_UMR       = 0xc,
1851 };
1852
1853 enum {
1854         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1855         MLX5_QPC_PM_STATE_REARM     = 0x1,
1856         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1857         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1858 };
1859
1860 enum {
1861         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1862         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1863 };
1864
1865 enum {
1866         MLX5_QPC_MTU_256_BYTES        = 0x1,
1867         MLX5_QPC_MTU_512_BYTES        = 0x2,
1868         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1869         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1870         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1871         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1872 };
1873
1874 enum {
1875         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1876         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1877         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1878         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1879         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1880         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1881         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1882         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1883 };
1884
1885 enum {
1886         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1887         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1888         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1889 };
1890
1891 enum {
1892         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1893         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1894         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1895 };
1896
1897 struct mlx5_ifc_qpc_bits {
1898         u8         state[0x4];
1899         u8         reserved_at_4[0x4];
1900         u8         st[0x8];
1901         u8         reserved_at_10[0x3];
1902         u8         pm_state[0x2];
1903         u8         reserved_at_15[0x7];
1904         u8         end_padding_mode[0x2];
1905         u8         reserved_at_1e[0x2];
1906
1907         u8         wq_signature[0x1];
1908         u8         block_lb_mc[0x1];
1909         u8         atomic_like_write_en[0x1];
1910         u8         latency_sensitive[0x1];
1911         u8         reserved_at_24[0x1];
1912         u8         drain_sigerr[0x1];
1913         u8         reserved_at_26[0x2];
1914         u8         pd[0x18];
1915
1916         u8         mtu[0x3];
1917         u8         log_msg_max[0x5];
1918         u8         reserved_at_48[0x1];
1919         u8         log_rq_size[0x4];
1920         u8         log_rq_stride[0x3];
1921         u8         no_sq[0x1];
1922         u8         log_sq_size[0x4];
1923         u8         reserved_at_55[0x6];
1924         u8         rlky[0x1];
1925         u8         ulp_stateless_offload_mode[0x4];
1926
1927         u8         counter_set_id[0x8];
1928         u8         uar_page[0x18];
1929
1930         u8         reserved_at_80[0x8];
1931         u8         user_index[0x18];
1932
1933         u8         reserved_at_a0[0x3];
1934         u8         log_page_size[0x5];
1935         u8         remote_qpn[0x18];
1936
1937         struct mlx5_ifc_ads_bits primary_address_path;
1938
1939         struct mlx5_ifc_ads_bits secondary_address_path;
1940
1941         u8         log_ack_req_freq[0x4];
1942         u8         reserved_at_384[0x4];
1943         u8         log_sra_max[0x3];
1944         u8         reserved_at_38b[0x2];
1945         u8         retry_count[0x3];
1946         u8         rnr_retry[0x3];
1947         u8         reserved_at_393[0x1];
1948         u8         fre[0x1];
1949         u8         cur_rnr_retry[0x3];
1950         u8         cur_retry_count[0x3];
1951         u8         reserved_at_39b[0x5];
1952
1953         u8         reserved_at_3a0[0x20];
1954
1955         u8         reserved_at_3c0[0x8];
1956         u8         next_send_psn[0x18];
1957
1958         u8         reserved_at_3e0[0x8];
1959         u8         cqn_snd[0x18];
1960
1961         u8         reserved_at_400[0x40];
1962
1963         u8         reserved_at_440[0x8];
1964         u8         last_acked_psn[0x18];
1965
1966         u8         reserved_at_460[0x8];
1967         u8         ssn[0x18];
1968
1969         u8         reserved_at_480[0x8];
1970         u8         log_rra_max[0x3];
1971         u8         reserved_at_48b[0x1];
1972         u8         atomic_mode[0x4];
1973         u8         rre[0x1];
1974         u8         rwe[0x1];
1975         u8         rae[0x1];
1976         u8         reserved_at_493[0x1];
1977         u8         page_offset[0x6];
1978         u8         reserved_at_49a[0x3];
1979         u8         cd_slave_receive[0x1];
1980         u8         cd_slave_send[0x1];
1981         u8         cd_master[0x1];
1982
1983         u8         reserved_at_4a0[0x3];
1984         u8         min_rnr_nak[0x5];
1985         u8         next_rcv_psn[0x18];
1986
1987         u8         reserved_at_4c0[0x8];
1988         u8         xrcd[0x18];
1989
1990         u8         reserved_at_4e0[0x8];
1991         u8         cqn_rcv[0x18];
1992
1993         u8         dbr_addr[0x40];
1994
1995         u8         q_key[0x20];
1996
1997         u8         reserved_at_560[0x5];
1998         u8         rq_type[0x3];
1999         u8         srqn_rmpn_xrqn[0x18];
2000
2001         u8         reserved_at_580[0x8];
2002         u8         rmsn[0x18];
2003
2004         u8         hw_sq_wqebb_counter[0x10];
2005         u8         sw_sq_wqebb_counter[0x10];
2006
2007         u8         hw_rq_counter[0x20];
2008
2009         u8         sw_rq_counter[0x20];
2010
2011         u8         reserved_at_600[0x20];
2012
2013         u8         reserved_at_620[0xf];
2014         u8         cgs[0x1];
2015         u8         cs_req[0x8];
2016         u8         cs_res[0x8];
2017
2018         u8         dc_access_key[0x40];
2019
2020         u8         reserved_at_680[0xc0];
2021 };
2022
2023 struct mlx5_ifc_roce_addr_layout_bits {
2024         u8         source_l3_address[16][0x8];
2025
2026         u8         reserved_at_80[0x3];
2027         u8         vlan_valid[0x1];
2028         u8         vlan_id[0xc];
2029         u8         source_mac_47_32[0x10];
2030
2031         u8         source_mac_31_0[0x20];
2032
2033         u8         reserved_at_c0[0x14];
2034         u8         roce_l3_type[0x4];
2035         u8         roce_version[0x8];
2036
2037         u8         reserved_at_e0[0x20];
2038 };
2039
2040 union mlx5_ifc_hca_cap_union_bits {
2041         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2042         struct mlx5_ifc_odp_cap_bits odp_cap;
2043         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2044         struct mlx5_ifc_roce_cap_bits roce_cap;
2045         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2046         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2047         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2048         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2049         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2050         struct mlx5_ifc_qos_cap_bits qos_cap;
2051         u8         reserved_at_0[0x8000];
2052 };
2053
2054 enum {
2055         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2056         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2057         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2058         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2059 };
2060
2061 struct mlx5_ifc_flow_context_bits {
2062         u8         reserved_at_0[0x20];
2063
2064         u8         group_id[0x20];
2065
2066         u8         reserved_at_40[0x8];
2067         u8         flow_tag[0x18];
2068
2069         u8         reserved_at_60[0x10];
2070         u8         action[0x10];
2071
2072         u8         reserved_at_80[0x8];
2073         u8         destination_list_size[0x18];
2074
2075         u8         reserved_at_a0[0x8];
2076         u8         flow_counter_list_size[0x18];
2077
2078         u8         reserved_at_c0[0x140];
2079
2080         struct mlx5_ifc_fte_match_param_bits match_value;
2081
2082         u8         reserved_at_1200[0x600];
2083
2084         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2085 };
2086
2087 enum {
2088         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2089         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2090 };
2091
2092 struct mlx5_ifc_xrc_srqc_bits {
2093         u8         state[0x4];
2094         u8         log_xrc_srq_size[0x4];
2095         u8         reserved_at_8[0x18];
2096
2097         u8         wq_signature[0x1];
2098         u8         cont_srq[0x1];
2099         u8         reserved_at_22[0x1];
2100         u8         rlky[0x1];
2101         u8         basic_cyclic_rcv_wqe[0x1];
2102         u8         log_rq_stride[0x3];
2103         u8         xrcd[0x18];
2104
2105         u8         page_offset[0x6];
2106         u8         reserved_at_46[0x2];
2107         u8         cqn[0x18];
2108
2109         u8         reserved_at_60[0x20];
2110
2111         u8         user_index_equal_xrc_srqn[0x1];
2112         u8         reserved_at_81[0x1];
2113         u8         log_page_size[0x6];
2114         u8         user_index[0x18];
2115
2116         u8         reserved_at_a0[0x20];
2117
2118         u8         reserved_at_c0[0x8];
2119         u8         pd[0x18];
2120
2121         u8         lwm[0x10];
2122         u8         wqe_cnt[0x10];
2123
2124         u8         reserved_at_100[0x40];
2125
2126         u8         db_record_addr_h[0x20];
2127
2128         u8         db_record_addr_l[0x1e];
2129         u8         reserved_at_17e[0x2];
2130
2131         u8         reserved_at_180[0x80];
2132 };
2133
2134 struct mlx5_ifc_traffic_counter_bits {
2135         u8         packets[0x40];
2136
2137         u8         octets[0x40];
2138 };
2139
2140 struct mlx5_ifc_tisc_bits {
2141         u8         reserved_at_0[0xc];
2142         u8         prio[0x4];
2143         u8         reserved_at_10[0x10];
2144
2145         u8         reserved_at_20[0x100];
2146
2147         u8         reserved_at_120[0x8];
2148         u8         transport_domain[0x18];
2149
2150         u8         reserved_at_140[0x3c0];
2151 };
2152
2153 enum {
2154         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2155         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2156 };
2157
2158 enum {
2159         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2160         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2161 };
2162
2163 enum {
2164         MLX5_RX_HASH_FN_NONE           = 0x0,
2165         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2166         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2167 };
2168
2169 enum {
2170         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2171         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2172 };
2173
2174 struct mlx5_ifc_tirc_bits {
2175         u8         reserved_at_0[0x20];
2176
2177         u8         disp_type[0x4];
2178         u8         reserved_at_24[0x1c];
2179
2180         u8         reserved_at_40[0x40];
2181
2182         u8         reserved_at_80[0x4];
2183         u8         lro_timeout_period_usecs[0x10];
2184         u8         lro_enable_mask[0x4];
2185         u8         lro_max_ip_payload_size[0x8];
2186
2187         u8         reserved_at_a0[0x40];
2188
2189         u8         reserved_at_e0[0x8];
2190         u8         inline_rqn[0x18];
2191
2192         u8         rx_hash_symmetric[0x1];
2193         u8         reserved_at_101[0x1];
2194         u8         tunneled_offload_en[0x1];
2195         u8         reserved_at_103[0x5];
2196         u8         indirect_table[0x18];
2197
2198         u8         rx_hash_fn[0x4];
2199         u8         reserved_at_124[0x2];
2200         u8         self_lb_block[0x2];
2201         u8         transport_domain[0x18];
2202
2203         u8         rx_hash_toeplitz_key[10][0x20];
2204
2205         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2206
2207         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2208
2209         u8         reserved_at_2c0[0x4c0];
2210 };
2211
2212 enum {
2213         MLX5_SRQC_STATE_GOOD   = 0x0,
2214         MLX5_SRQC_STATE_ERROR  = 0x1,
2215 };
2216
2217 struct mlx5_ifc_srqc_bits {
2218         u8         state[0x4];
2219         u8         log_srq_size[0x4];
2220         u8         reserved_at_8[0x18];
2221
2222         u8         wq_signature[0x1];
2223         u8         cont_srq[0x1];
2224         u8         reserved_at_22[0x1];
2225         u8         rlky[0x1];
2226         u8         reserved_at_24[0x1];
2227         u8         log_rq_stride[0x3];
2228         u8         xrcd[0x18];
2229
2230         u8         page_offset[0x6];
2231         u8         reserved_at_46[0x2];
2232         u8         cqn[0x18];
2233
2234         u8         reserved_at_60[0x20];
2235
2236         u8         reserved_at_80[0x2];
2237         u8         log_page_size[0x6];
2238         u8         reserved_at_88[0x18];
2239
2240         u8         reserved_at_a0[0x20];
2241
2242         u8         reserved_at_c0[0x8];
2243         u8         pd[0x18];
2244
2245         u8         lwm[0x10];
2246         u8         wqe_cnt[0x10];
2247
2248         u8         reserved_at_100[0x40];
2249
2250         u8         dbr_addr[0x40];
2251
2252         u8         reserved_at_180[0x80];
2253 };
2254
2255 enum {
2256         MLX5_SQC_STATE_RST  = 0x0,
2257         MLX5_SQC_STATE_RDY  = 0x1,
2258         MLX5_SQC_STATE_ERR  = 0x3,
2259 };
2260
2261 struct mlx5_ifc_sqc_bits {
2262         u8         rlky[0x1];
2263         u8         cd_master[0x1];
2264         u8         fre[0x1];
2265         u8         flush_in_error_en[0x1];
2266         u8         reserved_at_4[0x4];
2267         u8         state[0x4];
2268         u8         reg_umr[0x1];
2269         u8         reserved_at_d[0x13];
2270
2271         u8         reserved_at_20[0x8];
2272         u8         user_index[0x18];
2273
2274         u8         reserved_at_40[0x8];
2275         u8         cqn[0x18];
2276
2277         u8         reserved_at_60[0x90];
2278
2279         u8         packet_pacing_rate_limit_index[0x10];
2280         u8         tis_lst_sz[0x10];
2281         u8         reserved_at_110[0x10];
2282
2283         u8         reserved_at_120[0x40];
2284
2285         u8         reserved_at_160[0x8];
2286         u8         tis_num_0[0x18];
2287
2288         struct mlx5_ifc_wq_bits wq;
2289 };
2290
2291 struct mlx5_ifc_rqtc_bits {
2292         u8         reserved_at_0[0xa0];
2293
2294         u8         reserved_at_a0[0x10];
2295         u8         rqt_max_size[0x10];
2296
2297         u8         reserved_at_c0[0x10];
2298         u8         rqt_actual_size[0x10];
2299
2300         u8         reserved_at_e0[0x6a0];
2301
2302         struct mlx5_ifc_rq_num_bits rq_num[0];
2303 };
2304
2305 enum {
2306         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2307         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2308 };
2309
2310 enum {
2311         MLX5_RQC_STATE_RST  = 0x0,
2312         MLX5_RQC_STATE_RDY  = 0x1,
2313         MLX5_RQC_STATE_ERR  = 0x3,
2314 };
2315
2316 struct mlx5_ifc_rqc_bits {
2317         u8         rlky[0x1];
2318         u8         reserved_at_1[0x1];
2319         u8         scatter_fcs[0x1];
2320         u8         vsd[0x1];
2321         u8         mem_rq_type[0x4];
2322         u8         state[0x4];
2323         u8         reserved_at_c[0x1];
2324         u8         flush_in_error_en[0x1];
2325         u8         reserved_at_e[0x12];
2326
2327         u8         reserved_at_20[0x8];
2328         u8         user_index[0x18];
2329
2330         u8         reserved_at_40[0x8];
2331         u8         cqn[0x18];
2332
2333         u8         counter_set_id[0x8];
2334         u8         reserved_at_68[0x18];
2335
2336         u8         reserved_at_80[0x8];
2337         u8         rmpn[0x18];
2338
2339         u8         reserved_at_a0[0xe0];
2340
2341         struct mlx5_ifc_wq_bits wq;
2342 };
2343
2344 enum {
2345         MLX5_RMPC_STATE_RDY  = 0x1,
2346         MLX5_RMPC_STATE_ERR  = 0x3,
2347 };
2348
2349 struct mlx5_ifc_rmpc_bits {
2350         u8         reserved_at_0[0x8];
2351         u8         state[0x4];
2352         u8         reserved_at_c[0x14];
2353
2354         u8         basic_cyclic_rcv_wqe[0x1];
2355         u8         reserved_at_21[0x1f];
2356
2357         u8         reserved_at_40[0x140];
2358
2359         struct mlx5_ifc_wq_bits wq;
2360 };
2361
2362 struct mlx5_ifc_nic_vport_context_bits {
2363         u8         reserved_at_0[0x1f];
2364         u8         roce_en[0x1];
2365
2366         u8         arm_change_event[0x1];
2367         u8         reserved_at_21[0x1a];
2368         u8         event_on_mtu[0x1];
2369         u8         event_on_promisc_change[0x1];
2370         u8         event_on_vlan_change[0x1];
2371         u8         event_on_mc_address_change[0x1];
2372         u8         event_on_uc_address_change[0x1];
2373
2374         u8         reserved_at_40[0xf0];
2375
2376         u8         mtu[0x10];
2377
2378         u8         system_image_guid[0x40];
2379         u8         port_guid[0x40];
2380         u8         node_guid[0x40];
2381
2382         u8         reserved_at_200[0x140];
2383         u8         qkey_violation_counter[0x10];
2384         u8         reserved_at_350[0x430];
2385
2386         u8         promisc_uc[0x1];
2387         u8         promisc_mc[0x1];
2388         u8         promisc_all[0x1];
2389         u8         reserved_at_783[0x2];
2390         u8         allowed_list_type[0x3];
2391         u8         reserved_at_788[0xc];
2392         u8         allowed_list_size[0xc];
2393
2394         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2395
2396         u8         reserved_at_7e0[0x20];
2397
2398         u8         current_uc_mac_address[0][0x40];
2399 };
2400
2401 enum {
2402         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2403         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2404         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2405 };
2406
2407 struct mlx5_ifc_mkc_bits {
2408         u8         reserved_at_0[0x1];
2409         u8         free[0x1];
2410         u8         reserved_at_2[0xd];
2411         u8         small_fence_on_rdma_read_response[0x1];
2412         u8         umr_en[0x1];
2413         u8         a[0x1];
2414         u8         rw[0x1];
2415         u8         rr[0x1];
2416         u8         lw[0x1];
2417         u8         lr[0x1];
2418         u8         access_mode[0x2];
2419         u8         reserved_at_18[0x8];
2420
2421         u8         qpn[0x18];
2422         u8         mkey_7_0[0x8];
2423
2424         u8         reserved_at_40[0x20];
2425
2426         u8         length64[0x1];
2427         u8         bsf_en[0x1];
2428         u8         sync_umr[0x1];
2429         u8         reserved_at_63[0x2];
2430         u8         expected_sigerr_count[0x1];
2431         u8         reserved_at_66[0x1];
2432         u8         en_rinval[0x1];
2433         u8         pd[0x18];
2434
2435         u8         start_addr[0x40];
2436
2437         u8         len[0x40];
2438
2439         u8         bsf_octword_size[0x20];
2440
2441         u8         reserved_at_120[0x80];
2442
2443         u8         translations_octword_size[0x20];
2444
2445         u8         reserved_at_1c0[0x1b];
2446         u8         log_page_size[0x5];
2447
2448         u8         reserved_at_1e0[0x20];
2449 };
2450
2451 struct mlx5_ifc_pkey_bits {
2452         u8         reserved_at_0[0x10];
2453         u8         pkey[0x10];
2454 };
2455
2456 struct mlx5_ifc_array128_auto_bits {
2457         u8         array128_auto[16][0x8];
2458 };
2459
2460 struct mlx5_ifc_hca_vport_context_bits {
2461         u8         field_select[0x20];
2462
2463         u8         reserved_at_20[0xe0];
2464
2465         u8         sm_virt_aware[0x1];
2466         u8         has_smi[0x1];
2467         u8         has_raw[0x1];
2468         u8         grh_required[0x1];
2469         u8         reserved_at_104[0xc];
2470         u8         port_physical_state[0x4];
2471         u8         vport_state_policy[0x4];
2472         u8         port_state[0x4];
2473         u8         vport_state[0x4];
2474
2475         u8         reserved_at_120[0x20];
2476
2477         u8         system_image_guid[0x40];
2478
2479         u8         port_guid[0x40];
2480
2481         u8         node_guid[0x40];
2482
2483         u8         cap_mask1[0x20];
2484
2485         u8         cap_mask1_field_select[0x20];
2486
2487         u8         cap_mask2[0x20];
2488
2489         u8         cap_mask2_field_select[0x20];
2490
2491         u8         reserved_at_280[0x80];
2492
2493         u8         lid[0x10];
2494         u8         reserved_at_310[0x4];
2495         u8         init_type_reply[0x4];
2496         u8         lmc[0x3];
2497         u8         subnet_timeout[0x5];
2498
2499         u8         sm_lid[0x10];
2500         u8         sm_sl[0x4];
2501         u8         reserved_at_334[0xc];
2502
2503         u8         qkey_violation_counter[0x10];
2504         u8         pkey_violation_counter[0x10];
2505
2506         u8         reserved_at_360[0xca0];
2507 };
2508
2509 struct mlx5_ifc_esw_vport_context_bits {
2510         u8         reserved_at_0[0x3];
2511         u8         vport_svlan_strip[0x1];
2512         u8         vport_cvlan_strip[0x1];
2513         u8         vport_svlan_insert[0x1];
2514         u8         vport_cvlan_insert[0x2];
2515         u8         reserved_at_8[0x18];
2516
2517         u8         reserved_at_20[0x20];
2518
2519         u8         svlan_cfi[0x1];
2520         u8         svlan_pcp[0x3];
2521         u8         svlan_id[0xc];
2522         u8         cvlan_cfi[0x1];
2523         u8         cvlan_pcp[0x3];
2524         u8         cvlan_id[0xc];
2525
2526         u8         reserved_at_60[0x7a0];
2527 };
2528
2529 enum {
2530         MLX5_EQC_STATUS_OK                = 0x0,
2531         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2532 };
2533
2534 enum {
2535         MLX5_EQC_ST_ARMED  = 0x9,
2536         MLX5_EQC_ST_FIRED  = 0xa,
2537 };
2538
2539 struct mlx5_ifc_eqc_bits {
2540         u8         status[0x4];
2541         u8         reserved_at_4[0x9];
2542         u8         ec[0x1];
2543         u8         oi[0x1];
2544         u8         reserved_at_f[0x5];
2545         u8         st[0x4];
2546         u8         reserved_at_18[0x8];
2547
2548         u8         reserved_at_20[0x20];
2549
2550         u8         reserved_at_40[0x14];
2551         u8         page_offset[0x6];
2552         u8         reserved_at_5a[0x6];
2553
2554         u8         reserved_at_60[0x3];
2555         u8         log_eq_size[0x5];
2556         u8         uar_page[0x18];
2557
2558         u8         reserved_at_80[0x20];
2559
2560         u8         reserved_at_a0[0x18];
2561         u8         intr[0x8];
2562
2563         u8         reserved_at_c0[0x3];
2564         u8         log_page_size[0x5];
2565         u8         reserved_at_c8[0x18];
2566
2567         u8         reserved_at_e0[0x60];
2568
2569         u8         reserved_at_140[0x8];
2570         u8         consumer_counter[0x18];
2571
2572         u8         reserved_at_160[0x8];
2573         u8         producer_counter[0x18];
2574
2575         u8         reserved_at_180[0x80];
2576 };
2577
2578 enum {
2579         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2580         MLX5_DCTC_STATE_DRAINING  = 0x1,
2581         MLX5_DCTC_STATE_DRAINED   = 0x2,
2582 };
2583
2584 enum {
2585         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2586         MLX5_DCTC_CS_RES_NA         = 0x1,
2587         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2588 };
2589
2590 enum {
2591         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2592         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2593         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2594         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2595         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2596 };
2597
2598 struct mlx5_ifc_dctc_bits {
2599         u8         reserved_at_0[0x4];
2600         u8         state[0x4];
2601         u8         reserved_at_8[0x18];
2602
2603         u8         reserved_at_20[0x8];
2604         u8         user_index[0x18];
2605
2606         u8         reserved_at_40[0x8];
2607         u8         cqn[0x18];
2608
2609         u8         counter_set_id[0x8];
2610         u8         atomic_mode[0x4];
2611         u8         rre[0x1];
2612         u8         rwe[0x1];
2613         u8         rae[0x1];
2614         u8         atomic_like_write_en[0x1];
2615         u8         latency_sensitive[0x1];
2616         u8         rlky[0x1];
2617         u8         free_ar[0x1];
2618         u8         reserved_at_73[0xd];
2619
2620         u8         reserved_at_80[0x8];
2621         u8         cs_res[0x8];
2622         u8         reserved_at_90[0x3];
2623         u8         min_rnr_nak[0x5];
2624         u8         reserved_at_98[0x8];
2625
2626         u8         reserved_at_a0[0x8];
2627         u8         srqn_xrqn[0x18];
2628
2629         u8         reserved_at_c0[0x8];
2630         u8         pd[0x18];
2631
2632         u8         tclass[0x8];
2633         u8         reserved_at_e8[0x4];
2634         u8         flow_label[0x14];
2635
2636         u8         dc_access_key[0x40];
2637
2638         u8         reserved_at_140[0x5];
2639         u8         mtu[0x3];
2640         u8         port[0x8];
2641         u8         pkey_index[0x10];
2642
2643         u8         reserved_at_160[0x8];
2644         u8         my_addr_index[0x8];
2645         u8         reserved_at_170[0x8];
2646         u8         hop_limit[0x8];
2647
2648         u8         dc_access_key_violation_count[0x20];
2649
2650         u8         reserved_at_1a0[0x14];
2651         u8         dei_cfi[0x1];
2652         u8         eth_prio[0x3];
2653         u8         ecn[0x2];
2654         u8         dscp[0x6];
2655
2656         u8         reserved_at_1c0[0x40];
2657 };
2658
2659 enum {
2660         MLX5_CQC_STATUS_OK             = 0x0,
2661         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2662         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2663 };
2664
2665 enum {
2666         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2667         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2668 };
2669
2670 enum {
2671         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2672         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2673         MLX5_CQC_ST_FIRED                                 = 0xa,
2674 };
2675
2676 enum {
2677         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2678         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2679         MLX5_CQ_PERIOD_NUM_MODES
2680 };
2681
2682 struct mlx5_ifc_cqc_bits {
2683         u8         status[0x4];
2684         u8         reserved_at_4[0x4];
2685         u8         cqe_sz[0x3];
2686         u8         cc[0x1];
2687         u8         reserved_at_c[0x1];
2688         u8         scqe_break_moderation_en[0x1];
2689         u8         oi[0x1];
2690         u8         cq_period_mode[0x2];
2691         u8         cqe_comp_en[0x1];
2692         u8         mini_cqe_res_format[0x2];
2693         u8         st[0x4];
2694         u8         reserved_at_18[0x8];
2695
2696         u8         reserved_at_20[0x20];
2697
2698         u8         reserved_at_40[0x14];
2699         u8         page_offset[0x6];
2700         u8         reserved_at_5a[0x6];
2701
2702         u8         reserved_at_60[0x3];
2703         u8         log_cq_size[0x5];
2704         u8         uar_page[0x18];
2705
2706         u8         reserved_at_80[0x4];
2707         u8         cq_period[0xc];
2708         u8         cq_max_count[0x10];
2709
2710         u8         reserved_at_a0[0x18];
2711         u8         c_eqn[0x8];
2712
2713         u8         reserved_at_c0[0x3];
2714         u8         log_page_size[0x5];
2715         u8         reserved_at_c8[0x18];
2716
2717         u8         reserved_at_e0[0x20];
2718
2719         u8         reserved_at_100[0x8];
2720         u8         last_notified_index[0x18];
2721
2722         u8         reserved_at_120[0x8];
2723         u8         last_solicit_index[0x18];
2724
2725         u8         reserved_at_140[0x8];
2726         u8         consumer_counter[0x18];
2727
2728         u8         reserved_at_160[0x8];
2729         u8         producer_counter[0x18];
2730
2731         u8         reserved_at_180[0x40];
2732
2733         u8         dbr_addr[0x40];
2734 };
2735
2736 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2737         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2738         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2739         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2740         u8         reserved_at_0[0x800];
2741 };
2742
2743 struct mlx5_ifc_query_adapter_param_block_bits {
2744         u8         reserved_at_0[0xc0];
2745
2746         u8         reserved_at_c0[0x8];
2747         u8         ieee_vendor_id[0x18];
2748
2749         u8         reserved_at_e0[0x10];
2750         u8         vsd_vendor_id[0x10];
2751
2752         u8         vsd[208][0x8];
2753
2754         u8         vsd_contd_psid[16][0x8];
2755 };
2756
2757 enum {
2758         MLX5_XRQC_STATE_GOOD   = 0x0,
2759         MLX5_XRQC_STATE_ERROR  = 0x1,
2760 };
2761
2762 enum {
2763         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2764         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2765 };
2766
2767 enum {
2768         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2769 };
2770
2771 struct mlx5_ifc_tag_matching_topology_context_bits {
2772         u8         log_matching_list_sz[0x4];
2773         u8         reserved_at_4[0xc];
2774         u8         append_next_index[0x10];
2775
2776         u8         sw_phase_cnt[0x10];
2777         u8         hw_phase_cnt[0x10];
2778
2779         u8         reserved_at_40[0x40];
2780 };
2781
2782 struct mlx5_ifc_xrqc_bits {
2783         u8         state[0x4];
2784         u8         rlkey[0x1];
2785         u8         reserved_at_5[0xf];
2786         u8         topology[0x4];
2787         u8         reserved_at_18[0x4];
2788         u8         offload[0x4];
2789
2790         u8         reserved_at_20[0x8];
2791         u8         user_index[0x18];
2792
2793         u8         reserved_at_40[0x8];
2794         u8         cqn[0x18];
2795
2796         u8         reserved_at_60[0xa0];
2797
2798         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2799
2800         u8         reserved_at_180[0x180];
2801
2802         struct mlx5_ifc_wq_bits wq;
2803 };
2804
2805 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2806         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2807         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2808         u8         reserved_at_0[0x20];
2809 };
2810
2811 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2812         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2813         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2814         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2815         u8         reserved_at_0[0x20];
2816 };
2817
2818 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2819         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2820         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2821         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2822         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2823         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2824         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2825         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2826         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2827         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2828         u8         reserved_at_0[0x7c0];
2829 };
2830
2831 union mlx5_ifc_event_auto_bits {
2832         struct mlx5_ifc_comp_event_bits comp_event;
2833         struct mlx5_ifc_dct_events_bits dct_events;
2834         struct mlx5_ifc_qp_events_bits qp_events;
2835         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2836         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2837         struct mlx5_ifc_cq_error_bits cq_error;
2838         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2839         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2840         struct mlx5_ifc_gpio_event_bits gpio_event;
2841         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2842         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2843         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2844         u8         reserved_at_0[0xe0];
2845 };
2846
2847 struct mlx5_ifc_health_buffer_bits {
2848         u8         reserved_at_0[0x100];
2849
2850         u8         assert_existptr[0x20];
2851
2852         u8         assert_callra[0x20];
2853
2854         u8         reserved_at_140[0x40];
2855
2856         u8         fw_version[0x20];
2857
2858         u8         hw_id[0x20];
2859
2860         u8         reserved_at_1c0[0x20];
2861
2862         u8         irisc_index[0x8];
2863         u8         synd[0x8];
2864         u8         ext_synd[0x10];
2865 };
2866
2867 struct mlx5_ifc_register_loopback_control_bits {
2868         u8         no_lb[0x1];
2869         u8         reserved_at_1[0x7];
2870         u8         port[0x8];
2871         u8         reserved_at_10[0x10];
2872
2873         u8         reserved_at_20[0x60];
2874 };
2875
2876 struct mlx5_ifc_teardown_hca_out_bits {
2877         u8         status[0x8];
2878         u8         reserved_at_8[0x18];
2879
2880         u8         syndrome[0x20];
2881
2882         u8         reserved_at_40[0x40];
2883 };
2884
2885 enum {
2886         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2887         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2888 };
2889
2890 struct mlx5_ifc_teardown_hca_in_bits {
2891         u8         opcode[0x10];
2892         u8         reserved_at_10[0x10];
2893
2894         u8         reserved_at_20[0x10];
2895         u8         op_mod[0x10];
2896
2897         u8         reserved_at_40[0x10];
2898         u8         profile[0x10];
2899
2900         u8         reserved_at_60[0x20];
2901 };
2902
2903 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2904         u8         status[0x8];
2905         u8         reserved_at_8[0x18];
2906
2907         u8         syndrome[0x20];
2908
2909         u8         reserved_at_40[0x40];
2910 };
2911
2912 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2913         u8         opcode[0x10];
2914         u8         reserved_at_10[0x10];
2915
2916         u8         reserved_at_20[0x10];
2917         u8         op_mod[0x10];
2918
2919         u8         reserved_at_40[0x8];
2920         u8         qpn[0x18];
2921
2922         u8         reserved_at_60[0x20];
2923
2924         u8         opt_param_mask[0x20];
2925
2926         u8         reserved_at_a0[0x20];
2927
2928         struct mlx5_ifc_qpc_bits qpc;
2929
2930         u8         reserved_at_800[0x80];
2931 };
2932
2933 struct mlx5_ifc_sqd2rts_qp_out_bits {
2934         u8         status[0x8];
2935         u8         reserved_at_8[0x18];
2936
2937         u8         syndrome[0x20];
2938
2939         u8         reserved_at_40[0x40];
2940 };
2941
2942 struct mlx5_ifc_sqd2rts_qp_in_bits {
2943         u8         opcode[0x10];
2944         u8         reserved_at_10[0x10];
2945
2946         u8         reserved_at_20[0x10];
2947         u8         op_mod[0x10];
2948
2949         u8         reserved_at_40[0x8];
2950         u8         qpn[0x18];
2951
2952         u8         reserved_at_60[0x20];
2953
2954         u8         opt_param_mask[0x20];
2955
2956         u8         reserved_at_a0[0x20];
2957
2958         struct mlx5_ifc_qpc_bits qpc;
2959
2960         u8         reserved_at_800[0x80];
2961 };
2962
2963 struct mlx5_ifc_set_roce_address_out_bits {
2964         u8         status[0x8];
2965         u8         reserved_at_8[0x18];
2966
2967         u8         syndrome[0x20];
2968
2969         u8         reserved_at_40[0x40];
2970 };
2971
2972 struct mlx5_ifc_set_roce_address_in_bits {
2973         u8         opcode[0x10];
2974         u8         reserved_at_10[0x10];
2975
2976         u8         reserved_at_20[0x10];
2977         u8         op_mod[0x10];
2978
2979         u8         roce_address_index[0x10];
2980         u8         reserved_at_50[0x10];
2981
2982         u8         reserved_at_60[0x20];
2983
2984         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2985 };
2986
2987 struct mlx5_ifc_set_mad_demux_out_bits {
2988         u8         status[0x8];
2989         u8         reserved_at_8[0x18];
2990
2991         u8         syndrome[0x20];
2992
2993         u8         reserved_at_40[0x40];
2994 };
2995
2996 enum {
2997         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2998         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2999 };
3000
3001 struct mlx5_ifc_set_mad_demux_in_bits {
3002         u8         opcode[0x10];
3003         u8         reserved_at_10[0x10];
3004
3005         u8         reserved_at_20[0x10];
3006         u8         op_mod[0x10];
3007
3008         u8         reserved_at_40[0x20];
3009
3010         u8         reserved_at_60[0x6];
3011         u8         demux_mode[0x2];
3012         u8         reserved_at_68[0x18];
3013 };
3014
3015 struct mlx5_ifc_set_l2_table_entry_out_bits {
3016         u8         status[0x8];
3017         u8         reserved_at_8[0x18];
3018
3019         u8         syndrome[0x20];
3020
3021         u8         reserved_at_40[0x40];
3022 };
3023
3024 struct mlx5_ifc_set_l2_table_entry_in_bits {
3025         u8         opcode[0x10];
3026         u8         reserved_at_10[0x10];
3027
3028         u8         reserved_at_20[0x10];
3029         u8         op_mod[0x10];
3030
3031         u8         reserved_at_40[0x60];
3032
3033         u8         reserved_at_a0[0x8];
3034         u8         table_index[0x18];
3035
3036         u8         reserved_at_c0[0x20];
3037
3038         u8         reserved_at_e0[0x13];
3039         u8         vlan_valid[0x1];
3040         u8         vlan[0xc];
3041
3042         struct mlx5_ifc_mac_address_layout_bits mac_address;
3043
3044         u8         reserved_at_140[0xc0];
3045 };
3046
3047 struct mlx5_ifc_set_issi_out_bits {
3048         u8         status[0x8];
3049         u8         reserved_at_8[0x18];
3050
3051         u8         syndrome[0x20];
3052
3053         u8         reserved_at_40[0x40];
3054 };
3055
3056 struct mlx5_ifc_set_issi_in_bits {
3057         u8         opcode[0x10];
3058         u8         reserved_at_10[0x10];
3059
3060         u8         reserved_at_20[0x10];
3061         u8         op_mod[0x10];
3062
3063         u8         reserved_at_40[0x10];
3064         u8         current_issi[0x10];
3065
3066         u8         reserved_at_60[0x20];
3067 };
3068
3069 struct mlx5_ifc_set_hca_cap_out_bits {
3070         u8         status[0x8];
3071         u8         reserved_at_8[0x18];
3072
3073         u8         syndrome[0x20];
3074
3075         u8         reserved_at_40[0x40];
3076 };
3077
3078 struct mlx5_ifc_set_hca_cap_in_bits {
3079         u8         opcode[0x10];
3080         u8         reserved_at_10[0x10];
3081
3082         u8         reserved_at_20[0x10];
3083         u8         op_mod[0x10];
3084
3085         u8         reserved_at_40[0x40];
3086
3087         union mlx5_ifc_hca_cap_union_bits capability;
3088 };
3089
3090 enum {
3091         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3092         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3093         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3094         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3095 };
3096
3097 struct mlx5_ifc_set_fte_out_bits {
3098         u8         status[0x8];
3099         u8         reserved_at_8[0x18];
3100
3101         u8         syndrome[0x20];
3102
3103         u8         reserved_at_40[0x40];
3104 };
3105
3106 struct mlx5_ifc_set_fte_in_bits {
3107         u8         opcode[0x10];
3108         u8         reserved_at_10[0x10];
3109
3110         u8         reserved_at_20[0x10];
3111         u8         op_mod[0x10];
3112
3113         u8         other_vport[0x1];
3114         u8         reserved_at_41[0xf];
3115         u8         vport_number[0x10];
3116
3117         u8         reserved_at_60[0x20];
3118
3119         u8         table_type[0x8];
3120         u8         reserved_at_88[0x18];
3121
3122         u8         reserved_at_a0[0x8];
3123         u8         table_id[0x18];
3124
3125         u8         reserved_at_c0[0x18];
3126         u8         modify_enable_mask[0x8];
3127
3128         u8         reserved_at_e0[0x20];
3129
3130         u8         flow_index[0x20];
3131
3132         u8         reserved_at_120[0xe0];
3133
3134         struct mlx5_ifc_flow_context_bits flow_context;
3135 };
3136
3137 struct mlx5_ifc_rts2rts_qp_out_bits {
3138         u8         status[0x8];
3139         u8         reserved_at_8[0x18];
3140
3141         u8         syndrome[0x20];
3142
3143         u8         reserved_at_40[0x40];
3144 };
3145
3146 struct mlx5_ifc_rts2rts_qp_in_bits {
3147         u8         opcode[0x10];
3148         u8         reserved_at_10[0x10];
3149
3150         u8         reserved_at_20[0x10];
3151         u8         op_mod[0x10];
3152
3153         u8         reserved_at_40[0x8];
3154         u8         qpn[0x18];
3155
3156         u8         reserved_at_60[0x20];
3157
3158         u8         opt_param_mask[0x20];
3159
3160         u8         reserved_at_a0[0x20];
3161
3162         struct mlx5_ifc_qpc_bits qpc;
3163
3164         u8         reserved_at_800[0x80];
3165 };
3166
3167 struct mlx5_ifc_rtr2rts_qp_out_bits {
3168         u8         status[0x8];
3169         u8         reserved_at_8[0x18];
3170
3171         u8         syndrome[0x20];
3172
3173         u8         reserved_at_40[0x40];
3174 };
3175
3176 struct mlx5_ifc_rtr2rts_qp_in_bits {
3177         u8         opcode[0x10];
3178         u8         reserved_at_10[0x10];
3179
3180         u8         reserved_at_20[0x10];
3181         u8         op_mod[0x10];
3182
3183         u8         reserved_at_40[0x8];
3184         u8         qpn[0x18];
3185
3186         u8         reserved_at_60[0x20];
3187
3188         u8         opt_param_mask[0x20];
3189
3190         u8         reserved_at_a0[0x20];
3191
3192         struct mlx5_ifc_qpc_bits qpc;
3193
3194         u8         reserved_at_800[0x80];
3195 };
3196
3197 struct mlx5_ifc_rst2init_qp_out_bits {
3198         u8         status[0x8];
3199         u8         reserved_at_8[0x18];
3200
3201         u8         syndrome[0x20];
3202
3203         u8         reserved_at_40[0x40];
3204 };
3205
3206 struct mlx5_ifc_rst2init_qp_in_bits {
3207         u8         opcode[0x10];
3208         u8         reserved_at_10[0x10];
3209
3210         u8         reserved_at_20[0x10];
3211         u8         op_mod[0x10];
3212
3213         u8         reserved_at_40[0x8];
3214         u8         qpn[0x18];
3215
3216         u8         reserved_at_60[0x20];
3217
3218         u8         opt_param_mask[0x20];
3219
3220         u8         reserved_at_a0[0x20];
3221
3222         struct mlx5_ifc_qpc_bits qpc;
3223
3224         u8         reserved_at_800[0x80];
3225 };
3226
3227 struct mlx5_ifc_query_xrq_out_bits {
3228         u8         status[0x8];
3229         u8         reserved_at_8[0x18];
3230
3231         u8         syndrome[0x20];
3232
3233         u8         reserved_at_40[0x40];
3234
3235         struct mlx5_ifc_xrqc_bits xrq_context;
3236 };
3237
3238 struct mlx5_ifc_query_xrq_in_bits {
3239         u8         opcode[0x10];
3240         u8         reserved_at_10[0x10];
3241
3242         u8         reserved_at_20[0x10];
3243         u8         op_mod[0x10];
3244
3245         u8         reserved_at_40[0x8];
3246         u8         xrqn[0x18];
3247
3248         u8         reserved_at_60[0x20];
3249 };
3250
3251 struct mlx5_ifc_query_xrc_srq_out_bits {
3252         u8         status[0x8];
3253         u8         reserved_at_8[0x18];
3254
3255         u8         syndrome[0x20];
3256
3257         u8         reserved_at_40[0x40];
3258
3259         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3260
3261         u8         reserved_at_280[0x600];
3262
3263         u8         pas[0][0x40];
3264 };
3265
3266 struct mlx5_ifc_query_xrc_srq_in_bits {
3267         u8         opcode[0x10];
3268         u8         reserved_at_10[0x10];
3269
3270         u8         reserved_at_20[0x10];
3271         u8         op_mod[0x10];
3272
3273         u8         reserved_at_40[0x8];
3274         u8         xrc_srqn[0x18];
3275
3276         u8         reserved_at_60[0x20];
3277 };
3278
3279 enum {
3280         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3281         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3282 };
3283
3284 struct mlx5_ifc_query_vport_state_out_bits {
3285         u8         status[0x8];
3286         u8         reserved_at_8[0x18];
3287
3288         u8         syndrome[0x20];
3289
3290         u8         reserved_at_40[0x20];
3291
3292         u8         reserved_at_60[0x18];
3293         u8         admin_state[0x4];
3294         u8         state[0x4];
3295 };
3296
3297 enum {
3298         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3299         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3300 };
3301
3302 struct mlx5_ifc_query_vport_state_in_bits {
3303         u8         opcode[0x10];
3304         u8         reserved_at_10[0x10];
3305
3306         u8         reserved_at_20[0x10];
3307         u8         op_mod[0x10];
3308
3309         u8         other_vport[0x1];
3310         u8         reserved_at_41[0xf];
3311         u8         vport_number[0x10];
3312
3313         u8         reserved_at_60[0x20];
3314 };
3315
3316 struct mlx5_ifc_query_vport_counter_out_bits {
3317         u8         status[0x8];
3318         u8         reserved_at_8[0x18];
3319
3320         u8         syndrome[0x20];
3321
3322         u8         reserved_at_40[0x40];
3323
3324         struct mlx5_ifc_traffic_counter_bits received_errors;
3325
3326         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3327
3328         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3329
3330         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3331
3332         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3333
3334         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3335
3336         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3337
3338         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3339
3340         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3341
3342         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3343
3344         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3345
3346         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3347
3348         u8         reserved_at_680[0xa00];
3349 };
3350
3351 enum {
3352         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3353 };
3354
3355 struct mlx5_ifc_query_vport_counter_in_bits {
3356         u8         opcode[0x10];
3357         u8         reserved_at_10[0x10];
3358
3359         u8         reserved_at_20[0x10];
3360         u8         op_mod[0x10];
3361
3362         u8         other_vport[0x1];
3363         u8         reserved_at_41[0xb];
3364         u8         port_num[0x4];
3365         u8         vport_number[0x10];
3366
3367         u8         reserved_at_60[0x60];
3368
3369         u8         clear[0x1];
3370         u8         reserved_at_c1[0x1f];
3371
3372         u8         reserved_at_e0[0x20];
3373 };
3374
3375 struct mlx5_ifc_query_tis_out_bits {
3376         u8         status[0x8];
3377         u8         reserved_at_8[0x18];
3378
3379         u8         syndrome[0x20];
3380
3381         u8         reserved_at_40[0x40];
3382
3383         struct mlx5_ifc_tisc_bits tis_context;
3384 };
3385
3386 struct mlx5_ifc_query_tis_in_bits {
3387         u8         opcode[0x10];
3388         u8         reserved_at_10[0x10];
3389
3390         u8         reserved_at_20[0x10];
3391         u8         op_mod[0x10];
3392
3393         u8         reserved_at_40[0x8];
3394         u8         tisn[0x18];
3395
3396         u8         reserved_at_60[0x20];
3397 };
3398
3399 struct mlx5_ifc_query_tir_out_bits {
3400         u8         status[0x8];
3401         u8         reserved_at_8[0x18];
3402
3403         u8         syndrome[0x20];
3404
3405         u8         reserved_at_40[0xc0];
3406
3407         struct mlx5_ifc_tirc_bits tir_context;
3408 };
3409
3410 struct mlx5_ifc_query_tir_in_bits {
3411         u8         opcode[0x10];
3412         u8         reserved_at_10[0x10];
3413
3414         u8         reserved_at_20[0x10];
3415         u8         op_mod[0x10];
3416
3417         u8         reserved_at_40[0x8];
3418         u8         tirn[0x18];
3419
3420         u8         reserved_at_60[0x20];
3421 };
3422
3423 struct mlx5_ifc_query_srq_out_bits {
3424         u8         status[0x8];
3425         u8         reserved_at_8[0x18];
3426
3427         u8         syndrome[0x20];
3428
3429         u8         reserved_at_40[0x40];
3430
3431         struct mlx5_ifc_srqc_bits srq_context_entry;
3432
3433         u8         reserved_at_280[0x600];
3434
3435         u8         pas[0][0x40];
3436 };
3437
3438 struct mlx5_ifc_query_srq_in_bits {
3439         u8         opcode[0x10];
3440         u8         reserved_at_10[0x10];
3441
3442         u8         reserved_at_20[0x10];
3443         u8         op_mod[0x10];
3444
3445         u8         reserved_at_40[0x8];
3446         u8         srqn[0x18];
3447
3448         u8         reserved_at_60[0x20];
3449 };
3450
3451 struct mlx5_ifc_query_sq_out_bits {
3452         u8         status[0x8];
3453         u8         reserved_at_8[0x18];
3454
3455         u8         syndrome[0x20];
3456
3457         u8         reserved_at_40[0xc0];
3458
3459         struct mlx5_ifc_sqc_bits sq_context;
3460 };
3461
3462 struct mlx5_ifc_query_sq_in_bits {
3463         u8         opcode[0x10];
3464         u8         reserved_at_10[0x10];
3465
3466         u8         reserved_at_20[0x10];
3467         u8         op_mod[0x10];
3468
3469         u8         reserved_at_40[0x8];
3470         u8         sqn[0x18];
3471
3472         u8         reserved_at_60[0x20];
3473 };
3474
3475 struct mlx5_ifc_query_special_contexts_out_bits {
3476         u8         status[0x8];
3477         u8         reserved_at_8[0x18];
3478
3479         u8         syndrome[0x20];
3480
3481         u8         reserved_at_40[0x20];
3482
3483         u8         resd_lkey[0x20];
3484 };
3485
3486 struct mlx5_ifc_query_special_contexts_in_bits {
3487         u8         opcode[0x10];
3488         u8         reserved_at_10[0x10];
3489
3490         u8         reserved_at_20[0x10];
3491         u8         op_mod[0x10];
3492
3493         u8         reserved_at_40[0x40];
3494 };
3495
3496 struct mlx5_ifc_query_rqt_out_bits {
3497         u8         status[0x8];
3498         u8         reserved_at_8[0x18];
3499
3500         u8         syndrome[0x20];
3501
3502         u8         reserved_at_40[0xc0];
3503
3504         struct mlx5_ifc_rqtc_bits rqt_context;
3505 };
3506
3507 struct mlx5_ifc_query_rqt_in_bits {
3508         u8         opcode[0x10];
3509         u8         reserved_at_10[0x10];
3510
3511         u8         reserved_at_20[0x10];
3512         u8         op_mod[0x10];
3513
3514         u8         reserved_at_40[0x8];
3515         u8         rqtn[0x18];
3516
3517         u8         reserved_at_60[0x20];
3518 };
3519
3520 struct mlx5_ifc_query_rq_out_bits {
3521         u8         status[0x8];
3522         u8         reserved_at_8[0x18];
3523
3524         u8         syndrome[0x20];
3525
3526         u8         reserved_at_40[0xc0];
3527
3528         struct mlx5_ifc_rqc_bits rq_context;
3529 };
3530
3531 struct mlx5_ifc_query_rq_in_bits {
3532         u8         opcode[0x10];
3533         u8         reserved_at_10[0x10];
3534
3535         u8         reserved_at_20[0x10];
3536         u8         op_mod[0x10];
3537
3538         u8         reserved_at_40[0x8];
3539         u8         rqn[0x18];
3540
3541         u8         reserved_at_60[0x20];
3542 };
3543
3544 struct mlx5_ifc_query_roce_address_out_bits {
3545         u8         status[0x8];
3546         u8         reserved_at_8[0x18];
3547
3548         u8         syndrome[0x20];
3549
3550         u8         reserved_at_40[0x40];
3551
3552         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3553 };
3554
3555 struct mlx5_ifc_query_roce_address_in_bits {
3556         u8         opcode[0x10];
3557         u8         reserved_at_10[0x10];
3558
3559         u8         reserved_at_20[0x10];
3560         u8         op_mod[0x10];
3561
3562         u8         roce_address_index[0x10];
3563         u8         reserved_at_50[0x10];
3564
3565         u8         reserved_at_60[0x20];
3566 };
3567
3568 struct mlx5_ifc_query_rmp_out_bits {
3569         u8         status[0x8];
3570         u8         reserved_at_8[0x18];
3571
3572         u8         syndrome[0x20];
3573
3574         u8         reserved_at_40[0xc0];
3575
3576         struct mlx5_ifc_rmpc_bits rmp_context;
3577 };
3578
3579 struct mlx5_ifc_query_rmp_in_bits {
3580         u8         opcode[0x10];
3581         u8         reserved_at_10[0x10];
3582
3583         u8         reserved_at_20[0x10];
3584         u8         op_mod[0x10];
3585
3586         u8         reserved_at_40[0x8];
3587         u8         rmpn[0x18];
3588
3589         u8         reserved_at_60[0x20];
3590 };
3591
3592 struct mlx5_ifc_query_qp_out_bits {
3593         u8         status[0x8];
3594         u8         reserved_at_8[0x18];
3595
3596         u8         syndrome[0x20];
3597
3598         u8         reserved_at_40[0x40];
3599
3600         u8         opt_param_mask[0x20];
3601
3602         u8         reserved_at_a0[0x20];
3603
3604         struct mlx5_ifc_qpc_bits qpc;
3605
3606         u8         reserved_at_800[0x80];
3607
3608         u8         pas[0][0x40];
3609 };
3610
3611 struct mlx5_ifc_query_qp_in_bits {
3612         u8         opcode[0x10];
3613         u8         reserved_at_10[0x10];
3614
3615         u8         reserved_at_20[0x10];
3616         u8         op_mod[0x10];
3617
3618         u8         reserved_at_40[0x8];
3619         u8         qpn[0x18];
3620
3621         u8         reserved_at_60[0x20];
3622 };
3623
3624 struct mlx5_ifc_query_q_counter_out_bits {
3625         u8         status[0x8];
3626         u8         reserved_at_8[0x18];
3627
3628         u8         syndrome[0x20];
3629
3630         u8         reserved_at_40[0x40];
3631
3632         u8         rx_write_requests[0x20];
3633
3634         u8         reserved_at_a0[0x20];
3635
3636         u8         rx_read_requests[0x20];
3637
3638         u8         reserved_at_e0[0x20];
3639
3640         u8         rx_atomic_requests[0x20];
3641
3642         u8         reserved_at_120[0x20];
3643
3644         u8         rx_dct_connect[0x20];
3645
3646         u8         reserved_at_160[0x20];
3647
3648         u8         out_of_buffer[0x20];
3649
3650         u8         reserved_at_1a0[0x20];
3651
3652         u8         out_of_sequence[0x20];
3653
3654         u8         reserved_at_1e0[0x20];
3655
3656         u8         duplicate_request[0x20];
3657
3658         u8         reserved_at_220[0x20];
3659
3660         u8         rnr_nak_retry_err[0x20];
3661
3662         u8         reserved_at_260[0x20];
3663
3664         u8         packet_seq_err[0x20];
3665
3666         u8         reserved_at_2a0[0x20];
3667
3668         u8         implied_nak_seq_err[0x20];
3669
3670         u8         reserved_at_2e0[0x20];
3671
3672         u8         local_ack_timeout_err[0x20];
3673
3674         u8         reserved_at_320[0x4e0];
3675 };
3676
3677 struct mlx5_ifc_query_q_counter_in_bits {
3678         u8         opcode[0x10];
3679         u8         reserved_at_10[0x10];
3680
3681         u8         reserved_at_20[0x10];
3682         u8         op_mod[0x10];
3683
3684         u8         reserved_at_40[0x80];
3685
3686         u8         clear[0x1];
3687         u8         reserved_at_c1[0x1f];
3688
3689         u8         reserved_at_e0[0x18];
3690         u8         counter_set_id[0x8];
3691 };
3692
3693 struct mlx5_ifc_query_pages_out_bits {
3694         u8         status[0x8];
3695         u8         reserved_at_8[0x18];
3696
3697         u8         syndrome[0x20];
3698
3699         u8         reserved_at_40[0x10];
3700         u8         function_id[0x10];
3701
3702         u8         num_pages[0x20];
3703 };
3704
3705 enum {
3706         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3707         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3708         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3709 };
3710
3711 struct mlx5_ifc_query_pages_in_bits {
3712         u8         opcode[0x10];
3713         u8         reserved_at_10[0x10];
3714
3715         u8         reserved_at_20[0x10];
3716         u8         op_mod[0x10];
3717
3718         u8         reserved_at_40[0x10];
3719         u8         function_id[0x10];
3720
3721         u8         reserved_at_60[0x20];
3722 };
3723
3724 struct mlx5_ifc_query_nic_vport_context_out_bits {
3725         u8         status[0x8];
3726         u8         reserved_at_8[0x18];
3727
3728         u8         syndrome[0x20];
3729
3730         u8         reserved_at_40[0x40];
3731
3732         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3733 };
3734
3735 struct mlx5_ifc_query_nic_vport_context_in_bits {
3736         u8         opcode[0x10];
3737         u8         reserved_at_10[0x10];
3738
3739         u8         reserved_at_20[0x10];
3740         u8         op_mod[0x10];
3741
3742         u8         other_vport[0x1];
3743         u8         reserved_at_41[0xf];
3744         u8         vport_number[0x10];
3745
3746         u8         reserved_at_60[0x5];
3747         u8         allowed_list_type[0x3];
3748         u8         reserved_at_68[0x18];
3749 };
3750
3751 struct mlx5_ifc_query_mkey_out_bits {
3752         u8         status[0x8];
3753         u8         reserved_at_8[0x18];
3754
3755         u8         syndrome[0x20];
3756
3757         u8         reserved_at_40[0x40];
3758
3759         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3760
3761         u8         reserved_at_280[0x600];
3762
3763         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3764
3765         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3766 };
3767
3768 struct mlx5_ifc_query_mkey_in_bits {
3769         u8         opcode[0x10];
3770         u8         reserved_at_10[0x10];
3771
3772         u8         reserved_at_20[0x10];
3773         u8         op_mod[0x10];
3774
3775         u8         reserved_at_40[0x8];
3776         u8         mkey_index[0x18];
3777
3778         u8         pg_access[0x1];
3779         u8         reserved_at_61[0x1f];
3780 };
3781
3782 struct mlx5_ifc_query_mad_demux_out_bits {
3783         u8         status[0x8];
3784         u8         reserved_at_8[0x18];
3785
3786         u8         syndrome[0x20];
3787
3788         u8         reserved_at_40[0x40];
3789
3790         u8         mad_dumux_parameters_block[0x20];
3791 };
3792
3793 struct mlx5_ifc_query_mad_demux_in_bits {
3794         u8         opcode[0x10];
3795         u8         reserved_at_10[0x10];
3796
3797         u8         reserved_at_20[0x10];
3798         u8         op_mod[0x10];
3799
3800         u8         reserved_at_40[0x40];
3801 };
3802
3803 struct mlx5_ifc_query_l2_table_entry_out_bits {
3804         u8         status[0x8];
3805         u8         reserved_at_8[0x18];
3806
3807         u8         syndrome[0x20];
3808
3809         u8         reserved_at_40[0xa0];
3810
3811         u8         reserved_at_e0[0x13];
3812         u8         vlan_valid[0x1];
3813         u8         vlan[0xc];
3814
3815         struct mlx5_ifc_mac_address_layout_bits mac_address;
3816
3817         u8         reserved_at_140[0xc0];
3818 };
3819
3820 struct mlx5_ifc_query_l2_table_entry_in_bits {
3821         u8         opcode[0x10];
3822         u8         reserved_at_10[0x10];
3823
3824         u8         reserved_at_20[0x10];
3825         u8         op_mod[0x10];
3826
3827         u8         reserved_at_40[0x60];
3828
3829         u8         reserved_at_a0[0x8];
3830         u8         table_index[0x18];
3831
3832         u8         reserved_at_c0[0x140];
3833 };
3834
3835 struct mlx5_ifc_query_issi_out_bits {
3836         u8         status[0x8];
3837         u8         reserved_at_8[0x18];
3838
3839         u8         syndrome[0x20];
3840
3841         u8         reserved_at_40[0x10];
3842         u8         current_issi[0x10];
3843
3844         u8         reserved_at_60[0xa0];
3845
3846         u8         reserved_at_100[76][0x8];
3847         u8         supported_issi_dw0[0x20];
3848 };
3849
3850 struct mlx5_ifc_query_issi_in_bits {
3851         u8         opcode[0x10];
3852         u8         reserved_at_10[0x10];
3853
3854         u8         reserved_at_20[0x10];
3855         u8         op_mod[0x10];
3856
3857         u8         reserved_at_40[0x40];
3858 };
3859
3860 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3861         u8         status[0x8];
3862         u8         reserved_at_8[0x18];
3863
3864         u8         syndrome[0x20];
3865
3866         u8         reserved_at_40[0x40];
3867
3868         struct mlx5_ifc_pkey_bits pkey[0];
3869 };
3870
3871 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3872         u8         opcode[0x10];
3873         u8         reserved_at_10[0x10];
3874
3875         u8         reserved_at_20[0x10];
3876         u8         op_mod[0x10];
3877
3878         u8         other_vport[0x1];
3879         u8         reserved_at_41[0xb];
3880         u8         port_num[0x4];
3881         u8         vport_number[0x10];
3882
3883         u8         reserved_at_60[0x10];
3884         u8         pkey_index[0x10];
3885 };
3886
3887 enum {
3888         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
3889         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
3890         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3891 };
3892
3893 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3894         u8         status[0x8];
3895         u8         reserved_at_8[0x18];
3896
3897         u8         syndrome[0x20];
3898
3899         u8         reserved_at_40[0x20];
3900
3901         u8         gids_num[0x10];
3902         u8         reserved_at_70[0x10];
3903
3904         struct mlx5_ifc_array128_auto_bits gid[0];
3905 };
3906
3907 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3908         u8         opcode[0x10];
3909         u8         reserved_at_10[0x10];
3910
3911         u8         reserved_at_20[0x10];
3912         u8         op_mod[0x10];
3913
3914         u8         other_vport[0x1];
3915         u8         reserved_at_41[0xb];
3916         u8         port_num[0x4];
3917         u8         vport_number[0x10];
3918
3919         u8         reserved_at_60[0x10];
3920         u8         gid_index[0x10];
3921 };
3922
3923 struct mlx5_ifc_query_hca_vport_context_out_bits {
3924         u8         status[0x8];
3925         u8         reserved_at_8[0x18];
3926
3927         u8         syndrome[0x20];
3928
3929         u8         reserved_at_40[0x40];
3930
3931         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3932 };
3933
3934 struct mlx5_ifc_query_hca_vport_context_in_bits {
3935         u8         opcode[0x10];
3936         u8         reserved_at_10[0x10];
3937
3938         u8         reserved_at_20[0x10];
3939         u8         op_mod[0x10];
3940
3941         u8         other_vport[0x1];
3942         u8         reserved_at_41[0xb];
3943         u8         port_num[0x4];
3944         u8         vport_number[0x10];
3945
3946         u8         reserved_at_60[0x20];
3947 };
3948
3949 struct mlx5_ifc_query_hca_cap_out_bits {
3950         u8         status[0x8];
3951         u8         reserved_at_8[0x18];
3952
3953         u8         syndrome[0x20];
3954
3955         u8         reserved_at_40[0x40];
3956
3957         union mlx5_ifc_hca_cap_union_bits capability;
3958 };
3959
3960 struct mlx5_ifc_query_hca_cap_in_bits {
3961         u8         opcode[0x10];
3962         u8         reserved_at_10[0x10];
3963
3964         u8         reserved_at_20[0x10];
3965         u8         op_mod[0x10];
3966
3967         u8         reserved_at_40[0x40];
3968 };
3969
3970 struct mlx5_ifc_query_flow_table_out_bits {
3971         u8         status[0x8];
3972         u8         reserved_at_8[0x18];
3973
3974         u8         syndrome[0x20];
3975
3976         u8         reserved_at_40[0x80];
3977
3978         u8         reserved_at_c0[0x8];
3979         u8         level[0x8];
3980         u8         reserved_at_d0[0x8];
3981         u8         log_size[0x8];
3982
3983         u8         reserved_at_e0[0x120];
3984 };
3985
3986 struct mlx5_ifc_query_flow_table_in_bits {
3987         u8         opcode[0x10];
3988         u8         reserved_at_10[0x10];
3989
3990         u8         reserved_at_20[0x10];
3991         u8         op_mod[0x10];
3992
3993         u8         reserved_at_40[0x40];
3994
3995         u8         table_type[0x8];
3996         u8         reserved_at_88[0x18];
3997
3998         u8         reserved_at_a0[0x8];
3999         u8         table_id[0x18];
4000
4001         u8         reserved_at_c0[0x140];
4002 };
4003
4004 struct mlx5_ifc_query_fte_out_bits {
4005         u8         status[0x8];
4006         u8         reserved_at_8[0x18];
4007
4008         u8         syndrome[0x20];
4009
4010         u8         reserved_at_40[0x1c0];
4011
4012         struct mlx5_ifc_flow_context_bits flow_context;
4013 };
4014
4015 struct mlx5_ifc_query_fte_in_bits {
4016         u8         opcode[0x10];
4017         u8         reserved_at_10[0x10];
4018
4019         u8         reserved_at_20[0x10];
4020         u8         op_mod[0x10];
4021
4022         u8         reserved_at_40[0x40];
4023
4024         u8         table_type[0x8];
4025         u8         reserved_at_88[0x18];
4026
4027         u8         reserved_at_a0[0x8];
4028         u8         table_id[0x18];
4029
4030         u8         reserved_at_c0[0x40];
4031
4032         u8         flow_index[0x20];
4033
4034         u8         reserved_at_120[0xe0];
4035 };
4036
4037 enum {
4038         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4039         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4040         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4041 };
4042
4043 struct mlx5_ifc_query_flow_group_out_bits {
4044         u8         status[0x8];
4045         u8         reserved_at_8[0x18];
4046
4047         u8         syndrome[0x20];
4048
4049         u8         reserved_at_40[0xa0];
4050
4051         u8         start_flow_index[0x20];
4052
4053         u8         reserved_at_100[0x20];
4054
4055         u8         end_flow_index[0x20];
4056
4057         u8         reserved_at_140[0xa0];
4058
4059         u8         reserved_at_1e0[0x18];
4060         u8         match_criteria_enable[0x8];
4061
4062         struct mlx5_ifc_fte_match_param_bits match_criteria;
4063
4064         u8         reserved_at_1200[0xe00];
4065 };
4066
4067 struct mlx5_ifc_query_flow_group_in_bits {
4068         u8         opcode[0x10];
4069         u8         reserved_at_10[0x10];
4070
4071         u8         reserved_at_20[0x10];
4072         u8         op_mod[0x10];
4073
4074         u8         reserved_at_40[0x40];
4075
4076         u8         table_type[0x8];
4077         u8         reserved_at_88[0x18];
4078
4079         u8         reserved_at_a0[0x8];
4080         u8         table_id[0x18];
4081
4082         u8         group_id[0x20];
4083
4084         u8         reserved_at_e0[0x120];
4085 };
4086
4087 struct mlx5_ifc_query_flow_counter_out_bits {
4088         u8         status[0x8];
4089         u8         reserved_at_8[0x18];
4090
4091         u8         syndrome[0x20];
4092
4093         u8         reserved_at_40[0x40];
4094
4095         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4096 };
4097
4098 struct mlx5_ifc_query_flow_counter_in_bits {
4099         u8         opcode[0x10];
4100         u8         reserved_at_10[0x10];
4101
4102         u8         reserved_at_20[0x10];
4103         u8         op_mod[0x10];
4104
4105         u8         reserved_at_40[0x80];
4106
4107         u8         clear[0x1];
4108         u8         reserved_at_c1[0xf];
4109         u8         num_of_counters[0x10];
4110
4111         u8         reserved_at_e0[0x10];
4112         u8         flow_counter_id[0x10];
4113 };
4114
4115 struct mlx5_ifc_query_esw_vport_context_out_bits {
4116         u8         status[0x8];
4117         u8         reserved_at_8[0x18];
4118
4119         u8         syndrome[0x20];
4120
4121         u8         reserved_at_40[0x40];
4122
4123         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4124 };
4125
4126 struct mlx5_ifc_query_esw_vport_context_in_bits {
4127         u8         opcode[0x10];
4128         u8         reserved_at_10[0x10];
4129
4130         u8         reserved_at_20[0x10];
4131         u8         op_mod[0x10];
4132
4133         u8         other_vport[0x1];
4134         u8         reserved_at_41[0xf];
4135         u8         vport_number[0x10];
4136
4137         u8         reserved_at_60[0x20];
4138 };
4139
4140 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4141         u8         status[0x8];
4142         u8         reserved_at_8[0x18];
4143
4144         u8         syndrome[0x20];
4145
4146         u8         reserved_at_40[0x40];
4147 };
4148
4149 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4150         u8         reserved_at_0[0x1c];
4151         u8         vport_cvlan_insert[0x1];
4152         u8         vport_svlan_insert[0x1];
4153         u8         vport_cvlan_strip[0x1];
4154         u8         vport_svlan_strip[0x1];
4155 };
4156
4157 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4158         u8         opcode[0x10];
4159         u8         reserved_at_10[0x10];
4160
4161         u8         reserved_at_20[0x10];
4162         u8         op_mod[0x10];
4163
4164         u8         other_vport[0x1];
4165         u8         reserved_at_41[0xf];
4166         u8         vport_number[0x10];
4167
4168         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4169
4170         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4171 };
4172
4173 struct mlx5_ifc_query_eq_out_bits {
4174         u8         status[0x8];
4175         u8         reserved_at_8[0x18];
4176
4177         u8         syndrome[0x20];
4178
4179         u8         reserved_at_40[0x40];
4180
4181         struct mlx5_ifc_eqc_bits eq_context_entry;
4182
4183         u8         reserved_at_280[0x40];
4184
4185         u8         event_bitmask[0x40];
4186
4187         u8         reserved_at_300[0x580];
4188
4189         u8         pas[0][0x40];
4190 };
4191
4192 struct mlx5_ifc_query_eq_in_bits {
4193         u8         opcode[0x10];
4194         u8         reserved_at_10[0x10];
4195
4196         u8         reserved_at_20[0x10];
4197         u8         op_mod[0x10];
4198
4199         u8         reserved_at_40[0x18];
4200         u8         eq_number[0x8];
4201
4202         u8         reserved_at_60[0x20];
4203 };
4204
4205 struct mlx5_ifc_query_dct_out_bits {
4206         u8         status[0x8];
4207         u8         reserved_at_8[0x18];
4208
4209         u8         syndrome[0x20];
4210
4211         u8         reserved_at_40[0x40];
4212
4213         struct mlx5_ifc_dctc_bits dct_context_entry;
4214
4215         u8         reserved_at_280[0x180];
4216 };
4217
4218 struct mlx5_ifc_query_dct_in_bits {
4219         u8         opcode[0x10];
4220         u8         reserved_at_10[0x10];
4221
4222         u8         reserved_at_20[0x10];
4223         u8         op_mod[0x10];
4224
4225         u8         reserved_at_40[0x8];
4226         u8         dctn[0x18];
4227
4228         u8         reserved_at_60[0x20];
4229 };
4230
4231 struct mlx5_ifc_query_cq_out_bits {
4232         u8         status[0x8];
4233         u8         reserved_at_8[0x18];
4234
4235         u8         syndrome[0x20];
4236
4237         u8         reserved_at_40[0x40];
4238
4239         struct mlx5_ifc_cqc_bits cq_context;
4240
4241         u8         reserved_at_280[0x600];
4242
4243         u8         pas[0][0x40];
4244 };
4245
4246 struct mlx5_ifc_query_cq_in_bits {
4247         u8         opcode[0x10];
4248         u8         reserved_at_10[0x10];
4249
4250         u8         reserved_at_20[0x10];
4251         u8         op_mod[0x10];
4252
4253         u8         reserved_at_40[0x8];
4254         u8         cqn[0x18];
4255
4256         u8         reserved_at_60[0x20];
4257 };
4258
4259 struct mlx5_ifc_query_cong_status_out_bits {
4260         u8         status[0x8];
4261         u8         reserved_at_8[0x18];
4262
4263         u8         syndrome[0x20];
4264
4265         u8         reserved_at_40[0x20];
4266
4267         u8         enable[0x1];
4268         u8         tag_enable[0x1];
4269         u8         reserved_at_62[0x1e];
4270 };
4271
4272 struct mlx5_ifc_query_cong_status_in_bits {
4273         u8         opcode[0x10];
4274         u8         reserved_at_10[0x10];
4275
4276         u8         reserved_at_20[0x10];
4277         u8         op_mod[0x10];
4278
4279         u8         reserved_at_40[0x18];
4280         u8         priority[0x4];
4281         u8         cong_protocol[0x4];
4282
4283         u8         reserved_at_60[0x20];
4284 };
4285
4286 struct mlx5_ifc_query_cong_statistics_out_bits {
4287         u8         status[0x8];
4288         u8         reserved_at_8[0x18];
4289
4290         u8         syndrome[0x20];
4291
4292         u8         reserved_at_40[0x40];
4293
4294         u8         cur_flows[0x20];
4295
4296         u8         sum_flows[0x20];
4297
4298         u8         cnp_ignored_high[0x20];
4299
4300         u8         cnp_ignored_low[0x20];
4301
4302         u8         cnp_handled_high[0x20];
4303
4304         u8         cnp_handled_low[0x20];
4305
4306         u8         reserved_at_140[0x100];
4307
4308         u8         time_stamp_high[0x20];
4309
4310         u8         time_stamp_low[0x20];
4311
4312         u8         accumulators_period[0x20];
4313
4314         u8         ecn_marked_roce_packets_high[0x20];
4315
4316         u8         ecn_marked_roce_packets_low[0x20];
4317
4318         u8         cnps_sent_high[0x20];
4319
4320         u8         cnps_sent_low[0x20];
4321
4322         u8         reserved_at_320[0x560];
4323 };
4324
4325 struct mlx5_ifc_query_cong_statistics_in_bits {
4326         u8         opcode[0x10];
4327         u8         reserved_at_10[0x10];
4328
4329         u8         reserved_at_20[0x10];
4330         u8         op_mod[0x10];
4331
4332         u8         clear[0x1];
4333         u8         reserved_at_41[0x1f];
4334
4335         u8         reserved_at_60[0x20];
4336 };
4337
4338 struct mlx5_ifc_query_cong_params_out_bits {
4339         u8         status[0x8];
4340         u8         reserved_at_8[0x18];
4341
4342         u8         syndrome[0x20];
4343
4344         u8         reserved_at_40[0x40];
4345
4346         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4347 };
4348
4349 struct mlx5_ifc_query_cong_params_in_bits {
4350         u8         opcode[0x10];
4351         u8         reserved_at_10[0x10];
4352
4353         u8         reserved_at_20[0x10];
4354         u8         op_mod[0x10];
4355
4356         u8         reserved_at_40[0x1c];
4357         u8         cong_protocol[0x4];
4358
4359         u8         reserved_at_60[0x20];
4360 };
4361
4362 struct mlx5_ifc_query_adapter_out_bits {
4363         u8         status[0x8];
4364         u8         reserved_at_8[0x18];
4365
4366         u8         syndrome[0x20];
4367
4368         u8         reserved_at_40[0x40];
4369
4370         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4371 };
4372
4373 struct mlx5_ifc_query_adapter_in_bits {
4374         u8         opcode[0x10];
4375         u8         reserved_at_10[0x10];
4376
4377         u8         reserved_at_20[0x10];
4378         u8         op_mod[0x10];
4379
4380         u8         reserved_at_40[0x40];
4381 };
4382
4383 struct mlx5_ifc_qp_2rst_out_bits {
4384         u8         status[0x8];
4385         u8         reserved_at_8[0x18];
4386
4387         u8         syndrome[0x20];
4388
4389         u8         reserved_at_40[0x40];
4390 };
4391
4392 struct mlx5_ifc_qp_2rst_in_bits {
4393         u8         opcode[0x10];
4394         u8         reserved_at_10[0x10];
4395
4396         u8         reserved_at_20[0x10];
4397         u8         op_mod[0x10];
4398
4399         u8         reserved_at_40[0x8];
4400         u8         qpn[0x18];
4401
4402         u8         reserved_at_60[0x20];
4403 };
4404
4405 struct mlx5_ifc_qp_2err_out_bits {
4406         u8         status[0x8];
4407         u8         reserved_at_8[0x18];
4408
4409         u8         syndrome[0x20];
4410
4411         u8         reserved_at_40[0x40];
4412 };
4413
4414 struct mlx5_ifc_qp_2err_in_bits {
4415         u8         opcode[0x10];
4416         u8         reserved_at_10[0x10];
4417
4418         u8         reserved_at_20[0x10];
4419         u8         op_mod[0x10];
4420
4421         u8         reserved_at_40[0x8];
4422         u8         qpn[0x18];
4423
4424         u8         reserved_at_60[0x20];
4425 };
4426
4427 struct mlx5_ifc_page_fault_resume_out_bits {
4428         u8         status[0x8];
4429         u8         reserved_at_8[0x18];
4430
4431         u8         syndrome[0x20];
4432
4433         u8         reserved_at_40[0x40];
4434 };
4435
4436 struct mlx5_ifc_page_fault_resume_in_bits {
4437         u8         opcode[0x10];
4438         u8         reserved_at_10[0x10];
4439
4440         u8         reserved_at_20[0x10];
4441         u8         op_mod[0x10];
4442
4443         u8         error[0x1];
4444         u8         reserved_at_41[0x4];
4445         u8         rdma[0x1];
4446         u8         read_write[0x1];
4447         u8         req_res[0x1];
4448         u8         qpn[0x18];
4449
4450         u8         reserved_at_60[0x20];
4451 };
4452
4453 struct mlx5_ifc_nop_out_bits {
4454         u8         status[0x8];
4455         u8         reserved_at_8[0x18];
4456
4457         u8         syndrome[0x20];
4458
4459         u8         reserved_at_40[0x40];
4460 };
4461
4462 struct mlx5_ifc_nop_in_bits {
4463         u8         opcode[0x10];
4464         u8         reserved_at_10[0x10];
4465
4466         u8         reserved_at_20[0x10];
4467         u8         op_mod[0x10];
4468
4469         u8         reserved_at_40[0x40];
4470 };
4471
4472 struct mlx5_ifc_modify_vport_state_out_bits {
4473         u8         status[0x8];
4474         u8         reserved_at_8[0x18];
4475
4476         u8         syndrome[0x20];
4477
4478         u8         reserved_at_40[0x40];
4479 };
4480
4481 struct mlx5_ifc_modify_vport_state_in_bits {
4482         u8         opcode[0x10];
4483         u8         reserved_at_10[0x10];
4484
4485         u8         reserved_at_20[0x10];
4486         u8         op_mod[0x10];
4487
4488         u8         other_vport[0x1];
4489         u8         reserved_at_41[0xf];
4490         u8         vport_number[0x10];
4491
4492         u8         reserved_at_60[0x18];
4493         u8         admin_state[0x4];
4494         u8         reserved_at_7c[0x4];
4495 };
4496
4497 struct mlx5_ifc_modify_tis_out_bits {
4498         u8         status[0x8];
4499         u8         reserved_at_8[0x18];
4500
4501         u8         syndrome[0x20];
4502
4503         u8         reserved_at_40[0x40];
4504 };
4505
4506 struct mlx5_ifc_modify_tis_bitmask_bits {
4507         u8         reserved_at_0[0x20];
4508
4509         u8         reserved_at_20[0x1f];
4510         u8         prio[0x1];
4511 };
4512
4513 struct mlx5_ifc_modify_tis_in_bits {
4514         u8         opcode[0x10];
4515         u8         reserved_at_10[0x10];
4516
4517         u8         reserved_at_20[0x10];
4518         u8         op_mod[0x10];
4519
4520         u8         reserved_at_40[0x8];
4521         u8         tisn[0x18];
4522
4523         u8         reserved_at_60[0x20];
4524
4525         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4526
4527         u8         reserved_at_c0[0x40];
4528
4529         struct mlx5_ifc_tisc_bits ctx;
4530 };
4531
4532 struct mlx5_ifc_modify_tir_bitmask_bits {
4533         u8         reserved_at_0[0x20];
4534
4535         u8         reserved_at_20[0x1b];
4536         u8         self_lb_en[0x1];
4537         u8         reserved_at_3c[0x1];
4538         u8         hash[0x1];
4539         u8         reserved_at_3e[0x1];
4540         u8         lro[0x1];
4541 };
4542
4543 struct mlx5_ifc_modify_tir_out_bits {
4544         u8         status[0x8];
4545         u8         reserved_at_8[0x18];
4546
4547         u8         syndrome[0x20];
4548
4549         u8         reserved_at_40[0x40];
4550 };
4551
4552 struct mlx5_ifc_modify_tir_in_bits {
4553         u8         opcode[0x10];
4554         u8         reserved_at_10[0x10];
4555
4556         u8         reserved_at_20[0x10];
4557         u8         op_mod[0x10];
4558
4559         u8         reserved_at_40[0x8];
4560         u8         tirn[0x18];
4561
4562         u8         reserved_at_60[0x20];
4563
4564         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4565
4566         u8         reserved_at_c0[0x40];
4567
4568         struct mlx5_ifc_tirc_bits ctx;
4569 };
4570
4571 struct mlx5_ifc_modify_sq_out_bits {
4572         u8         status[0x8];
4573         u8         reserved_at_8[0x18];
4574
4575         u8         syndrome[0x20];
4576
4577         u8         reserved_at_40[0x40];
4578 };
4579
4580 struct mlx5_ifc_modify_sq_in_bits {
4581         u8         opcode[0x10];
4582         u8         reserved_at_10[0x10];
4583
4584         u8         reserved_at_20[0x10];
4585         u8         op_mod[0x10];
4586
4587         u8         sq_state[0x4];
4588         u8         reserved_at_44[0x4];
4589         u8         sqn[0x18];
4590
4591         u8         reserved_at_60[0x20];
4592
4593         u8         modify_bitmask[0x40];
4594
4595         u8         reserved_at_c0[0x40];
4596
4597         struct mlx5_ifc_sqc_bits ctx;
4598 };
4599
4600 struct mlx5_ifc_modify_rqt_out_bits {
4601         u8         status[0x8];
4602         u8         reserved_at_8[0x18];
4603
4604         u8         syndrome[0x20];
4605
4606         u8         reserved_at_40[0x40];
4607 };
4608
4609 struct mlx5_ifc_rqt_bitmask_bits {
4610         u8         reserved_at_0[0x20];
4611
4612         u8         reserved_at_20[0x1f];
4613         u8         rqn_list[0x1];
4614 };
4615
4616 struct mlx5_ifc_modify_rqt_in_bits {
4617         u8         opcode[0x10];
4618         u8         reserved_at_10[0x10];
4619
4620         u8         reserved_at_20[0x10];
4621         u8         op_mod[0x10];
4622
4623         u8         reserved_at_40[0x8];
4624         u8         rqtn[0x18];
4625
4626         u8         reserved_at_60[0x20];
4627
4628         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4629
4630         u8         reserved_at_c0[0x40];
4631
4632         struct mlx5_ifc_rqtc_bits ctx;
4633 };
4634
4635 struct mlx5_ifc_modify_rq_out_bits {
4636         u8         status[0x8];
4637         u8         reserved_at_8[0x18];
4638
4639         u8         syndrome[0x20];
4640
4641         u8         reserved_at_40[0x40];
4642 };
4643
4644 struct mlx5_ifc_modify_rq_in_bits {
4645         u8         opcode[0x10];
4646         u8         reserved_at_10[0x10];
4647
4648         u8         reserved_at_20[0x10];
4649         u8         op_mod[0x10];
4650
4651         u8         rq_state[0x4];
4652         u8         reserved_at_44[0x4];
4653         u8         rqn[0x18];
4654
4655         u8         reserved_at_60[0x20];
4656
4657         u8         modify_bitmask[0x40];
4658
4659         u8         reserved_at_c0[0x40];
4660
4661         struct mlx5_ifc_rqc_bits ctx;
4662 };
4663
4664 struct mlx5_ifc_modify_rmp_out_bits {
4665         u8         status[0x8];
4666         u8         reserved_at_8[0x18];
4667
4668         u8         syndrome[0x20];
4669
4670         u8         reserved_at_40[0x40];
4671 };
4672
4673 struct mlx5_ifc_rmp_bitmask_bits {
4674         u8         reserved_at_0[0x20];
4675
4676         u8         reserved_at_20[0x1f];
4677         u8         lwm[0x1];
4678 };
4679
4680 struct mlx5_ifc_modify_rmp_in_bits {
4681         u8         opcode[0x10];
4682         u8         reserved_at_10[0x10];
4683
4684         u8         reserved_at_20[0x10];
4685         u8         op_mod[0x10];
4686
4687         u8         rmp_state[0x4];
4688         u8         reserved_at_44[0x4];
4689         u8         rmpn[0x18];
4690
4691         u8         reserved_at_60[0x20];
4692
4693         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4694
4695         u8         reserved_at_c0[0x40];
4696
4697         struct mlx5_ifc_rmpc_bits ctx;
4698 };
4699
4700 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4701         u8         status[0x8];
4702         u8         reserved_at_8[0x18];
4703
4704         u8         syndrome[0x20];
4705
4706         u8         reserved_at_40[0x40];
4707 };
4708
4709 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4710         u8         reserved_at_0[0x19];
4711         u8         mtu[0x1];
4712         u8         change_event[0x1];
4713         u8         promisc[0x1];
4714         u8         permanent_address[0x1];
4715         u8         addresses_list[0x1];
4716         u8         roce_en[0x1];
4717         u8         reserved_at_1f[0x1];
4718 };
4719
4720 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4721         u8         opcode[0x10];
4722         u8         reserved_at_10[0x10];
4723
4724         u8         reserved_at_20[0x10];
4725         u8         op_mod[0x10];
4726
4727         u8         other_vport[0x1];
4728         u8         reserved_at_41[0xf];
4729         u8         vport_number[0x10];
4730
4731         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4732
4733         u8         reserved_at_80[0x780];
4734
4735         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4736 };
4737
4738 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4739         u8         status[0x8];
4740         u8         reserved_at_8[0x18];
4741
4742         u8         syndrome[0x20];
4743
4744         u8         reserved_at_40[0x40];
4745 };
4746
4747 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4748         u8         opcode[0x10];
4749         u8         reserved_at_10[0x10];
4750
4751         u8         reserved_at_20[0x10];
4752         u8         op_mod[0x10];
4753
4754         u8         other_vport[0x1];
4755         u8         reserved_at_41[0xb];
4756         u8         port_num[0x4];
4757         u8         vport_number[0x10];
4758
4759         u8         reserved_at_60[0x20];
4760
4761         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4762 };
4763
4764 struct mlx5_ifc_modify_cq_out_bits {
4765         u8         status[0x8];
4766         u8         reserved_at_8[0x18];
4767
4768         u8         syndrome[0x20];
4769
4770         u8         reserved_at_40[0x40];
4771 };
4772
4773 enum {
4774         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4775         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4776 };
4777
4778 struct mlx5_ifc_modify_cq_in_bits {
4779         u8         opcode[0x10];
4780         u8         reserved_at_10[0x10];
4781
4782         u8         reserved_at_20[0x10];
4783         u8         op_mod[0x10];
4784
4785         u8         reserved_at_40[0x8];
4786         u8         cqn[0x18];
4787
4788         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4789
4790         struct mlx5_ifc_cqc_bits cq_context;
4791
4792         u8         reserved_at_280[0x600];
4793
4794         u8         pas[0][0x40];
4795 };
4796
4797 struct mlx5_ifc_modify_cong_status_out_bits {
4798         u8         status[0x8];
4799         u8         reserved_at_8[0x18];
4800
4801         u8         syndrome[0x20];
4802
4803         u8         reserved_at_40[0x40];
4804 };
4805
4806 struct mlx5_ifc_modify_cong_status_in_bits {
4807         u8         opcode[0x10];
4808         u8         reserved_at_10[0x10];
4809
4810         u8         reserved_at_20[0x10];
4811         u8         op_mod[0x10];
4812
4813         u8         reserved_at_40[0x18];
4814         u8         priority[0x4];
4815         u8         cong_protocol[0x4];
4816
4817         u8         enable[0x1];
4818         u8         tag_enable[0x1];
4819         u8         reserved_at_62[0x1e];
4820 };
4821
4822 struct mlx5_ifc_modify_cong_params_out_bits {
4823         u8         status[0x8];
4824         u8         reserved_at_8[0x18];
4825
4826         u8         syndrome[0x20];
4827
4828         u8         reserved_at_40[0x40];
4829 };
4830
4831 struct mlx5_ifc_modify_cong_params_in_bits {
4832         u8         opcode[0x10];
4833         u8         reserved_at_10[0x10];
4834
4835         u8         reserved_at_20[0x10];
4836         u8         op_mod[0x10];
4837
4838         u8         reserved_at_40[0x1c];
4839         u8         cong_protocol[0x4];
4840
4841         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4842
4843         u8         reserved_at_80[0x80];
4844
4845         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4846 };
4847
4848 struct mlx5_ifc_manage_pages_out_bits {
4849         u8         status[0x8];
4850         u8         reserved_at_8[0x18];
4851
4852         u8         syndrome[0x20];
4853
4854         u8         output_num_entries[0x20];
4855
4856         u8         reserved_at_60[0x20];
4857
4858         u8         pas[0][0x40];
4859 };
4860
4861 enum {
4862         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4863         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4864         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4865 };
4866
4867 struct mlx5_ifc_manage_pages_in_bits {
4868         u8         opcode[0x10];
4869         u8         reserved_at_10[0x10];
4870
4871         u8         reserved_at_20[0x10];
4872         u8         op_mod[0x10];
4873
4874         u8         reserved_at_40[0x10];
4875         u8         function_id[0x10];
4876
4877         u8         input_num_entries[0x20];
4878
4879         u8         pas[0][0x40];
4880 };
4881
4882 struct mlx5_ifc_mad_ifc_out_bits {
4883         u8         status[0x8];
4884         u8         reserved_at_8[0x18];
4885
4886         u8         syndrome[0x20];
4887
4888         u8         reserved_at_40[0x40];
4889
4890         u8         response_mad_packet[256][0x8];
4891 };
4892
4893 struct mlx5_ifc_mad_ifc_in_bits {
4894         u8         opcode[0x10];
4895         u8         reserved_at_10[0x10];
4896
4897         u8         reserved_at_20[0x10];
4898         u8         op_mod[0x10];
4899
4900         u8         remote_lid[0x10];
4901         u8         reserved_at_50[0x8];
4902         u8         port[0x8];
4903
4904         u8         reserved_at_60[0x20];
4905
4906         u8         mad[256][0x8];
4907 };
4908
4909 struct mlx5_ifc_init_hca_out_bits {
4910         u8         status[0x8];
4911         u8         reserved_at_8[0x18];
4912
4913         u8         syndrome[0x20];
4914
4915         u8         reserved_at_40[0x40];
4916 };
4917
4918 struct mlx5_ifc_init_hca_in_bits {
4919         u8         opcode[0x10];
4920         u8         reserved_at_10[0x10];
4921
4922         u8         reserved_at_20[0x10];
4923         u8         op_mod[0x10];
4924
4925         u8         reserved_at_40[0x40];
4926 };
4927
4928 struct mlx5_ifc_init2rtr_qp_out_bits {
4929         u8         status[0x8];
4930         u8         reserved_at_8[0x18];
4931
4932         u8         syndrome[0x20];
4933
4934         u8         reserved_at_40[0x40];
4935 };
4936
4937 struct mlx5_ifc_init2rtr_qp_in_bits {
4938         u8         opcode[0x10];
4939         u8         reserved_at_10[0x10];
4940
4941         u8         reserved_at_20[0x10];
4942         u8         op_mod[0x10];
4943
4944         u8         reserved_at_40[0x8];
4945         u8         qpn[0x18];
4946
4947         u8         reserved_at_60[0x20];
4948
4949         u8         opt_param_mask[0x20];
4950
4951         u8         reserved_at_a0[0x20];
4952
4953         struct mlx5_ifc_qpc_bits qpc;
4954
4955         u8         reserved_at_800[0x80];
4956 };
4957
4958 struct mlx5_ifc_init2init_qp_out_bits {
4959         u8         status[0x8];
4960         u8         reserved_at_8[0x18];
4961
4962         u8         syndrome[0x20];
4963
4964         u8         reserved_at_40[0x40];
4965 };
4966
4967 struct mlx5_ifc_init2init_qp_in_bits {
4968         u8         opcode[0x10];
4969         u8         reserved_at_10[0x10];
4970
4971         u8         reserved_at_20[0x10];
4972         u8         op_mod[0x10];
4973
4974         u8         reserved_at_40[0x8];
4975         u8         qpn[0x18];
4976
4977         u8         reserved_at_60[0x20];
4978
4979         u8         opt_param_mask[0x20];
4980
4981         u8         reserved_at_a0[0x20];
4982
4983         struct mlx5_ifc_qpc_bits qpc;
4984
4985         u8         reserved_at_800[0x80];
4986 };
4987
4988 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4989         u8         status[0x8];
4990         u8         reserved_at_8[0x18];
4991
4992         u8         syndrome[0x20];
4993
4994         u8         reserved_at_40[0x40];
4995
4996         u8         packet_headers_log[128][0x8];
4997
4998         u8         packet_syndrome[64][0x8];
4999 };
5000
5001 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5002         u8         opcode[0x10];
5003         u8         reserved_at_10[0x10];
5004
5005         u8         reserved_at_20[0x10];
5006         u8         op_mod[0x10];
5007
5008         u8         reserved_at_40[0x40];
5009 };
5010
5011 struct mlx5_ifc_gen_eqe_in_bits {
5012         u8         opcode[0x10];
5013         u8         reserved_at_10[0x10];
5014
5015         u8         reserved_at_20[0x10];
5016         u8         op_mod[0x10];
5017
5018         u8         reserved_at_40[0x18];
5019         u8         eq_number[0x8];
5020
5021         u8         reserved_at_60[0x20];
5022
5023         u8         eqe[64][0x8];
5024 };
5025
5026 struct mlx5_ifc_gen_eq_out_bits {
5027         u8         status[0x8];
5028         u8         reserved_at_8[0x18];
5029
5030         u8         syndrome[0x20];
5031
5032         u8         reserved_at_40[0x40];
5033 };
5034
5035 struct mlx5_ifc_enable_hca_out_bits {
5036         u8         status[0x8];
5037         u8         reserved_at_8[0x18];
5038
5039         u8         syndrome[0x20];
5040
5041         u8         reserved_at_40[0x20];
5042 };
5043
5044 struct mlx5_ifc_enable_hca_in_bits {
5045         u8         opcode[0x10];
5046         u8         reserved_at_10[0x10];
5047
5048         u8         reserved_at_20[0x10];
5049         u8         op_mod[0x10];
5050
5051         u8         reserved_at_40[0x10];
5052         u8         function_id[0x10];
5053
5054         u8         reserved_at_60[0x20];
5055 };
5056
5057 struct mlx5_ifc_drain_dct_out_bits {
5058         u8         status[0x8];
5059         u8         reserved_at_8[0x18];
5060
5061         u8         syndrome[0x20];
5062
5063         u8         reserved_at_40[0x40];
5064 };
5065
5066 struct mlx5_ifc_drain_dct_in_bits {
5067         u8         opcode[0x10];
5068         u8         reserved_at_10[0x10];
5069
5070         u8         reserved_at_20[0x10];
5071         u8         op_mod[0x10];
5072
5073         u8         reserved_at_40[0x8];
5074         u8         dctn[0x18];
5075
5076         u8         reserved_at_60[0x20];
5077 };
5078
5079 struct mlx5_ifc_disable_hca_out_bits {
5080         u8         status[0x8];
5081         u8         reserved_at_8[0x18];
5082
5083         u8         syndrome[0x20];
5084
5085         u8         reserved_at_40[0x20];
5086 };
5087
5088 struct mlx5_ifc_disable_hca_in_bits {
5089         u8         opcode[0x10];
5090         u8         reserved_at_10[0x10];
5091
5092         u8         reserved_at_20[0x10];
5093         u8         op_mod[0x10];
5094
5095         u8         reserved_at_40[0x10];
5096         u8         function_id[0x10];
5097
5098         u8         reserved_at_60[0x20];
5099 };
5100
5101 struct mlx5_ifc_detach_from_mcg_out_bits {
5102         u8         status[0x8];
5103         u8         reserved_at_8[0x18];
5104
5105         u8         syndrome[0x20];
5106
5107         u8         reserved_at_40[0x40];
5108 };
5109
5110 struct mlx5_ifc_detach_from_mcg_in_bits {
5111         u8         opcode[0x10];
5112         u8         reserved_at_10[0x10];
5113
5114         u8         reserved_at_20[0x10];
5115         u8         op_mod[0x10];
5116
5117         u8         reserved_at_40[0x8];
5118         u8         qpn[0x18];
5119
5120         u8         reserved_at_60[0x20];
5121
5122         u8         multicast_gid[16][0x8];
5123 };
5124
5125 struct mlx5_ifc_destroy_xrq_out_bits {
5126         u8         status[0x8];
5127         u8         reserved_at_8[0x18];
5128
5129         u8         syndrome[0x20];
5130
5131         u8         reserved_at_40[0x40];
5132 };
5133
5134 struct mlx5_ifc_destroy_xrq_in_bits {
5135         u8         opcode[0x10];
5136         u8         reserved_at_10[0x10];
5137
5138         u8         reserved_at_20[0x10];
5139         u8         op_mod[0x10];
5140
5141         u8         reserved_at_40[0x8];
5142         u8         xrqn[0x18];
5143
5144         u8         reserved_at_60[0x20];
5145 };
5146
5147 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5148         u8         status[0x8];
5149         u8         reserved_at_8[0x18];
5150
5151         u8         syndrome[0x20];
5152
5153         u8         reserved_at_40[0x40];
5154 };
5155
5156 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5157         u8         opcode[0x10];
5158         u8         reserved_at_10[0x10];
5159
5160         u8         reserved_at_20[0x10];
5161         u8         op_mod[0x10];
5162
5163         u8         reserved_at_40[0x8];
5164         u8         xrc_srqn[0x18];
5165
5166         u8         reserved_at_60[0x20];
5167 };
5168
5169 struct mlx5_ifc_destroy_tis_out_bits {
5170         u8         status[0x8];
5171         u8         reserved_at_8[0x18];
5172
5173         u8         syndrome[0x20];
5174
5175         u8         reserved_at_40[0x40];
5176 };
5177
5178 struct mlx5_ifc_destroy_tis_in_bits {
5179         u8         opcode[0x10];
5180         u8         reserved_at_10[0x10];
5181
5182         u8         reserved_at_20[0x10];
5183         u8         op_mod[0x10];
5184
5185         u8         reserved_at_40[0x8];
5186         u8         tisn[0x18];
5187
5188         u8         reserved_at_60[0x20];
5189 };
5190
5191 struct mlx5_ifc_destroy_tir_out_bits {
5192         u8         status[0x8];
5193         u8         reserved_at_8[0x18];
5194
5195         u8         syndrome[0x20];
5196
5197         u8         reserved_at_40[0x40];
5198 };
5199
5200 struct mlx5_ifc_destroy_tir_in_bits {
5201         u8         opcode[0x10];
5202         u8         reserved_at_10[0x10];
5203
5204         u8         reserved_at_20[0x10];
5205         u8         op_mod[0x10];
5206
5207         u8         reserved_at_40[0x8];
5208         u8         tirn[0x18];
5209
5210         u8         reserved_at_60[0x20];
5211 };
5212
5213 struct mlx5_ifc_destroy_srq_out_bits {
5214         u8         status[0x8];
5215         u8         reserved_at_8[0x18];
5216
5217         u8         syndrome[0x20];
5218
5219         u8         reserved_at_40[0x40];
5220 };
5221
5222 struct mlx5_ifc_destroy_srq_in_bits {
5223         u8         opcode[0x10];
5224         u8         reserved_at_10[0x10];
5225
5226         u8         reserved_at_20[0x10];
5227         u8         op_mod[0x10];
5228
5229         u8         reserved_at_40[0x8];
5230         u8         srqn[0x18];
5231
5232         u8         reserved_at_60[0x20];
5233 };
5234
5235 struct mlx5_ifc_destroy_sq_out_bits {
5236         u8         status[0x8];
5237         u8         reserved_at_8[0x18];
5238
5239         u8         syndrome[0x20];
5240
5241         u8         reserved_at_40[0x40];
5242 };
5243
5244 struct mlx5_ifc_destroy_sq_in_bits {
5245         u8         opcode[0x10];
5246         u8         reserved_at_10[0x10];
5247
5248         u8         reserved_at_20[0x10];
5249         u8         op_mod[0x10];
5250
5251         u8         reserved_at_40[0x8];
5252         u8         sqn[0x18];
5253
5254         u8         reserved_at_60[0x20];
5255 };
5256
5257 struct mlx5_ifc_destroy_rqt_out_bits {
5258         u8         status[0x8];
5259         u8         reserved_at_8[0x18];
5260
5261         u8         syndrome[0x20];
5262
5263         u8         reserved_at_40[0x40];
5264 };
5265
5266 struct mlx5_ifc_destroy_rqt_in_bits {
5267         u8         opcode[0x10];
5268         u8         reserved_at_10[0x10];
5269
5270         u8         reserved_at_20[0x10];
5271         u8         op_mod[0x10];
5272
5273         u8         reserved_at_40[0x8];
5274         u8         rqtn[0x18];
5275
5276         u8         reserved_at_60[0x20];
5277 };
5278
5279 struct mlx5_ifc_destroy_rq_out_bits {
5280         u8         status[0x8];
5281         u8         reserved_at_8[0x18];
5282
5283         u8         syndrome[0x20];
5284
5285         u8         reserved_at_40[0x40];
5286 };
5287
5288 struct mlx5_ifc_destroy_rq_in_bits {
5289         u8         opcode[0x10];
5290         u8         reserved_at_10[0x10];
5291
5292         u8         reserved_at_20[0x10];
5293         u8         op_mod[0x10];
5294
5295         u8         reserved_at_40[0x8];
5296         u8         rqn[0x18];
5297
5298         u8         reserved_at_60[0x20];
5299 };
5300
5301 struct mlx5_ifc_destroy_rmp_out_bits {
5302         u8         status[0x8];
5303         u8         reserved_at_8[0x18];
5304
5305         u8         syndrome[0x20];
5306
5307         u8         reserved_at_40[0x40];
5308 };
5309
5310 struct mlx5_ifc_destroy_rmp_in_bits {
5311         u8         opcode[0x10];
5312         u8         reserved_at_10[0x10];
5313
5314         u8         reserved_at_20[0x10];
5315         u8         op_mod[0x10];
5316
5317         u8         reserved_at_40[0x8];
5318         u8         rmpn[0x18];
5319
5320         u8         reserved_at_60[0x20];
5321 };
5322
5323 struct mlx5_ifc_destroy_qp_out_bits {
5324         u8         status[0x8];
5325         u8         reserved_at_8[0x18];
5326
5327         u8         syndrome[0x20];
5328
5329         u8         reserved_at_40[0x40];
5330 };
5331
5332 struct mlx5_ifc_destroy_qp_in_bits {
5333         u8         opcode[0x10];
5334         u8         reserved_at_10[0x10];
5335
5336         u8         reserved_at_20[0x10];
5337         u8         op_mod[0x10];
5338
5339         u8         reserved_at_40[0x8];
5340         u8         qpn[0x18];
5341
5342         u8         reserved_at_60[0x20];
5343 };
5344
5345 struct mlx5_ifc_destroy_psv_out_bits {
5346         u8         status[0x8];
5347         u8         reserved_at_8[0x18];
5348
5349         u8         syndrome[0x20];
5350
5351         u8         reserved_at_40[0x40];
5352 };
5353
5354 struct mlx5_ifc_destroy_psv_in_bits {
5355         u8         opcode[0x10];
5356         u8         reserved_at_10[0x10];
5357
5358         u8         reserved_at_20[0x10];
5359         u8         op_mod[0x10];
5360
5361         u8         reserved_at_40[0x8];
5362         u8         psvn[0x18];
5363
5364         u8         reserved_at_60[0x20];
5365 };
5366
5367 struct mlx5_ifc_destroy_mkey_out_bits {
5368         u8         status[0x8];
5369         u8         reserved_at_8[0x18];
5370
5371         u8         syndrome[0x20];
5372
5373         u8         reserved_at_40[0x40];
5374 };
5375
5376 struct mlx5_ifc_destroy_mkey_in_bits {
5377         u8         opcode[0x10];
5378         u8         reserved_at_10[0x10];
5379
5380         u8         reserved_at_20[0x10];
5381         u8         op_mod[0x10];
5382
5383         u8         reserved_at_40[0x8];
5384         u8         mkey_index[0x18];
5385
5386         u8         reserved_at_60[0x20];
5387 };
5388
5389 struct mlx5_ifc_destroy_flow_table_out_bits {
5390         u8         status[0x8];
5391         u8         reserved_at_8[0x18];
5392
5393         u8         syndrome[0x20];
5394
5395         u8         reserved_at_40[0x40];
5396 };
5397
5398 struct mlx5_ifc_destroy_flow_table_in_bits {
5399         u8         opcode[0x10];
5400         u8         reserved_at_10[0x10];
5401
5402         u8         reserved_at_20[0x10];
5403         u8         op_mod[0x10];
5404
5405         u8         other_vport[0x1];
5406         u8         reserved_at_41[0xf];
5407         u8         vport_number[0x10];
5408
5409         u8         reserved_at_60[0x20];
5410
5411         u8         table_type[0x8];
5412         u8         reserved_at_88[0x18];
5413
5414         u8         reserved_at_a0[0x8];
5415         u8         table_id[0x18];
5416
5417         u8         reserved_at_c0[0x140];
5418 };
5419
5420 struct mlx5_ifc_destroy_flow_group_out_bits {
5421         u8         status[0x8];
5422         u8         reserved_at_8[0x18];
5423
5424         u8         syndrome[0x20];
5425
5426         u8         reserved_at_40[0x40];
5427 };
5428
5429 struct mlx5_ifc_destroy_flow_group_in_bits {
5430         u8         opcode[0x10];
5431         u8         reserved_at_10[0x10];
5432
5433         u8         reserved_at_20[0x10];
5434         u8         op_mod[0x10];
5435
5436         u8         other_vport[0x1];
5437         u8         reserved_at_41[0xf];
5438         u8         vport_number[0x10];
5439
5440         u8         reserved_at_60[0x20];
5441
5442         u8         table_type[0x8];
5443         u8         reserved_at_88[0x18];
5444
5445         u8         reserved_at_a0[0x8];
5446         u8         table_id[0x18];
5447
5448         u8         group_id[0x20];
5449
5450         u8         reserved_at_e0[0x120];
5451 };
5452
5453 struct mlx5_ifc_destroy_eq_out_bits {
5454         u8         status[0x8];
5455         u8         reserved_at_8[0x18];
5456
5457         u8         syndrome[0x20];
5458
5459         u8         reserved_at_40[0x40];
5460 };
5461
5462 struct mlx5_ifc_destroy_eq_in_bits {
5463         u8         opcode[0x10];
5464         u8         reserved_at_10[0x10];
5465
5466         u8         reserved_at_20[0x10];
5467         u8         op_mod[0x10];
5468
5469         u8         reserved_at_40[0x18];
5470         u8         eq_number[0x8];
5471
5472         u8         reserved_at_60[0x20];
5473 };
5474
5475 struct mlx5_ifc_destroy_dct_out_bits {
5476         u8         status[0x8];
5477         u8         reserved_at_8[0x18];
5478
5479         u8         syndrome[0x20];
5480
5481         u8         reserved_at_40[0x40];
5482 };
5483
5484 struct mlx5_ifc_destroy_dct_in_bits {
5485         u8         opcode[0x10];
5486         u8         reserved_at_10[0x10];
5487
5488         u8         reserved_at_20[0x10];
5489         u8         op_mod[0x10];
5490
5491         u8         reserved_at_40[0x8];
5492         u8         dctn[0x18];
5493
5494         u8         reserved_at_60[0x20];
5495 };
5496
5497 struct mlx5_ifc_destroy_cq_out_bits {
5498         u8         status[0x8];
5499         u8         reserved_at_8[0x18];
5500
5501         u8         syndrome[0x20];
5502
5503         u8         reserved_at_40[0x40];
5504 };
5505
5506 struct mlx5_ifc_destroy_cq_in_bits {
5507         u8         opcode[0x10];
5508         u8         reserved_at_10[0x10];
5509
5510         u8         reserved_at_20[0x10];
5511         u8         op_mod[0x10];
5512
5513         u8         reserved_at_40[0x8];
5514         u8         cqn[0x18];
5515
5516         u8         reserved_at_60[0x20];
5517 };
5518
5519 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5520         u8         status[0x8];
5521         u8         reserved_at_8[0x18];
5522
5523         u8         syndrome[0x20];
5524
5525         u8         reserved_at_40[0x40];
5526 };
5527
5528 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5529         u8         opcode[0x10];
5530         u8         reserved_at_10[0x10];
5531
5532         u8         reserved_at_20[0x10];
5533         u8         op_mod[0x10];
5534
5535         u8         reserved_at_40[0x20];
5536
5537         u8         reserved_at_60[0x10];
5538         u8         vxlan_udp_port[0x10];
5539 };
5540
5541 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5542         u8         status[0x8];
5543         u8         reserved_at_8[0x18];
5544
5545         u8         syndrome[0x20];
5546
5547         u8         reserved_at_40[0x40];
5548 };
5549
5550 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5551         u8         opcode[0x10];
5552         u8         reserved_at_10[0x10];
5553
5554         u8         reserved_at_20[0x10];
5555         u8         op_mod[0x10];
5556
5557         u8         reserved_at_40[0x60];
5558
5559         u8         reserved_at_a0[0x8];
5560         u8         table_index[0x18];
5561
5562         u8         reserved_at_c0[0x140];
5563 };
5564
5565 struct mlx5_ifc_delete_fte_out_bits {
5566         u8         status[0x8];
5567         u8         reserved_at_8[0x18];
5568
5569         u8         syndrome[0x20];
5570
5571         u8         reserved_at_40[0x40];
5572 };
5573
5574 struct mlx5_ifc_delete_fte_in_bits {
5575         u8         opcode[0x10];
5576         u8         reserved_at_10[0x10];
5577
5578         u8         reserved_at_20[0x10];
5579         u8         op_mod[0x10];
5580
5581         u8         other_vport[0x1];
5582         u8         reserved_at_41[0xf];
5583         u8         vport_number[0x10];
5584
5585         u8         reserved_at_60[0x20];
5586
5587         u8         table_type[0x8];
5588         u8         reserved_at_88[0x18];
5589
5590         u8         reserved_at_a0[0x8];
5591         u8         table_id[0x18];
5592
5593         u8         reserved_at_c0[0x40];
5594
5595         u8         flow_index[0x20];
5596
5597         u8         reserved_at_120[0xe0];
5598 };
5599
5600 struct mlx5_ifc_dealloc_xrcd_out_bits {
5601         u8         status[0x8];
5602         u8         reserved_at_8[0x18];
5603
5604         u8         syndrome[0x20];
5605
5606         u8         reserved_at_40[0x40];
5607 };
5608
5609 struct mlx5_ifc_dealloc_xrcd_in_bits {
5610         u8         opcode[0x10];
5611         u8         reserved_at_10[0x10];
5612
5613         u8         reserved_at_20[0x10];
5614         u8         op_mod[0x10];
5615
5616         u8         reserved_at_40[0x8];
5617         u8         xrcd[0x18];
5618
5619         u8         reserved_at_60[0x20];
5620 };
5621
5622 struct mlx5_ifc_dealloc_uar_out_bits {
5623         u8         status[0x8];
5624         u8         reserved_at_8[0x18];
5625
5626         u8         syndrome[0x20];
5627
5628         u8         reserved_at_40[0x40];
5629 };
5630
5631 struct mlx5_ifc_dealloc_uar_in_bits {
5632         u8         opcode[0x10];
5633         u8         reserved_at_10[0x10];
5634
5635         u8         reserved_at_20[0x10];
5636         u8         op_mod[0x10];
5637
5638         u8         reserved_at_40[0x8];
5639         u8         uar[0x18];
5640
5641         u8         reserved_at_60[0x20];
5642 };
5643
5644 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5645         u8         status[0x8];
5646         u8         reserved_at_8[0x18];
5647
5648         u8         syndrome[0x20];
5649
5650         u8         reserved_at_40[0x40];
5651 };
5652
5653 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5654         u8         opcode[0x10];
5655         u8         reserved_at_10[0x10];
5656
5657         u8         reserved_at_20[0x10];
5658         u8         op_mod[0x10];
5659
5660         u8         reserved_at_40[0x8];
5661         u8         transport_domain[0x18];
5662
5663         u8         reserved_at_60[0x20];
5664 };
5665
5666 struct mlx5_ifc_dealloc_q_counter_out_bits {
5667         u8         status[0x8];
5668         u8         reserved_at_8[0x18];
5669
5670         u8         syndrome[0x20];
5671
5672         u8         reserved_at_40[0x40];
5673 };
5674
5675 struct mlx5_ifc_dealloc_q_counter_in_bits {
5676         u8         opcode[0x10];
5677         u8         reserved_at_10[0x10];
5678
5679         u8         reserved_at_20[0x10];
5680         u8         op_mod[0x10];
5681
5682         u8         reserved_at_40[0x18];
5683         u8         counter_set_id[0x8];
5684
5685         u8         reserved_at_60[0x20];
5686 };
5687
5688 struct mlx5_ifc_dealloc_pd_out_bits {
5689         u8         status[0x8];
5690         u8         reserved_at_8[0x18];
5691
5692         u8         syndrome[0x20];
5693
5694         u8         reserved_at_40[0x40];
5695 };
5696
5697 struct mlx5_ifc_dealloc_pd_in_bits {
5698         u8         opcode[0x10];
5699         u8         reserved_at_10[0x10];
5700
5701         u8         reserved_at_20[0x10];
5702         u8         op_mod[0x10];
5703
5704         u8         reserved_at_40[0x8];
5705         u8         pd[0x18];
5706
5707         u8         reserved_at_60[0x20];
5708 };
5709
5710 struct mlx5_ifc_dealloc_flow_counter_out_bits {
5711         u8         status[0x8];
5712         u8         reserved_at_8[0x18];
5713
5714         u8         syndrome[0x20];
5715
5716         u8         reserved_at_40[0x40];
5717 };
5718
5719 struct mlx5_ifc_dealloc_flow_counter_in_bits {
5720         u8         opcode[0x10];
5721         u8         reserved_at_10[0x10];
5722
5723         u8         reserved_at_20[0x10];
5724         u8         op_mod[0x10];
5725
5726         u8         reserved_at_40[0x10];
5727         u8         flow_counter_id[0x10];
5728
5729         u8         reserved_at_60[0x20];
5730 };
5731
5732 struct mlx5_ifc_create_xrq_out_bits {
5733         u8         status[0x8];
5734         u8         reserved_at_8[0x18];
5735
5736         u8         syndrome[0x20];
5737
5738         u8         reserved_at_40[0x8];
5739         u8         xrqn[0x18];
5740
5741         u8         reserved_at_60[0x20];
5742 };
5743
5744 struct mlx5_ifc_create_xrq_in_bits {
5745         u8         opcode[0x10];
5746         u8         reserved_at_10[0x10];
5747
5748         u8         reserved_at_20[0x10];
5749         u8         op_mod[0x10];
5750
5751         u8         reserved_at_40[0x40];
5752
5753         struct mlx5_ifc_xrqc_bits xrq_context;
5754 };
5755
5756 struct mlx5_ifc_create_xrc_srq_out_bits {
5757         u8         status[0x8];
5758         u8         reserved_at_8[0x18];
5759
5760         u8         syndrome[0x20];
5761
5762         u8         reserved_at_40[0x8];
5763         u8         xrc_srqn[0x18];
5764
5765         u8         reserved_at_60[0x20];
5766 };
5767
5768 struct mlx5_ifc_create_xrc_srq_in_bits {
5769         u8         opcode[0x10];
5770         u8         reserved_at_10[0x10];
5771
5772         u8         reserved_at_20[0x10];
5773         u8         op_mod[0x10];
5774
5775         u8         reserved_at_40[0x40];
5776
5777         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5778
5779         u8         reserved_at_280[0x600];
5780
5781         u8         pas[0][0x40];
5782 };
5783
5784 struct mlx5_ifc_create_tis_out_bits {
5785         u8         status[0x8];
5786         u8         reserved_at_8[0x18];
5787
5788         u8         syndrome[0x20];
5789
5790         u8         reserved_at_40[0x8];
5791         u8         tisn[0x18];
5792
5793         u8         reserved_at_60[0x20];
5794 };
5795
5796 struct mlx5_ifc_create_tis_in_bits {
5797         u8         opcode[0x10];
5798         u8         reserved_at_10[0x10];
5799
5800         u8         reserved_at_20[0x10];
5801         u8         op_mod[0x10];
5802
5803         u8         reserved_at_40[0xc0];
5804
5805         struct mlx5_ifc_tisc_bits ctx;
5806 };
5807
5808 struct mlx5_ifc_create_tir_out_bits {
5809         u8         status[0x8];
5810         u8         reserved_at_8[0x18];
5811
5812         u8         syndrome[0x20];
5813
5814         u8         reserved_at_40[0x8];
5815         u8         tirn[0x18];
5816
5817         u8         reserved_at_60[0x20];
5818 };
5819
5820 struct mlx5_ifc_create_tir_in_bits {
5821         u8         opcode[0x10];
5822         u8         reserved_at_10[0x10];
5823
5824         u8         reserved_at_20[0x10];
5825         u8         op_mod[0x10];
5826
5827         u8         reserved_at_40[0xc0];
5828
5829         struct mlx5_ifc_tirc_bits ctx;
5830 };
5831
5832 struct mlx5_ifc_create_srq_out_bits {
5833         u8         status[0x8];
5834         u8         reserved_at_8[0x18];
5835
5836         u8         syndrome[0x20];
5837
5838         u8         reserved_at_40[0x8];
5839         u8         srqn[0x18];
5840
5841         u8         reserved_at_60[0x20];
5842 };
5843
5844 struct mlx5_ifc_create_srq_in_bits {
5845         u8         opcode[0x10];
5846         u8         reserved_at_10[0x10];
5847
5848         u8         reserved_at_20[0x10];
5849         u8         op_mod[0x10];
5850
5851         u8         reserved_at_40[0x40];
5852
5853         struct mlx5_ifc_srqc_bits srq_context_entry;
5854
5855         u8         reserved_at_280[0x600];
5856
5857         u8         pas[0][0x40];
5858 };
5859
5860 struct mlx5_ifc_create_sq_out_bits {
5861         u8         status[0x8];
5862         u8         reserved_at_8[0x18];
5863
5864         u8         syndrome[0x20];
5865
5866         u8         reserved_at_40[0x8];
5867         u8         sqn[0x18];
5868
5869         u8         reserved_at_60[0x20];
5870 };
5871
5872 struct mlx5_ifc_create_sq_in_bits {
5873         u8         opcode[0x10];
5874         u8         reserved_at_10[0x10];
5875
5876         u8         reserved_at_20[0x10];
5877         u8         op_mod[0x10];
5878
5879         u8         reserved_at_40[0xc0];
5880
5881         struct mlx5_ifc_sqc_bits ctx;
5882 };
5883
5884 struct mlx5_ifc_create_rqt_out_bits {
5885         u8         status[0x8];
5886         u8         reserved_at_8[0x18];
5887
5888         u8         syndrome[0x20];
5889
5890         u8         reserved_at_40[0x8];
5891         u8         rqtn[0x18];
5892
5893         u8         reserved_at_60[0x20];
5894 };
5895
5896 struct mlx5_ifc_create_rqt_in_bits {
5897         u8         opcode[0x10];
5898         u8         reserved_at_10[0x10];
5899
5900         u8         reserved_at_20[0x10];
5901         u8         op_mod[0x10];
5902
5903         u8         reserved_at_40[0xc0];
5904
5905         struct mlx5_ifc_rqtc_bits rqt_context;
5906 };
5907
5908 struct mlx5_ifc_create_rq_out_bits {
5909         u8         status[0x8];
5910         u8         reserved_at_8[0x18];
5911
5912         u8         syndrome[0x20];
5913
5914         u8         reserved_at_40[0x8];
5915         u8         rqn[0x18];
5916
5917         u8         reserved_at_60[0x20];
5918 };
5919
5920 struct mlx5_ifc_create_rq_in_bits {
5921         u8         opcode[0x10];
5922         u8         reserved_at_10[0x10];
5923
5924         u8         reserved_at_20[0x10];
5925         u8         op_mod[0x10];
5926
5927         u8         reserved_at_40[0xc0];
5928
5929         struct mlx5_ifc_rqc_bits ctx;
5930 };
5931
5932 struct mlx5_ifc_create_rmp_out_bits {
5933         u8         status[0x8];
5934         u8         reserved_at_8[0x18];
5935
5936         u8         syndrome[0x20];
5937
5938         u8         reserved_at_40[0x8];
5939         u8         rmpn[0x18];
5940
5941         u8         reserved_at_60[0x20];
5942 };
5943
5944 struct mlx5_ifc_create_rmp_in_bits {
5945         u8         opcode[0x10];
5946         u8         reserved_at_10[0x10];
5947
5948         u8         reserved_at_20[0x10];
5949         u8         op_mod[0x10];
5950
5951         u8         reserved_at_40[0xc0];
5952
5953         struct mlx5_ifc_rmpc_bits ctx;
5954 };
5955
5956 struct mlx5_ifc_create_qp_out_bits {
5957         u8         status[0x8];
5958         u8         reserved_at_8[0x18];
5959
5960         u8         syndrome[0x20];
5961
5962         u8         reserved_at_40[0x8];
5963         u8         qpn[0x18];
5964
5965         u8         reserved_at_60[0x20];
5966 };
5967
5968 struct mlx5_ifc_create_qp_in_bits {
5969         u8         opcode[0x10];
5970         u8         reserved_at_10[0x10];
5971
5972         u8         reserved_at_20[0x10];
5973         u8         op_mod[0x10];
5974
5975         u8         reserved_at_40[0x40];
5976
5977         u8         opt_param_mask[0x20];
5978
5979         u8         reserved_at_a0[0x20];
5980
5981         struct mlx5_ifc_qpc_bits qpc;
5982
5983         u8         reserved_at_800[0x80];
5984
5985         u8         pas[0][0x40];
5986 };
5987
5988 struct mlx5_ifc_create_psv_out_bits {
5989         u8         status[0x8];
5990         u8         reserved_at_8[0x18];
5991
5992         u8         syndrome[0x20];
5993
5994         u8         reserved_at_40[0x40];
5995
5996         u8         reserved_at_80[0x8];
5997         u8         psv0_index[0x18];
5998
5999         u8         reserved_at_a0[0x8];
6000         u8         psv1_index[0x18];
6001
6002         u8         reserved_at_c0[0x8];
6003         u8         psv2_index[0x18];
6004
6005         u8         reserved_at_e0[0x8];
6006         u8         psv3_index[0x18];
6007 };
6008
6009 struct mlx5_ifc_create_psv_in_bits {
6010         u8         opcode[0x10];
6011         u8         reserved_at_10[0x10];
6012
6013         u8         reserved_at_20[0x10];
6014         u8         op_mod[0x10];
6015
6016         u8         num_psv[0x4];
6017         u8         reserved_at_44[0x4];
6018         u8         pd[0x18];
6019
6020         u8         reserved_at_60[0x20];
6021 };
6022
6023 struct mlx5_ifc_create_mkey_out_bits {
6024         u8         status[0x8];
6025         u8         reserved_at_8[0x18];
6026
6027         u8         syndrome[0x20];
6028
6029         u8         reserved_at_40[0x8];
6030         u8         mkey_index[0x18];
6031
6032         u8         reserved_at_60[0x20];
6033 };
6034
6035 struct mlx5_ifc_create_mkey_in_bits {
6036         u8         opcode[0x10];
6037         u8         reserved_at_10[0x10];
6038
6039         u8         reserved_at_20[0x10];
6040         u8         op_mod[0x10];
6041
6042         u8         reserved_at_40[0x20];
6043
6044         u8         pg_access[0x1];
6045         u8         reserved_at_61[0x1f];
6046
6047         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6048
6049         u8         reserved_at_280[0x80];
6050
6051         u8         translations_octword_actual_size[0x20];
6052
6053         u8         reserved_at_320[0x560];
6054
6055         u8         klm_pas_mtt[0][0x20];
6056 };
6057
6058 struct mlx5_ifc_create_flow_table_out_bits {
6059         u8         status[0x8];
6060         u8         reserved_at_8[0x18];
6061
6062         u8         syndrome[0x20];
6063
6064         u8         reserved_at_40[0x8];
6065         u8         table_id[0x18];
6066
6067         u8         reserved_at_60[0x20];
6068 };
6069
6070 struct mlx5_ifc_create_flow_table_in_bits {
6071         u8         opcode[0x10];
6072         u8         reserved_at_10[0x10];
6073
6074         u8         reserved_at_20[0x10];
6075         u8         op_mod[0x10];
6076
6077         u8         other_vport[0x1];
6078         u8         reserved_at_41[0xf];
6079         u8         vport_number[0x10];
6080
6081         u8         reserved_at_60[0x20];
6082
6083         u8         table_type[0x8];
6084         u8         reserved_at_88[0x18];
6085
6086         u8         reserved_at_a0[0x20];
6087
6088         u8         reserved_at_c0[0x4];
6089         u8         table_miss_mode[0x4];
6090         u8         level[0x8];
6091         u8         reserved_at_d0[0x8];
6092         u8         log_size[0x8];
6093
6094         u8         reserved_at_e0[0x8];
6095         u8         table_miss_id[0x18];
6096
6097         u8         reserved_at_100[0x100];
6098 };
6099
6100 struct mlx5_ifc_create_flow_group_out_bits {
6101         u8         status[0x8];
6102         u8         reserved_at_8[0x18];
6103
6104         u8         syndrome[0x20];
6105
6106         u8         reserved_at_40[0x8];
6107         u8         group_id[0x18];
6108
6109         u8         reserved_at_60[0x20];
6110 };
6111
6112 enum {
6113         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6114         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6115         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6116 };
6117
6118 struct mlx5_ifc_create_flow_group_in_bits {
6119         u8         opcode[0x10];
6120         u8         reserved_at_10[0x10];
6121
6122         u8         reserved_at_20[0x10];
6123         u8         op_mod[0x10];
6124
6125         u8         other_vport[0x1];
6126         u8         reserved_at_41[0xf];
6127         u8         vport_number[0x10];
6128
6129         u8         reserved_at_60[0x20];
6130
6131         u8         table_type[0x8];
6132         u8         reserved_at_88[0x18];
6133
6134         u8         reserved_at_a0[0x8];
6135         u8         table_id[0x18];
6136
6137         u8         reserved_at_c0[0x20];
6138
6139         u8         start_flow_index[0x20];
6140
6141         u8         reserved_at_100[0x20];
6142
6143         u8         end_flow_index[0x20];
6144
6145         u8         reserved_at_140[0xa0];
6146
6147         u8         reserved_at_1e0[0x18];
6148         u8         match_criteria_enable[0x8];
6149
6150         struct mlx5_ifc_fte_match_param_bits match_criteria;
6151
6152         u8         reserved_at_1200[0xe00];
6153 };
6154
6155 struct mlx5_ifc_create_eq_out_bits {
6156         u8         status[0x8];
6157         u8         reserved_at_8[0x18];
6158
6159         u8         syndrome[0x20];
6160
6161         u8         reserved_at_40[0x18];
6162         u8         eq_number[0x8];
6163
6164         u8         reserved_at_60[0x20];
6165 };
6166
6167 struct mlx5_ifc_create_eq_in_bits {
6168         u8         opcode[0x10];
6169         u8         reserved_at_10[0x10];
6170
6171         u8         reserved_at_20[0x10];
6172         u8         op_mod[0x10];
6173
6174         u8         reserved_at_40[0x40];
6175
6176         struct mlx5_ifc_eqc_bits eq_context_entry;
6177
6178         u8         reserved_at_280[0x40];
6179
6180         u8         event_bitmask[0x40];
6181
6182         u8         reserved_at_300[0x580];
6183
6184         u8         pas[0][0x40];
6185 };
6186
6187 struct mlx5_ifc_create_dct_out_bits {
6188         u8         status[0x8];
6189         u8         reserved_at_8[0x18];
6190
6191         u8         syndrome[0x20];
6192
6193         u8         reserved_at_40[0x8];
6194         u8         dctn[0x18];
6195
6196         u8         reserved_at_60[0x20];
6197 };
6198
6199 struct mlx5_ifc_create_dct_in_bits {
6200         u8         opcode[0x10];
6201         u8         reserved_at_10[0x10];
6202
6203         u8         reserved_at_20[0x10];
6204         u8         op_mod[0x10];
6205
6206         u8         reserved_at_40[0x40];
6207
6208         struct mlx5_ifc_dctc_bits dct_context_entry;
6209
6210         u8         reserved_at_280[0x180];
6211 };
6212
6213 struct mlx5_ifc_create_cq_out_bits {
6214         u8         status[0x8];
6215         u8         reserved_at_8[0x18];
6216
6217         u8         syndrome[0x20];
6218
6219         u8         reserved_at_40[0x8];
6220         u8         cqn[0x18];
6221
6222         u8         reserved_at_60[0x20];
6223 };
6224
6225 struct mlx5_ifc_create_cq_in_bits {
6226         u8         opcode[0x10];
6227         u8         reserved_at_10[0x10];
6228
6229         u8         reserved_at_20[0x10];
6230         u8         op_mod[0x10];
6231
6232         u8         reserved_at_40[0x40];
6233
6234         struct mlx5_ifc_cqc_bits cq_context;
6235
6236         u8         reserved_at_280[0x600];
6237
6238         u8         pas[0][0x40];
6239 };
6240
6241 struct mlx5_ifc_config_int_moderation_out_bits {
6242         u8         status[0x8];
6243         u8         reserved_at_8[0x18];
6244
6245         u8         syndrome[0x20];
6246
6247         u8         reserved_at_40[0x4];
6248         u8         min_delay[0xc];
6249         u8         int_vector[0x10];
6250
6251         u8         reserved_at_60[0x20];
6252 };
6253
6254 enum {
6255         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6256         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6257 };
6258
6259 struct mlx5_ifc_config_int_moderation_in_bits {
6260         u8         opcode[0x10];
6261         u8         reserved_at_10[0x10];
6262
6263         u8         reserved_at_20[0x10];
6264         u8         op_mod[0x10];
6265
6266         u8         reserved_at_40[0x4];
6267         u8         min_delay[0xc];
6268         u8         int_vector[0x10];
6269
6270         u8         reserved_at_60[0x20];
6271 };
6272
6273 struct mlx5_ifc_attach_to_mcg_out_bits {
6274         u8         status[0x8];
6275         u8         reserved_at_8[0x18];
6276
6277         u8         syndrome[0x20];
6278
6279         u8         reserved_at_40[0x40];
6280 };
6281
6282 struct mlx5_ifc_attach_to_mcg_in_bits {
6283         u8         opcode[0x10];
6284         u8         reserved_at_10[0x10];
6285
6286         u8         reserved_at_20[0x10];
6287         u8         op_mod[0x10];
6288
6289         u8         reserved_at_40[0x8];
6290         u8         qpn[0x18];
6291
6292         u8         reserved_at_60[0x20];
6293
6294         u8         multicast_gid[16][0x8];
6295 };
6296
6297 struct mlx5_ifc_arm_xrq_out_bits {
6298         u8         status[0x8];
6299         u8         reserved_at_8[0x18];
6300
6301         u8         syndrome[0x20];
6302
6303         u8         reserved_at_40[0x40];
6304 };
6305
6306 struct mlx5_ifc_arm_xrq_in_bits {
6307         u8         opcode[0x10];
6308         u8         reserved_at_10[0x10];
6309
6310         u8         reserved_at_20[0x10];
6311         u8         op_mod[0x10];
6312
6313         u8         reserved_at_40[0x8];
6314         u8         xrqn[0x18];
6315
6316         u8         reserved_at_60[0x10];
6317         u8         lwm[0x10];
6318 };
6319
6320 struct mlx5_ifc_arm_xrc_srq_out_bits {
6321         u8         status[0x8];
6322         u8         reserved_at_8[0x18];
6323
6324         u8         syndrome[0x20];
6325
6326         u8         reserved_at_40[0x40];
6327 };
6328
6329 enum {
6330         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6331 };
6332
6333 struct mlx5_ifc_arm_xrc_srq_in_bits {
6334         u8         opcode[0x10];
6335         u8         reserved_at_10[0x10];
6336
6337         u8         reserved_at_20[0x10];
6338         u8         op_mod[0x10];
6339
6340         u8         reserved_at_40[0x8];
6341         u8         xrc_srqn[0x18];
6342
6343         u8         reserved_at_60[0x10];
6344         u8         lwm[0x10];
6345 };
6346
6347 struct mlx5_ifc_arm_rq_out_bits {
6348         u8         status[0x8];
6349         u8         reserved_at_8[0x18];
6350
6351         u8         syndrome[0x20];
6352
6353         u8         reserved_at_40[0x40];
6354 };
6355
6356 enum {
6357         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6358         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6359 };
6360
6361 struct mlx5_ifc_arm_rq_in_bits {
6362         u8         opcode[0x10];
6363         u8         reserved_at_10[0x10];
6364
6365         u8         reserved_at_20[0x10];
6366         u8         op_mod[0x10];
6367
6368         u8         reserved_at_40[0x8];
6369         u8         srq_number[0x18];
6370
6371         u8         reserved_at_60[0x10];
6372         u8         lwm[0x10];
6373 };
6374
6375 struct mlx5_ifc_arm_dct_out_bits {
6376         u8         status[0x8];
6377         u8         reserved_at_8[0x18];
6378
6379         u8         syndrome[0x20];
6380
6381         u8         reserved_at_40[0x40];
6382 };
6383
6384 struct mlx5_ifc_arm_dct_in_bits {
6385         u8         opcode[0x10];
6386         u8         reserved_at_10[0x10];
6387
6388         u8         reserved_at_20[0x10];
6389         u8         op_mod[0x10];
6390
6391         u8         reserved_at_40[0x8];
6392         u8         dct_number[0x18];
6393
6394         u8         reserved_at_60[0x20];
6395 };
6396
6397 struct mlx5_ifc_alloc_xrcd_out_bits {
6398         u8         status[0x8];
6399         u8         reserved_at_8[0x18];
6400
6401         u8         syndrome[0x20];
6402
6403         u8         reserved_at_40[0x8];
6404         u8         xrcd[0x18];
6405
6406         u8         reserved_at_60[0x20];
6407 };
6408
6409 struct mlx5_ifc_alloc_xrcd_in_bits {
6410         u8         opcode[0x10];
6411         u8         reserved_at_10[0x10];
6412
6413         u8         reserved_at_20[0x10];
6414         u8         op_mod[0x10];
6415
6416         u8         reserved_at_40[0x40];
6417 };
6418
6419 struct mlx5_ifc_alloc_uar_out_bits {
6420         u8         status[0x8];
6421         u8         reserved_at_8[0x18];
6422
6423         u8         syndrome[0x20];
6424
6425         u8         reserved_at_40[0x8];
6426         u8         uar[0x18];
6427
6428         u8         reserved_at_60[0x20];
6429 };
6430
6431 struct mlx5_ifc_alloc_uar_in_bits {
6432         u8         opcode[0x10];
6433         u8         reserved_at_10[0x10];
6434
6435         u8         reserved_at_20[0x10];
6436         u8         op_mod[0x10];
6437
6438         u8         reserved_at_40[0x40];
6439 };
6440
6441 struct mlx5_ifc_alloc_transport_domain_out_bits {
6442         u8         status[0x8];
6443         u8         reserved_at_8[0x18];
6444
6445         u8         syndrome[0x20];
6446
6447         u8         reserved_at_40[0x8];
6448         u8         transport_domain[0x18];
6449
6450         u8         reserved_at_60[0x20];
6451 };
6452
6453 struct mlx5_ifc_alloc_transport_domain_in_bits {
6454         u8         opcode[0x10];
6455         u8         reserved_at_10[0x10];
6456
6457         u8         reserved_at_20[0x10];
6458         u8         op_mod[0x10];
6459
6460         u8         reserved_at_40[0x40];
6461 };
6462
6463 struct mlx5_ifc_alloc_q_counter_out_bits {
6464         u8         status[0x8];
6465         u8         reserved_at_8[0x18];
6466
6467         u8         syndrome[0x20];
6468
6469         u8         reserved_at_40[0x18];
6470         u8         counter_set_id[0x8];
6471
6472         u8         reserved_at_60[0x20];
6473 };
6474
6475 struct mlx5_ifc_alloc_q_counter_in_bits {
6476         u8         opcode[0x10];
6477         u8         reserved_at_10[0x10];
6478
6479         u8         reserved_at_20[0x10];
6480         u8         op_mod[0x10];
6481
6482         u8         reserved_at_40[0x40];
6483 };
6484
6485 struct mlx5_ifc_alloc_pd_out_bits {
6486         u8         status[0x8];
6487         u8         reserved_at_8[0x18];
6488
6489         u8         syndrome[0x20];
6490
6491         u8         reserved_at_40[0x8];
6492         u8         pd[0x18];
6493
6494         u8         reserved_at_60[0x20];
6495 };
6496
6497 struct mlx5_ifc_alloc_pd_in_bits {
6498         u8         opcode[0x10];
6499         u8         reserved_at_10[0x10];
6500
6501         u8         reserved_at_20[0x10];
6502         u8         op_mod[0x10];
6503
6504         u8         reserved_at_40[0x40];
6505 };
6506
6507 struct mlx5_ifc_alloc_flow_counter_out_bits {
6508         u8         status[0x8];
6509         u8         reserved_at_8[0x18];
6510
6511         u8         syndrome[0x20];
6512
6513         u8         reserved_at_40[0x10];
6514         u8         flow_counter_id[0x10];
6515
6516         u8         reserved_at_60[0x20];
6517 };
6518
6519 struct mlx5_ifc_alloc_flow_counter_in_bits {
6520         u8         opcode[0x10];
6521         u8         reserved_at_10[0x10];
6522
6523         u8         reserved_at_20[0x10];
6524         u8         op_mod[0x10];
6525
6526         u8         reserved_at_40[0x40];
6527 };
6528
6529 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6530         u8         status[0x8];
6531         u8         reserved_at_8[0x18];
6532
6533         u8         syndrome[0x20];
6534
6535         u8         reserved_at_40[0x40];
6536 };
6537
6538 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6539         u8         opcode[0x10];
6540         u8         reserved_at_10[0x10];
6541
6542         u8         reserved_at_20[0x10];
6543         u8         op_mod[0x10];
6544
6545         u8         reserved_at_40[0x20];
6546
6547         u8         reserved_at_60[0x10];
6548         u8         vxlan_udp_port[0x10];
6549 };
6550
6551 struct mlx5_ifc_set_rate_limit_out_bits {
6552         u8         status[0x8];
6553         u8         reserved_at_8[0x18];
6554
6555         u8         syndrome[0x20];
6556
6557         u8         reserved_at_40[0x40];
6558 };
6559
6560 struct mlx5_ifc_set_rate_limit_in_bits {
6561         u8         opcode[0x10];
6562         u8         reserved_at_10[0x10];
6563
6564         u8         reserved_at_20[0x10];
6565         u8         op_mod[0x10];
6566
6567         u8         reserved_at_40[0x10];
6568         u8         rate_limit_index[0x10];
6569
6570         u8         reserved_at_60[0x20];
6571
6572         u8         rate_limit[0x20];
6573 };
6574
6575 struct mlx5_ifc_access_register_out_bits {
6576         u8         status[0x8];
6577         u8         reserved_at_8[0x18];
6578
6579         u8         syndrome[0x20];
6580
6581         u8         reserved_at_40[0x40];
6582
6583         u8         register_data[0][0x20];
6584 };
6585
6586 enum {
6587         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6588         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6589 };
6590
6591 struct mlx5_ifc_access_register_in_bits {
6592         u8         opcode[0x10];
6593         u8         reserved_at_10[0x10];
6594
6595         u8         reserved_at_20[0x10];
6596         u8         op_mod[0x10];
6597
6598         u8         reserved_at_40[0x10];
6599         u8         register_id[0x10];
6600
6601         u8         argument[0x20];
6602
6603         u8         register_data[0][0x20];
6604 };
6605
6606 struct mlx5_ifc_sltp_reg_bits {
6607         u8         status[0x4];
6608         u8         version[0x4];
6609         u8         local_port[0x8];
6610         u8         pnat[0x2];
6611         u8         reserved_at_12[0x2];
6612         u8         lane[0x4];
6613         u8         reserved_at_18[0x8];
6614
6615         u8         reserved_at_20[0x20];
6616
6617         u8         reserved_at_40[0x7];
6618         u8         polarity[0x1];
6619         u8         ob_tap0[0x8];
6620         u8         ob_tap1[0x8];
6621         u8         ob_tap2[0x8];
6622
6623         u8         reserved_at_60[0xc];
6624         u8         ob_preemp_mode[0x4];
6625         u8         ob_reg[0x8];
6626         u8         ob_bias[0x8];
6627
6628         u8         reserved_at_80[0x20];
6629 };
6630
6631 struct mlx5_ifc_slrg_reg_bits {
6632         u8         status[0x4];
6633         u8         version[0x4];
6634         u8         local_port[0x8];
6635         u8         pnat[0x2];
6636         u8         reserved_at_12[0x2];
6637         u8         lane[0x4];
6638         u8         reserved_at_18[0x8];
6639
6640         u8         time_to_link_up[0x10];
6641         u8         reserved_at_30[0xc];
6642         u8         grade_lane_speed[0x4];
6643
6644         u8         grade_version[0x8];
6645         u8         grade[0x18];
6646
6647         u8         reserved_at_60[0x4];
6648         u8         height_grade_type[0x4];
6649         u8         height_grade[0x18];
6650
6651         u8         height_dz[0x10];
6652         u8         height_dv[0x10];
6653
6654         u8         reserved_at_a0[0x10];
6655         u8         height_sigma[0x10];
6656
6657         u8         reserved_at_c0[0x20];
6658
6659         u8         reserved_at_e0[0x4];
6660         u8         phase_grade_type[0x4];
6661         u8         phase_grade[0x18];
6662
6663         u8         reserved_at_100[0x8];
6664         u8         phase_eo_pos[0x8];
6665         u8         reserved_at_110[0x8];
6666         u8         phase_eo_neg[0x8];
6667
6668         u8         ffe_set_tested[0x10];
6669         u8         test_errors_per_lane[0x10];
6670 };
6671
6672 struct mlx5_ifc_pvlc_reg_bits {
6673         u8         reserved_at_0[0x8];
6674         u8         local_port[0x8];
6675         u8         reserved_at_10[0x10];
6676
6677         u8         reserved_at_20[0x1c];
6678         u8         vl_hw_cap[0x4];
6679
6680         u8         reserved_at_40[0x1c];
6681         u8         vl_admin[0x4];
6682
6683         u8         reserved_at_60[0x1c];
6684         u8         vl_operational[0x4];
6685 };
6686
6687 struct mlx5_ifc_pude_reg_bits {
6688         u8         swid[0x8];
6689         u8         local_port[0x8];
6690         u8         reserved_at_10[0x4];
6691         u8         admin_status[0x4];
6692         u8         reserved_at_18[0x4];
6693         u8         oper_status[0x4];
6694
6695         u8         reserved_at_20[0x60];
6696 };
6697
6698 struct mlx5_ifc_ptys_reg_bits {
6699         u8         an_disable_cap[0x1];
6700         u8         an_disable_admin[0x1];
6701         u8         reserved_at_2[0x6];
6702         u8         local_port[0x8];
6703         u8         reserved_at_10[0xd];
6704         u8         proto_mask[0x3];
6705
6706         u8         an_status[0x4];
6707         u8         reserved_at_24[0x3c];
6708
6709         u8         eth_proto_capability[0x20];
6710
6711         u8         ib_link_width_capability[0x10];
6712         u8         ib_proto_capability[0x10];
6713
6714         u8         reserved_at_a0[0x20];
6715
6716         u8         eth_proto_admin[0x20];
6717
6718         u8         ib_link_width_admin[0x10];
6719         u8         ib_proto_admin[0x10];
6720
6721         u8         reserved_at_100[0x20];
6722
6723         u8         eth_proto_oper[0x20];
6724
6725         u8         ib_link_width_oper[0x10];
6726         u8         ib_proto_oper[0x10];
6727
6728         u8         reserved_at_160[0x20];
6729
6730         u8         eth_proto_lp_advertise[0x20];
6731
6732         u8         reserved_at_1a0[0x60];
6733 };
6734
6735 struct mlx5_ifc_mlcr_reg_bits {
6736         u8         reserved_at_0[0x8];
6737         u8         local_port[0x8];
6738         u8         reserved_at_10[0x20];
6739
6740         u8         beacon_duration[0x10];
6741         u8         reserved_at_40[0x10];
6742
6743         u8         beacon_remain[0x10];
6744 };
6745
6746 struct mlx5_ifc_ptas_reg_bits {
6747         u8         reserved_at_0[0x20];
6748
6749         u8         algorithm_options[0x10];
6750         u8         reserved_at_30[0x4];
6751         u8         repetitions_mode[0x4];
6752         u8         num_of_repetitions[0x8];
6753
6754         u8         grade_version[0x8];
6755         u8         height_grade_type[0x4];
6756         u8         phase_grade_type[0x4];
6757         u8         height_grade_weight[0x8];
6758         u8         phase_grade_weight[0x8];
6759
6760         u8         gisim_measure_bits[0x10];
6761         u8         adaptive_tap_measure_bits[0x10];
6762
6763         u8         ber_bath_high_error_threshold[0x10];
6764         u8         ber_bath_mid_error_threshold[0x10];
6765
6766         u8         ber_bath_low_error_threshold[0x10];
6767         u8         one_ratio_high_threshold[0x10];
6768
6769         u8         one_ratio_high_mid_threshold[0x10];
6770         u8         one_ratio_low_mid_threshold[0x10];
6771
6772         u8         one_ratio_low_threshold[0x10];
6773         u8         ndeo_error_threshold[0x10];
6774
6775         u8         mixer_offset_step_size[0x10];
6776         u8         reserved_at_110[0x8];
6777         u8         mix90_phase_for_voltage_bath[0x8];
6778
6779         u8         mixer_offset_start[0x10];
6780         u8         mixer_offset_end[0x10];
6781
6782         u8         reserved_at_140[0x15];
6783         u8         ber_test_time[0xb];
6784 };
6785
6786 struct mlx5_ifc_pspa_reg_bits {
6787         u8         swid[0x8];
6788         u8         local_port[0x8];
6789         u8         sub_port[0x8];
6790         u8         reserved_at_18[0x8];
6791
6792         u8         reserved_at_20[0x20];
6793 };
6794
6795 struct mlx5_ifc_pqdr_reg_bits {
6796         u8         reserved_at_0[0x8];
6797         u8         local_port[0x8];
6798         u8         reserved_at_10[0x5];
6799         u8         prio[0x3];
6800         u8         reserved_at_18[0x6];
6801         u8         mode[0x2];
6802
6803         u8         reserved_at_20[0x20];
6804
6805         u8         reserved_at_40[0x10];
6806         u8         min_threshold[0x10];
6807
6808         u8         reserved_at_60[0x10];
6809         u8         max_threshold[0x10];
6810
6811         u8         reserved_at_80[0x10];
6812         u8         mark_probability_denominator[0x10];
6813
6814         u8         reserved_at_a0[0x60];
6815 };
6816
6817 struct mlx5_ifc_ppsc_reg_bits {
6818         u8         reserved_at_0[0x8];
6819         u8         local_port[0x8];
6820         u8         reserved_at_10[0x10];
6821
6822         u8         reserved_at_20[0x60];
6823
6824         u8         reserved_at_80[0x1c];
6825         u8         wrps_admin[0x4];
6826
6827         u8         reserved_at_a0[0x1c];
6828         u8         wrps_status[0x4];
6829
6830         u8         reserved_at_c0[0x8];
6831         u8         up_threshold[0x8];
6832         u8         reserved_at_d0[0x8];
6833         u8         down_threshold[0x8];
6834
6835         u8         reserved_at_e0[0x20];
6836
6837         u8         reserved_at_100[0x1c];
6838         u8         srps_admin[0x4];
6839
6840         u8         reserved_at_120[0x1c];
6841         u8         srps_status[0x4];
6842
6843         u8         reserved_at_140[0x40];
6844 };
6845
6846 struct mlx5_ifc_pplr_reg_bits {
6847         u8         reserved_at_0[0x8];
6848         u8         local_port[0x8];
6849         u8         reserved_at_10[0x10];
6850
6851         u8         reserved_at_20[0x8];
6852         u8         lb_cap[0x8];
6853         u8         reserved_at_30[0x8];
6854         u8         lb_en[0x8];
6855 };
6856
6857 struct mlx5_ifc_pplm_reg_bits {
6858         u8         reserved_at_0[0x8];
6859         u8         local_port[0x8];
6860         u8         reserved_at_10[0x10];
6861
6862         u8         reserved_at_20[0x20];
6863
6864         u8         port_profile_mode[0x8];
6865         u8         static_port_profile[0x8];
6866         u8         active_port_profile[0x8];
6867         u8         reserved_at_58[0x8];
6868
6869         u8         retransmission_active[0x8];
6870         u8         fec_mode_active[0x18];
6871
6872         u8         reserved_at_80[0x20];
6873 };
6874
6875 struct mlx5_ifc_ppcnt_reg_bits {
6876         u8         swid[0x8];
6877         u8         local_port[0x8];
6878         u8         pnat[0x2];
6879         u8         reserved_at_12[0x8];
6880         u8         grp[0x6];
6881
6882         u8         clr[0x1];
6883         u8         reserved_at_21[0x1c];
6884         u8         prio_tc[0x3];
6885
6886         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6887 };
6888
6889 struct mlx5_ifc_ppad_reg_bits {
6890         u8         reserved_at_0[0x3];
6891         u8         single_mac[0x1];
6892         u8         reserved_at_4[0x4];
6893         u8         local_port[0x8];
6894         u8         mac_47_32[0x10];
6895
6896         u8         mac_31_0[0x20];
6897
6898         u8         reserved_at_40[0x40];
6899 };
6900
6901 struct mlx5_ifc_pmtu_reg_bits {
6902         u8         reserved_at_0[0x8];
6903         u8         local_port[0x8];
6904         u8         reserved_at_10[0x10];
6905
6906         u8         max_mtu[0x10];
6907         u8         reserved_at_30[0x10];
6908
6909         u8         admin_mtu[0x10];
6910         u8         reserved_at_50[0x10];
6911
6912         u8         oper_mtu[0x10];
6913         u8         reserved_at_70[0x10];
6914 };
6915
6916 struct mlx5_ifc_pmpr_reg_bits {
6917         u8         reserved_at_0[0x8];
6918         u8         module[0x8];
6919         u8         reserved_at_10[0x10];
6920
6921         u8         reserved_at_20[0x18];
6922         u8         attenuation_5g[0x8];
6923
6924         u8         reserved_at_40[0x18];
6925         u8         attenuation_7g[0x8];
6926
6927         u8         reserved_at_60[0x18];
6928         u8         attenuation_12g[0x8];
6929 };
6930
6931 struct mlx5_ifc_pmpe_reg_bits {
6932         u8         reserved_at_0[0x8];
6933         u8         module[0x8];
6934         u8         reserved_at_10[0xc];
6935         u8         module_status[0x4];
6936
6937         u8         reserved_at_20[0x60];
6938 };
6939
6940 struct mlx5_ifc_pmpc_reg_bits {
6941         u8         module_state_updated[32][0x8];
6942 };
6943
6944 struct mlx5_ifc_pmlpn_reg_bits {
6945         u8         reserved_at_0[0x4];
6946         u8         mlpn_status[0x4];
6947         u8         local_port[0x8];
6948         u8         reserved_at_10[0x10];
6949
6950         u8         e[0x1];
6951         u8         reserved_at_21[0x1f];
6952 };
6953
6954 struct mlx5_ifc_pmlp_reg_bits {
6955         u8         rxtx[0x1];
6956         u8         reserved_at_1[0x7];
6957         u8         local_port[0x8];
6958         u8         reserved_at_10[0x8];
6959         u8         width[0x8];
6960
6961         u8         lane0_module_mapping[0x20];
6962
6963         u8         lane1_module_mapping[0x20];
6964
6965         u8         lane2_module_mapping[0x20];
6966
6967         u8         lane3_module_mapping[0x20];
6968
6969         u8         reserved_at_a0[0x160];
6970 };
6971
6972 struct mlx5_ifc_pmaos_reg_bits {
6973         u8         reserved_at_0[0x8];
6974         u8         module[0x8];
6975         u8         reserved_at_10[0x4];
6976         u8         admin_status[0x4];
6977         u8         reserved_at_18[0x4];
6978         u8         oper_status[0x4];
6979
6980         u8         ase[0x1];
6981         u8         ee[0x1];
6982         u8         reserved_at_22[0x1c];
6983         u8         e[0x2];
6984
6985         u8         reserved_at_40[0x40];
6986 };
6987
6988 struct mlx5_ifc_plpc_reg_bits {
6989         u8         reserved_at_0[0x4];
6990         u8         profile_id[0xc];
6991         u8         reserved_at_10[0x4];
6992         u8         proto_mask[0x4];
6993         u8         reserved_at_18[0x8];
6994
6995         u8         reserved_at_20[0x10];
6996         u8         lane_speed[0x10];
6997
6998         u8         reserved_at_40[0x17];
6999         u8         lpbf[0x1];
7000         u8         fec_mode_policy[0x8];
7001
7002         u8         retransmission_capability[0x8];
7003         u8         fec_mode_capability[0x18];
7004
7005         u8         retransmission_support_admin[0x8];
7006         u8         fec_mode_support_admin[0x18];
7007
7008         u8         retransmission_request_admin[0x8];
7009         u8         fec_mode_request_admin[0x18];
7010
7011         u8         reserved_at_c0[0x80];
7012 };
7013
7014 struct mlx5_ifc_plib_reg_bits {
7015         u8         reserved_at_0[0x8];
7016         u8         local_port[0x8];
7017         u8         reserved_at_10[0x8];
7018         u8         ib_port[0x8];
7019
7020         u8         reserved_at_20[0x60];
7021 };
7022
7023 struct mlx5_ifc_plbf_reg_bits {
7024         u8         reserved_at_0[0x8];
7025         u8         local_port[0x8];
7026         u8         reserved_at_10[0xd];
7027         u8         lbf_mode[0x3];
7028
7029         u8         reserved_at_20[0x20];
7030 };
7031
7032 struct mlx5_ifc_pipg_reg_bits {
7033         u8         reserved_at_0[0x8];
7034         u8         local_port[0x8];
7035         u8         reserved_at_10[0x10];
7036
7037         u8         dic[0x1];
7038         u8         reserved_at_21[0x19];
7039         u8         ipg[0x4];
7040         u8         reserved_at_3e[0x2];
7041 };
7042
7043 struct mlx5_ifc_pifr_reg_bits {
7044         u8         reserved_at_0[0x8];
7045         u8         local_port[0x8];
7046         u8         reserved_at_10[0x10];
7047
7048         u8         reserved_at_20[0xe0];
7049
7050         u8         port_filter[8][0x20];
7051
7052         u8         port_filter_update_en[8][0x20];
7053 };
7054
7055 struct mlx5_ifc_pfcc_reg_bits {
7056         u8         reserved_at_0[0x8];
7057         u8         local_port[0x8];
7058         u8         reserved_at_10[0x10];
7059
7060         u8         ppan[0x4];
7061         u8         reserved_at_24[0x4];
7062         u8         prio_mask_tx[0x8];
7063         u8         reserved_at_30[0x8];
7064         u8         prio_mask_rx[0x8];
7065
7066         u8         pptx[0x1];
7067         u8         aptx[0x1];
7068         u8         reserved_at_42[0x6];
7069         u8         pfctx[0x8];
7070         u8         reserved_at_50[0x10];
7071
7072         u8         pprx[0x1];
7073         u8         aprx[0x1];
7074         u8         reserved_at_62[0x6];
7075         u8         pfcrx[0x8];
7076         u8         reserved_at_70[0x10];
7077
7078         u8         reserved_at_80[0x80];
7079 };
7080
7081 struct mlx5_ifc_pelc_reg_bits {
7082         u8         op[0x4];
7083         u8         reserved_at_4[0x4];
7084         u8         local_port[0x8];
7085         u8         reserved_at_10[0x10];
7086
7087         u8         op_admin[0x8];
7088         u8         op_capability[0x8];
7089         u8         op_request[0x8];
7090         u8         op_active[0x8];
7091
7092         u8         admin[0x40];
7093
7094         u8         capability[0x40];
7095
7096         u8         request[0x40];
7097
7098         u8         active[0x40];
7099
7100         u8         reserved_at_140[0x80];
7101 };
7102
7103 struct mlx5_ifc_peir_reg_bits {
7104         u8         reserved_at_0[0x8];
7105         u8         local_port[0x8];
7106         u8         reserved_at_10[0x10];
7107
7108         u8         reserved_at_20[0xc];
7109         u8         error_count[0x4];
7110         u8         reserved_at_30[0x10];
7111
7112         u8         reserved_at_40[0xc];
7113         u8         lane[0x4];
7114         u8         reserved_at_50[0x8];
7115         u8         error_type[0x8];
7116 };
7117
7118 struct mlx5_ifc_pcap_reg_bits {
7119         u8         reserved_at_0[0x8];
7120         u8         local_port[0x8];
7121         u8         reserved_at_10[0x10];
7122
7123         u8         port_capability_mask[4][0x20];
7124 };
7125
7126 struct mlx5_ifc_paos_reg_bits {
7127         u8         swid[0x8];
7128         u8         local_port[0x8];
7129         u8         reserved_at_10[0x4];
7130         u8         admin_status[0x4];
7131         u8         reserved_at_18[0x4];
7132         u8         oper_status[0x4];
7133
7134         u8         ase[0x1];
7135         u8         ee[0x1];
7136         u8         reserved_at_22[0x1c];
7137         u8         e[0x2];
7138
7139         u8         reserved_at_40[0x40];
7140 };
7141
7142 struct mlx5_ifc_pamp_reg_bits {
7143         u8         reserved_at_0[0x8];
7144         u8         opamp_group[0x8];
7145         u8         reserved_at_10[0xc];
7146         u8         opamp_group_type[0x4];
7147
7148         u8         start_index[0x10];
7149         u8         reserved_at_30[0x4];
7150         u8         num_of_indices[0xc];
7151
7152         u8         index_data[18][0x10];
7153 };
7154
7155 struct mlx5_ifc_pcmr_reg_bits {
7156         u8         reserved_at_0[0x8];
7157         u8         local_port[0x8];
7158         u8         reserved_at_10[0x2e];
7159         u8         fcs_cap[0x1];
7160         u8         reserved_at_3f[0x1f];
7161         u8         fcs_chk[0x1];
7162         u8         reserved_at_5f[0x1];
7163 };
7164
7165 struct mlx5_ifc_lane_2_module_mapping_bits {
7166         u8         reserved_at_0[0x6];
7167         u8         rx_lane[0x2];
7168         u8         reserved_at_8[0x6];
7169         u8         tx_lane[0x2];
7170         u8         reserved_at_10[0x8];
7171         u8         module[0x8];
7172 };
7173
7174 struct mlx5_ifc_bufferx_reg_bits {
7175         u8         reserved_at_0[0x6];
7176         u8         lossy[0x1];
7177         u8         epsb[0x1];
7178         u8         reserved_at_8[0xc];
7179         u8         size[0xc];
7180
7181         u8         xoff_threshold[0x10];
7182         u8         xon_threshold[0x10];
7183 };
7184
7185 struct mlx5_ifc_set_node_in_bits {
7186         u8         node_description[64][0x8];
7187 };
7188
7189 struct mlx5_ifc_register_power_settings_bits {
7190         u8         reserved_at_0[0x18];
7191         u8         power_settings_level[0x8];
7192
7193         u8         reserved_at_20[0x60];
7194 };
7195
7196 struct mlx5_ifc_register_host_endianness_bits {
7197         u8         he[0x1];
7198         u8         reserved_at_1[0x1f];
7199
7200         u8         reserved_at_20[0x60];
7201 };
7202
7203 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7204         u8         reserved_at_0[0x20];
7205
7206         u8         mkey[0x20];
7207
7208         u8         addressh_63_32[0x20];
7209
7210         u8         addressl_31_0[0x20];
7211 };
7212
7213 struct mlx5_ifc_ud_adrs_vector_bits {
7214         u8         dc_key[0x40];
7215
7216         u8         ext[0x1];
7217         u8         reserved_at_41[0x7];
7218         u8         destination_qp_dct[0x18];
7219
7220         u8         static_rate[0x4];
7221         u8         sl_eth_prio[0x4];
7222         u8         fl[0x1];
7223         u8         mlid[0x7];
7224         u8         rlid_udp_sport[0x10];
7225
7226         u8         reserved_at_80[0x20];
7227
7228         u8         rmac_47_16[0x20];
7229
7230         u8         rmac_15_0[0x10];
7231         u8         tclass[0x8];
7232         u8         hop_limit[0x8];
7233
7234         u8         reserved_at_e0[0x1];
7235         u8         grh[0x1];
7236         u8         reserved_at_e2[0x2];
7237         u8         src_addr_index[0x8];
7238         u8         flow_label[0x14];
7239
7240         u8         rgid_rip[16][0x8];
7241 };
7242
7243 struct mlx5_ifc_pages_req_event_bits {
7244         u8         reserved_at_0[0x10];
7245         u8         function_id[0x10];
7246
7247         u8         num_pages[0x20];
7248
7249         u8         reserved_at_40[0xa0];
7250 };
7251
7252 struct mlx5_ifc_eqe_bits {
7253         u8         reserved_at_0[0x8];
7254         u8         event_type[0x8];
7255         u8         reserved_at_10[0x8];
7256         u8         event_sub_type[0x8];
7257
7258         u8         reserved_at_20[0xe0];
7259
7260         union mlx5_ifc_event_auto_bits event_data;
7261
7262         u8         reserved_at_1e0[0x10];
7263         u8         signature[0x8];
7264         u8         reserved_at_1f8[0x7];
7265         u8         owner[0x1];
7266 };
7267
7268 enum {
7269         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7270 };
7271
7272 struct mlx5_ifc_cmd_queue_entry_bits {
7273         u8         type[0x8];
7274         u8         reserved_at_8[0x18];
7275
7276         u8         input_length[0x20];
7277
7278         u8         input_mailbox_pointer_63_32[0x20];
7279
7280         u8         input_mailbox_pointer_31_9[0x17];
7281         u8         reserved_at_77[0x9];
7282
7283         u8         command_input_inline_data[16][0x8];
7284
7285         u8         command_output_inline_data[16][0x8];
7286
7287         u8         output_mailbox_pointer_63_32[0x20];
7288
7289         u8         output_mailbox_pointer_31_9[0x17];
7290         u8         reserved_at_1b7[0x9];
7291
7292         u8         output_length[0x20];
7293
7294         u8         token[0x8];
7295         u8         signature[0x8];
7296         u8         reserved_at_1f0[0x8];
7297         u8         status[0x7];
7298         u8         ownership[0x1];
7299 };
7300
7301 struct mlx5_ifc_cmd_out_bits {
7302         u8         status[0x8];
7303         u8         reserved_at_8[0x18];
7304
7305         u8         syndrome[0x20];
7306
7307         u8         command_output[0x20];
7308 };
7309
7310 struct mlx5_ifc_cmd_in_bits {
7311         u8         opcode[0x10];
7312         u8         reserved_at_10[0x10];
7313
7314         u8         reserved_at_20[0x10];
7315         u8         op_mod[0x10];
7316
7317         u8         command[0][0x20];
7318 };
7319
7320 struct mlx5_ifc_cmd_if_box_bits {
7321         u8         mailbox_data[512][0x8];
7322
7323         u8         reserved_at_1000[0x180];
7324
7325         u8         next_pointer_63_32[0x20];
7326
7327         u8         next_pointer_31_10[0x16];
7328         u8         reserved_at_11b6[0xa];
7329
7330         u8         block_number[0x20];
7331
7332         u8         reserved_at_11e0[0x8];
7333         u8         token[0x8];
7334         u8         ctrl_signature[0x8];
7335         u8         signature[0x8];
7336 };
7337
7338 struct mlx5_ifc_mtt_bits {
7339         u8         ptag_63_32[0x20];
7340
7341         u8         ptag_31_8[0x18];
7342         u8         reserved_at_38[0x6];
7343         u8         wr_en[0x1];
7344         u8         rd_en[0x1];
7345 };
7346
7347 struct mlx5_ifc_query_wol_rol_out_bits {
7348         u8         status[0x8];
7349         u8         reserved_at_8[0x18];
7350
7351         u8         syndrome[0x20];
7352
7353         u8         reserved_at_40[0x10];
7354         u8         rol_mode[0x8];
7355         u8         wol_mode[0x8];
7356
7357         u8         reserved_at_60[0x20];
7358 };
7359
7360 struct mlx5_ifc_query_wol_rol_in_bits {
7361         u8         opcode[0x10];
7362         u8         reserved_at_10[0x10];
7363
7364         u8         reserved_at_20[0x10];
7365         u8         op_mod[0x10];
7366
7367         u8         reserved_at_40[0x40];
7368 };
7369
7370 struct mlx5_ifc_set_wol_rol_out_bits {
7371         u8         status[0x8];
7372         u8         reserved_at_8[0x18];
7373
7374         u8         syndrome[0x20];
7375
7376         u8         reserved_at_40[0x40];
7377 };
7378
7379 struct mlx5_ifc_set_wol_rol_in_bits {
7380         u8         opcode[0x10];
7381         u8         reserved_at_10[0x10];
7382
7383         u8         reserved_at_20[0x10];
7384         u8         op_mod[0x10];
7385
7386         u8         rol_mode_valid[0x1];
7387         u8         wol_mode_valid[0x1];
7388         u8         reserved_at_42[0xe];
7389         u8         rol_mode[0x8];
7390         u8         wol_mode[0x8];
7391
7392         u8         reserved_at_60[0x20];
7393 };
7394
7395 enum {
7396         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7397         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7398         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7399 };
7400
7401 enum {
7402         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7403         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7404         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7405 };
7406
7407 enum {
7408         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7409         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7410         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7411         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7412         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7413         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7414         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7415         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7416         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7417         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7418         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7419 };
7420
7421 struct mlx5_ifc_initial_seg_bits {
7422         u8         fw_rev_minor[0x10];
7423         u8         fw_rev_major[0x10];
7424
7425         u8         cmd_interface_rev[0x10];
7426         u8         fw_rev_subminor[0x10];
7427
7428         u8         reserved_at_40[0x40];
7429
7430         u8         cmdq_phy_addr_63_32[0x20];
7431
7432         u8         cmdq_phy_addr_31_12[0x14];
7433         u8         reserved_at_b4[0x2];
7434         u8         nic_interface[0x2];
7435         u8         log_cmdq_size[0x4];
7436         u8         log_cmdq_stride[0x4];
7437
7438         u8         command_doorbell_vector[0x20];
7439
7440         u8         reserved_at_e0[0xf00];
7441
7442         u8         initializing[0x1];
7443         u8         reserved_at_fe1[0x4];
7444         u8         nic_interface_supported[0x3];
7445         u8         reserved_at_fe8[0x18];
7446
7447         struct mlx5_ifc_health_buffer_bits health_buffer;
7448
7449         u8         no_dram_nic_offset[0x20];
7450
7451         u8         reserved_at_1220[0x6e40];
7452
7453         u8         reserved_at_8060[0x1f];
7454         u8         clear_int[0x1];
7455
7456         u8         health_syndrome[0x8];
7457         u8         health_counter[0x18];
7458
7459         u8         reserved_at_80a0[0x17fc0];
7460 };
7461
7462 union mlx5_ifc_ports_control_registers_document_bits {
7463         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7464         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7465         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7466         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7467         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7468         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7469         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7470         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7471         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7472         struct mlx5_ifc_pamp_reg_bits pamp_reg;
7473         struct mlx5_ifc_paos_reg_bits paos_reg;
7474         struct mlx5_ifc_pcap_reg_bits pcap_reg;
7475         struct mlx5_ifc_peir_reg_bits peir_reg;
7476         struct mlx5_ifc_pelc_reg_bits pelc_reg;
7477         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7478         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7479         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7480         struct mlx5_ifc_pifr_reg_bits pifr_reg;
7481         struct mlx5_ifc_pipg_reg_bits pipg_reg;
7482         struct mlx5_ifc_plbf_reg_bits plbf_reg;
7483         struct mlx5_ifc_plib_reg_bits plib_reg;
7484         struct mlx5_ifc_plpc_reg_bits plpc_reg;
7485         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7486         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7487         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7488         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7489         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7490         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7491         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7492         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7493         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7494         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7495         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7496         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7497         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7498         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7499         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7500         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7501         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7502         struct mlx5_ifc_pude_reg_bits pude_reg;
7503         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7504         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7505         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7506         u8         reserved_at_0[0x60e0];
7507 };
7508
7509 union mlx5_ifc_debug_enhancements_document_bits {
7510         struct mlx5_ifc_health_buffer_bits health_buffer;
7511         u8         reserved_at_0[0x200];
7512 };
7513
7514 union mlx5_ifc_uplink_pci_interface_document_bits {
7515         struct mlx5_ifc_initial_seg_bits initial_seg;
7516         u8         reserved_at_0[0x20060];
7517 };
7518
7519 struct mlx5_ifc_set_flow_table_root_out_bits {
7520         u8         status[0x8];
7521         u8         reserved_at_8[0x18];
7522
7523         u8         syndrome[0x20];
7524
7525         u8         reserved_at_40[0x40];
7526 };
7527
7528 struct mlx5_ifc_set_flow_table_root_in_bits {
7529         u8         opcode[0x10];
7530         u8         reserved_at_10[0x10];
7531
7532         u8         reserved_at_20[0x10];
7533         u8         op_mod[0x10];
7534
7535         u8         other_vport[0x1];
7536         u8         reserved_at_41[0xf];
7537         u8         vport_number[0x10];
7538
7539         u8         reserved_at_60[0x20];
7540
7541         u8         table_type[0x8];
7542         u8         reserved_at_88[0x18];
7543
7544         u8         reserved_at_a0[0x8];
7545         u8         table_id[0x18];
7546
7547         u8         reserved_at_c0[0x140];
7548 };
7549
7550 enum {
7551         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7552 };
7553
7554 struct mlx5_ifc_modify_flow_table_out_bits {
7555         u8         status[0x8];
7556         u8         reserved_at_8[0x18];
7557
7558         u8         syndrome[0x20];
7559
7560         u8         reserved_at_40[0x40];
7561 };
7562
7563 struct mlx5_ifc_modify_flow_table_in_bits {
7564         u8         opcode[0x10];
7565         u8         reserved_at_10[0x10];
7566
7567         u8         reserved_at_20[0x10];
7568         u8         op_mod[0x10];
7569
7570         u8         other_vport[0x1];
7571         u8         reserved_at_41[0xf];
7572         u8         vport_number[0x10];
7573
7574         u8         reserved_at_60[0x10];
7575         u8         modify_field_select[0x10];
7576
7577         u8         table_type[0x8];
7578         u8         reserved_at_88[0x18];
7579
7580         u8         reserved_at_a0[0x8];
7581         u8         table_id[0x18];
7582
7583         u8         reserved_at_c0[0x4];
7584         u8         table_miss_mode[0x4];
7585         u8         reserved_at_c8[0x18];
7586
7587         u8         reserved_at_e0[0x8];
7588         u8         table_miss_id[0x18];
7589
7590         u8         reserved_at_100[0x100];
7591 };
7592
7593 struct mlx5_ifc_ets_tcn_config_reg_bits {
7594         u8         g[0x1];
7595         u8         b[0x1];
7596         u8         r[0x1];
7597         u8         reserved_at_3[0x9];
7598         u8         group[0x4];
7599         u8         reserved_at_10[0x9];
7600         u8         bw_allocation[0x7];
7601
7602         u8         reserved_at_20[0xc];
7603         u8         max_bw_units[0x4];
7604         u8         reserved_at_30[0x8];
7605         u8         max_bw_value[0x8];
7606 };
7607
7608 struct mlx5_ifc_ets_global_config_reg_bits {
7609         u8         reserved_at_0[0x2];
7610         u8         r[0x1];
7611         u8         reserved_at_3[0x1d];
7612
7613         u8         reserved_at_20[0xc];
7614         u8         max_bw_units[0x4];
7615         u8         reserved_at_30[0x8];
7616         u8         max_bw_value[0x8];
7617 };
7618
7619 struct mlx5_ifc_qetc_reg_bits {
7620         u8                                         reserved_at_0[0x8];
7621         u8                                         port_number[0x8];
7622         u8                                         reserved_at_10[0x30];
7623
7624         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
7625         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7626 };
7627
7628 struct mlx5_ifc_qtct_reg_bits {
7629         u8         reserved_at_0[0x8];
7630         u8         port_number[0x8];
7631         u8         reserved_at_10[0xd];
7632         u8         prio[0x3];
7633
7634         u8         reserved_at_20[0x1d];
7635         u8         tclass[0x3];
7636 };
7637
7638 struct mlx5_ifc_mcia_reg_bits {
7639         u8         l[0x1];
7640         u8         reserved_at_1[0x7];
7641         u8         module[0x8];
7642         u8         reserved_at_10[0x8];
7643         u8         status[0x8];
7644
7645         u8         i2c_device_address[0x8];
7646         u8         page_number[0x8];
7647         u8         device_address[0x10];
7648
7649         u8         reserved_at_40[0x10];
7650         u8         size[0x10];
7651
7652         u8         reserved_at_60[0x20];
7653
7654         u8         dword_0[0x20];
7655         u8         dword_1[0x20];
7656         u8         dword_2[0x20];
7657         u8         dword_3[0x20];
7658         u8         dword_4[0x20];
7659         u8         dword_5[0x20];
7660         u8         dword_6[0x20];
7661         u8         dword_7[0x20];
7662         u8         dword_8[0x20];
7663         u8         dword_9[0x20];
7664         u8         dword_10[0x20];
7665         u8         dword_11[0x20];
7666 };
7667
7668 struct mlx5_ifc_dcbx_param_bits {
7669         u8         dcbx_cee_cap[0x1];
7670         u8         dcbx_ieee_cap[0x1];
7671         u8         dcbx_standby_cap[0x1];
7672         u8         reserved_at_0[0x5];
7673         u8         port_number[0x8];
7674         u8         reserved_at_10[0xa];
7675         u8         max_application_table_size[6];
7676         u8         reserved_at_20[0x15];
7677         u8         version_oper[0x3];
7678         u8         reserved_at_38[5];
7679         u8         version_admin[0x3];
7680         u8         willing_admin[0x1];
7681         u8         reserved_at_41[0x3];
7682         u8         pfc_cap_oper[0x4];
7683         u8         reserved_at_48[0x4];
7684         u8         pfc_cap_admin[0x4];
7685         u8         reserved_at_50[0x4];
7686         u8         num_of_tc_oper[0x4];
7687         u8         reserved_at_58[0x4];
7688         u8         num_of_tc_admin[0x4];
7689         u8         remote_willing[0x1];
7690         u8         reserved_at_61[3];
7691         u8         remote_pfc_cap[4];
7692         u8         reserved_at_68[0x14];
7693         u8         remote_num_of_tc[0x4];
7694         u8         reserved_at_80[0x18];
7695         u8         error[0x8];
7696         u8         reserved_at_a0[0x160];
7697 };
7698 #endif /* MLX5_IFC_H */