include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  87         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  88         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  89         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  90         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  91         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  92         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  93         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  94         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  95         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  96         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  97         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  98         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  99         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 100         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 101         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 102         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 103         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 104         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 105         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 106         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 107         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 108         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 109         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 110         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 111         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 112         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 113         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 114         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 115         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 116         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 117         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 118         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 119         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 120         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 121         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 122         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 123         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 124         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 125         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 126         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 127         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 128         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 129         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 130         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 131         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 132         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 133         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 134         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 135         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 136         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 137         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 138         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 139         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 140         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 141         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 142         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 143         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 144         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 145         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 146         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 147         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 148         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 149         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 150         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 151         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 152         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 153         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 154         MLX5_CMD_OP_NOP                           = 0x80d,
 155         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 156         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 157         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 158         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 159         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 160         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 161         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 162         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 163         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 164         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 165         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 166         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 167         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 168         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 169         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 170         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 171         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 172         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 173         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 174         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 175         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 176         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 177         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 178         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 179         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 180         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 181         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 182         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 183         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 184         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 185         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 186         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 187         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 188         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 189         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 190         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 191         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 192         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 193         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 194         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 195         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 196         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 197         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 198         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 199         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 200         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 201         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 202         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 203         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 204         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 205         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c
 206 };
 207
 208 struct mlx5_ifc_flow_table_fields_supported_bits {
 209         u8         outer_dmac[0x1];
 210         u8         outer_smac[0x1];
 211         u8         outer_ether_type[0x1];
 212         u8         reserved_at_3[0x1];
 213         u8         outer_first_prio[0x1];
 214         u8         outer_first_cfi[0x1];
 215         u8         outer_first_vid[0x1];
 216         u8         reserved_at_7[0x1];
 217         u8         outer_second_prio[0x1];
 218         u8         outer_second_cfi[0x1];
 219         u8         outer_second_vid[0x1];
 220         u8         reserved_at_b[0x1];
 221         u8         outer_sip[0x1];
 222         u8         outer_dip[0x1];
 223         u8         outer_frag[0x1];
 224         u8         outer_ip_protocol[0x1];
 225         u8         outer_ip_ecn[0x1];
 226         u8         outer_ip_dscp[0x1];
 227         u8         outer_udp_sport[0x1];
 228         u8         outer_udp_dport[0x1];
 229         u8         outer_tcp_sport[0x1];
 230         u8         outer_tcp_dport[0x1];
 231         u8         outer_tcp_flags[0x1];
 232         u8         outer_gre_protocol[0x1];
 233         u8         outer_gre_key[0x1];
 234         u8         outer_vxlan_vni[0x1];
 235         u8         reserved_at_1a[0x5];
 236         u8         source_eswitch_port[0x1];
 237
 238         u8         inner_dmac[0x1];
 239         u8         inner_smac[0x1];
 240         u8         inner_ether_type[0x1];
 241         u8         reserved_at_23[0x1];
 242         u8         inner_first_prio[0x1];
 243         u8         inner_first_cfi[0x1];
 244         u8         inner_first_vid[0x1];
 245         u8         reserved_at_27[0x1];
 246         u8         inner_second_prio[0x1];
 247         u8         inner_second_cfi[0x1];
 248         u8         inner_second_vid[0x1];
 249         u8         reserved_at_2b[0x1];
 250         u8         inner_sip[0x1];
 251         u8         inner_dip[0x1];
 252         u8         inner_frag[0x1];
 253         u8         inner_ip_protocol[0x1];
 254         u8         inner_ip_ecn[0x1];
 255         u8         inner_ip_dscp[0x1];
 256         u8         inner_udp_sport[0x1];
 257         u8         inner_udp_dport[0x1];
 258         u8         inner_tcp_sport[0x1];
 259         u8         inner_tcp_dport[0x1];
 260         u8         inner_tcp_flags[0x1];
 261         u8         reserved_at_37[0x9];
 262
 263         u8         reserved_at_40[0x40];
 264 };
 265
 266 struct mlx5_ifc_flow_table_prop_layout_bits {
 267         u8         ft_support[0x1];
 268         u8         reserved_at_1[0x2];
 269         u8         flow_modify_en[0x1];
 270         u8         modify_root[0x1];
 271         u8         identified_miss_table_mode[0x1];
 272         u8         flow_table_modify[0x1];
 273         u8         reserved_at_7[0x19];
 274
 275         u8         reserved_at_20[0x2];
 276         u8         log_max_ft_size[0x6];
 277         u8         reserved_at_28[0x10];
 278         u8         max_ft_level[0x8];
 279
 280         u8         reserved_at_40[0x20];
 281
 282         u8         reserved_at_60[0x18];
 283         u8         log_max_ft_num[0x8];
 284
 285         u8         reserved_at_80[0x18];
 286         u8         log_max_destination[0x8];
 287
 288         u8         reserved_at_a0[0x18];
 289         u8         log_max_flow[0x8];
 290
 291         u8         reserved_at_c0[0x40];
 292
 293         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 294
 295         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 296 };
 297
 298 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 299         u8         send[0x1];
 300         u8         receive[0x1];
 301         u8         write[0x1];
 302         u8         read[0x1];
 303         u8         reserved_at_4[0x1];
 304         u8         srq_receive[0x1];
 305         u8         reserved_at_6[0x1a];
 306 };
 307
 308 struct mlx5_ifc_ipv4_layout_bits {
 309         u8         reserved_at_0[0x60];
 310
 311         u8         ipv4[0x20];
 312 };
 313
 314 struct mlx5_ifc_ipv6_layout_bits {
 315         u8         ipv6[16][0x8];
 316 };
 317
 318 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 319         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 320         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 321         u8         reserved_at_0[0x80];
 322 };
 323
 324 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 325         u8         smac_47_16[0x20];
 326
 327         u8         smac_15_0[0x10];
 328         u8         ethertype[0x10];
 329
 330         u8         dmac_47_16[0x20];
 331
 332         u8         dmac_15_0[0x10];
 333         u8         first_prio[0x3];
 334         u8         first_cfi[0x1];
 335         u8         first_vid[0xc];
 336
 337         u8         ip_protocol[0x8];
 338         u8         ip_dscp[0x6];
 339         u8         ip_ecn[0x2];
 340         u8         vlan_tag[0x1];
 341         u8         reserved_at_91[0x1];
 342         u8         frag[0x1];
 343         u8         reserved_at_93[0x4];
 344         u8         tcp_flags[0x9];
 345
 346         u8         tcp_sport[0x10];
 347         u8         tcp_dport[0x10];
 348
 349         u8         reserved_at_c0[0x20];
 350
 351         u8         udp_sport[0x10];
 352         u8         udp_dport[0x10];
 353
 354         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 355
 356         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 357 };
 358
 359 struct mlx5_ifc_fte_match_set_misc_bits {
 360         u8         reserved_at_0[0x20];
 361
 362         u8         reserved_at_20[0x10];
 363         u8         source_port[0x10];
 364
 365         u8         outer_second_prio[0x3];
 366         u8         outer_second_cfi[0x1];
 367         u8         outer_second_vid[0xc];
 368         u8         inner_second_prio[0x3];
 369         u8         inner_second_cfi[0x1];
 370         u8         inner_second_vid[0xc];
 371
 372         u8         outer_second_vlan_tag[0x1];
 373         u8         inner_second_vlan_tag[0x1];
 374         u8         reserved_at_62[0xe];
 375         u8         gre_protocol[0x10];
 376
 377         u8         gre_key_h[0x18];
 378         u8         gre_key_l[0x8];
 379
 380         u8         vxlan_vni[0x18];
 381         u8         reserved_at_b8[0x8];
 382
 383         u8         reserved_at_c0[0x20];
 384
 385         u8         reserved_at_e0[0xc];
 386         u8         outer_ipv6_flow_label[0x14];
 387
 388         u8         reserved_at_100[0xc];
 389         u8         inner_ipv6_flow_label[0x14];
 390
 391         u8         reserved_at_120[0xe0];
 392 };
 393
 394 struct mlx5_ifc_cmd_pas_bits {
 395         u8         pa_h[0x20];
 396
 397         u8         pa_l[0x14];
 398         u8         reserved_at_34[0xc];
 399 };
 400
 401 struct mlx5_ifc_uint64_bits {
 402         u8         hi[0x20];
 403
 404         u8         lo[0x20];
 405 };
 406
 407 enum {
 408         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 409         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 410         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 411         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 412         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 413         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 414         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 415         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 416         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 417         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 418 };
 419
 420 struct mlx5_ifc_ads_bits {
 421         u8         fl[0x1];
 422         u8         free_ar[0x1];
 423         u8         reserved_at_2[0xe];
 424         u8         pkey_index[0x10];
 425
 426         u8         reserved_at_20[0x8];
 427         u8         grh[0x1];
 428         u8         mlid[0x7];
 429         u8         rlid[0x10];
 430
 431         u8         ack_timeout[0x5];
 432         u8         reserved_at_45[0x3];
 433         u8         src_addr_index[0x8];
 434         u8         reserved_at_50[0x4];
 435         u8         stat_rate[0x4];
 436         u8         hop_limit[0x8];
 437
 438         u8         reserved_at_60[0x4];
 439         u8         tclass[0x8];
 440         u8         flow_label[0x14];
 441
 442         u8         rgid_rip[16][0x8];
 443
 444         u8         reserved_at_100[0x4];
 445         u8         f_dscp[0x1];
 446         u8         f_ecn[0x1];
 447         u8         reserved_at_106[0x1];
 448         u8         f_eth_prio[0x1];
 449         u8         ecn[0x2];
 450         u8         dscp[0x6];
 451         u8         udp_sport[0x10];
 452
 453         u8         dei_cfi[0x1];
 454         u8         eth_prio[0x3];
 455         u8         sl[0x4];
 456         u8         port[0x8];
 457         u8         rmac_47_32[0x10];
 458
 459         u8         rmac_31_0[0x20];
 460 };
 461
 462 struct mlx5_ifc_flow_table_nic_cap_bits {
 463         u8         nic_rx_multi_path_tirs[0x1];
 464         u8         reserved_at_1[0x1ff];
 465
 466         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 467
 468         u8         reserved_at_400[0x200];
 469
 470         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 471
 472         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 473
 474         u8         reserved_at_a00[0x200];
 475
 476         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 477
 478         u8         reserved_at_e00[0x7200];
 479 };
 480
 481 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 482         u8     reserved_at_0[0x200];
 483
 484         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 485
 486         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 487
 488         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 489
 490         u8      reserved_at_800[0x7800];
 491 };
 492
 493 struct mlx5_ifc_e_switch_cap_bits {
 494         u8         vport_svlan_strip[0x1];
 495         u8         vport_cvlan_strip[0x1];
 496         u8         vport_svlan_insert[0x1];
 497         u8         vport_cvlan_insert_if_not_exist[0x1];
 498         u8         vport_cvlan_insert_overwrite[0x1];
 499         u8         reserved_at_5[0x1b];
 500
 501         u8         reserved_at_20[0x7e0];
 502 };
 503
 504 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 505         u8         csum_cap[0x1];
 506         u8         vlan_cap[0x1];
 507         u8         lro_cap[0x1];
 508         u8         lro_psh_flag[0x1];
 509         u8         lro_time_stamp[0x1];
 510         u8         reserved_at_5[0x3];
 511         u8         self_lb_en_modifiable[0x1];
 512         u8         reserved_at_9[0x2];
 513         u8         max_lso_cap[0x5];
 514         u8         reserved_at_10[0x4];
 515         u8         rss_ind_tbl_cap[0x4];
 516         u8         reserved_at_18[0x3];
 517         u8         tunnel_lso_const_out_ip_id[0x1];
 518         u8         reserved_at_1c[0x2];
 519         u8         tunnel_statless_gre[0x1];
 520         u8         tunnel_stateless_vxlan[0x1];
 521
 522         u8         reserved_at_20[0x20];
 523
 524         u8         reserved_at_40[0x10];
 525         u8         lro_min_mss_size[0x10];
 526
 527         u8         reserved_at_60[0x120];
 528
 529         u8         lro_timer_supported_periods[4][0x20];
 530
 531         u8         reserved_at_200[0x600];
 532 };
 533
 534 struct mlx5_ifc_roce_cap_bits {
 535         u8         roce_apm[0x1];
 536         u8         reserved_at_1[0x1f];
 537
 538         u8         reserved_at_20[0x60];
 539
 540         u8         reserved_at_80[0xc];
 541         u8         l3_type[0x4];
 542         u8         reserved_at_90[0x8];
 543         u8         roce_version[0x8];
 544
 545         u8         reserved_at_a0[0x10];
 546         u8         r_roce_dest_udp_port[0x10];
 547
 548         u8         r_roce_max_src_udp_port[0x10];
 549         u8         r_roce_min_src_udp_port[0x10];
 550
 551         u8         reserved_at_e0[0x10];
 552         u8         roce_address_table_size[0x10];
 553
 554         u8         reserved_at_100[0x700];
 555 };
 556
 557 enum {
 558         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 559         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 560         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 561         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 562         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 563         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 564         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 565         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 566         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 567 };
 568
 569 enum {
 570         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 571         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 572         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 573         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 574         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 575         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 576         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 577         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 578         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 579 };
 580
 581 struct mlx5_ifc_atomic_caps_bits {
 582         u8         reserved_at_0[0x40];
 583
 584         u8         atomic_req_8B_endianess_mode[0x2];
 585         u8         reserved_at_42[0x4];
 586         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 587
 588         u8         reserved_at_47[0x19];
 589
 590         u8         reserved_at_60[0x20];
 591
 592         u8         reserved_at_80[0x10];
 593         u8         atomic_operations[0x10];
 594
 595         u8         reserved_at_a0[0x10];
 596         u8         atomic_size_qp[0x10];
 597
 598         u8         reserved_at_c0[0x10];
 599         u8         atomic_size_dc[0x10];
 600
 601         u8         reserved_at_e0[0x720];
 602 };
 603
 604 struct mlx5_ifc_odp_cap_bits {
 605         u8         reserved_at_0[0x40];
 606
 607         u8         sig[0x1];
 608         u8         reserved_at_41[0x1f];
 609
 610         u8         reserved_at_60[0x20];
 611
 612         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 613
 614         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 615
 616         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 617
 618         u8         reserved_at_e0[0x720];
 619 };
 620
 621 enum {
 622         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 623         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 624         MLX5_WQ_TYPE_STRQ         = 0x2,
 625 };
 626
 627 enum {
 628         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 629         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 630 };
 631
 632 enum {
 633         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 634         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 635         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 636         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 637         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 638 };
 639
 640 enum {
 641         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 642         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 643         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 644         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 645         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 646         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 647 };
 648
 649 enum {
 650         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 651         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 652 };
 653
 654 enum {
 655         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 656         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 657         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 658 };
 659
 660 enum {
 661         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 662         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 663 };
 664
 665 struct mlx5_ifc_cmd_hca_cap_bits {
 666         u8         reserved_at_0[0x80];
 667
 668         u8         log_max_srq_sz[0x8];
 669         u8         log_max_qp_sz[0x8];
 670         u8         reserved_at_90[0xb];
 671         u8         log_max_qp[0x5];
 672
 673         u8         reserved_at_a0[0xb];
 674         u8         log_max_srq[0x5];
 675         u8         reserved_at_b0[0x10];
 676
 677         u8         reserved_at_c0[0x8];
 678         u8         log_max_cq_sz[0x8];
 679         u8         reserved_at_d0[0xb];
 680         u8         log_max_cq[0x5];
 681
 682         u8         log_max_eq_sz[0x8];
 683         u8         reserved_at_e8[0x2];
 684         u8         log_max_mkey[0x6];
 685         u8         reserved_at_f0[0xc];
 686         u8         log_max_eq[0x4];
 687
 688         u8         max_indirection[0x8];
 689         u8         reserved_at_108[0x1];
 690         u8         log_max_mrw_sz[0x7];
 691         u8         reserved_at_110[0x2];
 692         u8         log_max_bsf_list_size[0x6];
 693         u8         reserved_at_118[0x2];
 694         u8         log_max_klm_list_size[0x6];
 695
 696         u8         reserved_at_120[0xa];
 697         u8         log_max_ra_req_dc[0x6];
 698         u8         reserved_at_130[0xa];
 699         u8         log_max_ra_res_dc[0x6];
 700
 701         u8         reserved_at_140[0xa];
 702         u8         log_max_ra_req_qp[0x6];
 703         u8         reserved_at_150[0xa];
 704         u8         log_max_ra_res_qp[0x6];
 705
 706         u8         pad_cap[0x1];
 707         u8         cc_query_allowed[0x1];
 708         u8         cc_modify_allowed[0x1];
 709         u8         reserved_at_163[0xd];
 710         u8         gid_table_size[0x10];
 711
 712         u8         out_of_seq_cnt[0x1];
 713         u8         vport_counters[0x1];
 714         u8         reserved_at_182[0x4];
 715         u8         max_qp_cnt[0xa];
 716         u8         pkey_table_size[0x10];
 717
 718         u8         vport_group_manager[0x1];
 719         u8         vhca_group_manager[0x1];
 720         u8         ib_virt[0x1];
 721         u8         eth_virt[0x1];
 722         u8         reserved_at_1a4[0x1];
 723         u8         ets[0x1];
 724         u8         nic_flow_table[0x1];
 725         u8         eswitch_flow_table[0x1];
 726         u8         early_vf_enable;
 727         u8         reserved_at_1a8[0x2];
 728         u8         local_ca_ack_delay[0x5];
 729         u8         reserved_at_1af[0x6];
 730         u8         port_type[0x2];
 731         u8         num_ports[0x8];
 732
 733         u8         reserved_at_1bf[0x3];
 734         u8         log_max_msg[0x5];
 735         u8         reserved_at_1c7[0x4];
 736         u8         max_tc[0x4];
 737         u8         reserved_at_1cf[0x6];
 738         u8         rol_s[0x1];
 739         u8         rol_g[0x1];
 740         u8         reserved_at_1d7[0x1];
 741         u8         wol_s[0x1];
 742         u8         wol_g[0x1];
 743         u8         wol_a[0x1];
 744         u8         wol_b[0x1];
 745         u8         wol_m[0x1];
 746         u8         wol_u[0x1];
 747         u8         wol_p[0x1];
 748
 749         u8         stat_rate_support[0x10];
 750         u8         reserved_at_1ef[0xc];
 751         u8         cqe_version[0x4];
 752
 753         u8         compact_address_vector[0x1];
 754         u8         reserved_at_200[0x3];
 755         u8         ipoib_basic_offloads[0x1];
 756         u8         reserved_at_204[0xa];
 757         u8         drain_sigerr[0x1];
 758         u8         cmdif_checksum[0x2];
 759         u8         sigerr_cqe[0x1];
 760         u8         reserved_at_212[0x1];
 761         u8         wq_signature[0x1];
 762         u8         sctr_data_cqe[0x1];
 763         u8         reserved_at_215[0x1];
 764         u8         sho[0x1];
 765         u8         tph[0x1];
 766         u8         rf[0x1];
 767         u8         dct[0x1];
 768         u8         reserved_at_21a[0x1];
 769         u8         eth_net_offloads[0x1];
 770         u8         roce[0x1];
 771         u8         atomic[0x1];
 772         u8         reserved_at_21e[0x1];
 773
 774         u8         cq_oi[0x1];
 775         u8         cq_resize[0x1];
 776         u8         cq_moderation[0x1];
 777         u8         reserved_at_222[0x3];
 778         u8         cq_eq_remap[0x1];
 779         u8         pg[0x1];
 780         u8         block_lb_mc[0x1];
 781         u8         reserved_at_228[0x1];
 782         u8         scqe_break_moderation[0x1];
 783         u8         reserved_at_22a[0x1];
 784         u8         cd[0x1];
 785         u8         reserved_at_22c[0x1];
 786         u8         apm[0x1];
 787         u8         reserved_at_22e[0x2];
 788         u8         imaicl[0x1];
 789         u8         reserved_at_231[0x4];
 790         u8         qkv[0x1];
 791         u8         pkv[0x1];
 792         u8         set_deth_sqpn[0x1];
 793         u8         reserved_at_239[0x3];
 794         u8         xrc[0x1];
 795         u8         ud[0x1];
 796         u8         uc[0x1];
 797         u8         rc[0x1];
 798
 799         u8         reserved_at_23f[0xa];
 800         u8         uar_sz[0x6];
 801         u8         reserved_at_24f[0x8];
 802         u8         log_pg_sz[0x8];
 803
 804         u8         bf[0x1];
 805         u8         reserved_at_260[0x1];
 806         u8         pad_tx_eth_packet[0x1];
 807         u8         reserved_at_262[0x8];
 808         u8         log_bf_reg_size[0x5];
 809         u8         reserved_at_26f[0x10];
 810
 811         u8         reserved_at_27f[0x10];
 812         u8         max_wqe_sz_sq[0x10];
 813
 814         u8         reserved_at_29f[0x10];
 815         u8         max_wqe_sz_rq[0x10];
 816
 817         u8         reserved_at_2bf[0x10];
 818         u8         max_wqe_sz_sq_dc[0x10];
 819
 820         u8         reserved_at_2df[0x7];
 821         u8         max_qp_mcg[0x19];
 822
 823         u8         reserved_at_2ff[0x18];
 824         u8         log_max_mcg[0x8];
 825
 826         u8         reserved_at_31f[0x3];
 827         u8         log_max_transport_domain[0x5];
 828         u8         reserved_at_327[0x3];
 829         u8         log_max_pd[0x5];
 830         u8         reserved_at_32f[0xb];
 831         u8         log_max_xrcd[0x5];
 832
 833         u8         reserved_at_33f[0x20];
 834
 835         u8         reserved_at_35f[0x3];
 836         u8         log_max_rq[0x5];
 837         u8         reserved_at_367[0x3];
 838         u8         log_max_sq[0x5];
 839         u8         reserved_at_36f[0x3];
 840         u8         log_max_tir[0x5];
 841         u8         reserved_at_377[0x3];
 842         u8         log_max_tis[0x5];
 843
 844         u8         basic_cyclic_rcv_wqe[0x1];
 845         u8         reserved_at_380[0x2];
 846         u8         log_max_rmp[0x5];
 847         u8         reserved_at_387[0x3];
 848         u8         log_max_rqt[0x5];
 849         u8         reserved_at_38f[0x3];
 850         u8         log_max_rqt_size[0x5];
 851         u8         reserved_at_397[0x3];
 852         u8         log_max_tis_per_sq[0x5];
 853
 854         u8         reserved_at_39f[0x3];
 855         u8         log_max_stride_sz_rq[0x5];
 856         u8         reserved_at_3a7[0x3];
 857         u8         log_min_stride_sz_rq[0x5];
 858         u8         reserved_at_3af[0x3];
 859         u8         log_max_stride_sz_sq[0x5];
 860         u8         reserved_at_3b7[0x3];
 861         u8         log_min_stride_sz_sq[0x5];
 862
 863         u8         reserved_at_3bf[0x1b];
 864         u8         log_max_wq_sz[0x5];
 865
 866         u8         nic_vport_change_event[0x1];
 867         u8         reserved_at_3e0[0xa];
 868         u8         log_max_vlan_list[0x5];
 869         u8         reserved_at_3ef[0x3];
 870         u8         log_max_current_mc_list[0x5];
 871         u8         reserved_at_3f7[0x3];
 872         u8         log_max_current_uc_list[0x5];
 873
 874         u8         reserved_at_3ff[0x80];
 875
 876         u8         reserved_at_47f[0x3];
 877         u8         log_max_l2_table[0x5];
 878         u8         reserved_at_487[0x8];
 879         u8         log_uar_page_sz[0x10];
 880
 881         u8         reserved_at_49f[0x20];
 882         u8         device_frequency_mhz[0x20];
 883         u8         device_frequency_khz[0x20];
 884         u8         reserved_at_4ff[0x5f];
 885         u8         cqe_zip[0x1];
 886
 887         u8         cqe_zip_timeout[0x10];
 888         u8         cqe_zip_max_num[0x10];
 889
 890         u8         reserved_at_57f[0x220];
 891 };
 892
 893 enum mlx5_flow_destination_type {
 894         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 895         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 896         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 897 };
 898
 899 struct mlx5_ifc_dest_format_struct_bits {
 900         u8         destination_type[0x8];
 901         u8         destination_id[0x18];
 902
 903         u8         reserved_at_20[0x20];
 904 };
 905
 906 struct mlx5_ifc_fte_match_param_bits {
 907         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 908
 909         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 910
 911         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 912
 913         u8         reserved_at_600[0xa00];
 914 };
 915
 916 enum {
 917         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 918         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 919         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 920         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 921         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 922 };
 923
 924 struct mlx5_ifc_rx_hash_field_select_bits {
 925         u8         l3_prot_type[0x1];
 926         u8         l4_prot_type[0x1];
 927         u8         selected_fields[0x1e];
 928 };
 929
 930 enum {
 931         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
 932         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
 933 };
 934
 935 enum {
 936         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
 937         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
 938 };
 939
 940 struct mlx5_ifc_wq_bits {
 941         u8         wq_type[0x4];
 942         u8         wq_signature[0x1];
 943         u8         end_padding_mode[0x2];
 944         u8         cd_slave[0x1];
 945         u8         reserved_at_8[0x18];
 946
 947         u8         hds_skip_first_sge[0x1];
 948         u8         log2_hds_buf_size[0x3];
 949         u8         reserved_at_24[0x7];
 950         u8         page_offset[0x5];
 951         u8         lwm[0x10];
 952
 953         u8         reserved_at_40[0x8];
 954         u8         pd[0x18];
 955
 956         u8         reserved_at_60[0x8];
 957         u8         uar_page[0x18];
 958
 959         u8         dbr_addr[0x40];
 960
 961         u8         hw_counter[0x20];
 962
 963         u8         sw_counter[0x20];
 964
 965         u8         reserved_at_100[0xc];
 966         u8         log_wq_stride[0x4];
 967         u8         reserved_at_110[0x3];
 968         u8         log_wq_pg_sz[0x5];
 969         u8         reserved_at_118[0x3];
 970         u8         log_wq_sz[0x5];
 971
 972         u8         reserved_at_120[0x4e0];
 973
 974         struct mlx5_ifc_cmd_pas_bits pas[0];
 975 };
 976
 977 struct mlx5_ifc_rq_num_bits {
 978         u8         reserved_at_0[0x8];
 979         u8         rq_num[0x18];
 980 };
 981
 982 struct mlx5_ifc_mac_address_layout_bits {
 983         u8         reserved_at_0[0x10];
 984         u8         mac_addr_47_32[0x10];
 985
 986         u8         mac_addr_31_0[0x20];
 987 };
 988
 989 struct mlx5_ifc_vlan_layout_bits {
 990         u8         reserved_at_0[0x14];
 991         u8         vlan[0x0c];
 992
 993         u8         reserved_at_20[0x20];
 994 };
 995
 996 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
 997         u8         reserved_at_0[0xa0];
 998
 999         u8         min_time_between_cnps[0x20];
1000
1001         u8         reserved_at_c0[0x12];
1002         u8         cnp_dscp[0x6];
1003         u8         reserved_at_d8[0x5];
1004         u8         cnp_802p_prio[0x3];
1005
1006         u8         reserved_at_e0[0x720];
1007 };
1008
1009 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1010         u8         reserved_at_0[0x60];
1011
1012         u8         reserved_at_60[0x4];
1013         u8         clamp_tgt_rate[0x1];
1014         u8         reserved_at_65[0x3];
1015         u8         clamp_tgt_rate_after_time_inc[0x1];
1016         u8         reserved_at_69[0x17];
1017
1018         u8         reserved_at_80[0x20];
1019
1020         u8         rpg_time_reset[0x20];
1021
1022         u8         rpg_byte_reset[0x20];
1023
1024         u8         rpg_threshold[0x20];
1025
1026         u8         rpg_max_rate[0x20];
1027
1028         u8         rpg_ai_rate[0x20];
1029
1030         u8         rpg_hai_rate[0x20];
1031
1032         u8         rpg_gd[0x20];
1033
1034         u8         rpg_min_dec_fac[0x20];
1035
1036         u8         rpg_min_rate[0x20];
1037
1038         u8         reserved_at_1c0[0xe0];
1039
1040         u8         rate_to_set_on_first_cnp[0x20];
1041
1042         u8         dce_tcp_g[0x20];
1043
1044         u8         dce_tcp_rtt[0x20];
1045
1046         u8         rate_reduce_monitor_period[0x20];
1047
1048         u8         reserved_at_320[0x20];
1049
1050         u8         initial_alpha_value[0x20];
1051
1052         u8         reserved_at_360[0x4a0];
1053 };
1054
1055 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1056         u8         reserved_at_0[0x80];
1057
1058         u8         rppp_max_rps[0x20];
1059
1060         u8         rpg_time_reset[0x20];
1061
1062         u8         rpg_byte_reset[0x20];
1063
1064         u8         rpg_threshold[0x20];
1065
1066         u8         rpg_max_rate[0x20];
1067
1068         u8         rpg_ai_rate[0x20];
1069
1070         u8         rpg_hai_rate[0x20];
1071
1072         u8         rpg_gd[0x20];
1073
1074         u8         rpg_min_dec_fac[0x20];
1075
1076         u8         rpg_min_rate[0x20];
1077
1078         u8         reserved_at_1c0[0x640];
1079 };
1080
1081 enum {
1082         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1083         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1084         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1085 };
1086
1087 struct mlx5_ifc_resize_field_select_bits {
1088         u8         resize_field_select[0x20];
1089 };
1090
1091 enum {
1092         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1093         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1094         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1095         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1096 };
1097
1098 struct mlx5_ifc_modify_field_select_bits {
1099         u8         modify_field_select[0x20];
1100 };
1101
1102 struct mlx5_ifc_field_select_r_roce_np_bits {
1103         u8         field_select_r_roce_np[0x20];
1104 };
1105
1106 struct mlx5_ifc_field_select_r_roce_rp_bits {
1107         u8         field_select_r_roce_rp[0x20];
1108 };
1109
1110 enum {
1111         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1112         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1113         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1114         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1115         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1116         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1117         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1118         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1119         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1120         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1121 };
1122
1123 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1124         u8         field_select_8021qaurp[0x20];
1125 };
1126
1127 struct mlx5_ifc_phys_layer_cntrs_bits {
1128         u8         time_since_last_clear_high[0x20];
1129
1130         u8         time_since_last_clear_low[0x20];
1131
1132         u8         symbol_errors_high[0x20];
1133
1134         u8         symbol_errors_low[0x20];
1135
1136         u8         sync_headers_errors_high[0x20];
1137
1138         u8         sync_headers_errors_low[0x20];
1139
1140         u8         edpl_bip_errors_lane0_high[0x20];
1141
1142         u8         edpl_bip_errors_lane0_low[0x20];
1143
1144         u8         edpl_bip_errors_lane1_high[0x20];
1145
1146         u8         edpl_bip_errors_lane1_low[0x20];
1147
1148         u8         edpl_bip_errors_lane2_high[0x20];
1149
1150         u8         edpl_bip_errors_lane2_low[0x20];
1151
1152         u8         edpl_bip_errors_lane3_high[0x20];
1153
1154         u8         edpl_bip_errors_lane3_low[0x20];
1155
1156         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1157
1158         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1159
1160         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1161
1162         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1163
1164         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1165
1166         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1167
1168         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1169
1170         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1171
1172         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1173
1174         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1175
1176         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1177
1178         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1179
1180         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1181
1182         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1183
1184         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1185
1186         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1187
1188         u8         rs_fec_corrected_blocks_high[0x20];
1189
1190         u8         rs_fec_corrected_blocks_low[0x20];
1191
1192         u8         rs_fec_uncorrectable_blocks_high[0x20];
1193
1194         u8         rs_fec_uncorrectable_blocks_low[0x20];
1195
1196         u8         rs_fec_no_errors_blocks_high[0x20];
1197
1198         u8         rs_fec_no_errors_blocks_low[0x20];
1199
1200         u8         rs_fec_single_error_blocks_high[0x20];
1201
1202         u8         rs_fec_single_error_blocks_low[0x20];
1203
1204         u8         rs_fec_corrected_symbols_total_high[0x20];
1205
1206         u8         rs_fec_corrected_symbols_total_low[0x20];
1207
1208         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1209
1210         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1211
1212         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1213
1214         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1215
1216         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1217
1218         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1219
1220         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1221
1222         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1223
1224         u8         link_down_events[0x20];
1225
1226         u8         successful_recovery_events[0x20];
1227
1228         u8         reserved_at_640[0x180];
1229 };
1230
1231 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1232         u8         symbol_error_counter[0x10];
1233
1234         u8         link_error_recovery_counter[0x8];
1235
1236         u8         link_downed_counter[0x8];
1237
1238         u8         port_rcv_errors[0x10];
1239
1240         u8         port_rcv_remote_physical_errors[0x10];
1241
1242         u8         port_rcv_switch_relay_errors[0x10];
1243
1244         u8         port_xmit_discards[0x10];
1245
1246         u8         port_xmit_constraint_errors[0x8];
1247
1248         u8         port_rcv_constraint_errors[0x8];
1249
1250         u8         reserved_at_70[0x8];
1251
1252         u8         link_overrun_errors[0x8];
1253
1254         u8         reserved_at_80[0x10];
1255
1256         u8         vl_15_dropped[0x10];
1257
1258         u8         reserved_at_a0[0xa0];
1259 };
1260
1261 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1262         u8         transmit_queue_high[0x20];
1263
1264         u8         transmit_queue_low[0x20];
1265
1266         u8         reserved_at_40[0x780];
1267 };
1268
1269 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1270         u8         rx_octets_high[0x20];
1271
1272         u8         rx_octets_low[0x20];
1273
1274         u8         reserved_at_40[0xc0];
1275
1276         u8         rx_frames_high[0x20];
1277
1278         u8         rx_frames_low[0x20];
1279
1280         u8         tx_octets_high[0x20];
1281
1282         u8         tx_octets_low[0x20];
1283
1284         u8         reserved_at_180[0xc0];
1285
1286         u8         tx_frames_high[0x20];
1287
1288         u8         tx_frames_low[0x20];
1289
1290         u8         rx_pause_high[0x20];
1291
1292         u8         rx_pause_low[0x20];
1293
1294         u8         rx_pause_duration_high[0x20];
1295
1296         u8         rx_pause_duration_low[0x20];
1297
1298         u8         tx_pause_high[0x20];
1299
1300         u8         tx_pause_low[0x20];
1301
1302         u8         tx_pause_duration_high[0x20];
1303
1304         u8         tx_pause_duration_low[0x20];
1305
1306         u8         rx_pause_transition_high[0x20];
1307
1308         u8         rx_pause_transition_low[0x20];
1309
1310         u8         reserved_at_3c0[0x400];
1311 };
1312
1313 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1314         u8         port_transmit_wait_high[0x20];
1315
1316         u8         port_transmit_wait_low[0x20];
1317
1318         u8         reserved_at_40[0x780];
1319 };
1320
1321 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1322         u8         dot3stats_alignment_errors_high[0x20];
1323
1324         u8         dot3stats_alignment_errors_low[0x20];
1325
1326         u8         dot3stats_fcs_errors_high[0x20];
1327
1328         u8         dot3stats_fcs_errors_low[0x20];
1329
1330         u8         dot3stats_single_collision_frames_high[0x20];
1331
1332         u8         dot3stats_single_collision_frames_low[0x20];
1333
1334         u8         dot3stats_multiple_collision_frames_high[0x20];
1335
1336         u8         dot3stats_multiple_collision_frames_low[0x20];
1337
1338         u8         dot3stats_sqe_test_errors_high[0x20];
1339
1340         u8         dot3stats_sqe_test_errors_low[0x20];
1341
1342         u8         dot3stats_deferred_transmissions_high[0x20];
1343
1344         u8         dot3stats_deferred_transmissions_low[0x20];
1345
1346         u8         dot3stats_late_collisions_high[0x20];
1347
1348         u8         dot3stats_late_collisions_low[0x20];
1349
1350         u8         dot3stats_excessive_collisions_high[0x20];
1351
1352         u8         dot3stats_excessive_collisions_low[0x20];
1353
1354         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1355
1356         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1357
1358         u8         dot3stats_carrier_sense_errors_high[0x20];
1359
1360         u8         dot3stats_carrier_sense_errors_low[0x20];
1361
1362         u8         dot3stats_frame_too_longs_high[0x20];
1363
1364         u8         dot3stats_frame_too_longs_low[0x20];
1365
1366         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1367
1368         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1369
1370         u8         dot3stats_symbol_errors_high[0x20];
1371
1372         u8         dot3stats_symbol_errors_low[0x20];
1373
1374         u8         dot3control_in_unknown_opcodes_high[0x20];
1375
1376         u8         dot3control_in_unknown_opcodes_low[0x20];
1377
1378         u8         dot3in_pause_frames_high[0x20];
1379
1380         u8         dot3in_pause_frames_low[0x20];
1381
1382         u8         dot3out_pause_frames_high[0x20];
1383
1384         u8         dot3out_pause_frames_low[0x20];
1385
1386         u8         reserved_at_400[0x3c0];
1387 };
1388
1389 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1390         u8         ether_stats_drop_events_high[0x20];
1391
1392         u8         ether_stats_drop_events_low[0x20];
1393
1394         u8         ether_stats_octets_high[0x20];
1395
1396         u8         ether_stats_octets_low[0x20];
1397
1398         u8         ether_stats_pkts_high[0x20];
1399
1400         u8         ether_stats_pkts_low[0x20];
1401
1402         u8         ether_stats_broadcast_pkts_high[0x20];
1403
1404         u8         ether_stats_broadcast_pkts_low[0x20];
1405
1406         u8         ether_stats_multicast_pkts_high[0x20];
1407
1408         u8         ether_stats_multicast_pkts_low[0x20];
1409
1410         u8         ether_stats_crc_align_errors_high[0x20];
1411
1412         u8         ether_stats_crc_align_errors_low[0x20];
1413
1414         u8         ether_stats_undersize_pkts_high[0x20];
1415
1416         u8         ether_stats_undersize_pkts_low[0x20];
1417
1418         u8         ether_stats_oversize_pkts_high[0x20];
1419
1420         u8         ether_stats_oversize_pkts_low[0x20];
1421
1422         u8         ether_stats_fragments_high[0x20];
1423
1424         u8         ether_stats_fragments_low[0x20];
1425
1426         u8         ether_stats_jabbers_high[0x20];
1427
1428         u8         ether_stats_jabbers_low[0x20];
1429
1430         u8         ether_stats_collisions_high[0x20];
1431
1432         u8         ether_stats_collisions_low[0x20];
1433
1434         u8         ether_stats_pkts64octets_high[0x20];
1435
1436         u8         ether_stats_pkts64octets_low[0x20];
1437
1438         u8         ether_stats_pkts65to127octets_high[0x20];
1439
1440         u8         ether_stats_pkts65to127octets_low[0x20];
1441
1442         u8         ether_stats_pkts128to255octets_high[0x20];
1443
1444         u8         ether_stats_pkts128to255octets_low[0x20];
1445
1446         u8         ether_stats_pkts256to511octets_high[0x20];
1447
1448         u8         ether_stats_pkts256to511octets_low[0x20];
1449
1450         u8         ether_stats_pkts512to1023octets_high[0x20];
1451
1452         u8         ether_stats_pkts512to1023octets_low[0x20];
1453
1454         u8         ether_stats_pkts1024to1518octets_high[0x20];
1455
1456         u8         ether_stats_pkts1024to1518octets_low[0x20];
1457
1458         u8         ether_stats_pkts1519to2047octets_high[0x20];
1459
1460         u8         ether_stats_pkts1519to2047octets_low[0x20];
1461
1462         u8         ether_stats_pkts2048to4095octets_high[0x20];
1463
1464         u8         ether_stats_pkts2048to4095octets_low[0x20];
1465
1466         u8         ether_stats_pkts4096to8191octets_high[0x20];
1467
1468         u8         ether_stats_pkts4096to8191octets_low[0x20];
1469
1470         u8         ether_stats_pkts8192to10239octets_high[0x20];
1471
1472         u8         ether_stats_pkts8192to10239octets_low[0x20];
1473
1474         u8         reserved_at_540[0x280];
1475 };
1476
1477 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1478         u8         if_in_octets_high[0x20];
1479
1480         u8         if_in_octets_low[0x20];
1481
1482         u8         if_in_ucast_pkts_high[0x20];
1483
1484         u8         if_in_ucast_pkts_low[0x20];
1485
1486         u8         if_in_discards_high[0x20];
1487
1488         u8         if_in_discards_low[0x20];
1489
1490         u8         if_in_errors_high[0x20];
1491
1492         u8         if_in_errors_low[0x20];
1493
1494         u8         if_in_unknown_protos_high[0x20];
1495
1496         u8         if_in_unknown_protos_low[0x20];
1497
1498         u8         if_out_octets_high[0x20];
1499
1500         u8         if_out_octets_low[0x20];
1501
1502         u8         if_out_ucast_pkts_high[0x20];
1503
1504         u8         if_out_ucast_pkts_low[0x20];
1505
1506         u8         if_out_discards_high[0x20];
1507
1508         u8         if_out_discards_low[0x20];
1509
1510         u8         if_out_errors_high[0x20];
1511
1512         u8         if_out_errors_low[0x20];
1513
1514         u8         if_in_multicast_pkts_high[0x20];
1515
1516         u8         if_in_multicast_pkts_low[0x20];
1517
1518         u8         if_in_broadcast_pkts_high[0x20];
1519
1520         u8         if_in_broadcast_pkts_low[0x20];
1521
1522         u8         if_out_multicast_pkts_high[0x20];
1523
1524         u8         if_out_multicast_pkts_low[0x20];
1525
1526         u8         if_out_broadcast_pkts_high[0x20];
1527
1528         u8         if_out_broadcast_pkts_low[0x20];
1529
1530         u8         reserved_at_340[0x480];
1531 };
1532
1533 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1534         u8         a_frames_transmitted_ok_high[0x20];
1535
1536         u8         a_frames_transmitted_ok_low[0x20];
1537
1538         u8         a_frames_received_ok_high[0x20];
1539
1540         u8         a_frames_received_ok_low[0x20];
1541
1542         u8         a_frame_check_sequence_errors_high[0x20];
1543
1544         u8         a_frame_check_sequence_errors_low[0x20];
1545
1546         u8         a_alignment_errors_high[0x20];
1547
1548         u8         a_alignment_errors_low[0x20];
1549
1550         u8         a_octets_transmitted_ok_high[0x20];
1551
1552         u8         a_octets_transmitted_ok_low[0x20];
1553
1554         u8         a_octets_received_ok_high[0x20];
1555
1556         u8         a_octets_received_ok_low[0x20];
1557
1558         u8         a_multicast_frames_xmitted_ok_high[0x20];
1559
1560         u8         a_multicast_frames_xmitted_ok_low[0x20];
1561
1562         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1563
1564         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1565
1566         u8         a_multicast_frames_received_ok_high[0x20];
1567
1568         u8         a_multicast_frames_received_ok_low[0x20];
1569
1570         u8         a_broadcast_frames_received_ok_high[0x20];
1571
1572         u8         a_broadcast_frames_received_ok_low[0x20];
1573
1574         u8         a_in_range_length_errors_high[0x20];
1575
1576         u8         a_in_range_length_errors_low[0x20];
1577
1578         u8         a_out_of_range_length_field_high[0x20];
1579
1580         u8         a_out_of_range_length_field_low[0x20];
1581
1582         u8         a_frame_too_long_errors_high[0x20];
1583
1584         u8         a_frame_too_long_errors_low[0x20];
1585
1586         u8         a_symbol_error_during_carrier_high[0x20];
1587
1588         u8         a_symbol_error_during_carrier_low[0x20];
1589
1590         u8         a_mac_control_frames_transmitted_high[0x20];
1591
1592         u8         a_mac_control_frames_transmitted_low[0x20];
1593
1594         u8         a_mac_control_frames_received_high[0x20];
1595
1596         u8         a_mac_control_frames_received_low[0x20];
1597
1598         u8         a_unsupported_opcodes_received_high[0x20];
1599
1600         u8         a_unsupported_opcodes_received_low[0x20];
1601
1602         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1603
1604         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1605
1606         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1607
1608         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1609
1610         u8         reserved_at_4c0[0x300];
1611 };
1612
1613 struct mlx5_ifc_cmd_inter_comp_event_bits {
1614         u8         command_completion_vector[0x20];
1615
1616         u8         reserved_at_20[0xc0];
1617 };
1618
1619 struct mlx5_ifc_stall_vl_event_bits {
1620         u8         reserved_at_0[0x18];
1621         u8         port_num[0x1];
1622         u8         reserved_at_19[0x3];
1623         u8         vl[0x4];
1624
1625         u8         reserved_at_20[0xa0];
1626 };
1627
1628 struct mlx5_ifc_db_bf_congestion_event_bits {
1629         u8         event_subtype[0x8];
1630         u8         reserved_at_8[0x8];
1631         u8         congestion_level[0x8];
1632         u8         reserved_at_18[0x8];
1633
1634         u8         reserved_at_20[0xa0];
1635 };
1636
1637 struct mlx5_ifc_gpio_event_bits {
1638         u8         reserved_at_0[0x60];
1639
1640         u8         gpio_event_hi[0x20];
1641
1642         u8         gpio_event_lo[0x20];
1643
1644         u8         reserved_at_a0[0x40];
1645 };
1646
1647 struct mlx5_ifc_port_state_change_event_bits {
1648         u8         reserved_at_0[0x40];
1649
1650         u8         port_num[0x4];
1651         u8         reserved_at_44[0x1c];
1652
1653         u8         reserved_at_60[0x80];
1654 };
1655
1656 struct mlx5_ifc_dropped_packet_logged_bits {
1657         u8         reserved_at_0[0xe0];
1658 };
1659
1660 enum {
1661         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1662         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1663 };
1664
1665 struct mlx5_ifc_cq_error_bits {
1666         u8         reserved_at_0[0x8];
1667         u8         cqn[0x18];
1668
1669         u8         reserved_at_20[0x20];
1670
1671         u8         reserved_at_40[0x18];
1672         u8         syndrome[0x8];
1673
1674         u8         reserved_at_60[0x80];
1675 };
1676
1677 struct mlx5_ifc_rdma_page_fault_event_bits {
1678         u8         bytes_committed[0x20];
1679
1680         u8         r_key[0x20];
1681
1682         u8         reserved_at_40[0x10];
1683         u8         packet_len[0x10];
1684
1685         u8         rdma_op_len[0x20];
1686
1687         u8         rdma_va[0x40];
1688
1689         u8         reserved_at_c0[0x5];
1690         u8         rdma[0x1];
1691         u8         write[0x1];
1692         u8         requestor[0x1];
1693         u8         qp_number[0x18];
1694 };
1695
1696 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1697         u8         bytes_committed[0x20];
1698
1699         u8         reserved_at_20[0x10];
1700         u8         wqe_index[0x10];
1701
1702         u8         reserved_at_40[0x10];
1703         u8         len[0x10];
1704
1705         u8         reserved_at_60[0x60];
1706
1707         u8         reserved_at_c0[0x5];
1708         u8         rdma[0x1];
1709         u8         write_read[0x1];
1710         u8         requestor[0x1];
1711         u8         qpn[0x18];
1712 };
1713
1714 struct mlx5_ifc_qp_events_bits {
1715         u8         reserved_at_0[0xa0];
1716
1717         u8         type[0x8];
1718         u8         reserved_at_a8[0x18];
1719
1720         u8         reserved_at_c0[0x8];
1721         u8         qpn_rqn_sqn[0x18];
1722 };
1723
1724 struct mlx5_ifc_dct_events_bits {
1725         u8         reserved_at_0[0xc0];
1726
1727         u8         reserved_at_c0[0x8];
1728         u8         dct_number[0x18];
1729 };
1730
1731 struct mlx5_ifc_comp_event_bits {
1732         u8         reserved_at_0[0xc0];
1733
1734         u8         reserved_at_c0[0x8];
1735         u8         cq_number[0x18];
1736 };
1737
1738 enum {
1739         MLX5_QPC_STATE_RST        = 0x0,
1740         MLX5_QPC_STATE_INIT       = 0x1,
1741         MLX5_QPC_STATE_RTR        = 0x2,
1742         MLX5_QPC_STATE_RTS        = 0x3,
1743         MLX5_QPC_STATE_SQER       = 0x4,
1744         MLX5_QPC_STATE_ERR        = 0x6,
1745         MLX5_QPC_STATE_SQD        = 0x7,
1746         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1747 };
1748
1749 enum {
1750         MLX5_QPC_ST_RC            = 0x0,
1751         MLX5_QPC_ST_UC            = 0x1,
1752         MLX5_QPC_ST_UD            = 0x2,
1753         MLX5_QPC_ST_XRC           = 0x3,
1754         MLX5_QPC_ST_DCI           = 0x5,
1755         MLX5_QPC_ST_QP0           = 0x7,
1756         MLX5_QPC_ST_QP1           = 0x8,
1757         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1758         MLX5_QPC_ST_REG_UMR       = 0xc,
1759 };
1760
1761 enum {
1762         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1763         MLX5_QPC_PM_STATE_REARM     = 0x1,
1764         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1765         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1766 };
1767
1768 enum {
1769         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1770         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1771 };
1772
1773 enum {
1774         MLX5_QPC_MTU_256_BYTES        = 0x1,
1775         MLX5_QPC_MTU_512_BYTES        = 0x2,
1776         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1777         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1778         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1779         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1780 };
1781
1782 enum {
1783         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1784         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1785         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1786         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1787         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1788         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1789         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1790         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1791 };
1792
1793 enum {
1794         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1795         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1796         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1797 };
1798
1799 enum {
1800         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1801         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1802         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1803 };
1804
1805 struct mlx5_ifc_qpc_bits {
1806         u8         state[0x4];
1807         u8         reserved_at_4[0x4];
1808         u8         st[0x8];
1809         u8         reserved_at_10[0x3];
1810         u8         pm_state[0x2];
1811         u8         reserved_at_15[0x7];
1812         u8         end_padding_mode[0x2];
1813         u8         reserved_at_1e[0x2];
1814
1815         u8         wq_signature[0x1];
1816         u8         block_lb_mc[0x1];
1817         u8         atomic_like_write_en[0x1];
1818         u8         latency_sensitive[0x1];
1819         u8         reserved_at_24[0x1];
1820         u8         drain_sigerr[0x1];
1821         u8         reserved_at_26[0x2];
1822         u8         pd[0x18];
1823
1824         u8         mtu[0x3];
1825         u8         log_msg_max[0x5];
1826         u8         reserved_at_48[0x1];
1827         u8         log_rq_size[0x4];
1828         u8         log_rq_stride[0x3];
1829         u8         no_sq[0x1];
1830         u8         log_sq_size[0x4];
1831         u8         reserved_at_55[0x6];
1832         u8         rlky[0x1];
1833         u8         ulp_stateless_offload_mode[0x4];
1834
1835         u8         counter_set_id[0x8];
1836         u8         uar_page[0x18];
1837
1838         u8         reserved_at_80[0x8];
1839         u8         user_index[0x18];
1840
1841         u8         reserved_at_a0[0x3];
1842         u8         log_page_size[0x5];
1843         u8         remote_qpn[0x18];
1844
1845         struct mlx5_ifc_ads_bits primary_address_path;
1846
1847         struct mlx5_ifc_ads_bits secondary_address_path;
1848
1849         u8         log_ack_req_freq[0x4];
1850         u8         reserved_at_384[0x4];
1851         u8         log_sra_max[0x3];
1852         u8         reserved_at_38b[0x2];
1853         u8         retry_count[0x3];
1854         u8         rnr_retry[0x3];
1855         u8         reserved_at_393[0x1];
1856         u8         fre[0x1];
1857         u8         cur_rnr_retry[0x3];
1858         u8         cur_retry_count[0x3];
1859         u8         reserved_at_39b[0x5];
1860
1861         u8         reserved_at_3a0[0x20];
1862
1863         u8         reserved_at_3c0[0x8];
1864         u8         next_send_psn[0x18];
1865
1866         u8         reserved_at_3e0[0x8];
1867         u8         cqn_snd[0x18];
1868
1869         u8         reserved_at_400[0x40];
1870
1871         u8         reserved_at_440[0x8];
1872         u8         last_acked_psn[0x18];
1873
1874         u8         reserved_at_460[0x8];
1875         u8         ssn[0x18];
1876
1877         u8         reserved_at_480[0x8];
1878         u8         log_rra_max[0x3];
1879         u8         reserved_at_48b[0x1];
1880         u8         atomic_mode[0x4];
1881         u8         rre[0x1];
1882         u8         rwe[0x1];
1883         u8         rae[0x1];
1884         u8         reserved_at_493[0x1];
1885         u8         page_offset[0x6];
1886         u8         reserved_at_49a[0x3];
1887         u8         cd_slave_receive[0x1];
1888         u8         cd_slave_send[0x1];
1889         u8         cd_master[0x1];
1890
1891         u8         reserved_at_4a0[0x3];
1892         u8         min_rnr_nak[0x5];
1893         u8         next_rcv_psn[0x18];
1894
1895         u8         reserved_at_4c0[0x8];
1896         u8         xrcd[0x18];
1897
1898         u8         reserved_at_4e0[0x8];
1899         u8         cqn_rcv[0x18];
1900
1901         u8         dbr_addr[0x40];
1902
1903         u8         q_key[0x20];
1904
1905         u8         reserved_at_560[0x5];
1906         u8         rq_type[0x3];
1907         u8         srqn_rmpn[0x18];
1908
1909         u8         reserved_at_580[0x8];
1910         u8         rmsn[0x18];
1911
1912         u8         hw_sq_wqebb_counter[0x10];
1913         u8         sw_sq_wqebb_counter[0x10];
1914
1915         u8         hw_rq_counter[0x20];
1916
1917         u8         sw_rq_counter[0x20];
1918
1919         u8         reserved_at_600[0x20];
1920
1921         u8         reserved_at_620[0xf];
1922         u8         cgs[0x1];
1923         u8         cs_req[0x8];
1924         u8         cs_res[0x8];
1925
1926         u8         dc_access_key[0x40];
1927
1928         u8         reserved_at_680[0xc0];
1929 };
1930
1931 struct mlx5_ifc_roce_addr_layout_bits {
1932         u8         source_l3_address[16][0x8];
1933
1934         u8         reserved_at_80[0x3];
1935         u8         vlan_valid[0x1];
1936         u8         vlan_id[0xc];
1937         u8         source_mac_47_32[0x10];
1938
1939         u8         source_mac_31_0[0x20];
1940
1941         u8         reserved_at_c0[0x14];
1942         u8         roce_l3_type[0x4];
1943         u8         roce_version[0x8];
1944
1945         u8         reserved_at_e0[0x20];
1946 };
1947
1948 union mlx5_ifc_hca_cap_union_bits {
1949         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1950         struct mlx5_ifc_odp_cap_bits odp_cap;
1951         struct mlx5_ifc_atomic_caps_bits atomic_caps;
1952         struct mlx5_ifc_roce_cap_bits roce_cap;
1953         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1954         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1955         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1956         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1957         u8         reserved_at_0[0x8000];
1958 };
1959
1960 enum {
1961         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1962         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1963         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1964 };
1965
1966 struct mlx5_ifc_flow_context_bits {
1967         u8         reserved_at_0[0x20];
1968
1969         u8         group_id[0x20];
1970
1971         u8         reserved_at_40[0x8];
1972         u8         flow_tag[0x18];
1973
1974         u8         reserved_at_60[0x10];
1975         u8         action[0x10];
1976
1977         u8         reserved_at_80[0x8];
1978         u8         destination_list_size[0x18];
1979
1980         u8         reserved_at_a0[0x160];
1981
1982         struct mlx5_ifc_fte_match_param_bits match_value;
1983
1984         u8         reserved_at_1200[0x600];
1985
1986         struct mlx5_ifc_dest_format_struct_bits destination[0];
1987 };
1988
1989 enum {
1990         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1991         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1992 };
1993
1994 struct mlx5_ifc_xrc_srqc_bits {
1995         u8         state[0x4];
1996         u8         log_xrc_srq_size[0x4];
1997         u8         reserved_at_8[0x18];
1998
1999         u8         wq_signature[0x1];
2000         u8         cont_srq[0x1];
2001         u8         reserved_at_22[0x1];
2002         u8         rlky[0x1];
2003         u8         basic_cyclic_rcv_wqe[0x1];
2004         u8         log_rq_stride[0x3];
2005         u8         xrcd[0x18];
2006
2007         u8         page_offset[0x6];
2008         u8         reserved_at_46[0x2];
2009         u8         cqn[0x18];
2010
2011         u8         reserved_at_60[0x20];
2012
2013         u8         user_index_equal_xrc_srqn[0x1];
2014         u8         reserved_at_81[0x1];
2015         u8         log_page_size[0x6];
2016         u8         user_index[0x18];
2017
2018         u8         reserved_at_a0[0x20];
2019
2020         u8         reserved_at_c0[0x8];
2021         u8         pd[0x18];
2022
2023         u8         lwm[0x10];
2024         u8         wqe_cnt[0x10];
2025
2026         u8         reserved_at_100[0x40];
2027
2028         u8         db_record_addr_h[0x20];
2029
2030         u8         db_record_addr_l[0x1e];
2031         u8         reserved_at_17e[0x2];
2032
2033         u8         reserved_at_180[0x80];
2034 };
2035
2036 struct mlx5_ifc_traffic_counter_bits {
2037         u8         packets[0x40];
2038
2039         u8         octets[0x40];
2040 };
2041
2042 struct mlx5_ifc_tisc_bits {
2043         u8         reserved_at_0[0xc];
2044         u8         prio[0x4];
2045         u8         reserved_at_10[0x10];
2046
2047         u8         reserved_at_20[0x100];
2048
2049         u8         reserved_at_120[0x8];
2050         u8         transport_domain[0x18];
2051
2052         u8         reserved_at_140[0x3c0];
2053 };
2054
2055 enum {
2056         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2057         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2058 };
2059
2060 enum {
2061         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2062         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2063 };
2064
2065 enum {
2066         MLX5_RX_HASH_FN_NONE           = 0x0,
2067         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2068         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2069 };
2070
2071 enum {
2072         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2073         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2074 };
2075
2076 struct mlx5_ifc_tirc_bits {
2077         u8         reserved_at_0[0x20];
2078
2079         u8         disp_type[0x4];
2080         u8         reserved_at_24[0x1c];
2081
2082         u8         reserved_at_40[0x40];
2083
2084         u8         reserved_at_80[0x4];
2085         u8         lro_timeout_period_usecs[0x10];
2086         u8         lro_enable_mask[0x4];
2087         u8         lro_max_ip_payload_size[0x8];
2088
2089         u8         reserved_at_a0[0x40];
2090
2091         u8         reserved_at_e0[0x8];
2092         u8         inline_rqn[0x18];
2093
2094         u8         rx_hash_symmetric[0x1];
2095         u8         reserved_at_101[0x1];
2096         u8         tunneled_offload_en[0x1];
2097         u8         reserved_at_103[0x5];
2098         u8         indirect_table[0x18];
2099
2100         u8         rx_hash_fn[0x4];
2101         u8         reserved_at_124[0x2];
2102         u8         self_lb_block[0x2];
2103         u8         transport_domain[0x18];
2104
2105         u8         rx_hash_toeplitz_key[10][0x20];
2106
2107         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2108
2109         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2110
2111         u8         reserved_at_2c0[0x4c0];
2112 };
2113
2114 enum {
2115         MLX5_SRQC_STATE_GOOD   = 0x0,
2116         MLX5_SRQC_STATE_ERROR  = 0x1,
2117 };
2118
2119 struct mlx5_ifc_srqc_bits {
2120         u8         state[0x4];
2121         u8         log_srq_size[0x4];
2122         u8         reserved_at_8[0x18];
2123
2124         u8         wq_signature[0x1];
2125         u8         cont_srq[0x1];
2126         u8         reserved_at_22[0x1];
2127         u8         rlky[0x1];
2128         u8         reserved_at_24[0x1];
2129         u8         log_rq_stride[0x3];
2130         u8         xrcd[0x18];
2131
2132         u8         page_offset[0x6];
2133         u8         reserved_at_46[0x2];
2134         u8         cqn[0x18];
2135
2136         u8         reserved_at_60[0x20];
2137
2138         u8         reserved_at_80[0x2];
2139         u8         log_page_size[0x6];
2140         u8         reserved_at_88[0x18];
2141
2142         u8         reserved_at_a0[0x20];
2143
2144         u8         reserved_at_c0[0x8];
2145         u8         pd[0x18];
2146
2147         u8         lwm[0x10];
2148         u8         wqe_cnt[0x10];
2149
2150         u8         reserved_at_100[0x40];
2151
2152         u8         dbr_addr[0x40];
2153
2154         u8         reserved_at_180[0x80];
2155 };
2156
2157 enum {
2158         MLX5_SQC_STATE_RST  = 0x0,
2159         MLX5_SQC_STATE_RDY  = 0x1,
2160         MLX5_SQC_STATE_ERR  = 0x3,
2161 };
2162
2163 struct mlx5_ifc_sqc_bits {
2164         u8         rlky[0x1];
2165         u8         cd_master[0x1];
2166         u8         fre[0x1];
2167         u8         flush_in_error_en[0x1];
2168         u8         reserved_at_4[0x4];
2169         u8         state[0x4];
2170         u8         reserved_at_c[0x14];
2171
2172         u8         reserved_at_20[0x8];
2173         u8         user_index[0x18];
2174
2175         u8         reserved_at_40[0x8];
2176         u8         cqn[0x18];
2177
2178         u8         reserved_at_60[0xa0];
2179
2180         u8         tis_lst_sz[0x10];
2181         u8         reserved_at_110[0x10];
2182
2183         u8         reserved_at_120[0x40];
2184
2185         u8         reserved_at_160[0x8];
2186         u8         tis_num_0[0x18];
2187
2188         struct mlx5_ifc_wq_bits wq;
2189 };
2190
2191 struct mlx5_ifc_rqtc_bits {
2192         u8         reserved_at_0[0xa0];
2193
2194         u8         reserved_at_a0[0x10];
2195         u8         rqt_max_size[0x10];
2196
2197         u8         reserved_at_c0[0x10];
2198         u8         rqt_actual_size[0x10];
2199
2200         u8         reserved_at_e0[0x6a0];
2201
2202         struct mlx5_ifc_rq_num_bits rq_num[0];
2203 };
2204
2205 enum {
2206         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2207         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2208 };
2209
2210 enum {
2211         MLX5_RQC_STATE_RST  = 0x0,
2212         MLX5_RQC_STATE_RDY  = 0x1,
2213         MLX5_RQC_STATE_ERR  = 0x3,
2214 };
2215
2216 struct mlx5_ifc_rqc_bits {
2217         u8         rlky[0x1];
2218         u8         reserved_at_1[0x2];
2219         u8         vsd[0x1];
2220         u8         mem_rq_type[0x4];
2221         u8         state[0x4];
2222         u8         reserved_at_c[0x1];
2223         u8         flush_in_error_en[0x1];
2224         u8         reserved_at_e[0x12];
2225
2226         u8         reserved_at_20[0x8];
2227         u8         user_index[0x18];
2228
2229         u8         reserved_at_40[0x8];
2230         u8         cqn[0x18];
2231
2232         u8         counter_set_id[0x8];
2233         u8         reserved_at_68[0x18];
2234
2235         u8         reserved_at_80[0x8];
2236         u8         rmpn[0x18];
2237
2238         u8         reserved_at_a0[0xe0];
2239
2240         struct mlx5_ifc_wq_bits wq;
2241 };
2242
2243 enum {
2244         MLX5_RMPC_STATE_RDY  = 0x1,
2245         MLX5_RMPC_STATE_ERR  = 0x3,
2246 };
2247
2248 struct mlx5_ifc_rmpc_bits {
2249         u8         reserved_at_0[0x8];
2250         u8         state[0x4];
2251         u8         reserved_at_c[0x14];
2252
2253         u8         basic_cyclic_rcv_wqe[0x1];
2254         u8         reserved_at_21[0x1f];
2255
2256         u8         reserved_at_40[0x140];
2257
2258         struct mlx5_ifc_wq_bits wq;
2259 };
2260
2261 struct mlx5_ifc_nic_vport_context_bits {
2262         u8         reserved_at_0[0x1f];
2263         u8         roce_en[0x1];
2264
2265         u8         arm_change_event[0x1];
2266         u8         reserved_at_21[0x1a];
2267         u8         event_on_mtu[0x1];
2268         u8         event_on_promisc_change[0x1];
2269         u8         event_on_vlan_change[0x1];
2270         u8         event_on_mc_address_change[0x1];
2271         u8         event_on_uc_address_change[0x1];
2272
2273         u8         reserved_at_40[0xf0];
2274
2275         u8         mtu[0x10];
2276
2277         u8         system_image_guid[0x40];
2278         u8         port_guid[0x40];
2279         u8         node_guid[0x40];
2280
2281         u8         reserved_at_200[0x140];
2282         u8         qkey_violation_counter[0x10];
2283         u8         reserved_at_350[0x430];
2284
2285         u8         promisc_uc[0x1];
2286         u8         promisc_mc[0x1];
2287         u8         promisc_all[0x1];
2288         u8         reserved_at_783[0x2];
2289         u8         allowed_list_type[0x3];
2290         u8         reserved_at_788[0xc];
2291         u8         allowed_list_size[0xc];
2292
2293         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2294
2295         u8         reserved_at_7e0[0x20];
2296
2297         u8         current_uc_mac_address[0][0x40];
2298 };
2299
2300 enum {
2301         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2302         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2303         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2304 };
2305
2306 struct mlx5_ifc_mkc_bits {
2307         u8         reserved_at_0[0x1];
2308         u8         free[0x1];
2309         u8         reserved_at_2[0xd];
2310         u8         small_fence_on_rdma_read_response[0x1];
2311         u8         umr_en[0x1];
2312         u8         a[0x1];
2313         u8         rw[0x1];
2314         u8         rr[0x1];
2315         u8         lw[0x1];
2316         u8         lr[0x1];
2317         u8         access_mode[0x2];
2318         u8         reserved_at_18[0x8];
2319
2320         u8         qpn[0x18];
2321         u8         mkey_7_0[0x8];
2322
2323         u8         reserved_at_40[0x20];
2324
2325         u8         length64[0x1];
2326         u8         bsf_en[0x1];
2327         u8         sync_umr[0x1];
2328         u8         reserved_at_63[0x2];
2329         u8         expected_sigerr_count[0x1];
2330         u8         reserved_at_66[0x1];
2331         u8         en_rinval[0x1];
2332         u8         pd[0x18];
2333
2334         u8         start_addr[0x40];
2335
2336         u8         len[0x40];
2337
2338         u8         bsf_octword_size[0x20];
2339
2340         u8         reserved_at_120[0x80];
2341
2342         u8         translations_octword_size[0x20];
2343
2344         u8         reserved_at_1c0[0x1b];
2345         u8         log_page_size[0x5];
2346
2347         u8         reserved_at_1e0[0x20];
2348 };
2349
2350 struct mlx5_ifc_pkey_bits {
2351         u8         reserved_at_0[0x10];
2352         u8         pkey[0x10];
2353 };
2354
2355 struct mlx5_ifc_array128_auto_bits {
2356         u8         array128_auto[16][0x8];
2357 };
2358
2359 struct mlx5_ifc_hca_vport_context_bits {
2360         u8         field_select[0x20];
2361
2362         u8         reserved_at_20[0xe0];
2363
2364         u8         sm_virt_aware[0x1];
2365         u8         has_smi[0x1];
2366         u8         has_raw[0x1];
2367         u8         grh_required[0x1];
2368         u8         reserved_at_104[0xc];
2369         u8         port_physical_state[0x4];
2370         u8         vport_state_policy[0x4];
2371         u8         port_state[0x4];
2372         u8         vport_state[0x4];
2373
2374         u8         reserved_at_120[0x20];
2375
2376         u8         system_image_guid[0x40];
2377
2378         u8         port_guid[0x40];
2379
2380         u8         node_guid[0x40];
2381
2382         u8         cap_mask1[0x20];
2383
2384         u8         cap_mask1_field_select[0x20];
2385
2386         u8         cap_mask2[0x20];
2387
2388         u8         cap_mask2_field_select[0x20];
2389
2390         u8         reserved_at_280[0x80];
2391
2392         u8         lid[0x10];
2393         u8         reserved_at_310[0x4];
2394         u8         init_type_reply[0x4];
2395         u8         lmc[0x3];
2396         u8         subnet_timeout[0x5];
2397
2398         u8         sm_lid[0x10];
2399         u8         sm_sl[0x4];
2400         u8         reserved_at_334[0xc];
2401
2402         u8         qkey_violation_counter[0x10];
2403         u8         pkey_violation_counter[0x10];
2404
2405         u8         reserved_at_360[0xca0];
2406 };
2407
2408 struct mlx5_ifc_esw_vport_context_bits {
2409         u8         reserved_at_0[0x3];
2410         u8         vport_svlan_strip[0x1];
2411         u8         vport_cvlan_strip[0x1];
2412         u8         vport_svlan_insert[0x1];
2413         u8         vport_cvlan_insert[0x2];
2414         u8         reserved_at_8[0x18];
2415
2416         u8         reserved_at_20[0x20];
2417
2418         u8         svlan_cfi[0x1];
2419         u8         svlan_pcp[0x3];
2420         u8         svlan_id[0xc];
2421         u8         cvlan_cfi[0x1];
2422         u8         cvlan_pcp[0x3];
2423         u8         cvlan_id[0xc];
2424
2425         u8         reserved_at_60[0x7a0];
2426 };
2427
2428 enum {
2429         MLX5_EQC_STATUS_OK                = 0x0,
2430         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2431 };
2432
2433 enum {
2434         MLX5_EQC_ST_ARMED  = 0x9,
2435         MLX5_EQC_ST_FIRED  = 0xa,
2436 };
2437
2438 struct mlx5_ifc_eqc_bits {
2439         u8         status[0x4];
2440         u8         reserved_at_4[0x9];
2441         u8         ec[0x1];
2442         u8         oi[0x1];
2443         u8         reserved_at_f[0x5];
2444         u8         st[0x4];
2445         u8         reserved_at_18[0x8];
2446
2447         u8         reserved_at_20[0x20];
2448
2449         u8         reserved_at_40[0x14];
2450         u8         page_offset[0x6];
2451         u8         reserved_at_5a[0x6];
2452
2453         u8         reserved_at_60[0x3];
2454         u8         log_eq_size[0x5];
2455         u8         uar_page[0x18];
2456
2457         u8         reserved_at_80[0x20];
2458
2459         u8         reserved_at_a0[0x18];
2460         u8         intr[0x8];
2461
2462         u8         reserved_at_c0[0x3];
2463         u8         log_page_size[0x5];
2464         u8         reserved_at_c8[0x18];
2465
2466         u8         reserved_at_e0[0x60];
2467
2468         u8         reserved_at_140[0x8];
2469         u8         consumer_counter[0x18];
2470
2471         u8         reserved_at_160[0x8];
2472         u8         producer_counter[0x18];
2473
2474         u8         reserved_at_180[0x80];
2475 };
2476
2477 enum {
2478         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2479         MLX5_DCTC_STATE_DRAINING  = 0x1,
2480         MLX5_DCTC_STATE_DRAINED   = 0x2,
2481 };
2482
2483 enum {
2484         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2485         MLX5_DCTC_CS_RES_NA         = 0x1,
2486         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2487 };
2488
2489 enum {
2490         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2491         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2492         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2493         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2494         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2495 };
2496
2497 struct mlx5_ifc_dctc_bits {
2498         u8         reserved_at_0[0x4];
2499         u8         state[0x4];
2500         u8         reserved_at_8[0x18];
2501
2502         u8         reserved_at_20[0x8];
2503         u8         user_index[0x18];
2504
2505         u8         reserved_at_40[0x8];
2506         u8         cqn[0x18];
2507
2508         u8         counter_set_id[0x8];
2509         u8         atomic_mode[0x4];
2510         u8         rre[0x1];
2511         u8         rwe[0x1];
2512         u8         rae[0x1];
2513         u8         atomic_like_write_en[0x1];
2514         u8         latency_sensitive[0x1];
2515         u8         rlky[0x1];
2516         u8         free_ar[0x1];
2517         u8         reserved_at_73[0xd];
2518
2519         u8         reserved_at_80[0x8];
2520         u8         cs_res[0x8];
2521         u8         reserved_at_90[0x3];
2522         u8         min_rnr_nak[0x5];
2523         u8         reserved_at_98[0x8];
2524
2525         u8         reserved_at_a0[0x8];
2526         u8         srqn[0x18];
2527
2528         u8         reserved_at_c0[0x8];
2529         u8         pd[0x18];
2530
2531         u8         tclass[0x8];
2532         u8         reserved_at_e8[0x4];
2533         u8         flow_label[0x14];
2534
2535         u8         dc_access_key[0x40];
2536
2537         u8         reserved_at_140[0x5];
2538         u8         mtu[0x3];
2539         u8         port[0x8];
2540         u8         pkey_index[0x10];
2541
2542         u8         reserved_at_160[0x8];
2543         u8         my_addr_index[0x8];
2544         u8         reserved_at_170[0x8];
2545         u8         hop_limit[0x8];
2546
2547         u8         dc_access_key_violation_count[0x20];
2548
2549         u8         reserved_at_1a0[0x14];
2550         u8         dei_cfi[0x1];
2551         u8         eth_prio[0x3];
2552         u8         ecn[0x2];
2553         u8         dscp[0x6];
2554
2555         u8         reserved_at_1c0[0x40];
2556 };
2557
2558 enum {
2559         MLX5_CQC_STATUS_OK             = 0x0,
2560         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2561         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2562 };
2563
2564 enum {
2565         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2566         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2567 };
2568
2569 enum {
2570         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2571         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2572         MLX5_CQC_ST_FIRED                                 = 0xa,
2573 };
2574
2575 struct mlx5_ifc_cqc_bits {
2576         u8         status[0x4];
2577         u8         reserved_at_4[0x4];
2578         u8         cqe_sz[0x3];
2579         u8         cc[0x1];
2580         u8         reserved_at_c[0x1];
2581         u8         scqe_break_moderation_en[0x1];
2582         u8         oi[0x1];
2583         u8         reserved_at_f[0x2];
2584         u8         cqe_zip_en[0x1];
2585         u8         mini_cqe_res_format[0x2];
2586         u8         st[0x4];
2587         u8         reserved_at_18[0x8];
2588
2589         u8         reserved_at_20[0x20];
2590
2591         u8         reserved_at_40[0x14];
2592         u8         page_offset[0x6];
2593         u8         reserved_at_5a[0x6];
2594
2595         u8         reserved_at_60[0x3];
2596         u8         log_cq_size[0x5];
2597         u8         uar_page[0x18];
2598
2599         u8         reserved_at_80[0x4];
2600         u8         cq_period[0xc];
2601         u8         cq_max_count[0x10];
2602
2603         u8         reserved_at_a0[0x18];
2604         u8         c_eqn[0x8];
2605
2606         u8         reserved_at_c0[0x3];
2607         u8         log_page_size[0x5];
2608         u8         reserved_at_c8[0x18];
2609
2610         u8         reserved_at_e0[0x20];
2611
2612         u8         reserved_at_100[0x8];
2613         u8         last_notified_index[0x18];
2614
2615         u8         reserved_at_120[0x8];
2616         u8         last_solicit_index[0x18];
2617
2618         u8         reserved_at_140[0x8];
2619         u8         consumer_counter[0x18];
2620
2621         u8         reserved_at_160[0x8];
2622         u8         producer_counter[0x18];
2623
2624         u8         reserved_at_180[0x40];
2625
2626         u8         dbr_addr[0x40];
2627 };
2628
2629 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2630         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2631         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2632         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2633         u8         reserved_at_0[0x800];
2634 };
2635
2636 struct mlx5_ifc_query_adapter_param_block_bits {
2637         u8         reserved_at_0[0xc0];
2638
2639         u8         reserved_at_c0[0x8];
2640         u8         ieee_vendor_id[0x18];
2641
2642         u8         reserved_at_e0[0x10];
2643         u8         vsd_vendor_id[0x10];
2644
2645         u8         vsd[208][0x8];
2646
2647         u8         vsd_contd_psid[16][0x8];
2648 };
2649
2650 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2651         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2652         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2653         u8         reserved_at_0[0x20];
2654 };
2655
2656 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2657         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2658         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2659         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2660         u8         reserved_at_0[0x20];
2661 };
2662
2663 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2664         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2665         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2666         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2667         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2668         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2669         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2670         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2671         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2672         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2673         u8         reserved_at_0[0x7c0];
2674 };
2675
2676 union mlx5_ifc_event_auto_bits {
2677         struct mlx5_ifc_comp_event_bits comp_event;
2678         struct mlx5_ifc_dct_events_bits dct_events;
2679         struct mlx5_ifc_qp_events_bits qp_events;
2680         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2681         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2682         struct mlx5_ifc_cq_error_bits cq_error;
2683         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2684         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2685         struct mlx5_ifc_gpio_event_bits gpio_event;
2686         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2687         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2688         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2689         u8         reserved_at_0[0xe0];
2690 };
2691
2692 struct mlx5_ifc_health_buffer_bits {
2693         u8         reserved_at_0[0x100];
2694
2695         u8         assert_existptr[0x20];
2696
2697         u8         assert_callra[0x20];
2698
2699         u8         reserved_at_140[0x40];
2700
2701         u8         fw_version[0x20];
2702
2703         u8         hw_id[0x20];
2704
2705         u8         reserved_at_1c0[0x20];
2706
2707         u8         irisc_index[0x8];
2708         u8         synd[0x8];
2709         u8         ext_synd[0x10];
2710 };
2711
2712 struct mlx5_ifc_register_loopback_control_bits {
2713         u8         no_lb[0x1];
2714         u8         reserved_at_1[0x7];
2715         u8         port[0x8];
2716         u8         reserved_at_10[0x10];
2717
2718         u8         reserved_at_20[0x60];
2719 };
2720
2721 struct mlx5_ifc_teardown_hca_out_bits {
2722         u8         status[0x8];
2723         u8         reserved_at_8[0x18];
2724
2725         u8         syndrome[0x20];
2726
2727         u8         reserved_at_40[0x40];
2728 };
2729
2730 enum {
2731         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2732         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2733 };
2734
2735 struct mlx5_ifc_teardown_hca_in_bits {
2736         u8         opcode[0x10];
2737         u8         reserved_at_10[0x10];
2738
2739         u8         reserved_at_20[0x10];
2740         u8         op_mod[0x10];
2741
2742         u8         reserved_at_40[0x10];
2743         u8         profile[0x10];
2744
2745         u8         reserved_at_60[0x20];
2746 };
2747
2748 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2749         u8         status[0x8];
2750         u8         reserved_at_8[0x18];
2751
2752         u8         syndrome[0x20];
2753
2754         u8         reserved_at_40[0x40];
2755 };
2756
2757 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2758         u8         opcode[0x10];
2759         u8         reserved_at_10[0x10];
2760
2761         u8         reserved_at_20[0x10];
2762         u8         op_mod[0x10];
2763
2764         u8         reserved_at_40[0x8];
2765         u8         qpn[0x18];
2766
2767         u8         reserved_at_60[0x20];
2768
2769         u8         opt_param_mask[0x20];
2770
2771         u8         reserved_at_a0[0x20];
2772
2773         struct mlx5_ifc_qpc_bits qpc;
2774
2775         u8         reserved_at_800[0x80];
2776 };
2777
2778 struct mlx5_ifc_sqd2rts_qp_out_bits {
2779         u8         status[0x8];
2780         u8         reserved_at_8[0x18];
2781
2782         u8         syndrome[0x20];
2783
2784         u8         reserved_at_40[0x40];
2785 };
2786
2787 struct mlx5_ifc_sqd2rts_qp_in_bits {
2788         u8         opcode[0x10];
2789         u8         reserved_at_10[0x10];
2790
2791         u8         reserved_at_20[0x10];
2792         u8         op_mod[0x10];
2793
2794         u8         reserved_at_40[0x8];
2795         u8         qpn[0x18];
2796
2797         u8         reserved_at_60[0x20];
2798
2799         u8         opt_param_mask[0x20];
2800
2801         u8         reserved_at_a0[0x20];
2802
2803         struct mlx5_ifc_qpc_bits qpc;
2804
2805         u8         reserved_at_800[0x80];
2806 };
2807
2808 struct mlx5_ifc_set_roce_address_out_bits {
2809         u8         status[0x8];
2810         u8         reserved_at_8[0x18];
2811
2812         u8         syndrome[0x20];
2813
2814         u8         reserved_at_40[0x40];
2815 };
2816
2817 struct mlx5_ifc_set_roce_address_in_bits {
2818         u8         opcode[0x10];
2819         u8         reserved_at_10[0x10];
2820
2821         u8         reserved_at_20[0x10];
2822         u8         op_mod[0x10];
2823
2824         u8         roce_address_index[0x10];
2825         u8         reserved_at_50[0x10];
2826
2827         u8         reserved_at_60[0x20];
2828
2829         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2830 };
2831
2832 struct mlx5_ifc_set_mad_demux_out_bits {
2833         u8         status[0x8];
2834         u8         reserved_at_8[0x18];
2835
2836         u8         syndrome[0x20];
2837
2838         u8         reserved_at_40[0x40];
2839 };
2840
2841 enum {
2842         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2843         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2844 };
2845
2846 struct mlx5_ifc_set_mad_demux_in_bits {
2847         u8         opcode[0x10];
2848         u8         reserved_at_10[0x10];
2849
2850         u8         reserved_at_20[0x10];
2851         u8         op_mod[0x10];
2852
2853         u8         reserved_at_40[0x20];
2854
2855         u8         reserved_at_60[0x6];
2856         u8         demux_mode[0x2];
2857         u8         reserved_at_68[0x18];
2858 };
2859
2860 struct mlx5_ifc_set_l2_table_entry_out_bits {
2861         u8         status[0x8];
2862         u8         reserved_at_8[0x18];
2863
2864         u8         syndrome[0x20];
2865
2866         u8         reserved_at_40[0x40];
2867 };
2868
2869 struct mlx5_ifc_set_l2_table_entry_in_bits {
2870         u8         opcode[0x10];
2871         u8         reserved_at_10[0x10];
2872
2873         u8         reserved_at_20[0x10];
2874         u8         op_mod[0x10];
2875
2876         u8         reserved_at_40[0x60];
2877
2878         u8         reserved_at_a0[0x8];
2879         u8         table_index[0x18];
2880
2881         u8         reserved_at_c0[0x20];
2882
2883         u8         reserved_at_e0[0x13];
2884         u8         vlan_valid[0x1];
2885         u8         vlan[0xc];
2886
2887         struct mlx5_ifc_mac_address_layout_bits mac_address;
2888
2889         u8         reserved_at_140[0xc0];
2890 };
2891
2892 struct mlx5_ifc_set_issi_out_bits {
2893         u8         status[0x8];
2894         u8         reserved_at_8[0x18];
2895
2896         u8         syndrome[0x20];
2897
2898         u8         reserved_at_40[0x40];
2899 };
2900
2901 struct mlx5_ifc_set_issi_in_bits {
2902         u8         opcode[0x10];
2903         u8         reserved_at_10[0x10];
2904
2905         u8         reserved_at_20[0x10];
2906         u8         op_mod[0x10];
2907
2908         u8         reserved_at_40[0x10];
2909         u8         current_issi[0x10];
2910
2911         u8         reserved_at_60[0x20];
2912 };
2913
2914 struct mlx5_ifc_set_hca_cap_out_bits {
2915         u8         status[0x8];
2916         u8         reserved_at_8[0x18];
2917
2918         u8         syndrome[0x20];
2919
2920         u8         reserved_at_40[0x40];
2921 };
2922
2923 struct mlx5_ifc_set_hca_cap_in_bits {
2924         u8         opcode[0x10];
2925         u8         reserved_at_10[0x10];
2926
2927         u8         reserved_at_20[0x10];
2928         u8         op_mod[0x10];
2929
2930         u8         reserved_at_40[0x40];
2931
2932         union mlx5_ifc_hca_cap_union_bits capability;
2933 };
2934
2935 enum {
2936         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
2937         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
2938         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
2939         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
2940 };
2941
2942 struct mlx5_ifc_set_fte_out_bits {
2943         u8         status[0x8];
2944         u8         reserved_at_8[0x18];
2945
2946         u8         syndrome[0x20];
2947
2948         u8         reserved_at_40[0x40];
2949 };
2950
2951 struct mlx5_ifc_set_fte_in_bits {
2952         u8         opcode[0x10];
2953         u8         reserved_at_10[0x10];
2954
2955         u8         reserved_at_20[0x10];
2956         u8         op_mod[0x10];
2957
2958         u8         reserved_at_40[0x40];
2959
2960         u8         table_type[0x8];
2961         u8         reserved_at_88[0x18];
2962
2963         u8         reserved_at_a0[0x8];
2964         u8         table_id[0x18];
2965
2966         u8         reserved_at_c0[0x18];
2967         u8         modify_enable_mask[0x8];
2968
2969         u8         reserved_at_e0[0x20];
2970
2971         u8         flow_index[0x20];
2972
2973         u8         reserved_at_120[0xe0];
2974
2975         struct mlx5_ifc_flow_context_bits flow_context;
2976 };
2977
2978 struct mlx5_ifc_rts2rts_qp_out_bits {
2979         u8         status[0x8];
2980         u8         reserved_at_8[0x18];
2981
2982         u8         syndrome[0x20];
2983
2984         u8         reserved_at_40[0x40];
2985 };
2986
2987 struct mlx5_ifc_rts2rts_qp_in_bits {
2988         u8         opcode[0x10];
2989         u8         reserved_at_10[0x10];
2990
2991         u8         reserved_at_20[0x10];
2992         u8         op_mod[0x10];
2993
2994         u8         reserved_at_40[0x8];
2995         u8         qpn[0x18];
2996
2997         u8         reserved_at_60[0x20];
2998
2999         u8         opt_param_mask[0x20];
3000
3001         u8         reserved_at_a0[0x20];
3002
3003         struct mlx5_ifc_qpc_bits qpc;
3004
3005         u8         reserved_at_800[0x80];
3006 };
3007
3008 struct mlx5_ifc_rtr2rts_qp_out_bits {
3009         u8         status[0x8];
3010         u8         reserved_at_8[0x18];
3011
3012         u8         syndrome[0x20];
3013
3014         u8         reserved_at_40[0x40];
3015 };
3016
3017 struct mlx5_ifc_rtr2rts_qp_in_bits {
3018         u8         opcode[0x10];
3019         u8         reserved_at_10[0x10];
3020
3021         u8         reserved_at_20[0x10];
3022         u8         op_mod[0x10];
3023
3024         u8         reserved_at_40[0x8];
3025         u8         qpn[0x18];
3026
3027         u8         reserved_at_60[0x20];
3028
3029         u8         opt_param_mask[0x20];
3030
3031         u8         reserved_at_a0[0x20];
3032
3033         struct mlx5_ifc_qpc_bits qpc;
3034
3035         u8         reserved_at_800[0x80];
3036 };
3037
3038 struct mlx5_ifc_rst2init_qp_out_bits {
3039         u8         status[0x8];
3040         u8         reserved_at_8[0x18];
3041
3042         u8         syndrome[0x20];
3043
3044         u8         reserved_at_40[0x40];
3045 };
3046
3047 struct mlx5_ifc_rst2init_qp_in_bits {
3048         u8         opcode[0x10];
3049         u8         reserved_at_10[0x10];
3050
3051         u8         reserved_at_20[0x10];
3052         u8         op_mod[0x10];
3053
3054         u8         reserved_at_40[0x8];
3055         u8         qpn[0x18];
3056
3057         u8         reserved_at_60[0x20];
3058
3059         u8         opt_param_mask[0x20];
3060
3061         u8         reserved_at_a0[0x20];
3062
3063         struct mlx5_ifc_qpc_bits qpc;
3064
3065         u8         reserved_at_800[0x80];
3066 };
3067
3068 struct mlx5_ifc_query_xrc_srq_out_bits {
3069         u8         status[0x8];
3070         u8         reserved_at_8[0x18];
3071
3072         u8         syndrome[0x20];
3073
3074         u8         reserved_at_40[0x40];
3075
3076         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3077
3078         u8         reserved_at_280[0x600];
3079
3080         u8         pas[0][0x40];
3081 };
3082
3083 struct mlx5_ifc_query_xrc_srq_in_bits {
3084         u8         opcode[0x10];
3085         u8         reserved_at_10[0x10];
3086
3087         u8         reserved_at_20[0x10];
3088         u8         op_mod[0x10];
3089
3090         u8         reserved_at_40[0x8];
3091         u8         xrc_srqn[0x18];
3092
3093         u8         reserved_at_60[0x20];
3094 };
3095
3096 enum {
3097         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3098         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3099 };
3100
3101 struct mlx5_ifc_query_vport_state_out_bits {
3102         u8         status[0x8];
3103         u8         reserved_at_8[0x18];
3104
3105         u8         syndrome[0x20];
3106
3107         u8         reserved_at_40[0x20];
3108
3109         u8         reserved_at_60[0x18];
3110         u8         admin_state[0x4];
3111         u8         state[0x4];
3112 };
3113
3114 enum {
3115         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3116         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3117 };
3118
3119 struct mlx5_ifc_query_vport_state_in_bits {
3120         u8         opcode[0x10];
3121         u8         reserved_at_10[0x10];
3122
3123         u8         reserved_at_20[0x10];
3124         u8         op_mod[0x10];
3125
3126         u8         other_vport[0x1];
3127         u8         reserved_at_41[0xf];
3128         u8         vport_number[0x10];
3129
3130         u8         reserved_at_60[0x20];
3131 };
3132
3133 struct mlx5_ifc_query_vport_counter_out_bits {
3134         u8         status[0x8];
3135         u8         reserved_at_8[0x18];
3136
3137         u8         syndrome[0x20];
3138
3139         u8         reserved_at_40[0x40];
3140
3141         struct mlx5_ifc_traffic_counter_bits received_errors;
3142
3143         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3144
3145         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3146
3147         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3148
3149         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3150
3151         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3152
3153         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3154
3155         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3156
3157         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3158
3159         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3160
3161         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3162
3163         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3164
3165         u8         reserved_at_680[0xa00];
3166 };
3167
3168 enum {
3169         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3170 };
3171
3172 struct mlx5_ifc_query_vport_counter_in_bits {
3173         u8         opcode[0x10];
3174         u8         reserved_at_10[0x10];
3175
3176         u8         reserved_at_20[0x10];
3177         u8         op_mod[0x10];
3178
3179         u8         other_vport[0x1];
3180         u8         reserved_at_41[0xb];
3181         u8         port_num[0x4];
3182         u8         vport_number[0x10];
3183
3184         u8         reserved_at_60[0x60];
3185
3186         u8         clear[0x1];
3187         u8         reserved_at_c1[0x1f];
3188
3189         u8         reserved_at_e0[0x20];
3190 };
3191
3192 struct mlx5_ifc_query_tis_out_bits {
3193         u8         status[0x8];
3194         u8         reserved_at_8[0x18];
3195
3196         u8         syndrome[0x20];
3197
3198         u8         reserved_at_40[0x40];
3199
3200         struct mlx5_ifc_tisc_bits tis_context;
3201 };
3202
3203 struct mlx5_ifc_query_tis_in_bits {
3204         u8         opcode[0x10];
3205         u8         reserved_at_10[0x10];
3206
3207         u8         reserved_at_20[0x10];
3208         u8         op_mod[0x10];
3209
3210         u8         reserved_at_40[0x8];
3211         u8         tisn[0x18];
3212
3213         u8         reserved_at_60[0x20];
3214 };
3215
3216 struct mlx5_ifc_query_tir_out_bits {
3217         u8         status[0x8];
3218         u8         reserved_at_8[0x18];
3219
3220         u8         syndrome[0x20];
3221
3222         u8         reserved_at_40[0xc0];
3223
3224         struct mlx5_ifc_tirc_bits tir_context;
3225 };
3226
3227 struct mlx5_ifc_query_tir_in_bits {
3228         u8         opcode[0x10];
3229         u8         reserved_at_10[0x10];
3230
3231         u8         reserved_at_20[0x10];
3232         u8         op_mod[0x10];
3233
3234         u8         reserved_at_40[0x8];
3235         u8         tirn[0x18];
3236
3237         u8         reserved_at_60[0x20];
3238 };
3239
3240 struct mlx5_ifc_query_srq_out_bits {
3241         u8         status[0x8];
3242         u8         reserved_at_8[0x18];
3243
3244         u8         syndrome[0x20];
3245
3246         u8         reserved_at_40[0x40];
3247
3248         struct mlx5_ifc_srqc_bits srq_context_entry;
3249
3250         u8         reserved_at_280[0x600];
3251
3252         u8         pas[0][0x40];
3253 };
3254
3255 struct mlx5_ifc_query_srq_in_bits {
3256         u8         opcode[0x10];
3257         u8         reserved_at_10[0x10];
3258
3259         u8         reserved_at_20[0x10];
3260         u8         op_mod[0x10];
3261
3262         u8         reserved_at_40[0x8];
3263         u8         srqn[0x18];
3264
3265         u8         reserved_at_60[0x20];
3266 };
3267
3268 struct mlx5_ifc_query_sq_out_bits {
3269         u8         status[0x8];
3270         u8         reserved_at_8[0x18];
3271
3272         u8         syndrome[0x20];
3273
3274         u8         reserved_at_40[0xc0];
3275
3276         struct mlx5_ifc_sqc_bits sq_context;
3277 };
3278
3279 struct mlx5_ifc_query_sq_in_bits {
3280         u8         opcode[0x10];
3281         u8         reserved_at_10[0x10];
3282
3283         u8         reserved_at_20[0x10];
3284         u8         op_mod[0x10];
3285
3286         u8         reserved_at_40[0x8];
3287         u8         sqn[0x18];
3288
3289         u8         reserved_at_60[0x20];
3290 };
3291
3292 struct mlx5_ifc_query_special_contexts_out_bits {
3293         u8         status[0x8];
3294         u8         reserved_at_8[0x18];
3295
3296         u8         syndrome[0x20];
3297
3298         u8         reserved_at_40[0x20];
3299
3300         u8         resd_lkey[0x20];
3301 };
3302
3303 struct mlx5_ifc_query_special_contexts_in_bits {
3304         u8         opcode[0x10];
3305         u8         reserved_at_10[0x10];
3306
3307         u8         reserved_at_20[0x10];
3308         u8         op_mod[0x10];
3309
3310         u8         reserved_at_40[0x40];
3311 };
3312
3313 struct mlx5_ifc_query_rqt_out_bits {
3314         u8         status[0x8];
3315         u8         reserved_at_8[0x18];
3316
3317         u8         syndrome[0x20];
3318
3319         u8         reserved_at_40[0xc0];
3320
3321         struct mlx5_ifc_rqtc_bits rqt_context;
3322 };
3323
3324 struct mlx5_ifc_query_rqt_in_bits {
3325         u8         opcode[0x10];
3326         u8         reserved_at_10[0x10];
3327
3328         u8         reserved_at_20[0x10];
3329         u8         op_mod[0x10];
3330
3331         u8         reserved_at_40[0x8];
3332         u8         rqtn[0x18];
3333
3334         u8         reserved_at_60[0x20];
3335 };
3336
3337 struct mlx5_ifc_query_rq_out_bits {
3338         u8         status[0x8];
3339         u8         reserved_at_8[0x18];
3340
3341         u8         syndrome[0x20];
3342
3343         u8         reserved_at_40[0xc0];
3344
3345         struct mlx5_ifc_rqc_bits rq_context;
3346 };
3347
3348 struct mlx5_ifc_query_rq_in_bits {
3349         u8         opcode[0x10];
3350         u8         reserved_at_10[0x10];
3351
3352         u8         reserved_at_20[0x10];
3353         u8         op_mod[0x10];
3354
3355         u8         reserved_at_40[0x8];
3356         u8         rqn[0x18];
3357
3358         u8         reserved_at_60[0x20];
3359 };
3360
3361 struct mlx5_ifc_query_roce_address_out_bits {
3362         u8         status[0x8];
3363         u8         reserved_at_8[0x18];
3364
3365         u8         syndrome[0x20];
3366
3367         u8         reserved_at_40[0x40];
3368
3369         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3370 };
3371
3372 struct mlx5_ifc_query_roce_address_in_bits {
3373         u8         opcode[0x10];
3374         u8         reserved_at_10[0x10];
3375
3376         u8         reserved_at_20[0x10];
3377         u8         op_mod[0x10];
3378
3379         u8         roce_address_index[0x10];
3380         u8         reserved_at_50[0x10];
3381
3382         u8         reserved_at_60[0x20];
3383 };
3384
3385 struct mlx5_ifc_query_rmp_out_bits {
3386         u8         status[0x8];
3387         u8         reserved_at_8[0x18];
3388
3389         u8         syndrome[0x20];
3390
3391         u8         reserved_at_40[0xc0];
3392
3393         struct mlx5_ifc_rmpc_bits rmp_context;
3394 };
3395
3396 struct mlx5_ifc_query_rmp_in_bits {
3397         u8         opcode[0x10];
3398         u8         reserved_at_10[0x10];
3399
3400         u8         reserved_at_20[0x10];
3401         u8         op_mod[0x10];
3402
3403         u8         reserved_at_40[0x8];
3404         u8         rmpn[0x18];
3405
3406         u8         reserved_at_60[0x20];
3407 };
3408
3409 struct mlx5_ifc_query_qp_out_bits {
3410         u8         status[0x8];
3411         u8         reserved_at_8[0x18];
3412
3413         u8         syndrome[0x20];
3414
3415         u8         reserved_at_40[0x40];
3416
3417         u8         opt_param_mask[0x20];
3418
3419         u8         reserved_at_a0[0x20];
3420
3421         struct mlx5_ifc_qpc_bits qpc;
3422
3423         u8         reserved_at_800[0x80];
3424
3425         u8         pas[0][0x40];
3426 };
3427
3428 struct mlx5_ifc_query_qp_in_bits {
3429         u8         opcode[0x10];
3430         u8         reserved_at_10[0x10];
3431
3432         u8         reserved_at_20[0x10];
3433         u8         op_mod[0x10];
3434
3435         u8         reserved_at_40[0x8];
3436         u8         qpn[0x18];
3437
3438         u8         reserved_at_60[0x20];
3439 };
3440
3441 struct mlx5_ifc_query_q_counter_out_bits {
3442         u8         status[0x8];
3443         u8         reserved_at_8[0x18];
3444
3445         u8         syndrome[0x20];
3446
3447         u8         reserved_at_40[0x40];
3448
3449         u8         rx_write_requests[0x20];
3450
3451         u8         reserved_at_a0[0x20];
3452
3453         u8         rx_read_requests[0x20];
3454
3455         u8         reserved_at_e0[0x20];
3456
3457         u8         rx_atomic_requests[0x20];
3458
3459         u8         reserved_at_120[0x20];
3460
3461         u8         rx_dct_connect[0x20];
3462
3463         u8         reserved_at_160[0x20];
3464
3465         u8         out_of_buffer[0x20];
3466
3467         u8         reserved_at_1a0[0x20];
3468
3469         u8         out_of_sequence[0x20];
3470
3471         u8         reserved_at_1e0[0x620];
3472 };
3473
3474 struct mlx5_ifc_query_q_counter_in_bits {
3475         u8         opcode[0x10];
3476         u8         reserved_at_10[0x10];
3477
3478         u8         reserved_at_20[0x10];
3479         u8         op_mod[0x10];
3480
3481         u8         reserved_at_40[0x80];
3482
3483         u8         clear[0x1];
3484         u8         reserved_at_c1[0x1f];
3485
3486         u8         reserved_at_e0[0x18];
3487         u8         counter_set_id[0x8];
3488 };
3489
3490 struct mlx5_ifc_query_pages_out_bits {
3491         u8         status[0x8];
3492         u8         reserved_at_8[0x18];
3493
3494         u8         syndrome[0x20];
3495
3496         u8         reserved_at_40[0x10];
3497         u8         function_id[0x10];
3498
3499         u8         num_pages[0x20];
3500 };
3501
3502 enum {
3503         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3504         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3505         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3506 };
3507
3508 struct mlx5_ifc_query_pages_in_bits {
3509         u8         opcode[0x10];
3510         u8         reserved_at_10[0x10];
3511
3512         u8         reserved_at_20[0x10];
3513         u8         op_mod[0x10];
3514
3515         u8         reserved_at_40[0x10];
3516         u8         function_id[0x10];
3517
3518         u8         reserved_at_60[0x20];
3519 };
3520
3521 struct mlx5_ifc_query_nic_vport_context_out_bits {
3522         u8         status[0x8];
3523         u8         reserved_at_8[0x18];
3524
3525         u8         syndrome[0x20];
3526
3527         u8         reserved_at_40[0x40];
3528
3529         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3530 };
3531
3532 struct mlx5_ifc_query_nic_vport_context_in_bits {
3533         u8         opcode[0x10];
3534         u8         reserved_at_10[0x10];
3535
3536         u8         reserved_at_20[0x10];
3537         u8         op_mod[0x10];
3538
3539         u8         other_vport[0x1];
3540         u8         reserved_at_41[0xf];
3541         u8         vport_number[0x10];
3542
3543         u8         reserved_at_60[0x5];
3544         u8         allowed_list_type[0x3];
3545         u8         reserved_at_68[0x18];
3546 };
3547
3548 struct mlx5_ifc_query_mkey_out_bits {
3549         u8         status[0x8];
3550         u8         reserved_at_8[0x18];
3551
3552         u8         syndrome[0x20];
3553
3554         u8         reserved_at_40[0x40];
3555
3556         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3557
3558         u8         reserved_at_280[0x600];
3559
3560         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3561
3562         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3563 };
3564
3565 struct mlx5_ifc_query_mkey_in_bits {
3566         u8         opcode[0x10];
3567         u8         reserved_at_10[0x10];
3568
3569         u8         reserved_at_20[0x10];
3570         u8         op_mod[0x10];
3571
3572         u8         reserved_at_40[0x8];
3573         u8         mkey_index[0x18];
3574
3575         u8         pg_access[0x1];
3576         u8         reserved_at_61[0x1f];
3577 };
3578
3579 struct mlx5_ifc_query_mad_demux_out_bits {
3580         u8         status[0x8];
3581         u8         reserved_at_8[0x18];
3582
3583         u8         syndrome[0x20];
3584
3585         u8         reserved_at_40[0x40];
3586
3587         u8         mad_dumux_parameters_block[0x20];
3588 };
3589
3590 struct mlx5_ifc_query_mad_demux_in_bits {
3591         u8         opcode[0x10];
3592         u8         reserved_at_10[0x10];
3593
3594         u8         reserved_at_20[0x10];
3595         u8         op_mod[0x10];
3596
3597         u8         reserved_at_40[0x40];
3598 };
3599
3600 struct mlx5_ifc_query_l2_table_entry_out_bits {
3601         u8         status[0x8];
3602         u8         reserved_at_8[0x18];
3603
3604         u8         syndrome[0x20];
3605
3606         u8         reserved_at_40[0xa0];
3607
3608         u8         reserved_at_e0[0x13];
3609         u8         vlan_valid[0x1];
3610         u8         vlan[0xc];
3611
3612         struct mlx5_ifc_mac_address_layout_bits mac_address;
3613
3614         u8         reserved_at_140[0xc0];
3615 };
3616
3617 struct mlx5_ifc_query_l2_table_entry_in_bits {
3618         u8         opcode[0x10];
3619         u8         reserved_at_10[0x10];
3620
3621         u8         reserved_at_20[0x10];
3622         u8         op_mod[0x10];
3623
3624         u8         reserved_at_40[0x60];
3625
3626         u8         reserved_at_a0[0x8];
3627         u8         table_index[0x18];
3628
3629         u8         reserved_at_c0[0x140];
3630 };
3631
3632 struct mlx5_ifc_query_issi_out_bits {
3633         u8         status[0x8];
3634         u8         reserved_at_8[0x18];
3635
3636         u8         syndrome[0x20];
3637
3638         u8         reserved_at_40[0x10];
3639         u8         current_issi[0x10];
3640
3641         u8         reserved_at_60[0xa0];
3642
3643         u8         reserved_at_100[76][0x8];
3644         u8         supported_issi_dw0[0x20];
3645 };
3646
3647 struct mlx5_ifc_query_issi_in_bits {
3648         u8         opcode[0x10];
3649         u8         reserved_at_10[0x10];
3650
3651         u8         reserved_at_20[0x10];
3652         u8         op_mod[0x10];
3653
3654         u8         reserved_at_40[0x40];
3655 };
3656
3657 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3658         u8         status[0x8];
3659         u8         reserved_at_8[0x18];
3660
3661         u8         syndrome[0x20];
3662
3663         u8         reserved_at_40[0x40];
3664
3665         struct mlx5_ifc_pkey_bits pkey[0];
3666 };
3667
3668 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3669         u8         opcode[0x10];
3670         u8         reserved_at_10[0x10];
3671
3672         u8         reserved_at_20[0x10];
3673         u8         op_mod[0x10];
3674
3675         u8         other_vport[0x1];
3676         u8         reserved_at_41[0xb];
3677         u8         port_num[0x4];
3678         u8         vport_number[0x10];
3679
3680         u8         reserved_at_60[0x10];
3681         u8         pkey_index[0x10];
3682 };
3683
3684 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3685         u8         status[0x8];
3686         u8         reserved_at_8[0x18];
3687
3688         u8         syndrome[0x20];
3689
3690         u8         reserved_at_40[0x20];
3691
3692         u8         gids_num[0x10];
3693         u8         reserved_at_70[0x10];
3694
3695         struct mlx5_ifc_array128_auto_bits gid[0];
3696 };
3697
3698 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3699         u8         opcode[0x10];
3700         u8         reserved_at_10[0x10];
3701
3702         u8         reserved_at_20[0x10];
3703         u8         op_mod[0x10];
3704
3705         u8         other_vport[0x1];
3706         u8         reserved_at_41[0xb];
3707         u8         port_num[0x4];
3708         u8         vport_number[0x10];
3709
3710         u8         reserved_at_60[0x10];
3711         u8         gid_index[0x10];
3712 };
3713
3714 struct mlx5_ifc_query_hca_vport_context_out_bits {
3715         u8         status[0x8];
3716         u8         reserved_at_8[0x18];
3717
3718         u8         syndrome[0x20];
3719
3720         u8         reserved_at_40[0x40];
3721
3722         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3723 };
3724
3725 struct mlx5_ifc_query_hca_vport_context_in_bits {
3726         u8         opcode[0x10];
3727         u8         reserved_at_10[0x10];
3728
3729         u8         reserved_at_20[0x10];
3730         u8         op_mod[0x10];
3731
3732         u8         other_vport[0x1];
3733         u8         reserved_at_41[0xb];
3734         u8         port_num[0x4];
3735         u8         vport_number[0x10];
3736
3737         u8         reserved_at_60[0x20];
3738 };
3739
3740 struct mlx5_ifc_query_hca_cap_out_bits {
3741         u8         status[0x8];
3742         u8         reserved_at_8[0x18];
3743
3744         u8         syndrome[0x20];
3745
3746         u8         reserved_at_40[0x40];
3747
3748         union mlx5_ifc_hca_cap_union_bits capability;
3749 };
3750
3751 struct mlx5_ifc_query_hca_cap_in_bits {
3752         u8         opcode[0x10];
3753         u8         reserved_at_10[0x10];
3754
3755         u8         reserved_at_20[0x10];
3756         u8         op_mod[0x10];
3757
3758         u8         reserved_at_40[0x40];
3759 };
3760
3761 struct mlx5_ifc_query_flow_table_out_bits {
3762         u8         status[0x8];
3763         u8         reserved_at_8[0x18];
3764
3765         u8         syndrome[0x20];
3766
3767         u8         reserved_at_40[0x80];
3768
3769         u8         reserved_at_c0[0x8];
3770         u8         level[0x8];
3771         u8         reserved_at_d0[0x8];
3772         u8         log_size[0x8];
3773
3774         u8         reserved_at_e0[0x120];
3775 };
3776
3777 struct mlx5_ifc_query_flow_table_in_bits {
3778         u8         opcode[0x10];
3779         u8         reserved_at_10[0x10];
3780
3781         u8         reserved_at_20[0x10];
3782         u8         op_mod[0x10];
3783
3784         u8         reserved_at_40[0x40];
3785
3786         u8         table_type[0x8];
3787         u8         reserved_at_88[0x18];
3788
3789         u8         reserved_at_a0[0x8];
3790         u8         table_id[0x18];
3791
3792         u8         reserved_at_c0[0x140];
3793 };
3794
3795 struct mlx5_ifc_query_fte_out_bits {
3796         u8         status[0x8];
3797         u8         reserved_at_8[0x18];
3798
3799         u8         syndrome[0x20];
3800
3801         u8         reserved_at_40[0x1c0];
3802
3803         struct mlx5_ifc_flow_context_bits flow_context;
3804 };
3805
3806 struct mlx5_ifc_query_fte_in_bits {
3807         u8         opcode[0x10];
3808         u8         reserved_at_10[0x10];
3809
3810         u8         reserved_at_20[0x10];
3811         u8         op_mod[0x10];
3812
3813         u8         reserved_at_40[0x40];
3814
3815         u8         table_type[0x8];
3816         u8         reserved_at_88[0x18];
3817
3818         u8         reserved_at_a0[0x8];
3819         u8         table_id[0x18];
3820
3821         u8         reserved_at_c0[0x40];
3822
3823         u8         flow_index[0x20];
3824
3825         u8         reserved_at_120[0xe0];
3826 };
3827
3828 enum {
3829         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3830         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3831         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3832 };
3833
3834 struct mlx5_ifc_query_flow_group_out_bits {
3835         u8         status[0x8];
3836         u8         reserved_at_8[0x18];
3837
3838         u8         syndrome[0x20];
3839
3840         u8         reserved_at_40[0xa0];
3841
3842         u8         start_flow_index[0x20];
3843
3844         u8         reserved_at_100[0x20];
3845
3846         u8         end_flow_index[0x20];
3847
3848         u8         reserved_at_140[0xa0];
3849
3850         u8         reserved_at_1e0[0x18];
3851         u8         match_criteria_enable[0x8];
3852
3853         struct mlx5_ifc_fte_match_param_bits match_criteria;
3854
3855         u8         reserved_at_1200[0xe00];
3856 };
3857
3858 struct mlx5_ifc_query_flow_group_in_bits {
3859         u8         opcode[0x10];
3860         u8         reserved_at_10[0x10];
3861
3862         u8         reserved_at_20[0x10];
3863         u8         op_mod[0x10];
3864
3865         u8         reserved_at_40[0x40];
3866
3867         u8         table_type[0x8];
3868         u8         reserved_at_88[0x18];
3869
3870         u8         reserved_at_a0[0x8];
3871         u8         table_id[0x18];
3872
3873         u8         group_id[0x20];
3874
3875         u8         reserved_at_e0[0x120];
3876 };
3877
3878 struct mlx5_ifc_query_esw_vport_context_out_bits {
3879         u8         status[0x8];
3880         u8         reserved_at_8[0x18];
3881
3882         u8         syndrome[0x20];
3883
3884         u8         reserved_at_40[0x40];
3885
3886         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3887 };
3888
3889 struct mlx5_ifc_query_esw_vport_context_in_bits {
3890         u8         opcode[0x10];
3891         u8         reserved_at_10[0x10];
3892
3893         u8         reserved_at_20[0x10];
3894         u8         op_mod[0x10];
3895
3896         u8         other_vport[0x1];
3897         u8         reserved_at_41[0xf];
3898         u8         vport_number[0x10];
3899
3900         u8         reserved_at_60[0x20];
3901 };
3902
3903 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3904         u8         status[0x8];
3905         u8         reserved_at_8[0x18];
3906
3907         u8         syndrome[0x20];
3908
3909         u8         reserved_at_40[0x40];
3910 };
3911
3912 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3913         u8         reserved_at_0[0x1c];
3914         u8         vport_cvlan_insert[0x1];
3915         u8         vport_svlan_insert[0x1];
3916         u8         vport_cvlan_strip[0x1];
3917         u8         vport_svlan_strip[0x1];
3918 };
3919
3920 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3921         u8         opcode[0x10];
3922         u8         reserved_at_10[0x10];
3923
3924         u8         reserved_at_20[0x10];
3925         u8         op_mod[0x10];
3926
3927         u8         other_vport[0x1];
3928         u8         reserved_at_41[0xf];
3929         u8         vport_number[0x10];
3930
3931         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3932
3933         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3934 };
3935
3936 struct mlx5_ifc_query_eq_out_bits {
3937         u8         status[0x8];
3938         u8         reserved_at_8[0x18];
3939
3940         u8         syndrome[0x20];
3941
3942         u8         reserved_at_40[0x40];
3943
3944         struct mlx5_ifc_eqc_bits eq_context_entry;
3945
3946         u8         reserved_at_280[0x40];
3947
3948         u8         event_bitmask[0x40];
3949
3950         u8         reserved_at_300[0x580];
3951
3952         u8         pas[0][0x40];
3953 };
3954
3955 struct mlx5_ifc_query_eq_in_bits {
3956         u8         opcode[0x10];
3957         u8         reserved_at_10[0x10];
3958
3959         u8         reserved_at_20[0x10];
3960         u8         op_mod[0x10];
3961
3962         u8         reserved_at_40[0x18];
3963         u8         eq_number[0x8];
3964
3965         u8         reserved_at_60[0x20];
3966 };
3967
3968 struct mlx5_ifc_query_dct_out_bits {
3969         u8         status[0x8];
3970         u8         reserved_at_8[0x18];
3971
3972         u8         syndrome[0x20];
3973
3974         u8         reserved_at_40[0x40];
3975
3976         struct mlx5_ifc_dctc_bits dct_context_entry;
3977
3978         u8         reserved_at_280[0x180];
3979 };
3980
3981 struct mlx5_ifc_query_dct_in_bits {
3982         u8         opcode[0x10];
3983         u8         reserved_at_10[0x10];
3984
3985         u8         reserved_at_20[0x10];
3986         u8         op_mod[0x10];
3987
3988         u8         reserved_at_40[0x8];
3989         u8         dctn[0x18];
3990
3991         u8         reserved_at_60[0x20];
3992 };
3993
3994 struct mlx5_ifc_query_cq_out_bits {
3995         u8         status[0x8];
3996         u8         reserved_at_8[0x18];
3997
3998         u8         syndrome[0x20];
3999
4000         u8         reserved_at_40[0x40];
4001
4002         struct mlx5_ifc_cqc_bits cq_context;
4003
4004         u8         reserved_at_280[0x600];
4005
4006         u8         pas[0][0x40];
4007 };
4008
4009 struct mlx5_ifc_query_cq_in_bits {
4010         u8         opcode[0x10];
4011         u8         reserved_at_10[0x10];
4012
4013         u8         reserved_at_20[0x10];
4014         u8         op_mod[0x10];
4015
4016         u8         reserved_at_40[0x8];
4017         u8         cqn[0x18];
4018
4019         u8         reserved_at_60[0x20];
4020 };
4021
4022 struct mlx5_ifc_query_cong_status_out_bits {
4023         u8         status[0x8];
4024         u8         reserved_at_8[0x18];
4025
4026         u8         syndrome[0x20];
4027
4028         u8         reserved_at_40[0x20];
4029
4030         u8         enable[0x1];
4031         u8         tag_enable[0x1];
4032         u8         reserved_at_62[0x1e];
4033 };
4034
4035 struct mlx5_ifc_query_cong_status_in_bits {
4036         u8         opcode[0x10];
4037         u8         reserved_at_10[0x10];
4038
4039         u8         reserved_at_20[0x10];
4040         u8         op_mod[0x10];
4041
4042         u8         reserved_at_40[0x18];
4043         u8         priority[0x4];
4044         u8         cong_protocol[0x4];
4045
4046         u8         reserved_at_60[0x20];
4047 };
4048
4049 struct mlx5_ifc_query_cong_statistics_out_bits {
4050         u8         status[0x8];
4051         u8         reserved_at_8[0x18];
4052
4053         u8         syndrome[0x20];
4054
4055         u8         reserved_at_40[0x40];
4056
4057         u8         cur_flows[0x20];
4058
4059         u8         sum_flows[0x20];
4060
4061         u8         cnp_ignored_high[0x20];
4062
4063         u8         cnp_ignored_low[0x20];
4064
4065         u8         cnp_handled_high[0x20];
4066
4067         u8         cnp_handled_low[0x20];
4068
4069         u8         reserved_at_140[0x100];
4070
4071         u8         time_stamp_high[0x20];
4072
4073         u8         time_stamp_low[0x20];
4074
4075         u8         accumulators_period[0x20];
4076
4077         u8         ecn_marked_roce_packets_high[0x20];
4078
4079         u8         ecn_marked_roce_packets_low[0x20];
4080
4081         u8         cnps_sent_high[0x20];
4082
4083         u8         cnps_sent_low[0x20];
4084
4085         u8         reserved_at_320[0x560];
4086 };
4087
4088 struct mlx5_ifc_query_cong_statistics_in_bits {
4089         u8         opcode[0x10];
4090         u8         reserved_at_10[0x10];
4091
4092         u8         reserved_at_20[0x10];
4093         u8         op_mod[0x10];
4094
4095         u8         clear[0x1];
4096         u8         reserved_at_41[0x1f];
4097
4098         u8         reserved_at_60[0x20];
4099 };
4100
4101 struct mlx5_ifc_query_cong_params_out_bits {
4102         u8         status[0x8];
4103         u8         reserved_at_8[0x18];
4104
4105         u8         syndrome[0x20];
4106
4107         u8         reserved_at_40[0x40];
4108
4109         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4110 };
4111
4112 struct mlx5_ifc_query_cong_params_in_bits {
4113         u8         opcode[0x10];
4114         u8         reserved_at_10[0x10];
4115
4116         u8         reserved_at_20[0x10];
4117         u8         op_mod[0x10];
4118
4119         u8         reserved_at_40[0x1c];
4120         u8         cong_protocol[0x4];
4121
4122         u8         reserved_at_60[0x20];
4123 };
4124
4125 struct mlx5_ifc_query_adapter_out_bits {
4126         u8         status[0x8];
4127         u8         reserved_at_8[0x18];
4128
4129         u8         syndrome[0x20];
4130
4131         u8         reserved_at_40[0x40];
4132
4133         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4134 };
4135
4136 struct mlx5_ifc_query_adapter_in_bits {
4137         u8         opcode[0x10];
4138         u8         reserved_at_10[0x10];
4139
4140         u8         reserved_at_20[0x10];
4141         u8         op_mod[0x10];
4142
4143         u8         reserved_at_40[0x40];
4144 };
4145
4146 struct mlx5_ifc_qp_2rst_out_bits {
4147         u8         status[0x8];
4148         u8         reserved_at_8[0x18];
4149
4150         u8         syndrome[0x20];
4151
4152         u8         reserved_at_40[0x40];
4153 };
4154
4155 struct mlx5_ifc_qp_2rst_in_bits {
4156         u8         opcode[0x10];
4157         u8         reserved_at_10[0x10];
4158
4159         u8         reserved_at_20[0x10];
4160         u8         op_mod[0x10];
4161
4162         u8         reserved_at_40[0x8];
4163         u8         qpn[0x18];
4164
4165         u8         reserved_at_60[0x20];
4166 };
4167
4168 struct mlx5_ifc_qp_2err_out_bits {
4169         u8         status[0x8];
4170         u8         reserved_at_8[0x18];
4171
4172         u8         syndrome[0x20];
4173
4174         u8         reserved_at_40[0x40];
4175 };
4176
4177 struct mlx5_ifc_qp_2err_in_bits {
4178         u8         opcode[0x10];
4179         u8         reserved_at_10[0x10];
4180
4181         u8         reserved_at_20[0x10];
4182         u8         op_mod[0x10];
4183
4184         u8         reserved_at_40[0x8];
4185         u8         qpn[0x18];
4186
4187         u8         reserved_at_60[0x20];
4188 };
4189
4190 struct mlx5_ifc_page_fault_resume_out_bits {
4191         u8         status[0x8];
4192         u8         reserved_at_8[0x18];
4193
4194         u8         syndrome[0x20];
4195
4196         u8         reserved_at_40[0x40];
4197 };
4198
4199 struct mlx5_ifc_page_fault_resume_in_bits {
4200         u8         opcode[0x10];
4201         u8         reserved_at_10[0x10];
4202
4203         u8         reserved_at_20[0x10];
4204         u8         op_mod[0x10];
4205
4206         u8         error[0x1];
4207         u8         reserved_at_41[0x4];
4208         u8         rdma[0x1];
4209         u8         read_write[0x1];
4210         u8         req_res[0x1];
4211         u8         qpn[0x18];
4212
4213         u8         reserved_at_60[0x20];
4214 };
4215
4216 struct mlx5_ifc_nop_out_bits {
4217         u8         status[0x8];
4218         u8         reserved_at_8[0x18];
4219
4220         u8         syndrome[0x20];
4221
4222         u8         reserved_at_40[0x40];
4223 };
4224
4225 struct mlx5_ifc_nop_in_bits {
4226         u8         opcode[0x10];
4227         u8         reserved_at_10[0x10];
4228
4229         u8         reserved_at_20[0x10];
4230         u8         op_mod[0x10];
4231
4232         u8         reserved_at_40[0x40];
4233 };
4234
4235 struct mlx5_ifc_modify_vport_state_out_bits {
4236         u8         status[0x8];
4237         u8         reserved_at_8[0x18];
4238
4239         u8         syndrome[0x20];
4240
4241         u8         reserved_at_40[0x40];
4242 };
4243
4244 struct mlx5_ifc_modify_vport_state_in_bits {
4245         u8         opcode[0x10];
4246         u8         reserved_at_10[0x10];
4247
4248         u8         reserved_at_20[0x10];
4249         u8         op_mod[0x10];
4250
4251         u8         other_vport[0x1];
4252         u8         reserved_at_41[0xf];
4253         u8         vport_number[0x10];
4254
4255         u8         reserved_at_60[0x18];
4256         u8         admin_state[0x4];
4257         u8         reserved_at_7c[0x4];
4258 };
4259
4260 struct mlx5_ifc_modify_tis_out_bits {
4261         u8         status[0x8];
4262         u8         reserved_at_8[0x18];
4263
4264         u8         syndrome[0x20];
4265
4266         u8         reserved_at_40[0x40];
4267 };
4268
4269 struct mlx5_ifc_modify_tis_bitmask_bits {
4270         u8         reserved_at_0[0x20];
4271
4272         u8         reserved_at_20[0x1f];
4273         u8         prio[0x1];
4274 };
4275
4276 struct mlx5_ifc_modify_tis_in_bits {
4277         u8         opcode[0x10];
4278         u8         reserved_at_10[0x10];
4279
4280         u8         reserved_at_20[0x10];
4281         u8         op_mod[0x10];
4282
4283         u8         reserved_at_40[0x8];
4284         u8         tisn[0x18];
4285
4286         u8         reserved_at_60[0x20];
4287
4288         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4289
4290         u8         reserved_at_c0[0x40];
4291
4292         struct mlx5_ifc_tisc_bits ctx;
4293 };
4294
4295 struct mlx5_ifc_modify_tir_bitmask_bits {
4296         u8         reserved_at_0[0x20];
4297
4298         u8         reserved_at_20[0x1b];
4299         u8         self_lb_en[0x1];
4300         u8         reserved_at_3c[0x1];
4301         u8         hash[0x1];
4302         u8         reserved_at_3e[0x1];
4303         u8         lro[0x1];
4304 };
4305
4306 struct mlx5_ifc_modify_tir_out_bits {
4307         u8         status[0x8];
4308         u8         reserved_at_8[0x18];
4309
4310         u8         syndrome[0x20];
4311
4312         u8         reserved_at_40[0x40];
4313 };
4314
4315 struct mlx5_ifc_modify_tir_in_bits {
4316         u8         opcode[0x10];
4317         u8         reserved_at_10[0x10];
4318
4319         u8         reserved_at_20[0x10];
4320         u8         op_mod[0x10];
4321
4322         u8         reserved_at_40[0x8];
4323         u8         tirn[0x18];
4324
4325         u8         reserved_at_60[0x20];
4326
4327         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4328
4329         u8         reserved_at_c0[0x40];
4330
4331         struct mlx5_ifc_tirc_bits ctx;
4332 };
4333
4334 struct mlx5_ifc_modify_sq_out_bits {
4335         u8         status[0x8];
4336         u8         reserved_at_8[0x18];
4337
4338         u8         syndrome[0x20];
4339
4340         u8         reserved_at_40[0x40];
4341 };
4342
4343 struct mlx5_ifc_modify_sq_in_bits {
4344         u8         opcode[0x10];
4345         u8         reserved_at_10[0x10];
4346
4347         u8         reserved_at_20[0x10];
4348         u8         op_mod[0x10];
4349
4350         u8         sq_state[0x4];
4351         u8         reserved_at_44[0x4];
4352         u8         sqn[0x18];
4353
4354         u8         reserved_at_60[0x20];
4355
4356         u8         modify_bitmask[0x40];
4357
4358         u8         reserved_at_c0[0x40];
4359
4360         struct mlx5_ifc_sqc_bits ctx;
4361 };
4362
4363 struct mlx5_ifc_modify_rqt_out_bits {
4364         u8         status[0x8];
4365         u8         reserved_at_8[0x18];
4366
4367         u8         syndrome[0x20];
4368
4369         u8         reserved_at_40[0x40];
4370 };
4371
4372 struct mlx5_ifc_rqt_bitmask_bits {
4373         u8         reserved_at_0[0x20];
4374
4375         u8         reserved_at_20[0x1f];
4376         u8         rqn_list[0x1];
4377 };
4378
4379 struct mlx5_ifc_modify_rqt_in_bits {
4380         u8         opcode[0x10];
4381         u8         reserved_at_10[0x10];
4382
4383         u8         reserved_at_20[0x10];
4384         u8         op_mod[0x10];
4385
4386         u8         reserved_at_40[0x8];
4387         u8         rqtn[0x18];
4388
4389         u8         reserved_at_60[0x20];
4390
4391         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4392
4393         u8         reserved_at_c0[0x40];
4394
4395         struct mlx5_ifc_rqtc_bits ctx;
4396 };
4397
4398 struct mlx5_ifc_modify_rq_out_bits {
4399         u8         status[0x8];
4400         u8         reserved_at_8[0x18];
4401
4402         u8         syndrome[0x20];
4403
4404         u8         reserved_at_40[0x40];
4405 };
4406
4407 struct mlx5_ifc_modify_rq_in_bits {
4408         u8         opcode[0x10];
4409         u8         reserved_at_10[0x10];
4410
4411         u8         reserved_at_20[0x10];
4412         u8         op_mod[0x10];
4413
4414         u8         rq_state[0x4];
4415         u8         reserved_at_44[0x4];
4416         u8         rqn[0x18];
4417
4418         u8         reserved_at_60[0x20];
4419
4420         u8         modify_bitmask[0x40];
4421
4422         u8         reserved_at_c0[0x40];
4423
4424         struct mlx5_ifc_rqc_bits ctx;
4425 };
4426
4427 struct mlx5_ifc_modify_rmp_out_bits {
4428         u8         status[0x8];
4429         u8         reserved_at_8[0x18];
4430
4431         u8         syndrome[0x20];
4432
4433         u8         reserved_at_40[0x40];
4434 };
4435
4436 struct mlx5_ifc_rmp_bitmask_bits {
4437         u8         reserved_at_0[0x20];
4438
4439         u8         reserved_at_20[0x1f];
4440         u8         lwm[0x1];
4441 };
4442
4443 struct mlx5_ifc_modify_rmp_in_bits {
4444         u8         opcode[0x10];
4445         u8         reserved_at_10[0x10];
4446
4447         u8         reserved_at_20[0x10];
4448         u8         op_mod[0x10];
4449
4450         u8         rmp_state[0x4];
4451         u8         reserved_at_44[0x4];
4452         u8         rmpn[0x18];
4453
4454         u8         reserved_at_60[0x20];
4455
4456         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4457
4458         u8         reserved_at_c0[0x40];
4459
4460         struct mlx5_ifc_rmpc_bits ctx;
4461 };
4462
4463 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4464         u8         status[0x8];
4465         u8         reserved_at_8[0x18];
4466
4467         u8         syndrome[0x20];
4468
4469         u8         reserved_at_40[0x40];
4470 };
4471
4472 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4473         u8         reserved_at_0[0x19];
4474         u8         mtu[0x1];
4475         u8         change_event[0x1];
4476         u8         promisc[0x1];
4477         u8         permanent_address[0x1];
4478         u8         addresses_list[0x1];
4479         u8         roce_en[0x1];
4480         u8         reserved_at_1f[0x1];
4481 };
4482
4483 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4484         u8         opcode[0x10];
4485         u8         reserved_at_10[0x10];
4486
4487         u8         reserved_at_20[0x10];
4488         u8         op_mod[0x10];
4489
4490         u8         other_vport[0x1];
4491         u8         reserved_at_41[0xf];
4492         u8         vport_number[0x10];
4493
4494         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4495
4496         u8         reserved_at_80[0x780];
4497
4498         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4499 };
4500
4501 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4502         u8         status[0x8];
4503         u8         reserved_at_8[0x18];
4504
4505         u8         syndrome[0x20];
4506
4507         u8         reserved_at_40[0x40];
4508 };
4509
4510 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4511         u8         opcode[0x10];
4512         u8         reserved_at_10[0x10];
4513
4514         u8         reserved_at_20[0x10];
4515         u8         op_mod[0x10];
4516
4517         u8         other_vport[0x1];
4518         u8         reserved_at_41[0xb];
4519         u8         port_num[0x4];
4520         u8         vport_number[0x10];
4521
4522         u8         reserved_at_60[0x20];
4523
4524         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4525 };
4526
4527 struct mlx5_ifc_modify_cq_out_bits {
4528         u8         status[0x8];
4529         u8         reserved_at_8[0x18];
4530
4531         u8         syndrome[0x20];
4532
4533         u8         reserved_at_40[0x40];
4534 };
4535
4536 enum {
4537         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4538         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4539 };
4540
4541 struct mlx5_ifc_modify_cq_in_bits {
4542         u8         opcode[0x10];
4543         u8         reserved_at_10[0x10];
4544
4545         u8         reserved_at_20[0x10];
4546         u8         op_mod[0x10];
4547
4548         u8         reserved_at_40[0x8];
4549         u8         cqn[0x18];
4550
4551         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4552
4553         struct mlx5_ifc_cqc_bits cq_context;
4554
4555         u8         reserved_at_280[0x600];
4556
4557         u8         pas[0][0x40];
4558 };
4559
4560 struct mlx5_ifc_modify_cong_status_out_bits {
4561         u8         status[0x8];
4562         u8         reserved_at_8[0x18];
4563
4564         u8         syndrome[0x20];
4565
4566         u8         reserved_at_40[0x40];
4567 };
4568
4569 struct mlx5_ifc_modify_cong_status_in_bits {
4570         u8         opcode[0x10];
4571         u8         reserved_at_10[0x10];
4572
4573         u8         reserved_at_20[0x10];
4574         u8         op_mod[0x10];
4575
4576         u8         reserved_at_40[0x18];
4577         u8         priority[0x4];
4578         u8         cong_protocol[0x4];
4579
4580         u8         enable[0x1];
4581         u8         tag_enable[0x1];
4582         u8         reserved_at_62[0x1e];
4583 };
4584
4585 struct mlx5_ifc_modify_cong_params_out_bits {
4586         u8         status[0x8];
4587         u8         reserved_at_8[0x18];
4588
4589         u8         syndrome[0x20];
4590
4591         u8         reserved_at_40[0x40];
4592 };
4593
4594 struct mlx5_ifc_modify_cong_params_in_bits {
4595         u8         opcode[0x10];
4596         u8         reserved_at_10[0x10];
4597
4598         u8         reserved_at_20[0x10];
4599         u8         op_mod[0x10];
4600
4601         u8         reserved_at_40[0x1c];
4602         u8         cong_protocol[0x4];
4603
4604         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4605
4606         u8         reserved_at_80[0x80];
4607
4608         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4609 };
4610
4611 struct mlx5_ifc_manage_pages_out_bits {
4612         u8         status[0x8];
4613         u8         reserved_at_8[0x18];
4614
4615         u8         syndrome[0x20];
4616
4617         u8         output_num_entries[0x20];
4618
4619         u8         reserved_at_60[0x20];
4620
4621         u8         pas[0][0x40];
4622 };
4623
4624 enum {
4625         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4626         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4627         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4628 };
4629
4630 struct mlx5_ifc_manage_pages_in_bits {
4631         u8         opcode[0x10];
4632         u8         reserved_at_10[0x10];
4633
4634         u8         reserved_at_20[0x10];
4635         u8         op_mod[0x10];
4636
4637         u8         reserved_at_40[0x10];
4638         u8         function_id[0x10];
4639
4640         u8         input_num_entries[0x20];
4641
4642         u8         pas[0][0x40];
4643 };
4644
4645 struct mlx5_ifc_mad_ifc_out_bits {
4646         u8         status[0x8];
4647         u8         reserved_at_8[0x18];
4648
4649         u8         syndrome[0x20];
4650
4651         u8         reserved_at_40[0x40];
4652
4653         u8         response_mad_packet[256][0x8];
4654 };
4655
4656 struct mlx5_ifc_mad_ifc_in_bits {
4657         u8         opcode[0x10];
4658         u8         reserved_at_10[0x10];
4659
4660         u8         reserved_at_20[0x10];
4661         u8         op_mod[0x10];
4662
4663         u8         remote_lid[0x10];
4664         u8         reserved_at_50[0x8];
4665         u8         port[0x8];
4666
4667         u8         reserved_at_60[0x20];
4668
4669         u8         mad[256][0x8];
4670 };
4671
4672 struct mlx5_ifc_init_hca_out_bits {
4673         u8         status[0x8];
4674         u8         reserved_at_8[0x18];
4675
4676         u8         syndrome[0x20];
4677
4678         u8         reserved_at_40[0x40];
4679 };
4680
4681 struct mlx5_ifc_init_hca_in_bits {
4682         u8         opcode[0x10];
4683         u8         reserved_at_10[0x10];
4684
4685         u8         reserved_at_20[0x10];
4686         u8         op_mod[0x10];
4687
4688         u8         reserved_at_40[0x40];
4689 };
4690
4691 struct mlx5_ifc_init2rtr_qp_out_bits {
4692         u8         status[0x8];
4693         u8         reserved_at_8[0x18];
4694
4695         u8         syndrome[0x20];
4696
4697         u8         reserved_at_40[0x40];
4698 };
4699
4700 struct mlx5_ifc_init2rtr_qp_in_bits {
4701         u8         opcode[0x10];
4702         u8         reserved_at_10[0x10];
4703
4704         u8         reserved_at_20[0x10];
4705         u8         op_mod[0x10];
4706
4707         u8         reserved_at_40[0x8];
4708         u8         qpn[0x18];
4709
4710         u8         reserved_at_60[0x20];
4711
4712         u8         opt_param_mask[0x20];
4713
4714         u8         reserved_at_a0[0x20];
4715
4716         struct mlx5_ifc_qpc_bits qpc;
4717
4718         u8         reserved_at_800[0x80];
4719 };
4720
4721 struct mlx5_ifc_init2init_qp_out_bits {
4722         u8         status[0x8];
4723         u8         reserved_at_8[0x18];
4724
4725         u8         syndrome[0x20];
4726
4727         u8         reserved_at_40[0x40];
4728 };
4729
4730 struct mlx5_ifc_init2init_qp_in_bits {
4731         u8         opcode[0x10];
4732         u8         reserved_at_10[0x10];
4733
4734         u8         reserved_at_20[0x10];
4735         u8         op_mod[0x10];
4736
4737         u8         reserved_at_40[0x8];
4738         u8         qpn[0x18];
4739
4740         u8         reserved_at_60[0x20];
4741
4742         u8         opt_param_mask[0x20];
4743
4744         u8         reserved_at_a0[0x20];
4745
4746         struct mlx5_ifc_qpc_bits qpc;
4747
4748         u8         reserved_at_800[0x80];
4749 };
4750
4751 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4752         u8         status[0x8];
4753         u8         reserved_at_8[0x18];
4754
4755         u8         syndrome[0x20];
4756
4757         u8         reserved_at_40[0x40];
4758
4759         u8         packet_headers_log[128][0x8];
4760
4761         u8         packet_syndrome[64][0x8];
4762 };
4763
4764 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4765         u8         opcode[0x10];
4766         u8         reserved_at_10[0x10];
4767
4768         u8         reserved_at_20[0x10];
4769         u8         op_mod[0x10];
4770
4771         u8         reserved_at_40[0x40];
4772 };
4773
4774 struct mlx5_ifc_gen_eqe_in_bits {
4775         u8         opcode[0x10];
4776         u8         reserved_at_10[0x10];
4777
4778         u8         reserved_at_20[0x10];
4779         u8         op_mod[0x10];
4780
4781         u8         reserved_at_40[0x18];
4782         u8         eq_number[0x8];
4783
4784         u8         reserved_at_60[0x20];
4785
4786         u8         eqe[64][0x8];
4787 };
4788
4789 struct mlx5_ifc_gen_eq_out_bits {
4790         u8         status[0x8];
4791         u8         reserved_at_8[0x18];
4792
4793         u8         syndrome[0x20];
4794
4795         u8         reserved_at_40[0x40];
4796 };
4797
4798 struct mlx5_ifc_enable_hca_out_bits {
4799         u8         status[0x8];
4800         u8         reserved_at_8[0x18];
4801
4802         u8         syndrome[0x20];
4803
4804         u8         reserved_at_40[0x20];
4805 };
4806
4807 struct mlx5_ifc_enable_hca_in_bits {
4808         u8         opcode[0x10];
4809         u8         reserved_at_10[0x10];
4810
4811         u8         reserved_at_20[0x10];
4812         u8         op_mod[0x10];
4813
4814         u8         reserved_at_40[0x10];
4815         u8         function_id[0x10];
4816
4817         u8         reserved_at_60[0x20];
4818 };
4819
4820 struct mlx5_ifc_drain_dct_out_bits {
4821         u8         status[0x8];
4822         u8         reserved_at_8[0x18];
4823
4824         u8         syndrome[0x20];
4825
4826         u8         reserved_at_40[0x40];
4827 };
4828
4829 struct mlx5_ifc_drain_dct_in_bits {
4830         u8         opcode[0x10];
4831         u8         reserved_at_10[0x10];
4832
4833         u8         reserved_at_20[0x10];
4834         u8         op_mod[0x10];
4835
4836         u8         reserved_at_40[0x8];
4837         u8         dctn[0x18];
4838
4839         u8         reserved_at_60[0x20];
4840 };
4841
4842 struct mlx5_ifc_disable_hca_out_bits {
4843         u8         status[0x8];
4844         u8         reserved_at_8[0x18];
4845
4846         u8         syndrome[0x20];
4847
4848         u8         reserved_at_40[0x20];
4849 };
4850
4851 struct mlx5_ifc_disable_hca_in_bits {
4852         u8         opcode[0x10];
4853         u8         reserved_at_10[0x10];
4854
4855         u8         reserved_at_20[0x10];
4856         u8         op_mod[0x10];
4857
4858         u8         reserved_at_40[0x10];
4859         u8         function_id[0x10];
4860
4861         u8         reserved_at_60[0x20];
4862 };
4863
4864 struct mlx5_ifc_detach_from_mcg_out_bits {
4865         u8         status[0x8];
4866         u8         reserved_at_8[0x18];
4867
4868         u8         syndrome[0x20];
4869
4870         u8         reserved_at_40[0x40];
4871 };
4872
4873 struct mlx5_ifc_detach_from_mcg_in_bits {
4874         u8         opcode[0x10];
4875         u8         reserved_at_10[0x10];
4876
4877         u8         reserved_at_20[0x10];
4878         u8         op_mod[0x10];
4879
4880         u8         reserved_at_40[0x8];
4881         u8         qpn[0x18];
4882
4883         u8         reserved_at_60[0x20];
4884
4885         u8         multicast_gid[16][0x8];
4886 };
4887
4888 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4889         u8         status[0x8];
4890         u8         reserved_at_8[0x18];
4891
4892         u8         syndrome[0x20];
4893
4894         u8         reserved_at_40[0x40];
4895 };
4896
4897 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4898         u8         opcode[0x10];
4899         u8         reserved_at_10[0x10];
4900
4901         u8         reserved_at_20[0x10];
4902         u8         op_mod[0x10];
4903
4904         u8         reserved_at_40[0x8];
4905         u8         xrc_srqn[0x18];
4906
4907         u8         reserved_at_60[0x20];
4908 };
4909
4910 struct mlx5_ifc_destroy_tis_out_bits {
4911         u8         status[0x8];
4912         u8         reserved_at_8[0x18];
4913
4914         u8         syndrome[0x20];
4915
4916         u8         reserved_at_40[0x40];
4917 };
4918
4919 struct mlx5_ifc_destroy_tis_in_bits {
4920         u8         opcode[0x10];
4921         u8         reserved_at_10[0x10];
4922
4923         u8         reserved_at_20[0x10];
4924         u8         op_mod[0x10];
4925
4926         u8         reserved_at_40[0x8];
4927         u8         tisn[0x18];
4928
4929         u8         reserved_at_60[0x20];
4930 };
4931
4932 struct mlx5_ifc_destroy_tir_out_bits {
4933         u8         status[0x8];
4934         u8         reserved_at_8[0x18];
4935
4936         u8         syndrome[0x20];
4937
4938         u8         reserved_at_40[0x40];
4939 };
4940
4941 struct mlx5_ifc_destroy_tir_in_bits {
4942         u8         opcode[0x10];
4943         u8         reserved_at_10[0x10];
4944
4945         u8         reserved_at_20[0x10];
4946         u8         op_mod[0x10];
4947
4948         u8         reserved_at_40[0x8];
4949         u8         tirn[0x18];
4950
4951         u8         reserved_at_60[0x20];
4952 };
4953
4954 struct mlx5_ifc_destroy_srq_out_bits {
4955         u8         status[0x8];
4956         u8         reserved_at_8[0x18];
4957
4958         u8         syndrome[0x20];
4959
4960         u8         reserved_at_40[0x40];
4961 };
4962
4963 struct mlx5_ifc_destroy_srq_in_bits {
4964         u8         opcode[0x10];
4965         u8         reserved_at_10[0x10];
4966
4967         u8         reserved_at_20[0x10];
4968         u8         op_mod[0x10];
4969
4970         u8         reserved_at_40[0x8];
4971         u8         srqn[0x18];
4972
4973         u8         reserved_at_60[0x20];
4974 };
4975
4976 struct mlx5_ifc_destroy_sq_out_bits {
4977         u8         status[0x8];
4978         u8         reserved_at_8[0x18];
4979
4980         u8         syndrome[0x20];
4981
4982         u8         reserved_at_40[0x40];
4983 };
4984
4985 struct mlx5_ifc_destroy_sq_in_bits {
4986         u8         opcode[0x10];
4987         u8         reserved_at_10[0x10];
4988
4989         u8         reserved_at_20[0x10];
4990         u8         op_mod[0x10];
4991
4992         u8         reserved_at_40[0x8];
4993         u8         sqn[0x18];
4994
4995         u8         reserved_at_60[0x20];
4996 };
4997
4998 struct mlx5_ifc_destroy_rqt_out_bits {
4999         u8         status[0x8];
5000         u8         reserved_at_8[0x18];
5001
5002         u8         syndrome[0x20];
5003
5004         u8         reserved_at_40[0x40];
5005 };
5006
5007 struct mlx5_ifc_destroy_rqt_in_bits {
5008         u8         opcode[0x10];
5009         u8         reserved_at_10[0x10];
5010
5011         u8         reserved_at_20[0x10];
5012         u8         op_mod[0x10];
5013
5014         u8         reserved_at_40[0x8];
5015         u8         rqtn[0x18];
5016
5017         u8         reserved_at_60[0x20];
5018 };
5019
5020 struct mlx5_ifc_destroy_rq_out_bits {
5021         u8         status[0x8];
5022         u8         reserved_at_8[0x18];
5023
5024         u8         syndrome[0x20];
5025
5026         u8         reserved_at_40[0x40];
5027 };
5028
5029 struct mlx5_ifc_destroy_rq_in_bits {
5030         u8         opcode[0x10];
5031         u8         reserved_at_10[0x10];
5032
5033         u8         reserved_at_20[0x10];
5034         u8         op_mod[0x10];
5035
5036         u8         reserved_at_40[0x8];
5037         u8         rqn[0x18];
5038
5039         u8         reserved_at_60[0x20];
5040 };
5041
5042 struct mlx5_ifc_destroy_rmp_out_bits {
5043         u8         status[0x8];
5044         u8         reserved_at_8[0x18];
5045
5046         u8         syndrome[0x20];
5047
5048         u8         reserved_at_40[0x40];
5049 };
5050
5051 struct mlx5_ifc_destroy_rmp_in_bits {
5052         u8         opcode[0x10];
5053         u8         reserved_at_10[0x10];
5054
5055         u8         reserved_at_20[0x10];
5056         u8         op_mod[0x10];
5057
5058         u8         reserved_at_40[0x8];
5059         u8         rmpn[0x18];
5060
5061         u8         reserved_at_60[0x20];
5062 };
5063
5064 struct mlx5_ifc_destroy_qp_out_bits {
5065         u8         status[0x8];
5066         u8         reserved_at_8[0x18];
5067
5068         u8         syndrome[0x20];
5069
5070         u8         reserved_at_40[0x40];
5071 };
5072
5073 struct mlx5_ifc_destroy_qp_in_bits {
5074         u8         opcode[0x10];
5075         u8         reserved_at_10[0x10];
5076
5077         u8         reserved_at_20[0x10];
5078         u8         op_mod[0x10];
5079
5080         u8         reserved_at_40[0x8];
5081         u8         qpn[0x18];
5082
5083         u8         reserved_at_60[0x20];
5084 };
5085
5086 struct mlx5_ifc_destroy_psv_out_bits {
5087         u8         status[0x8];
5088         u8         reserved_at_8[0x18];
5089
5090         u8         syndrome[0x20];
5091
5092         u8         reserved_at_40[0x40];
5093 };
5094
5095 struct mlx5_ifc_destroy_psv_in_bits {
5096         u8         opcode[0x10];
5097         u8         reserved_at_10[0x10];
5098
5099         u8         reserved_at_20[0x10];
5100         u8         op_mod[0x10];
5101
5102         u8         reserved_at_40[0x8];
5103         u8         psvn[0x18];
5104
5105         u8         reserved_at_60[0x20];
5106 };
5107
5108 struct mlx5_ifc_destroy_mkey_out_bits {
5109         u8         status[0x8];
5110         u8         reserved_at_8[0x18];
5111
5112         u8         syndrome[0x20];
5113
5114         u8         reserved_at_40[0x40];
5115 };
5116
5117 struct mlx5_ifc_destroy_mkey_in_bits {
5118         u8         opcode[0x10];
5119         u8         reserved_at_10[0x10];
5120
5121         u8         reserved_at_20[0x10];
5122         u8         op_mod[0x10];
5123
5124         u8         reserved_at_40[0x8];
5125         u8         mkey_index[0x18];
5126
5127         u8         reserved_at_60[0x20];
5128 };
5129
5130 struct mlx5_ifc_destroy_flow_table_out_bits {
5131         u8         status[0x8];
5132         u8         reserved_at_8[0x18];
5133
5134         u8         syndrome[0x20];
5135
5136         u8         reserved_at_40[0x40];
5137 };
5138
5139 struct mlx5_ifc_destroy_flow_table_in_bits {
5140         u8         opcode[0x10];
5141         u8         reserved_at_10[0x10];
5142
5143         u8         reserved_at_20[0x10];
5144         u8         op_mod[0x10];
5145
5146         u8         reserved_at_40[0x40];
5147
5148         u8         table_type[0x8];
5149         u8         reserved_at_88[0x18];
5150
5151         u8         reserved_at_a0[0x8];
5152         u8         table_id[0x18];
5153
5154         u8         reserved_at_c0[0x140];
5155 };
5156
5157 struct mlx5_ifc_destroy_flow_group_out_bits {
5158         u8         status[0x8];
5159         u8         reserved_at_8[0x18];
5160
5161         u8         syndrome[0x20];
5162
5163         u8         reserved_at_40[0x40];
5164 };
5165
5166 struct mlx5_ifc_destroy_flow_group_in_bits {
5167         u8         opcode[0x10];
5168         u8         reserved_at_10[0x10];
5169
5170         u8         reserved_at_20[0x10];
5171         u8         op_mod[0x10];
5172
5173         u8         reserved_at_40[0x40];
5174
5175         u8         table_type[0x8];
5176         u8         reserved_at_88[0x18];
5177
5178         u8         reserved_at_a0[0x8];
5179         u8         table_id[0x18];
5180
5181         u8         group_id[0x20];
5182
5183         u8         reserved_at_e0[0x120];
5184 };
5185
5186 struct mlx5_ifc_destroy_eq_out_bits {
5187         u8         status[0x8];
5188         u8         reserved_at_8[0x18];
5189
5190         u8         syndrome[0x20];
5191
5192         u8         reserved_at_40[0x40];
5193 };
5194
5195 struct mlx5_ifc_destroy_eq_in_bits {
5196         u8         opcode[0x10];
5197         u8         reserved_at_10[0x10];
5198
5199         u8         reserved_at_20[0x10];
5200         u8         op_mod[0x10];
5201
5202         u8         reserved_at_40[0x18];
5203         u8         eq_number[0x8];
5204
5205         u8         reserved_at_60[0x20];
5206 };
5207
5208 struct mlx5_ifc_destroy_dct_out_bits {
5209         u8         status[0x8];
5210         u8         reserved_at_8[0x18];
5211
5212         u8         syndrome[0x20];
5213
5214         u8         reserved_at_40[0x40];
5215 };
5216
5217 struct mlx5_ifc_destroy_dct_in_bits {
5218         u8         opcode[0x10];
5219         u8         reserved_at_10[0x10];
5220
5221         u8         reserved_at_20[0x10];
5222         u8         op_mod[0x10];
5223
5224         u8         reserved_at_40[0x8];
5225         u8         dctn[0x18];
5226
5227         u8         reserved_at_60[0x20];
5228 };
5229
5230 struct mlx5_ifc_destroy_cq_out_bits {
5231         u8         status[0x8];
5232         u8         reserved_at_8[0x18];
5233
5234         u8         syndrome[0x20];
5235
5236         u8         reserved_at_40[0x40];
5237 };
5238
5239 struct mlx5_ifc_destroy_cq_in_bits {
5240         u8         opcode[0x10];
5241         u8         reserved_at_10[0x10];
5242
5243         u8         reserved_at_20[0x10];
5244         u8         op_mod[0x10];
5245
5246         u8         reserved_at_40[0x8];
5247         u8         cqn[0x18];
5248
5249         u8         reserved_at_60[0x20];
5250 };
5251
5252 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5253         u8         status[0x8];
5254         u8         reserved_at_8[0x18];
5255
5256         u8         syndrome[0x20];
5257
5258         u8         reserved_at_40[0x40];
5259 };
5260
5261 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5262         u8         opcode[0x10];
5263         u8         reserved_at_10[0x10];
5264
5265         u8         reserved_at_20[0x10];
5266         u8         op_mod[0x10];
5267
5268         u8         reserved_at_40[0x20];
5269
5270         u8         reserved_at_60[0x10];
5271         u8         vxlan_udp_port[0x10];
5272 };
5273
5274 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5275         u8         status[0x8];
5276         u8         reserved_at_8[0x18];
5277
5278         u8         syndrome[0x20];
5279
5280         u8         reserved_at_40[0x40];
5281 };
5282
5283 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5284         u8         opcode[0x10];
5285         u8         reserved_at_10[0x10];
5286
5287         u8         reserved_at_20[0x10];
5288         u8         op_mod[0x10];
5289
5290         u8         reserved_at_40[0x60];
5291
5292         u8         reserved_at_a0[0x8];
5293         u8         table_index[0x18];
5294
5295         u8         reserved_at_c0[0x140];
5296 };
5297
5298 struct mlx5_ifc_delete_fte_out_bits {
5299         u8         status[0x8];
5300         u8         reserved_at_8[0x18];
5301
5302         u8         syndrome[0x20];
5303
5304         u8         reserved_at_40[0x40];
5305 };
5306
5307 struct mlx5_ifc_delete_fte_in_bits {
5308         u8         opcode[0x10];
5309         u8         reserved_at_10[0x10];
5310
5311         u8         reserved_at_20[0x10];
5312         u8         op_mod[0x10];
5313
5314         u8         reserved_at_40[0x40];
5315
5316         u8         table_type[0x8];
5317         u8         reserved_at_88[0x18];
5318
5319         u8         reserved_at_a0[0x8];
5320         u8         table_id[0x18];
5321
5322         u8         reserved_at_c0[0x40];
5323
5324         u8         flow_index[0x20];
5325
5326         u8         reserved_at_120[0xe0];
5327 };
5328
5329 struct mlx5_ifc_dealloc_xrcd_out_bits {
5330         u8         status[0x8];
5331         u8         reserved_at_8[0x18];
5332
5333         u8         syndrome[0x20];
5334
5335         u8         reserved_at_40[0x40];
5336 };
5337
5338 struct mlx5_ifc_dealloc_xrcd_in_bits {
5339         u8         opcode[0x10];
5340         u8         reserved_at_10[0x10];
5341
5342         u8         reserved_at_20[0x10];
5343         u8         op_mod[0x10];
5344
5345         u8         reserved_at_40[0x8];
5346         u8         xrcd[0x18];
5347
5348         u8         reserved_at_60[0x20];
5349 };
5350
5351 struct mlx5_ifc_dealloc_uar_out_bits {
5352         u8         status[0x8];
5353         u8         reserved_at_8[0x18];
5354
5355         u8         syndrome[0x20];
5356
5357         u8         reserved_at_40[0x40];
5358 };
5359
5360 struct mlx5_ifc_dealloc_uar_in_bits {
5361         u8         opcode[0x10];
5362         u8         reserved_at_10[0x10];
5363
5364         u8         reserved_at_20[0x10];
5365         u8         op_mod[0x10];
5366
5367         u8         reserved_at_40[0x8];
5368         u8         uar[0x18];
5369
5370         u8         reserved_at_60[0x20];
5371 };
5372
5373 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5374         u8         status[0x8];
5375         u8         reserved_at_8[0x18];
5376
5377         u8         syndrome[0x20];
5378
5379         u8         reserved_at_40[0x40];
5380 };
5381
5382 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5383         u8         opcode[0x10];
5384         u8         reserved_at_10[0x10];
5385
5386         u8         reserved_at_20[0x10];
5387         u8         op_mod[0x10];
5388
5389         u8         reserved_at_40[0x8];
5390         u8         transport_domain[0x18];
5391
5392         u8         reserved_at_60[0x20];
5393 };
5394
5395 struct mlx5_ifc_dealloc_q_counter_out_bits {
5396         u8         status[0x8];
5397         u8         reserved_at_8[0x18];
5398
5399         u8         syndrome[0x20];
5400
5401         u8         reserved_at_40[0x40];
5402 };
5403
5404 struct mlx5_ifc_dealloc_q_counter_in_bits {
5405         u8         opcode[0x10];
5406         u8         reserved_at_10[0x10];
5407
5408         u8         reserved_at_20[0x10];
5409         u8         op_mod[0x10];
5410
5411         u8         reserved_at_40[0x18];
5412         u8         counter_set_id[0x8];
5413
5414         u8         reserved_at_60[0x20];
5415 };
5416
5417 struct mlx5_ifc_dealloc_pd_out_bits {
5418         u8         status[0x8];
5419         u8         reserved_at_8[0x18];
5420
5421         u8         syndrome[0x20];
5422
5423         u8         reserved_at_40[0x40];
5424 };
5425
5426 struct mlx5_ifc_dealloc_pd_in_bits {
5427         u8         opcode[0x10];
5428         u8         reserved_at_10[0x10];
5429
5430         u8         reserved_at_20[0x10];
5431         u8         op_mod[0x10];
5432
5433         u8         reserved_at_40[0x8];
5434         u8         pd[0x18];
5435
5436         u8         reserved_at_60[0x20];
5437 };
5438
5439 struct mlx5_ifc_create_xrc_srq_out_bits {
5440         u8         status[0x8];
5441         u8         reserved_at_8[0x18];
5442
5443         u8         syndrome[0x20];
5444
5445         u8         reserved_at_40[0x8];
5446         u8         xrc_srqn[0x18];
5447
5448         u8         reserved_at_60[0x20];
5449 };
5450
5451 struct mlx5_ifc_create_xrc_srq_in_bits {
5452         u8         opcode[0x10];
5453         u8         reserved_at_10[0x10];
5454
5455         u8         reserved_at_20[0x10];
5456         u8         op_mod[0x10];
5457
5458         u8         reserved_at_40[0x40];
5459
5460         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5461
5462         u8         reserved_at_280[0x600];
5463
5464         u8         pas[0][0x40];
5465 };
5466
5467 struct mlx5_ifc_create_tis_out_bits {
5468         u8         status[0x8];
5469         u8         reserved_at_8[0x18];
5470
5471         u8         syndrome[0x20];
5472
5473         u8         reserved_at_40[0x8];
5474         u8         tisn[0x18];
5475
5476         u8         reserved_at_60[0x20];
5477 };
5478
5479 struct mlx5_ifc_create_tis_in_bits {
5480         u8         opcode[0x10];
5481         u8         reserved_at_10[0x10];
5482
5483         u8         reserved_at_20[0x10];
5484         u8         op_mod[0x10];
5485
5486         u8         reserved_at_40[0xc0];
5487
5488         struct mlx5_ifc_tisc_bits ctx;
5489 };
5490
5491 struct mlx5_ifc_create_tir_out_bits {
5492         u8         status[0x8];
5493         u8         reserved_at_8[0x18];
5494
5495         u8         syndrome[0x20];
5496
5497         u8         reserved_at_40[0x8];
5498         u8         tirn[0x18];
5499
5500         u8         reserved_at_60[0x20];
5501 };
5502
5503 struct mlx5_ifc_create_tir_in_bits {
5504         u8         opcode[0x10];
5505         u8         reserved_at_10[0x10];
5506
5507         u8         reserved_at_20[0x10];
5508         u8         op_mod[0x10];
5509
5510         u8         reserved_at_40[0xc0];
5511
5512         struct mlx5_ifc_tirc_bits ctx;
5513 };
5514
5515 struct mlx5_ifc_create_srq_out_bits {
5516         u8         status[0x8];
5517         u8         reserved_at_8[0x18];
5518
5519         u8         syndrome[0x20];
5520
5521         u8         reserved_at_40[0x8];
5522         u8         srqn[0x18];
5523
5524         u8         reserved_at_60[0x20];
5525 };
5526
5527 struct mlx5_ifc_create_srq_in_bits {
5528         u8         opcode[0x10];
5529         u8         reserved_at_10[0x10];
5530
5531         u8         reserved_at_20[0x10];
5532         u8         op_mod[0x10];
5533
5534         u8         reserved_at_40[0x40];
5535
5536         struct mlx5_ifc_srqc_bits srq_context_entry;
5537
5538         u8         reserved_at_280[0x600];
5539
5540         u8         pas[0][0x40];
5541 };
5542
5543 struct mlx5_ifc_create_sq_out_bits {
5544         u8         status[0x8];
5545         u8         reserved_at_8[0x18];
5546
5547         u8         syndrome[0x20];
5548
5549         u8         reserved_at_40[0x8];
5550         u8         sqn[0x18];
5551
5552         u8         reserved_at_60[0x20];
5553 };
5554
5555 struct mlx5_ifc_create_sq_in_bits {
5556         u8         opcode[0x10];
5557         u8         reserved_at_10[0x10];
5558
5559         u8         reserved_at_20[0x10];
5560         u8         op_mod[0x10];
5561
5562         u8         reserved_at_40[0xc0];
5563
5564         struct mlx5_ifc_sqc_bits ctx;
5565 };
5566
5567 struct mlx5_ifc_create_rqt_out_bits {
5568         u8         status[0x8];
5569         u8         reserved_at_8[0x18];
5570
5571         u8         syndrome[0x20];
5572
5573         u8         reserved_at_40[0x8];
5574         u8         rqtn[0x18];
5575
5576         u8         reserved_at_60[0x20];
5577 };
5578
5579 struct mlx5_ifc_create_rqt_in_bits {
5580         u8         opcode[0x10];
5581         u8         reserved_at_10[0x10];
5582
5583         u8         reserved_at_20[0x10];
5584         u8         op_mod[0x10];
5585
5586         u8         reserved_at_40[0xc0];
5587
5588         struct mlx5_ifc_rqtc_bits rqt_context;
5589 };
5590
5591 struct mlx5_ifc_create_rq_out_bits {
5592         u8         status[0x8];
5593         u8         reserved_at_8[0x18];
5594
5595         u8         syndrome[0x20];
5596
5597         u8         reserved_at_40[0x8];
5598         u8         rqn[0x18];
5599
5600         u8         reserved_at_60[0x20];
5601 };
5602
5603 struct mlx5_ifc_create_rq_in_bits {
5604         u8         opcode[0x10];
5605         u8         reserved_at_10[0x10];
5606
5607         u8         reserved_at_20[0x10];
5608         u8         op_mod[0x10];
5609
5610         u8         reserved_at_40[0xc0];
5611
5612         struct mlx5_ifc_rqc_bits ctx;
5613 };
5614
5615 struct mlx5_ifc_create_rmp_out_bits {
5616         u8         status[0x8];
5617         u8         reserved_at_8[0x18];
5618
5619         u8         syndrome[0x20];
5620
5621         u8         reserved_at_40[0x8];
5622         u8         rmpn[0x18];
5623
5624         u8         reserved_at_60[0x20];
5625 };
5626
5627 struct mlx5_ifc_create_rmp_in_bits {
5628         u8         opcode[0x10];
5629         u8         reserved_at_10[0x10];
5630
5631         u8         reserved_at_20[0x10];
5632         u8         op_mod[0x10];
5633
5634         u8         reserved_at_40[0xc0];
5635
5636         struct mlx5_ifc_rmpc_bits ctx;
5637 };
5638
5639 struct mlx5_ifc_create_qp_out_bits {
5640         u8         status[0x8];
5641         u8         reserved_at_8[0x18];
5642
5643         u8         syndrome[0x20];
5644
5645         u8         reserved_at_40[0x8];
5646         u8         qpn[0x18];
5647
5648         u8         reserved_at_60[0x20];
5649 };
5650
5651 struct mlx5_ifc_create_qp_in_bits {
5652         u8         opcode[0x10];
5653         u8         reserved_at_10[0x10];
5654
5655         u8         reserved_at_20[0x10];
5656         u8         op_mod[0x10];
5657
5658         u8         reserved_at_40[0x40];
5659
5660         u8         opt_param_mask[0x20];
5661
5662         u8         reserved_at_a0[0x20];
5663
5664         struct mlx5_ifc_qpc_bits qpc;
5665
5666         u8         reserved_at_800[0x80];
5667
5668         u8         pas[0][0x40];
5669 };
5670
5671 struct mlx5_ifc_create_psv_out_bits {
5672         u8         status[0x8];
5673         u8         reserved_at_8[0x18];
5674
5675         u8         syndrome[0x20];
5676
5677         u8         reserved_at_40[0x40];
5678
5679         u8         reserved_at_80[0x8];
5680         u8         psv0_index[0x18];
5681
5682         u8         reserved_at_a0[0x8];
5683         u8         psv1_index[0x18];
5684
5685         u8         reserved_at_c0[0x8];
5686         u8         psv2_index[0x18];
5687
5688         u8         reserved_at_e0[0x8];
5689         u8         psv3_index[0x18];
5690 };
5691
5692 struct mlx5_ifc_create_psv_in_bits {
5693         u8         opcode[0x10];
5694         u8         reserved_at_10[0x10];
5695
5696         u8         reserved_at_20[0x10];
5697         u8         op_mod[0x10];
5698
5699         u8         num_psv[0x4];
5700         u8         reserved_at_44[0x4];
5701         u8         pd[0x18];
5702
5703         u8         reserved_at_60[0x20];
5704 };
5705
5706 struct mlx5_ifc_create_mkey_out_bits {
5707         u8         status[0x8];
5708         u8         reserved_at_8[0x18];
5709
5710         u8         syndrome[0x20];
5711
5712         u8         reserved_at_40[0x8];
5713         u8         mkey_index[0x18];
5714
5715         u8         reserved_at_60[0x20];
5716 };
5717
5718 struct mlx5_ifc_create_mkey_in_bits {
5719         u8         opcode[0x10];
5720         u8         reserved_at_10[0x10];
5721
5722         u8         reserved_at_20[0x10];
5723         u8         op_mod[0x10];
5724
5725         u8         reserved_at_40[0x20];
5726
5727         u8         pg_access[0x1];
5728         u8         reserved_at_61[0x1f];
5729
5730         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5731
5732         u8         reserved_at_280[0x80];
5733
5734         u8         translations_octword_actual_size[0x20];
5735
5736         u8         reserved_at_320[0x560];
5737
5738         u8         klm_pas_mtt[0][0x20];
5739 };
5740
5741 struct mlx5_ifc_create_flow_table_out_bits {
5742         u8         status[0x8];
5743         u8         reserved_at_8[0x18];
5744
5745         u8         syndrome[0x20];
5746
5747         u8         reserved_at_40[0x8];
5748         u8         table_id[0x18];
5749
5750         u8         reserved_at_60[0x20];
5751 };
5752
5753 struct mlx5_ifc_create_flow_table_in_bits {
5754         u8         opcode[0x10];
5755         u8         reserved_at_10[0x10];
5756
5757         u8         reserved_at_20[0x10];
5758         u8         op_mod[0x10];
5759
5760         u8         reserved_at_40[0x40];
5761
5762         u8         table_type[0x8];
5763         u8         reserved_at_88[0x18];
5764
5765         u8         reserved_at_a0[0x20];
5766
5767         u8         reserved_at_c0[0x4];
5768         u8         table_miss_mode[0x4];
5769         u8         level[0x8];
5770         u8         reserved_at_d0[0x8];
5771         u8         log_size[0x8];
5772
5773         u8         reserved_at_e0[0x8];
5774         u8         table_miss_id[0x18];
5775
5776         u8         reserved_at_100[0x100];
5777 };
5778
5779 struct mlx5_ifc_create_flow_group_out_bits {
5780         u8         status[0x8];
5781         u8         reserved_at_8[0x18];
5782
5783         u8         syndrome[0x20];
5784
5785         u8         reserved_at_40[0x8];
5786         u8         group_id[0x18];
5787
5788         u8         reserved_at_60[0x20];
5789 };
5790
5791 enum {
5792         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5793         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5794         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5795 };
5796
5797 struct mlx5_ifc_create_flow_group_in_bits {
5798         u8         opcode[0x10];
5799         u8         reserved_at_10[0x10];
5800
5801         u8         reserved_at_20[0x10];
5802         u8         op_mod[0x10];
5803
5804         u8         reserved_at_40[0x40];
5805
5806         u8         table_type[0x8];
5807         u8         reserved_at_88[0x18];
5808
5809         u8         reserved_at_a0[0x8];
5810         u8         table_id[0x18];
5811
5812         u8         reserved_at_c0[0x20];
5813
5814         u8         start_flow_index[0x20];
5815
5816         u8         reserved_at_100[0x20];
5817
5818         u8         end_flow_index[0x20];
5819
5820         u8         reserved_at_140[0xa0];
5821
5822         u8         reserved_at_1e0[0x18];
5823         u8         match_criteria_enable[0x8];
5824
5825         struct mlx5_ifc_fte_match_param_bits match_criteria;
5826
5827         u8         reserved_at_1200[0xe00];
5828 };
5829
5830 struct mlx5_ifc_create_eq_out_bits {
5831         u8         status[0x8];
5832         u8         reserved_at_8[0x18];
5833
5834         u8         syndrome[0x20];
5835
5836         u8         reserved_at_40[0x18];
5837         u8         eq_number[0x8];
5838
5839         u8         reserved_at_60[0x20];
5840 };
5841
5842 struct mlx5_ifc_create_eq_in_bits {
5843         u8         opcode[0x10];
5844         u8         reserved_at_10[0x10];
5845
5846         u8         reserved_at_20[0x10];
5847         u8         op_mod[0x10];
5848
5849         u8         reserved_at_40[0x40];
5850
5851         struct mlx5_ifc_eqc_bits eq_context_entry;
5852
5853         u8         reserved_at_280[0x40];
5854
5855         u8         event_bitmask[0x40];
5856
5857         u8         reserved_at_300[0x580];
5858
5859         u8         pas[0][0x40];
5860 };
5861
5862 struct mlx5_ifc_create_dct_out_bits {
5863         u8         status[0x8];
5864         u8         reserved_at_8[0x18];
5865
5866         u8         syndrome[0x20];
5867
5868         u8         reserved_at_40[0x8];
5869         u8         dctn[0x18];
5870
5871         u8         reserved_at_60[0x20];
5872 };
5873
5874 struct mlx5_ifc_create_dct_in_bits {
5875         u8         opcode[0x10];
5876         u8         reserved_at_10[0x10];
5877
5878         u8         reserved_at_20[0x10];
5879         u8         op_mod[0x10];
5880
5881         u8         reserved_at_40[0x40];
5882
5883         struct mlx5_ifc_dctc_bits dct_context_entry;
5884
5885         u8         reserved_at_280[0x180];
5886 };
5887
5888 struct mlx5_ifc_create_cq_out_bits {
5889         u8         status[0x8];
5890         u8         reserved_at_8[0x18];
5891
5892         u8         syndrome[0x20];
5893
5894         u8         reserved_at_40[0x8];
5895         u8         cqn[0x18];
5896
5897         u8         reserved_at_60[0x20];
5898 };
5899
5900 struct mlx5_ifc_create_cq_in_bits {
5901         u8         opcode[0x10];
5902         u8         reserved_at_10[0x10];
5903
5904         u8         reserved_at_20[0x10];
5905         u8         op_mod[0x10];
5906
5907         u8         reserved_at_40[0x40];
5908
5909         struct mlx5_ifc_cqc_bits cq_context;
5910
5911         u8         reserved_at_280[0x600];
5912
5913         u8         pas[0][0x40];
5914 };
5915
5916 struct mlx5_ifc_config_int_moderation_out_bits {
5917         u8         status[0x8];
5918         u8         reserved_at_8[0x18];
5919
5920         u8         syndrome[0x20];
5921
5922         u8         reserved_at_40[0x4];
5923         u8         min_delay[0xc];
5924         u8         int_vector[0x10];
5925
5926         u8         reserved_at_60[0x20];
5927 };
5928
5929 enum {
5930         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
5931         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
5932 };
5933
5934 struct mlx5_ifc_config_int_moderation_in_bits {
5935         u8         opcode[0x10];
5936         u8         reserved_at_10[0x10];
5937
5938         u8         reserved_at_20[0x10];
5939         u8         op_mod[0x10];
5940
5941         u8         reserved_at_40[0x4];
5942         u8         min_delay[0xc];
5943         u8         int_vector[0x10];
5944
5945         u8         reserved_at_60[0x20];
5946 };
5947
5948 struct mlx5_ifc_attach_to_mcg_out_bits {
5949         u8         status[0x8];
5950         u8         reserved_at_8[0x18];
5951
5952         u8         syndrome[0x20];
5953
5954         u8         reserved_at_40[0x40];
5955 };
5956
5957 struct mlx5_ifc_attach_to_mcg_in_bits {
5958         u8         opcode[0x10];
5959         u8         reserved_at_10[0x10];
5960
5961         u8         reserved_at_20[0x10];
5962         u8         op_mod[0x10];
5963
5964         u8         reserved_at_40[0x8];
5965         u8         qpn[0x18];
5966
5967         u8         reserved_at_60[0x20];
5968
5969         u8         multicast_gid[16][0x8];
5970 };
5971
5972 struct mlx5_ifc_arm_xrc_srq_out_bits {
5973         u8         status[0x8];
5974         u8         reserved_at_8[0x18];
5975
5976         u8         syndrome[0x20];
5977
5978         u8         reserved_at_40[0x40];
5979 };
5980
5981 enum {
5982         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
5983 };
5984
5985 struct mlx5_ifc_arm_xrc_srq_in_bits {
5986         u8         opcode[0x10];
5987         u8         reserved_at_10[0x10];
5988
5989         u8         reserved_at_20[0x10];
5990         u8         op_mod[0x10];
5991
5992         u8         reserved_at_40[0x8];
5993         u8         xrc_srqn[0x18];
5994
5995         u8         reserved_at_60[0x10];
5996         u8         lwm[0x10];
5997 };
5998
5999 struct mlx5_ifc_arm_rq_out_bits {
6000         u8         status[0x8];
6001         u8         reserved_at_8[0x18];
6002
6003         u8         syndrome[0x20];
6004
6005         u8         reserved_at_40[0x40];
6006 };
6007
6008 enum {
6009         MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
6010 };
6011
6012 struct mlx5_ifc_arm_rq_in_bits {
6013         u8         opcode[0x10];
6014         u8         reserved_at_10[0x10];
6015
6016         u8         reserved_at_20[0x10];
6017         u8         op_mod[0x10];
6018
6019         u8         reserved_at_40[0x8];
6020         u8         srq_number[0x18];
6021
6022         u8         reserved_at_60[0x10];
6023         u8         lwm[0x10];
6024 };
6025
6026 struct mlx5_ifc_arm_dct_out_bits {
6027         u8         status[0x8];
6028         u8         reserved_at_8[0x18];
6029
6030         u8         syndrome[0x20];
6031
6032         u8         reserved_at_40[0x40];
6033 };
6034
6035 struct mlx5_ifc_arm_dct_in_bits {
6036         u8         opcode[0x10];
6037         u8         reserved_at_10[0x10];
6038
6039         u8         reserved_at_20[0x10];
6040         u8         op_mod[0x10];
6041
6042         u8         reserved_at_40[0x8];
6043         u8         dct_number[0x18];
6044
6045         u8         reserved_at_60[0x20];
6046 };
6047
6048 struct mlx5_ifc_alloc_xrcd_out_bits {
6049         u8         status[0x8];
6050         u8         reserved_at_8[0x18];
6051
6052         u8         syndrome[0x20];
6053
6054         u8         reserved_at_40[0x8];
6055         u8         xrcd[0x18];
6056
6057         u8         reserved_at_60[0x20];
6058 };
6059
6060 struct mlx5_ifc_alloc_xrcd_in_bits {
6061         u8         opcode[0x10];
6062         u8         reserved_at_10[0x10];
6063
6064         u8         reserved_at_20[0x10];
6065         u8         op_mod[0x10];
6066
6067         u8         reserved_at_40[0x40];
6068 };
6069
6070 struct mlx5_ifc_alloc_uar_out_bits {
6071         u8         status[0x8];
6072         u8         reserved_at_8[0x18];
6073
6074         u8         syndrome[0x20];
6075
6076         u8         reserved_at_40[0x8];
6077         u8         uar[0x18];
6078
6079         u8         reserved_at_60[0x20];
6080 };
6081
6082 struct mlx5_ifc_alloc_uar_in_bits {
6083         u8         opcode[0x10];
6084         u8         reserved_at_10[0x10];
6085
6086         u8         reserved_at_20[0x10];
6087         u8         op_mod[0x10];
6088
6089         u8         reserved_at_40[0x40];
6090 };
6091
6092 struct mlx5_ifc_alloc_transport_domain_out_bits {
6093         u8         status[0x8];
6094         u8         reserved_at_8[0x18];
6095
6096         u8         syndrome[0x20];
6097
6098         u8         reserved_at_40[0x8];
6099         u8         transport_domain[0x18];
6100
6101         u8         reserved_at_60[0x20];
6102 };
6103
6104 struct mlx5_ifc_alloc_transport_domain_in_bits {
6105         u8         opcode[0x10];
6106         u8         reserved_at_10[0x10];
6107
6108         u8         reserved_at_20[0x10];
6109         u8         op_mod[0x10];
6110
6111         u8         reserved_at_40[0x40];
6112 };
6113
6114 struct mlx5_ifc_alloc_q_counter_out_bits {
6115         u8         status[0x8];
6116         u8         reserved_at_8[0x18];
6117
6118         u8         syndrome[0x20];
6119
6120         u8         reserved_at_40[0x18];
6121         u8         counter_set_id[0x8];
6122
6123         u8         reserved_at_60[0x20];
6124 };
6125
6126 struct mlx5_ifc_alloc_q_counter_in_bits {
6127         u8         opcode[0x10];
6128         u8         reserved_at_10[0x10];
6129
6130         u8         reserved_at_20[0x10];
6131         u8         op_mod[0x10];
6132
6133         u8         reserved_at_40[0x40];
6134 };
6135
6136 struct mlx5_ifc_alloc_pd_out_bits {
6137         u8         status[0x8];
6138         u8         reserved_at_8[0x18];
6139
6140         u8         syndrome[0x20];
6141
6142         u8         reserved_at_40[0x8];
6143         u8         pd[0x18];
6144
6145         u8         reserved_at_60[0x20];
6146 };
6147
6148 struct mlx5_ifc_alloc_pd_in_bits {
6149         u8         opcode[0x10];
6150         u8         reserved_at_10[0x10];
6151
6152         u8         reserved_at_20[0x10];
6153         u8         op_mod[0x10];
6154
6155         u8         reserved_at_40[0x40];
6156 };
6157
6158 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6159         u8         status[0x8];
6160         u8         reserved_at_8[0x18];
6161
6162         u8         syndrome[0x20];
6163
6164         u8         reserved_at_40[0x40];
6165 };
6166
6167 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6168         u8         opcode[0x10];
6169         u8         reserved_at_10[0x10];
6170
6171         u8         reserved_at_20[0x10];
6172         u8         op_mod[0x10];
6173
6174         u8         reserved_at_40[0x20];
6175
6176         u8         reserved_at_60[0x10];
6177         u8         vxlan_udp_port[0x10];
6178 };
6179
6180 struct mlx5_ifc_access_register_out_bits {
6181         u8         status[0x8];
6182         u8         reserved_at_8[0x18];
6183
6184         u8         syndrome[0x20];
6185
6186         u8         reserved_at_40[0x40];
6187
6188         u8         register_data[0][0x20];
6189 };
6190
6191 enum {
6192         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6193         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6194 };
6195
6196 struct mlx5_ifc_access_register_in_bits {
6197         u8         opcode[0x10];
6198         u8         reserved_at_10[0x10];
6199
6200         u8         reserved_at_20[0x10];
6201         u8         op_mod[0x10];
6202
6203         u8         reserved_at_40[0x10];
6204         u8         register_id[0x10];
6205
6206         u8         argument[0x20];
6207
6208         u8         register_data[0][0x20];
6209 };
6210
6211 struct mlx5_ifc_sltp_reg_bits {
6212         u8         status[0x4];
6213         u8         version[0x4];
6214         u8         local_port[0x8];
6215         u8         pnat[0x2];
6216         u8         reserved_at_12[0x2];
6217         u8         lane[0x4];
6218         u8         reserved_at_18[0x8];
6219
6220         u8         reserved_at_20[0x20];
6221
6222         u8         reserved_at_40[0x7];
6223         u8         polarity[0x1];
6224         u8         ob_tap0[0x8];
6225         u8         ob_tap1[0x8];
6226         u8         ob_tap2[0x8];
6227
6228         u8         reserved_at_60[0xc];
6229         u8         ob_preemp_mode[0x4];
6230         u8         ob_reg[0x8];
6231         u8         ob_bias[0x8];
6232
6233         u8         reserved_at_80[0x20];
6234 };
6235
6236 struct mlx5_ifc_slrg_reg_bits {
6237         u8         status[0x4];
6238         u8         version[0x4];
6239         u8         local_port[0x8];
6240         u8         pnat[0x2];
6241         u8         reserved_at_12[0x2];
6242         u8         lane[0x4];
6243         u8         reserved_at_18[0x8];
6244
6245         u8         time_to_link_up[0x10];
6246         u8         reserved_at_30[0xc];
6247         u8         grade_lane_speed[0x4];
6248
6249         u8         grade_version[0x8];
6250         u8         grade[0x18];
6251
6252         u8         reserved_at_60[0x4];
6253         u8         height_grade_type[0x4];
6254         u8         height_grade[0x18];
6255
6256         u8         height_dz[0x10];
6257         u8         height_dv[0x10];
6258
6259         u8         reserved_at_a0[0x10];
6260         u8         height_sigma[0x10];
6261
6262         u8         reserved_at_c0[0x20];
6263
6264         u8         reserved_at_e0[0x4];
6265         u8         phase_grade_type[0x4];
6266         u8         phase_grade[0x18];
6267
6268         u8         reserved_at_100[0x8];
6269         u8         phase_eo_pos[0x8];
6270         u8         reserved_at_110[0x8];
6271         u8         phase_eo_neg[0x8];
6272
6273         u8         ffe_set_tested[0x10];
6274         u8         test_errors_per_lane[0x10];
6275 };
6276
6277 struct mlx5_ifc_pvlc_reg_bits {
6278         u8         reserved_at_0[0x8];
6279         u8         local_port[0x8];
6280         u8         reserved_at_10[0x10];
6281
6282         u8         reserved_at_20[0x1c];
6283         u8         vl_hw_cap[0x4];
6284
6285         u8         reserved_at_40[0x1c];
6286         u8         vl_admin[0x4];
6287
6288         u8         reserved_at_60[0x1c];
6289         u8         vl_operational[0x4];
6290 };
6291
6292 struct mlx5_ifc_pude_reg_bits {
6293         u8         swid[0x8];
6294         u8         local_port[0x8];
6295         u8         reserved_at_10[0x4];
6296         u8         admin_status[0x4];
6297         u8         reserved_at_18[0x4];
6298         u8         oper_status[0x4];
6299
6300         u8         reserved_at_20[0x60];
6301 };
6302
6303 struct mlx5_ifc_ptys_reg_bits {
6304         u8         reserved_at_0[0x8];
6305         u8         local_port[0x8];
6306         u8         reserved_at_10[0xd];
6307         u8         proto_mask[0x3];
6308
6309         u8         reserved_at_20[0x40];
6310
6311         u8         eth_proto_capability[0x20];
6312
6313         u8         ib_link_width_capability[0x10];
6314         u8         ib_proto_capability[0x10];
6315
6316         u8         reserved_at_a0[0x20];
6317
6318         u8         eth_proto_admin[0x20];
6319
6320         u8         ib_link_width_admin[0x10];
6321         u8         ib_proto_admin[0x10];
6322
6323         u8         reserved_at_100[0x20];
6324
6325         u8         eth_proto_oper[0x20];
6326
6327         u8         ib_link_width_oper[0x10];
6328         u8         ib_proto_oper[0x10];
6329
6330         u8         reserved_at_160[0x20];
6331
6332         u8         eth_proto_lp_advertise[0x20];
6333
6334         u8         reserved_at_1a0[0x60];
6335 };
6336
6337 struct mlx5_ifc_ptas_reg_bits {
6338         u8         reserved_at_0[0x20];
6339
6340         u8         algorithm_options[0x10];
6341         u8         reserved_at_30[0x4];
6342         u8         repetitions_mode[0x4];
6343         u8         num_of_repetitions[0x8];
6344
6345         u8         grade_version[0x8];
6346         u8         height_grade_type[0x4];
6347         u8         phase_grade_type[0x4];
6348         u8         height_grade_weight[0x8];
6349         u8         phase_grade_weight[0x8];
6350
6351         u8         gisim_measure_bits[0x10];
6352         u8         adaptive_tap_measure_bits[0x10];
6353
6354         u8         ber_bath_high_error_threshold[0x10];
6355         u8         ber_bath_mid_error_threshold[0x10];
6356
6357         u8         ber_bath_low_error_threshold[0x10];
6358         u8         one_ratio_high_threshold[0x10];
6359
6360         u8         one_ratio_high_mid_threshold[0x10];
6361         u8         one_ratio_low_mid_threshold[0x10];
6362
6363         u8         one_ratio_low_threshold[0x10];
6364         u8         ndeo_error_threshold[0x10];
6365
6366         u8         mixer_offset_step_size[0x10];
6367         u8         reserved_at_110[0x8];
6368         u8         mix90_phase_for_voltage_bath[0x8];
6369
6370         u8         mixer_offset_start[0x10];
6371         u8         mixer_offset_end[0x10];
6372
6373         u8         reserved_at_140[0x15];
6374         u8         ber_test_time[0xb];
6375 };
6376
6377 struct mlx5_ifc_pspa_reg_bits {
6378         u8         swid[0x8];
6379         u8         local_port[0x8];
6380         u8         sub_port[0x8];
6381         u8         reserved_at_18[0x8];
6382
6383         u8         reserved_at_20[0x20];
6384 };
6385
6386 struct mlx5_ifc_pqdr_reg_bits {
6387         u8         reserved_at_0[0x8];
6388         u8         local_port[0x8];
6389         u8         reserved_at_10[0x5];
6390         u8         prio[0x3];
6391         u8         reserved_at_18[0x6];
6392         u8         mode[0x2];
6393
6394         u8         reserved_at_20[0x20];
6395
6396         u8         reserved_at_40[0x10];
6397         u8         min_threshold[0x10];
6398
6399         u8         reserved_at_60[0x10];
6400         u8         max_threshold[0x10];
6401
6402         u8         reserved_at_80[0x10];
6403         u8         mark_probability_denominator[0x10];
6404
6405         u8         reserved_at_a0[0x60];
6406 };
6407
6408 struct mlx5_ifc_ppsc_reg_bits {
6409         u8         reserved_at_0[0x8];
6410         u8         local_port[0x8];
6411         u8         reserved_at_10[0x10];
6412
6413         u8         reserved_at_20[0x60];
6414
6415         u8         reserved_at_80[0x1c];
6416         u8         wrps_admin[0x4];
6417
6418         u8         reserved_at_a0[0x1c];
6419         u8         wrps_status[0x4];
6420
6421         u8         reserved_at_c0[0x8];
6422         u8         up_threshold[0x8];
6423         u8         reserved_at_d0[0x8];
6424         u8         down_threshold[0x8];
6425
6426         u8         reserved_at_e0[0x20];
6427
6428         u8         reserved_at_100[0x1c];
6429         u8         srps_admin[0x4];
6430
6431         u8         reserved_at_120[0x1c];
6432         u8         srps_status[0x4];
6433
6434         u8         reserved_at_140[0x40];
6435 };
6436
6437 struct mlx5_ifc_pplr_reg_bits {
6438         u8         reserved_at_0[0x8];
6439         u8         local_port[0x8];
6440         u8         reserved_at_10[0x10];
6441
6442         u8         reserved_at_20[0x8];
6443         u8         lb_cap[0x8];
6444         u8         reserved_at_30[0x8];
6445         u8         lb_en[0x8];
6446 };
6447
6448 struct mlx5_ifc_pplm_reg_bits {
6449         u8         reserved_at_0[0x8];
6450         u8         local_port[0x8];
6451         u8         reserved_at_10[0x10];
6452
6453         u8         reserved_at_20[0x20];
6454
6455         u8         port_profile_mode[0x8];
6456         u8         static_port_profile[0x8];
6457         u8         active_port_profile[0x8];
6458         u8         reserved_at_58[0x8];
6459
6460         u8         retransmission_active[0x8];
6461         u8         fec_mode_active[0x18];
6462
6463         u8         reserved_at_80[0x20];
6464 };
6465
6466 struct mlx5_ifc_ppcnt_reg_bits {
6467         u8         swid[0x8];
6468         u8         local_port[0x8];
6469         u8         pnat[0x2];
6470         u8         reserved_at_12[0x8];
6471         u8         grp[0x6];
6472
6473         u8         clr[0x1];
6474         u8         reserved_at_21[0x1c];
6475         u8         prio_tc[0x3];
6476
6477         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6478 };
6479
6480 struct mlx5_ifc_ppad_reg_bits {
6481         u8         reserved_at_0[0x3];
6482         u8         single_mac[0x1];
6483         u8         reserved_at_4[0x4];
6484         u8         local_port[0x8];
6485         u8         mac_47_32[0x10];
6486
6487         u8         mac_31_0[0x20];
6488
6489         u8         reserved_at_40[0x40];
6490 };
6491
6492 struct mlx5_ifc_pmtu_reg_bits {
6493         u8         reserved_at_0[0x8];
6494         u8         local_port[0x8];
6495         u8         reserved_at_10[0x10];
6496
6497         u8         max_mtu[0x10];
6498         u8         reserved_at_30[0x10];
6499
6500         u8         admin_mtu[0x10];
6501         u8         reserved_at_50[0x10];
6502
6503         u8         oper_mtu[0x10];
6504         u8         reserved_at_70[0x10];
6505 };
6506
6507 struct mlx5_ifc_pmpr_reg_bits {
6508         u8         reserved_at_0[0x8];
6509         u8         module[0x8];
6510         u8         reserved_at_10[0x10];
6511
6512         u8         reserved_at_20[0x18];
6513         u8         attenuation_5g[0x8];
6514
6515         u8         reserved_at_40[0x18];
6516         u8         attenuation_7g[0x8];
6517
6518         u8         reserved_at_60[0x18];
6519         u8         attenuation_12g[0x8];
6520 };
6521
6522 struct mlx5_ifc_pmpe_reg_bits {
6523         u8         reserved_at_0[0x8];
6524         u8         module[0x8];
6525         u8         reserved_at_10[0xc];
6526         u8         module_status[0x4];
6527
6528         u8         reserved_at_20[0x60];
6529 };
6530
6531 struct mlx5_ifc_pmpc_reg_bits {
6532         u8         module_state_updated[32][0x8];
6533 };
6534
6535 struct mlx5_ifc_pmlpn_reg_bits {
6536         u8         reserved_at_0[0x4];
6537         u8         mlpn_status[0x4];
6538         u8         local_port[0x8];
6539         u8         reserved_at_10[0x10];
6540
6541         u8         e[0x1];
6542         u8         reserved_at_21[0x1f];
6543 };
6544
6545 struct mlx5_ifc_pmlp_reg_bits {
6546         u8         rxtx[0x1];
6547         u8         reserved_at_1[0x7];
6548         u8         local_port[0x8];
6549         u8         reserved_at_10[0x8];
6550         u8         width[0x8];
6551
6552         u8         lane0_module_mapping[0x20];
6553
6554         u8         lane1_module_mapping[0x20];
6555
6556         u8         lane2_module_mapping[0x20];
6557
6558         u8         lane3_module_mapping[0x20];
6559
6560         u8         reserved_at_a0[0x160];
6561 };
6562
6563 struct mlx5_ifc_pmaos_reg_bits {
6564         u8         reserved_at_0[0x8];
6565         u8         module[0x8];
6566         u8         reserved_at_10[0x4];
6567         u8         admin_status[0x4];
6568         u8         reserved_at_18[0x4];
6569         u8         oper_status[0x4];
6570
6571         u8         ase[0x1];
6572         u8         ee[0x1];
6573         u8         reserved_at_22[0x1c];
6574         u8         e[0x2];
6575
6576         u8         reserved_at_40[0x40];
6577 };
6578
6579 struct mlx5_ifc_plpc_reg_bits {
6580         u8         reserved_at_0[0x4];
6581         u8         profile_id[0xc];
6582         u8         reserved_at_10[0x4];
6583         u8         proto_mask[0x4];
6584         u8         reserved_at_18[0x8];
6585
6586         u8         reserved_at_20[0x10];
6587         u8         lane_speed[0x10];
6588
6589         u8         reserved_at_40[0x17];
6590         u8         lpbf[0x1];
6591         u8         fec_mode_policy[0x8];
6592
6593         u8         retransmission_capability[0x8];
6594         u8         fec_mode_capability[0x18];
6595
6596         u8         retransmission_support_admin[0x8];
6597         u8         fec_mode_support_admin[0x18];
6598
6599         u8         retransmission_request_admin[0x8];
6600         u8         fec_mode_request_admin[0x18];
6601
6602         u8         reserved_at_c0[0x80];
6603 };
6604
6605 struct mlx5_ifc_plib_reg_bits {
6606         u8         reserved_at_0[0x8];
6607         u8         local_port[0x8];
6608         u8         reserved_at_10[0x8];
6609         u8         ib_port[0x8];
6610
6611         u8         reserved_at_20[0x60];
6612 };
6613
6614 struct mlx5_ifc_plbf_reg_bits {
6615         u8         reserved_at_0[0x8];
6616         u8         local_port[0x8];
6617         u8         reserved_at_10[0xd];
6618         u8         lbf_mode[0x3];
6619
6620         u8         reserved_at_20[0x20];
6621 };
6622
6623 struct mlx5_ifc_pipg_reg_bits {
6624         u8         reserved_at_0[0x8];
6625         u8         local_port[0x8];
6626         u8         reserved_at_10[0x10];
6627
6628         u8         dic[0x1];
6629         u8         reserved_at_21[0x19];
6630         u8         ipg[0x4];
6631         u8         reserved_at_3e[0x2];
6632 };
6633
6634 struct mlx5_ifc_pifr_reg_bits {
6635         u8         reserved_at_0[0x8];
6636         u8         local_port[0x8];
6637         u8         reserved_at_10[0x10];
6638
6639         u8         reserved_at_20[0xe0];
6640
6641         u8         port_filter[8][0x20];
6642
6643         u8         port_filter_update_en[8][0x20];
6644 };
6645
6646 struct mlx5_ifc_pfcc_reg_bits {
6647         u8         reserved_at_0[0x8];
6648         u8         local_port[0x8];
6649         u8         reserved_at_10[0x10];
6650
6651         u8         ppan[0x4];
6652         u8         reserved_at_24[0x4];
6653         u8         prio_mask_tx[0x8];
6654         u8         reserved_at_30[0x8];
6655         u8         prio_mask_rx[0x8];
6656
6657         u8         pptx[0x1];
6658         u8         aptx[0x1];
6659         u8         reserved_at_42[0x6];
6660         u8         pfctx[0x8];
6661         u8         reserved_at_50[0x10];
6662
6663         u8         pprx[0x1];
6664         u8         aprx[0x1];
6665         u8         reserved_at_62[0x6];
6666         u8         pfcrx[0x8];
6667         u8         reserved_at_70[0x10];
6668
6669         u8         reserved_at_80[0x80];
6670 };
6671
6672 struct mlx5_ifc_pelc_reg_bits {
6673         u8         op[0x4];
6674         u8         reserved_at_4[0x4];
6675         u8         local_port[0x8];
6676         u8         reserved_at_10[0x10];
6677
6678         u8         op_admin[0x8];
6679         u8         op_capability[0x8];
6680         u8         op_request[0x8];
6681         u8         op_active[0x8];
6682
6683         u8         admin[0x40];
6684
6685         u8         capability[0x40];
6686
6687         u8         request[0x40];
6688
6689         u8         active[0x40];
6690
6691         u8         reserved_at_140[0x80];
6692 };
6693
6694 struct mlx5_ifc_peir_reg_bits {
6695         u8         reserved_at_0[0x8];
6696         u8         local_port[0x8];
6697         u8         reserved_at_10[0x10];
6698
6699         u8         reserved_at_20[0xc];
6700         u8         error_count[0x4];
6701         u8         reserved_at_30[0x10];
6702
6703         u8         reserved_at_40[0xc];
6704         u8         lane[0x4];
6705         u8         reserved_at_50[0x8];
6706         u8         error_type[0x8];
6707 };
6708
6709 struct mlx5_ifc_pcap_reg_bits {
6710         u8         reserved_at_0[0x8];
6711         u8         local_port[0x8];
6712         u8         reserved_at_10[0x10];
6713
6714         u8         port_capability_mask[4][0x20];
6715 };
6716
6717 struct mlx5_ifc_paos_reg_bits {
6718         u8         swid[0x8];
6719         u8         local_port[0x8];
6720         u8         reserved_at_10[0x4];
6721         u8         admin_status[0x4];
6722         u8         reserved_at_18[0x4];
6723         u8         oper_status[0x4];
6724
6725         u8         ase[0x1];
6726         u8         ee[0x1];
6727         u8         reserved_at_22[0x1c];
6728         u8         e[0x2];
6729
6730         u8         reserved_at_40[0x40];
6731 };
6732
6733 struct mlx5_ifc_pamp_reg_bits {
6734         u8         reserved_at_0[0x8];
6735         u8         opamp_group[0x8];
6736         u8         reserved_at_10[0xc];
6737         u8         opamp_group_type[0x4];
6738
6739         u8         start_index[0x10];
6740         u8         reserved_at_30[0x4];
6741         u8         num_of_indices[0xc];
6742
6743         u8         index_data[18][0x10];
6744 };
6745
6746 struct mlx5_ifc_lane_2_module_mapping_bits {
6747         u8         reserved_at_0[0x6];
6748         u8         rx_lane[0x2];
6749         u8         reserved_at_8[0x6];
6750         u8         tx_lane[0x2];
6751         u8         reserved_at_10[0x8];
6752         u8         module[0x8];
6753 };
6754
6755 struct mlx5_ifc_bufferx_reg_bits {
6756         u8         reserved_at_0[0x6];
6757         u8         lossy[0x1];
6758         u8         epsb[0x1];
6759         u8         reserved_at_8[0xc];
6760         u8         size[0xc];
6761
6762         u8         xoff_threshold[0x10];
6763         u8         xon_threshold[0x10];
6764 };
6765
6766 struct mlx5_ifc_set_node_in_bits {
6767         u8         node_description[64][0x8];
6768 };
6769
6770 struct mlx5_ifc_register_power_settings_bits {
6771         u8         reserved_at_0[0x18];
6772         u8         power_settings_level[0x8];
6773
6774         u8         reserved_at_20[0x60];
6775 };
6776
6777 struct mlx5_ifc_register_host_endianness_bits {
6778         u8         he[0x1];
6779         u8         reserved_at_1[0x1f];
6780
6781         u8         reserved_at_20[0x60];
6782 };
6783
6784 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6785         u8         reserved_at_0[0x20];
6786
6787         u8         mkey[0x20];
6788
6789         u8         addressh_63_32[0x20];
6790
6791         u8         addressl_31_0[0x20];
6792 };
6793
6794 struct mlx5_ifc_ud_adrs_vector_bits {
6795         u8         dc_key[0x40];
6796
6797         u8         ext[0x1];
6798         u8         reserved_at_41[0x7];
6799         u8         destination_qp_dct[0x18];
6800
6801         u8         static_rate[0x4];
6802         u8         sl_eth_prio[0x4];
6803         u8         fl[0x1];
6804         u8         mlid[0x7];
6805         u8         rlid_udp_sport[0x10];
6806
6807         u8         reserved_at_80[0x20];
6808
6809         u8         rmac_47_16[0x20];
6810
6811         u8         rmac_15_0[0x10];
6812         u8         tclass[0x8];
6813         u8         hop_limit[0x8];
6814
6815         u8         reserved_at_e0[0x1];
6816         u8         grh[0x1];
6817         u8         reserved_at_e2[0x2];
6818         u8         src_addr_index[0x8];
6819         u8         flow_label[0x14];
6820
6821         u8         rgid_rip[16][0x8];
6822 };
6823
6824 struct mlx5_ifc_pages_req_event_bits {
6825         u8         reserved_at_0[0x10];
6826         u8         function_id[0x10];
6827
6828         u8         num_pages[0x20];
6829
6830         u8         reserved_at_40[0xa0];
6831 };
6832
6833 struct mlx5_ifc_eqe_bits {
6834         u8         reserved_at_0[0x8];
6835         u8         event_type[0x8];
6836         u8         reserved_at_10[0x8];
6837         u8         event_sub_type[0x8];
6838
6839         u8         reserved_at_20[0xe0];
6840
6841         union mlx5_ifc_event_auto_bits event_data;
6842
6843         u8         reserved_at_1e0[0x10];
6844         u8         signature[0x8];
6845         u8         reserved_at_1f8[0x7];
6846         u8         owner[0x1];
6847 };
6848
6849 enum {
6850         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6851 };
6852
6853 struct mlx5_ifc_cmd_queue_entry_bits {
6854         u8         type[0x8];
6855         u8         reserved_at_8[0x18];
6856
6857         u8         input_length[0x20];
6858
6859         u8         input_mailbox_pointer_63_32[0x20];
6860
6861         u8         input_mailbox_pointer_31_9[0x17];
6862         u8         reserved_at_77[0x9];
6863
6864         u8         command_input_inline_data[16][0x8];
6865
6866         u8         command_output_inline_data[16][0x8];
6867
6868         u8         output_mailbox_pointer_63_32[0x20];
6869
6870         u8         output_mailbox_pointer_31_9[0x17];
6871         u8         reserved_at_1b7[0x9];
6872
6873         u8         output_length[0x20];
6874
6875         u8         token[0x8];
6876         u8         signature[0x8];
6877         u8         reserved_at_1f0[0x8];
6878         u8         status[0x7];
6879         u8         ownership[0x1];
6880 };
6881
6882 struct mlx5_ifc_cmd_out_bits {
6883         u8         status[0x8];
6884         u8         reserved_at_8[0x18];
6885
6886         u8         syndrome[0x20];
6887
6888         u8         command_output[0x20];
6889 };
6890
6891 struct mlx5_ifc_cmd_in_bits {
6892         u8         opcode[0x10];
6893         u8         reserved_at_10[0x10];
6894
6895         u8         reserved_at_20[0x10];
6896         u8         op_mod[0x10];
6897
6898         u8         command[0][0x20];
6899 };
6900
6901 struct mlx5_ifc_cmd_if_box_bits {
6902         u8         mailbox_data[512][0x8];
6903
6904         u8         reserved_at_1000[0x180];
6905
6906         u8         next_pointer_63_32[0x20];
6907
6908         u8         next_pointer_31_10[0x16];
6909         u8         reserved_at_11b6[0xa];
6910
6911         u8         block_number[0x20];
6912
6913         u8         reserved_at_11e0[0x8];
6914         u8         token[0x8];
6915         u8         ctrl_signature[0x8];
6916         u8         signature[0x8];
6917 };
6918
6919 struct mlx5_ifc_mtt_bits {
6920         u8         ptag_63_32[0x20];
6921
6922         u8         ptag_31_8[0x18];
6923         u8         reserved_at_38[0x6];
6924         u8         wr_en[0x1];
6925         u8         rd_en[0x1];
6926 };
6927
6928 struct mlx5_ifc_query_wol_rol_out_bits {
6929         u8         status[0x8];
6930         u8         reserved_at_8[0x18];
6931
6932         u8         syndrome[0x20];
6933
6934         u8         reserved_at_40[0x10];
6935         u8         rol_mode[0x8];
6936         u8         wol_mode[0x8];
6937
6938         u8         reserved_at_60[0x20];
6939 };
6940
6941 struct mlx5_ifc_query_wol_rol_in_bits {
6942         u8         opcode[0x10];
6943         u8         reserved_at_10[0x10];
6944
6945         u8         reserved_at_20[0x10];
6946         u8         op_mod[0x10];
6947
6948         u8         reserved_at_40[0x40];
6949 };
6950
6951 struct mlx5_ifc_set_wol_rol_out_bits {
6952         u8         status[0x8];
6953         u8         reserved_at_8[0x18];
6954
6955         u8         syndrome[0x20];
6956
6957         u8         reserved_at_40[0x40];
6958 };
6959
6960 struct mlx5_ifc_set_wol_rol_in_bits {
6961         u8         opcode[0x10];
6962         u8         reserved_at_10[0x10];
6963
6964         u8         reserved_at_20[0x10];
6965         u8         op_mod[0x10];
6966
6967         u8         rol_mode_valid[0x1];
6968         u8         wol_mode_valid[0x1];
6969         u8         reserved_at_42[0xe];
6970         u8         rol_mode[0x8];
6971         u8         wol_mode[0x8];
6972
6973         u8         reserved_at_60[0x20];
6974 };
6975
6976 enum {
6977         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
6978         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
6979         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
6980 };
6981
6982 enum {
6983         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
6984         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
6985         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
6986 };
6987
6988 enum {
6989         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
6990         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
6991         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
6992         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
6993         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
6994         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
6995         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
6996         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
6997         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
6998         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
6999         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7000 };
7001
7002 struct mlx5_ifc_initial_seg_bits {
7003         u8         fw_rev_minor[0x10];
7004         u8         fw_rev_major[0x10];
7005
7006         u8         cmd_interface_rev[0x10];
7007         u8         fw_rev_subminor[0x10];
7008
7009         u8         reserved_at_40[0x40];
7010
7011         u8         cmdq_phy_addr_63_32[0x20];
7012
7013         u8         cmdq_phy_addr_31_12[0x14];
7014         u8         reserved_at_b4[0x2];
7015         u8         nic_interface[0x2];
7016         u8         log_cmdq_size[0x4];
7017         u8         log_cmdq_stride[0x4];
7018
7019         u8         command_doorbell_vector[0x20];
7020
7021         u8         reserved_at_e0[0xf00];
7022
7023         u8         initializing[0x1];
7024         u8         reserved_at_fe1[0x4];
7025         u8         nic_interface_supported[0x3];
7026         u8         reserved_at_fe8[0x18];
7027
7028         struct mlx5_ifc_health_buffer_bits health_buffer;
7029
7030         u8         no_dram_nic_offset[0x20];
7031
7032         u8         reserved_at_1220[0x6e40];
7033
7034         u8         reserved_at_8060[0x1f];
7035         u8         clear_int[0x1];
7036
7037         u8         health_syndrome[0x8];
7038         u8         health_counter[0x18];
7039
7040         u8         reserved_at_80a0[0x17fc0];
7041 };
7042
7043 union mlx5_ifc_ports_control_registers_document_bits {
7044         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7045         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7046         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7047         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7048         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7049         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7050         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7051         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7052         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7053         struct mlx5_ifc_pamp_reg_bits pamp_reg;
7054         struct mlx5_ifc_paos_reg_bits paos_reg;
7055         struct mlx5_ifc_pcap_reg_bits pcap_reg;
7056         struct mlx5_ifc_peir_reg_bits peir_reg;
7057         struct mlx5_ifc_pelc_reg_bits pelc_reg;
7058         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7059         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7060         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7061         struct mlx5_ifc_pifr_reg_bits pifr_reg;
7062         struct mlx5_ifc_pipg_reg_bits pipg_reg;
7063         struct mlx5_ifc_plbf_reg_bits plbf_reg;
7064         struct mlx5_ifc_plib_reg_bits plib_reg;
7065         struct mlx5_ifc_plpc_reg_bits plpc_reg;
7066         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7067         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7068         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7069         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7070         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7071         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7072         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7073         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7074         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7075         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7076         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7077         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7078         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7079         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7080         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7081         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7082         struct mlx5_ifc_pude_reg_bits pude_reg;
7083         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7084         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7085         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7086         u8         reserved_at_0[0x60e0];
7087 };
7088
7089 union mlx5_ifc_debug_enhancements_document_bits {
7090         struct mlx5_ifc_health_buffer_bits health_buffer;
7091         u8         reserved_at_0[0x200];
7092 };
7093
7094 union mlx5_ifc_uplink_pci_interface_document_bits {
7095         struct mlx5_ifc_initial_seg_bits initial_seg;
7096         u8         reserved_at_0[0x20060];
7097 };
7098
7099 struct mlx5_ifc_set_flow_table_root_out_bits {
7100         u8         status[0x8];
7101         u8         reserved_at_8[0x18];
7102
7103         u8         syndrome[0x20];
7104
7105         u8         reserved_at_40[0x40];
7106 };
7107
7108 struct mlx5_ifc_set_flow_table_root_in_bits {
7109         u8         opcode[0x10];
7110         u8         reserved_at_10[0x10];
7111
7112         u8         reserved_at_20[0x10];
7113         u8         op_mod[0x10];
7114
7115         u8         reserved_at_40[0x40];
7116
7117         u8         table_type[0x8];
7118         u8         reserved_at_88[0x18];
7119
7120         u8         reserved_at_a0[0x8];
7121         u8         table_id[0x18];
7122
7123         u8         reserved_at_c0[0x140];
7124 };
7125
7126 enum {
7127         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7128 };
7129
7130 struct mlx5_ifc_modify_flow_table_out_bits {
7131         u8         status[0x8];
7132         u8         reserved_at_8[0x18];
7133
7134         u8         syndrome[0x20];
7135
7136         u8         reserved_at_40[0x40];
7137 };
7138
7139 struct mlx5_ifc_modify_flow_table_in_bits {
7140         u8         opcode[0x10];
7141         u8         reserved_at_10[0x10];
7142
7143         u8         reserved_at_20[0x10];
7144         u8         op_mod[0x10];
7145
7146         u8         reserved_at_40[0x20];
7147
7148         u8         reserved_at_60[0x10];
7149         u8         modify_field_select[0x10];
7150
7151         u8         table_type[0x8];
7152         u8         reserved_at_88[0x18];
7153
7154         u8         reserved_at_a0[0x8];
7155         u8         table_id[0x18];
7156
7157         u8         reserved_at_c0[0x4];
7158         u8         table_miss_mode[0x4];
7159         u8         reserved_at_c8[0x18];
7160
7161         u8         reserved_at_e0[0x8];
7162         u8         table_miss_id[0x18];
7163
7164         u8         reserved_at_100[0x100];
7165 };
7166
7167 struct mlx5_ifc_ets_tcn_config_reg_bits {
7168         u8         g[0x1];
7169         u8         b[0x1];
7170         u8         r[0x1];
7171         u8         reserved_at_3[0x9];
7172         u8         group[0x4];
7173         u8         reserved_at_10[0x9];
7174         u8         bw_allocation[0x7];
7175
7176         u8         reserved_at_20[0xc];
7177         u8         max_bw_units[0x4];
7178         u8         reserved_at_30[0x8];
7179         u8         max_bw_value[0x8];
7180 };
7181
7182 struct mlx5_ifc_ets_global_config_reg_bits {
7183         u8         reserved_at_0[0x2];
7184         u8         r[0x1];
7185         u8         reserved_at_3[0x1d];
7186
7187         u8         reserved_at_20[0xc];
7188         u8         max_bw_units[0x4];
7189         u8         reserved_at_30[0x8];
7190         u8         max_bw_value[0x8];
7191 };
7192
7193 struct mlx5_ifc_qetc_reg_bits {
7194         u8                                         reserved_at_0[0x8];
7195         u8                                         port_number[0x8];
7196         u8                                         reserved_at_10[0x30];
7197
7198         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
7199         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7200 };
7201
7202 struct mlx5_ifc_qtct_reg_bits {
7203         u8         reserved_at_0[0x8];
7204         u8         port_number[0x8];
7205         u8         reserved_at_10[0xd];
7206         u8         prio[0x3];
7207
7208         u8         reserved_at_20[0x1d];
7209         u8         tclass[0x3];
7210 };
7211
7212 #endif /* MLX5_IFC_H */