include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  71         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  72         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  73         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  74         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  75         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  76         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  77         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  78         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  79         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  80         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  81         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  82         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  83         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  84         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  85         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  86         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  87         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  88         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  89         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  90         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  91         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  92         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  93         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  94         MLX5_CMD_OP_CREATE_QP                     = 0x500,
  95         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
  96         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
  97         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
  98         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
  99         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 100         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 101         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 102         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 103         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 104         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 105         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 106         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 107         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 108         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 109         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 110         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 111         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 112         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 113         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 114         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 115         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 116         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 117         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 118         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 119         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 120         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 121         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 122         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 123         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 124         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 125         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 126         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 127         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 128         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 129         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 130         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 131         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 132         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 133         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 134         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 135         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 136         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 137         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 138         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 139         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 140         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 141         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 142         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 143         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 144         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 145         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 146         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 147         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 148         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 149         MLX5_CMD_OP_NOP                           = 0x80d,
 150         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 151         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 152         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 153         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 154         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 155         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 156         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 157         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 158         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 159         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 160         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 161         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 162         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 163         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 164         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 165         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 166         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 167         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 168         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 169         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 170         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 171         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 172         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 173         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 174         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 175         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 176         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 177         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 178         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 179         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 180         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 181         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 182         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 183         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 184         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 185         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 186         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 187         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 188         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 189         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 190         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 191         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 192         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 193         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 194         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 195         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 196         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938
 197 };
 198
 199 struct mlx5_ifc_flow_table_fields_supported_bits {
 200         u8         outer_dmac[0x1];
 201         u8         outer_smac[0x1];
 202         u8         outer_ether_type[0x1];
 203         u8         reserved_0[0x1];
 204         u8         outer_first_prio[0x1];
 205         u8         outer_first_cfi[0x1];
 206         u8         outer_first_vid[0x1];
 207         u8         reserved_1[0x1];
 208         u8         outer_second_prio[0x1];
 209         u8         outer_second_cfi[0x1];
 210         u8         outer_second_vid[0x1];
 211         u8         reserved_2[0x1];
 212         u8         outer_sip[0x1];
 213         u8         outer_dip[0x1];
 214         u8         outer_frag[0x1];
 215         u8         outer_ip_protocol[0x1];
 216         u8         outer_ip_ecn[0x1];
 217         u8         outer_ip_dscp[0x1];
 218         u8         outer_udp_sport[0x1];
 219         u8         outer_udp_dport[0x1];
 220         u8         outer_tcp_sport[0x1];
 221         u8         outer_tcp_dport[0x1];
 222         u8         outer_tcp_flags[0x1];
 223         u8         outer_gre_protocol[0x1];
 224         u8         outer_gre_key[0x1];
 225         u8         outer_vxlan_vni[0x1];
 226         u8         reserved_3[0x5];
 227         u8         source_eswitch_port[0x1];
 228
 229         u8         inner_dmac[0x1];
 230         u8         inner_smac[0x1];
 231         u8         inner_ether_type[0x1];
 232         u8         reserved_4[0x1];
 233         u8         inner_first_prio[0x1];
 234         u8         inner_first_cfi[0x1];
 235         u8         inner_first_vid[0x1];
 236         u8         reserved_5[0x1];
 237         u8         inner_second_prio[0x1];
 238         u8         inner_second_cfi[0x1];
 239         u8         inner_second_vid[0x1];
 240         u8         reserved_6[0x1];
 241         u8         inner_sip[0x1];
 242         u8         inner_dip[0x1];
 243         u8         inner_frag[0x1];
 244         u8         inner_ip_protocol[0x1];
 245         u8         inner_ip_ecn[0x1];
 246         u8         inner_ip_dscp[0x1];
 247         u8         inner_udp_sport[0x1];
 248         u8         inner_udp_dport[0x1];
 249         u8         inner_tcp_sport[0x1];
 250         u8         inner_tcp_dport[0x1];
 251         u8         inner_tcp_flags[0x1];
 252         u8         reserved_7[0x9];
 253
 254         u8         reserved_8[0x40];
 255 };
 256
 257 struct mlx5_ifc_flow_table_prop_layout_bits {
 258         u8         ft_support[0x1];
 259         u8         reserved_0[0x1f];
 260
 261         u8         reserved_1[0x2];
 262         u8         log_max_ft_size[0x6];
 263         u8         reserved_2[0x10];
 264         u8         max_ft_level[0x8];
 265
 266         u8         reserved_3[0x20];
 267
 268         u8         reserved_4[0x18];
 269         u8         log_max_ft_num[0x8];
 270
 271         u8         reserved_5[0x18];
 272         u8         log_max_destination[0x8];
 273
 274         u8         reserved_6[0x18];
 275         u8         log_max_flow[0x8];
 276
 277         u8         reserved_7[0x40];
 278
 279         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 280
 281         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 282 };
 283
 284 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 285         u8         send[0x1];
 286         u8         receive[0x1];
 287         u8         write[0x1];
 288         u8         read[0x1];
 289         u8         reserved_0[0x1];
 290         u8         srq_receive[0x1];
 291         u8         reserved_1[0x1a];
 292 };
 293
 294 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 295         u8         smac_47_16[0x20];
 296
 297         u8         smac_15_0[0x10];
 298         u8         ethertype[0x10];
 299
 300         u8         dmac_47_16[0x20];
 301
 302         u8         dmac_15_0[0x10];
 303         u8         first_prio[0x3];
 304         u8         first_cfi[0x1];
 305         u8         first_vid[0xc];
 306
 307         u8         ip_protocol[0x8];
 308         u8         ip_dscp[0x6];
 309         u8         ip_ecn[0x2];
 310         u8         vlan_tag[0x1];
 311         u8         reserved_0[0x1];
 312         u8         frag[0x1];
 313         u8         reserved_1[0x4];
 314         u8         tcp_flags[0x9];
 315
 316         u8         tcp_sport[0x10];
 317         u8         tcp_dport[0x10];
 318
 319         u8         reserved_2[0x20];
 320
 321         u8         udp_sport[0x10];
 322         u8         udp_dport[0x10];
 323
 324         u8         src_ip[4][0x20];
 325
 326         u8         dst_ip[4][0x20];
 327 };
 328
 329 struct mlx5_ifc_fte_match_set_misc_bits {
 330         u8         reserved_0[0x20];
 331
 332         u8         reserved_1[0x10];
 333         u8         source_port[0x10];
 334
 335         u8         outer_second_prio[0x3];
 336         u8         outer_second_cfi[0x1];
 337         u8         outer_second_vid[0xc];
 338         u8         inner_second_prio[0x3];
 339         u8         inner_second_cfi[0x1];
 340         u8         inner_second_vid[0xc];
 341
 342         u8         outer_second_vlan_tag[0x1];
 343         u8         inner_second_vlan_tag[0x1];
 344         u8         reserved_2[0xe];
 345         u8         gre_protocol[0x10];
 346
 347         u8         gre_key_h[0x18];
 348         u8         gre_key_l[0x8];
 349
 350         u8         vxlan_vni[0x18];
 351         u8         reserved_3[0x8];
 352
 353         u8         reserved_4[0x20];
 354
 355         u8         reserved_5[0xc];
 356         u8         outer_ipv6_flow_label[0x14];
 357
 358         u8         reserved_6[0xc];
 359         u8         inner_ipv6_flow_label[0x14];
 360
 361         u8         reserved_7[0xe0];
 362 };
 363
 364 struct mlx5_ifc_cmd_pas_bits {
 365         u8         pa_h[0x20];
 366
 367         u8         pa_l[0x14];
 368         u8         reserved_0[0xc];
 369 };
 370
 371 struct mlx5_ifc_uint64_bits {
 372         u8         hi[0x20];
 373
 374         u8         lo[0x20];
 375 };
 376
 377 enum {
 378         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 379         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 380         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 381         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 382         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 383         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 384         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 385         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 386         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 387         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 388 };
 389
 390 struct mlx5_ifc_ads_bits {
 391         u8         fl[0x1];
 392         u8         free_ar[0x1];
 393         u8         reserved_0[0xe];
 394         u8         pkey_index[0x10];
 395
 396         u8         reserved_1[0x8];
 397         u8         grh[0x1];
 398         u8         mlid[0x7];
 399         u8         rlid[0x10];
 400
 401         u8         ack_timeout[0x5];
 402         u8         reserved_2[0x3];
 403         u8         src_addr_index[0x8];
 404         u8         reserved_3[0x4];
 405         u8         stat_rate[0x4];
 406         u8         hop_limit[0x8];
 407
 408         u8         reserved_4[0x4];
 409         u8         tclass[0x8];
 410         u8         flow_label[0x14];
 411
 412         u8         rgid_rip[16][0x8];
 413
 414         u8         reserved_5[0x4];
 415         u8         f_dscp[0x1];
 416         u8         f_ecn[0x1];
 417         u8         reserved_6[0x1];
 418         u8         f_eth_prio[0x1];
 419         u8         ecn[0x2];
 420         u8         dscp[0x6];
 421         u8         udp_sport[0x10];
 422
 423         u8         dei_cfi[0x1];
 424         u8         eth_prio[0x3];
 425         u8         sl[0x4];
 426         u8         port[0x8];
 427         u8         rmac_47_32[0x10];
 428
 429         u8         rmac_31_0[0x20];
 430 };
 431
 432 struct mlx5_ifc_flow_table_nic_cap_bits {
 433         u8         reserved_0[0x200];
 434
 435         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 436
 437         u8         reserved_1[0x200];
 438
 439         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 440
 441         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 442
 443         u8         reserved_2[0x200];
 444
 445         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 446
 447         u8         reserved_3[0x7200];
 448 };
 449
 450 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 451         u8     reserved_0[0x200];
 452
 453         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 454
 455         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 456
 457         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 458
 459         u8      reserved_1[0x7800];
 460 };
 461
 462 struct mlx5_ifc_e_switch_cap_bits {
 463         u8         vport_svlan_strip[0x1];
 464         u8         vport_cvlan_strip[0x1];
 465         u8         vport_svlan_insert[0x1];
 466         u8         vport_cvlan_insert_if_not_exist[0x1];
 467         u8         vport_cvlan_insert_overwrite[0x1];
 468         u8         reserved_0[0x1b];
 469
 470         u8         reserved_1[0x7e0];
 471 };
 472
 473 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 474         u8         csum_cap[0x1];
 475         u8         vlan_cap[0x1];
 476         u8         lro_cap[0x1];
 477         u8         lro_psh_flag[0x1];
 478         u8         lro_time_stamp[0x1];
 479         u8         reserved_0[0x3];
 480         u8         self_lb_en_modifiable[0x1];
 481         u8         reserved_1[0x2];
 482         u8         max_lso_cap[0x5];
 483         u8         reserved_2[0x4];
 484         u8         rss_ind_tbl_cap[0x4];
 485         u8         reserved_3[0x3];
 486         u8         tunnel_lso_const_out_ip_id[0x1];
 487         u8         reserved_4[0x2];
 488         u8         tunnel_statless_gre[0x1];
 489         u8         tunnel_stateless_vxlan[0x1];
 490
 491         u8         reserved_5[0x20];
 492
 493         u8         reserved_6[0x10];
 494         u8         lro_min_mss_size[0x10];
 495
 496         u8         reserved_7[0x120];
 497
 498         u8         lro_timer_supported_periods[4][0x20];
 499
 500         u8         reserved_8[0x600];
 501 };
 502
 503 struct mlx5_ifc_roce_cap_bits {
 504         u8         roce_apm[0x1];
 505         u8         reserved_0[0x1f];
 506
 507         u8         reserved_1[0x60];
 508
 509         u8         reserved_2[0xc];
 510         u8         l3_type[0x4];
 511         u8         reserved_3[0x8];
 512         u8         roce_version[0x8];
 513
 514         u8         reserved_4[0x10];
 515         u8         r_roce_dest_udp_port[0x10];
 516
 517         u8         r_roce_max_src_udp_port[0x10];
 518         u8         r_roce_min_src_udp_port[0x10];
 519
 520         u8         reserved_5[0x10];
 521         u8         roce_address_table_size[0x10];
 522
 523         u8         reserved_6[0x700];
 524 };
 525
 526 enum {
 527         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 528         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 529         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 530         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 531         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 532         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 533         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 534         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 535         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 536 };
 537
 538 enum {
 539         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 540         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 541         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 542         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 543         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 544         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 545         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 546         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 547         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 548 };
 549
 550 struct mlx5_ifc_atomic_caps_bits {
 551         u8         reserved_0[0x40];
 552
 553         u8         atomic_req_endianness[0x1];
 554         u8         reserved_1[0x1f];
 555
 556         u8         reserved_2[0x20];
 557
 558         u8         reserved_3[0x10];
 559         u8         atomic_operations[0x10];
 560
 561         u8         reserved_4[0x10];
 562         u8         atomic_size_qp[0x10];
 563
 564         u8         reserved_5[0x10];
 565         u8         atomic_size_dc[0x10];
 566
 567         u8         reserved_6[0x720];
 568 };
 569
 570 struct mlx5_ifc_odp_cap_bits {
 571         u8         reserved_0[0x40];
 572
 573         u8         sig[0x1];
 574         u8         reserved_1[0x1f];
 575
 576         u8         reserved_2[0x20];
 577
 578         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 579
 580         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 581
 582         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 583
 584         u8         reserved_3[0x720];
 585 };
 586
 587 enum {
 588         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 589         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 590         MLX5_WQ_TYPE_STRQ         = 0x2,
 591 };
 592
 593 enum {
 594         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 595         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 596 };
 597
 598 enum {
 599         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 600         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 601         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 602         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 603         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 604 };
 605
 606 enum {
 607         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 608         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 609         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 610         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 611         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 612         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 613 };
 614
 615 enum {
 616         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 617         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 618 };
 619
 620 enum {
 621         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 622         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 623         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 624 };
 625
 626 enum {
 627         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 628         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 629 };
 630
 631 struct mlx5_ifc_cmd_hca_cap_bits {
 632         u8         reserved_0[0x80];
 633
 634         u8         log_max_srq_sz[0x8];
 635         u8         log_max_qp_sz[0x8];
 636         u8         reserved_1[0xb];
 637         u8         log_max_qp[0x5];
 638
 639         u8         reserved_2[0xb];
 640         u8         log_max_srq[0x5];
 641         u8         reserved_3[0x10];
 642
 643         u8         reserved_4[0x8];
 644         u8         log_max_cq_sz[0x8];
 645         u8         reserved_5[0xb];
 646         u8         log_max_cq[0x5];
 647
 648         u8         log_max_eq_sz[0x8];
 649         u8         reserved_6[0x2];
 650         u8         log_max_mkey[0x6];
 651         u8         reserved_7[0xc];
 652         u8         log_max_eq[0x4];
 653
 654         u8         max_indirection[0x8];
 655         u8         reserved_8[0x1];
 656         u8         log_max_mrw_sz[0x7];
 657         u8         reserved_9[0x2];
 658         u8         log_max_bsf_list_size[0x6];
 659         u8         reserved_10[0x2];
 660         u8         log_max_klm_list_size[0x6];
 661
 662         u8         reserved_11[0xa];
 663         u8         log_max_ra_req_dc[0x6];
 664         u8         reserved_12[0xa];
 665         u8         log_max_ra_res_dc[0x6];
 666
 667         u8         reserved_13[0xa];
 668         u8         log_max_ra_req_qp[0x6];
 669         u8         reserved_14[0xa];
 670         u8         log_max_ra_res_qp[0x6];
 671
 672         u8         pad_cap[0x1];
 673         u8         cc_query_allowed[0x1];
 674         u8         cc_modify_allowed[0x1];
 675         u8         reserved_15[0xd];
 676         u8         gid_table_size[0x10];
 677
 678         u8         out_of_seq_cnt[0x1];
 679         u8         vport_counters[0x1];
 680         u8         reserved_16[0x4];
 681         u8         max_qp_cnt[0xa];
 682         u8         pkey_table_size[0x10];
 683
 684         u8         vport_group_manager[0x1];
 685         u8         vhca_group_manager[0x1];
 686         u8         ib_virt[0x1];
 687         u8         eth_virt[0x1];
 688         u8         reserved_17[0x1];
 689         u8         ets[0x1];
 690         u8         nic_flow_table[0x1];
 691         u8         eswitch_flow_table[0x1];
 692         u8         early_vf_enable;
 693         u8         reserved_18[0x2];
 694         u8         local_ca_ack_delay[0x5];
 695         u8         reserved_19[0x6];
 696         u8         port_type[0x2];
 697         u8         num_ports[0x8];
 698
 699         u8         reserved_20[0x3];
 700         u8         log_max_msg[0x5];
 701         u8         reserved_21[0x18];
 702
 703         u8         stat_rate_support[0x10];
 704         u8         reserved_22[0xc];
 705         u8         cqe_version[0x4];
 706
 707         u8         compact_address_vector[0x1];
 708         u8         reserved_23[0xe];
 709         u8         drain_sigerr[0x1];
 710         u8         cmdif_checksum[0x2];
 711         u8         sigerr_cqe[0x1];
 712         u8         reserved_24[0x1];
 713         u8         wq_signature[0x1];
 714         u8         sctr_data_cqe[0x1];
 715         u8         reserved_25[0x1];
 716         u8         sho[0x1];
 717         u8         tph[0x1];
 718         u8         rf[0x1];
 719         u8         dct[0x1];
 720         u8         reserved_26[0x1];
 721         u8         eth_net_offloads[0x1];
 722         u8         roce[0x1];
 723         u8         atomic[0x1];
 724         u8         reserved_27[0x1];
 725
 726         u8         cq_oi[0x1];
 727         u8         cq_resize[0x1];
 728         u8         cq_moderation[0x1];
 729         u8         reserved_28[0x3];
 730         u8         cq_eq_remap[0x1];
 731         u8         pg[0x1];
 732         u8         block_lb_mc[0x1];
 733         u8         reserved_29[0x1];
 734         u8         scqe_break_moderation[0x1];
 735         u8         reserved_30[0x1];
 736         u8         cd[0x1];
 737         u8         reserved_31[0x1];
 738         u8         apm[0x1];
 739         u8         reserved_32[0x7];
 740         u8         qkv[0x1];
 741         u8         pkv[0x1];
 742         u8         reserved_33[0x4];
 743         u8         xrc[0x1];
 744         u8         ud[0x1];
 745         u8         uc[0x1];
 746         u8         rc[0x1];
 747
 748         u8         reserved_34[0xa];
 749         u8         uar_sz[0x6];
 750         u8         reserved_35[0x8];
 751         u8         log_pg_sz[0x8];
 752
 753         u8         bf[0x1];
 754         u8         reserved_36[0x1];
 755         u8         pad_tx_eth_packet[0x1];
 756         u8         reserved_37[0x8];
 757         u8         log_bf_reg_size[0x5];
 758         u8         reserved_38[0x10];
 759
 760         u8         reserved_39[0x10];
 761         u8         max_wqe_sz_sq[0x10];
 762
 763         u8         reserved_40[0x10];
 764         u8         max_wqe_sz_rq[0x10];
 765
 766         u8         reserved_41[0x10];
 767         u8         max_wqe_sz_sq_dc[0x10];
 768
 769         u8         reserved_42[0x7];
 770         u8         max_qp_mcg[0x19];
 771
 772         u8         reserved_43[0x18];
 773         u8         log_max_mcg[0x8];
 774
 775         u8         reserved_44[0x3];
 776         u8         log_max_transport_domain[0x5];
 777         u8         reserved_45[0x3];
 778         u8         log_max_pd[0x5];
 779         u8         reserved_46[0xb];
 780         u8         log_max_xrcd[0x5];
 781
 782         u8         reserved_47[0x20];
 783
 784         u8         reserved_48[0x3];
 785         u8         log_max_rq[0x5];
 786         u8         reserved_49[0x3];
 787         u8         log_max_sq[0x5];
 788         u8         reserved_50[0x3];
 789         u8         log_max_tir[0x5];
 790         u8         reserved_51[0x3];
 791         u8         log_max_tis[0x5];
 792
 793         u8         basic_cyclic_rcv_wqe[0x1];
 794         u8         reserved_52[0x2];
 795         u8         log_max_rmp[0x5];
 796         u8         reserved_53[0x3];
 797         u8         log_max_rqt[0x5];
 798         u8         reserved_54[0x3];
 799         u8         log_max_rqt_size[0x5];
 800         u8         reserved_55[0x3];
 801         u8         log_max_tis_per_sq[0x5];
 802
 803         u8         reserved_56[0x3];
 804         u8         log_max_stride_sz_rq[0x5];
 805         u8         reserved_57[0x3];
 806         u8         log_min_stride_sz_rq[0x5];
 807         u8         reserved_58[0x3];
 808         u8         log_max_stride_sz_sq[0x5];
 809         u8         reserved_59[0x3];
 810         u8         log_min_stride_sz_sq[0x5];
 811
 812         u8         reserved_60[0x1b];
 813         u8         log_max_wq_sz[0x5];
 814
 815         u8         nic_vport_change_event[0x1];
 816         u8         reserved_61[0xa];
 817         u8         log_max_vlan_list[0x5];
 818         u8         reserved_62[0x3];
 819         u8         log_max_current_mc_list[0x5];
 820         u8         reserved_63[0x3];
 821         u8         log_max_current_uc_list[0x5];
 822
 823         u8         reserved_64[0x80];
 824
 825         u8         reserved_65[0x3];
 826         u8         log_max_l2_table[0x5];
 827         u8         reserved_66[0x8];
 828         u8         log_uar_page_sz[0x10];
 829
 830         u8         reserved_67[0xe0];
 831
 832         u8         reserved_68[0x1f];
 833         u8         cqe_zip[0x1];
 834
 835         u8         cqe_zip_timeout[0x10];
 836         u8         cqe_zip_max_num[0x10];
 837
 838         u8         reserved_69[0x220];
 839 };
 840
 841 enum mlx5_flow_destination_type {
 842         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 843         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 844         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 845 };
 846
 847 struct mlx5_ifc_dest_format_struct_bits {
 848         u8         destination_type[0x8];
 849         u8         destination_id[0x18];
 850
 851         u8         reserved_0[0x20];
 852 };
 853
 854 struct mlx5_ifc_fte_match_param_bits {
 855         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 856
 857         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 858
 859         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 860
 861         u8         reserved_0[0xa00];
 862 };
 863
 864 enum {
 865         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 866         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 867         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 868         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 869         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 870 };
 871
 872 struct mlx5_ifc_rx_hash_field_select_bits {
 873         u8         l3_prot_type[0x1];
 874         u8         l4_prot_type[0x1];
 875         u8         selected_fields[0x1e];
 876 };
 877
 878 enum {
 879         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
 880         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
 881 };
 882
 883 enum {
 884         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
 885         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
 886 };
 887
 888 struct mlx5_ifc_wq_bits {
 889         u8         wq_type[0x4];
 890         u8         wq_signature[0x1];
 891         u8         end_padding_mode[0x2];
 892         u8         cd_slave[0x1];
 893         u8         reserved_0[0x18];
 894
 895         u8         hds_skip_first_sge[0x1];
 896         u8         log2_hds_buf_size[0x3];
 897         u8         reserved_1[0x7];
 898         u8         page_offset[0x5];
 899         u8         lwm[0x10];
 900
 901         u8         reserved_2[0x8];
 902         u8         pd[0x18];
 903
 904         u8         reserved_3[0x8];
 905         u8         uar_page[0x18];
 906
 907         u8         dbr_addr[0x40];
 908
 909         u8         hw_counter[0x20];
 910
 911         u8         sw_counter[0x20];
 912
 913         u8         reserved_4[0xc];
 914         u8         log_wq_stride[0x4];
 915         u8         reserved_5[0x3];
 916         u8         log_wq_pg_sz[0x5];
 917         u8         reserved_6[0x3];
 918         u8         log_wq_sz[0x5];
 919
 920         u8         reserved_7[0x4e0];
 921
 922         struct mlx5_ifc_cmd_pas_bits pas[0];
 923 };
 924
 925 struct mlx5_ifc_rq_num_bits {
 926         u8         reserved_0[0x8];
 927         u8         rq_num[0x18];
 928 };
 929
 930 struct mlx5_ifc_mac_address_layout_bits {
 931         u8         reserved_0[0x10];
 932         u8         mac_addr_47_32[0x10];
 933
 934         u8         mac_addr_31_0[0x20];
 935 };
 936
 937 struct mlx5_ifc_vlan_layout_bits {
 938         u8         reserved_0[0x14];
 939         u8         vlan[0x0c];
 940
 941         u8         reserved_1[0x20];
 942 };
 943
 944 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
 945         u8         reserved_0[0xa0];
 946
 947         u8         min_time_between_cnps[0x20];
 948
 949         u8         reserved_1[0x12];
 950         u8         cnp_dscp[0x6];
 951         u8         reserved_2[0x5];
 952         u8         cnp_802p_prio[0x3];
 953
 954         u8         reserved_3[0x720];
 955 };
 956
 957 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
 958         u8         reserved_0[0x60];
 959
 960         u8         reserved_1[0x4];
 961         u8         clamp_tgt_rate[0x1];
 962         u8         reserved_2[0x3];
 963         u8         clamp_tgt_rate_after_time_inc[0x1];
 964         u8         reserved_3[0x17];
 965
 966         u8         reserved_4[0x20];
 967
 968         u8         rpg_time_reset[0x20];
 969
 970         u8         rpg_byte_reset[0x20];
 971
 972         u8         rpg_threshold[0x20];
 973
 974         u8         rpg_max_rate[0x20];
 975
 976         u8         rpg_ai_rate[0x20];
 977
 978         u8         rpg_hai_rate[0x20];
 979
 980         u8         rpg_gd[0x20];
 981
 982         u8         rpg_min_dec_fac[0x20];
 983
 984         u8         rpg_min_rate[0x20];
 985
 986         u8         reserved_5[0xe0];
 987
 988         u8         rate_to_set_on_first_cnp[0x20];
 989
 990         u8         dce_tcp_g[0x20];
 991
 992         u8         dce_tcp_rtt[0x20];
 993
 994         u8         rate_reduce_monitor_period[0x20];
 995
 996         u8         reserved_6[0x20];
 997
 998         u8         initial_alpha_value[0x20];
 999
1000         u8         reserved_7[0x4a0];
1001 };
1002
1003 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1004         u8         reserved_0[0x80];
1005
1006         u8         rppp_max_rps[0x20];
1007
1008         u8         rpg_time_reset[0x20];
1009
1010         u8         rpg_byte_reset[0x20];
1011
1012         u8         rpg_threshold[0x20];
1013
1014         u8         rpg_max_rate[0x20];
1015
1016         u8         rpg_ai_rate[0x20];
1017
1018         u8         rpg_hai_rate[0x20];
1019
1020         u8         rpg_gd[0x20];
1021
1022         u8         rpg_min_dec_fac[0x20];
1023
1024         u8         rpg_min_rate[0x20];
1025
1026         u8         reserved_1[0x640];
1027 };
1028
1029 enum {
1030         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1031         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1032         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1033 };
1034
1035 struct mlx5_ifc_resize_field_select_bits {
1036         u8         resize_field_select[0x20];
1037 };
1038
1039 enum {
1040         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1041         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1042         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1043         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1044 };
1045
1046 struct mlx5_ifc_modify_field_select_bits {
1047         u8         modify_field_select[0x20];
1048 };
1049
1050 struct mlx5_ifc_field_select_r_roce_np_bits {
1051         u8         field_select_r_roce_np[0x20];
1052 };
1053
1054 struct mlx5_ifc_field_select_r_roce_rp_bits {
1055         u8         field_select_r_roce_rp[0x20];
1056 };
1057
1058 enum {
1059         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1060         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1061         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1062         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1063         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1064         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1065         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1066         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1067         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1068         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1069 };
1070
1071 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1072         u8         field_select_8021qaurp[0x20];
1073 };
1074
1075 struct mlx5_ifc_phys_layer_cntrs_bits {
1076         u8         time_since_last_clear_high[0x20];
1077
1078         u8         time_since_last_clear_low[0x20];
1079
1080         u8         symbol_errors_high[0x20];
1081
1082         u8         symbol_errors_low[0x20];
1083
1084         u8         sync_headers_errors_high[0x20];
1085
1086         u8         sync_headers_errors_low[0x20];
1087
1088         u8         edpl_bip_errors_lane0_high[0x20];
1089
1090         u8         edpl_bip_errors_lane0_low[0x20];
1091
1092         u8         edpl_bip_errors_lane1_high[0x20];
1093
1094         u8         edpl_bip_errors_lane1_low[0x20];
1095
1096         u8         edpl_bip_errors_lane2_high[0x20];
1097
1098         u8         edpl_bip_errors_lane2_low[0x20];
1099
1100         u8         edpl_bip_errors_lane3_high[0x20];
1101
1102         u8         edpl_bip_errors_lane3_low[0x20];
1103
1104         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1105
1106         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1107
1108         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1109
1110         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1111
1112         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1113
1114         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1115
1116         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1117
1118         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1119
1120         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1121
1122         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1123
1124         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1125
1126         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1127
1128         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1129
1130         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1131
1132         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1133
1134         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1135
1136         u8         rs_fec_corrected_blocks_high[0x20];
1137
1138         u8         rs_fec_corrected_blocks_low[0x20];
1139
1140         u8         rs_fec_uncorrectable_blocks_high[0x20];
1141
1142         u8         rs_fec_uncorrectable_blocks_low[0x20];
1143
1144         u8         rs_fec_no_errors_blocks_high[0x20];
1145
1146         u8         rs_fec_no_errors_blocks_low[0x20];
1147
1148         u8         rs_fec_single_error_blocks_high[0x20];
1149
1150         u8         rs_fec_single_error_blocks_low[0x20];
1151
1152         u8         rs_fec_corrected_symbols_total_high[0x20];
1153
1154         u8         rs_fec_corrected_symbols_total_low[0x20];
1155
1156         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1157
1158         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1159
1160         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1161
1162         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1163
1164         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1165
1166         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1167
1168         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1169
1170         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1171
1172         u8         link_down_events[0x20];
1173
1174         u8         successful_recovery_events[0x20];
1175
1176         u8         reserved_0[0x180];
1177 };
1178
1179 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1180         u8         transmit_queue_high[0x20];
1181
1182         u8         transmit_queue_low[0x20];
1183
1184         u8         reserved_0[0x780];
1185 };
1186
1187 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1188         u8         rx_octets_high[0x20];
1189
1190         u8         rx_octets_low[0x20];
1191
1192         u8         reserved_0[0xc0];
1193
1194         u8         rx_frames_high[0x20];
1195
1196         u8         rx_frames_low[0x20];
1197
1198         u8         tx_octets_high[0x20];
1199
1200         u8         tx_octets_low[0x20];
1201
1202         u8         reserved_1[0xc0];
1203
1204         u8         tx_frames_high[0x20];
1205
1206         u8         tx_frames_low[0x20];
1207
1208         u8         rx_pause_high[0x20];
1209
1210         u8         rx_pause_low[0x20];
1211
1212         u8         rx_pause_duration_high[0x20];
1213
1214         u8         rx_pause_duration_low[0x20];
1215
1216         u8         tx_pause_high[0x20];
1217
1218         u8         tx_pause_low[0x20];
1219
1220         u8         tx_pause_duration_high[0x20];
1221
1222         u8         tx_pause_duration_low[0x20];
1223
1224         u8         rx_pause_transition_high[0x20];
1225
1226         u8         rx_pause_transition_low[0x20];
1227
1228         u8         reserved_2[0x400];
1229 };
1230
1231 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1232         u8         port_transmit_wait_high[0x20];
1233
1234         u8         port_transmit_wait_low[0x20];
1235
1236         u8         reserved_0[0x780];
1237 };
1238
1239 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1240         u8         dot3stats_alignment_errors_high[0x20];
1241
1242         u8         dot3stats_alignment_errors_low[0x20];
1243
1244         u8         dot3stats_fcs_errors_high[0x20];
1245
1246         u8         dot3stats_fcs_errors_low[0x20];
1247
1248         u8         dot3stats_single_collision_frames_high[0x20];
1249
1250         u8         dot3stats_single_collision_frames_low[0x20];
1251
1252         u8         dot3stats_multiple_collision_frames_high[0x20];
1253
1254         u8         dot3stats_multiple_collision_frames_low[0x20];
1255
1256         u8         dot3stats_sqe_test_errors_high[0x20];
1257
1258         u8         dot3stats_sqe_test_errors_low[0x20];
1259
1260         u8         dot3stats_deferred_transmissions_high[0x20];
1261
1262         u8         dot3stats_deferred_transmissions_low[0x20];
1263
1264         u8         dot3stats_late_collisions_high[0x20];
1265
1266         u8         dot3stats_late_collisions_low[0x20];
1267
1268         u8         dot3stats_excessive_collisions_high[0x20];
1269
1270         u8         dot3stats_excessive_collisions_low[0x20];
1271
1272         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1273
1274         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1275
1276         u8         dot3stats_carrier_sense_errors_high[0x20];
1277
1278         u8         dot3stats_carrier_sense_errors_low[0x20];
1279
1280         u8         dot3stats_frame_too_longs_high[0x20];
1281
1282         u8         dot3stats_frame_too_longs_low[0x20];
1283
1284         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1285
1286         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1287
1288         u8         dot3stats_symbol_errors_high[0x20];
1289
1290         u8         dot3stats_symbol_errors_low[0x20];
1291
1292         u8         dot3control_in_unknown_opcodes_high[0x20];
1293
1294         u8         dot3control_in_unknown_opcodes_low[0x20];
1295
1296         u8         dot3in_pause_frames_high[0x20];
1297
1298         u8         dot3in_pause_frames_low[0x20];
1299
1300         u8         dot3out_pause_frames_high[0x20];
1301
1302         u8         dot3out_pause_frames_low[0x20];
1303
1304         u8         reserved_0[0x3c0];
1305 };
1306
1307 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1308         u8         ether_stats_drop_events_high[0x20];
1309
1310         u8         ether_stats_drop_events_low[0x20];
1311
1312         u8         ether_stats_octets_high[0x20];
1313
1314         u8         ether_stats_octets_low[0x20];
1315
1316         u8         ether_stats_pkts_high[0x20];
1317
1318         u8         ether_stats_pkts_low[0x20];
1319
1320         u8         ether_stats_broadcast_pkts_high[0x20];
1321
1322         u8         ether_stats_broadcast_pkts_low[0x20];
1323
1324         u8         ether_stats_multicast_pkts_high[0x20];
1325
1326         u8         ether_stats_multicast_pkts_low[0x20];
1327
1328         u8         ether_stats_crc_align_errors_high[0x20];
1329
1330         u8         ether_stats_crc_align_errors_low[0x20];
1331
1332         u8         ether_stats_undersize_pkts_high[0x20];
1333
1334         u8         ether_stats_undersize_pkts_low[0x20];
1335
1336         u8         ether_stats_oversize_pkts_high[0x20];
1337
1338         u8         ether_stats_oversize_pkts_low[0x20];
1339
1340         u8         ether_stats_fragments_high[0x20];
1341
1342         u8         ether_stats_fragments_low[0x20];
1343
1344         u8         ether_stats_jabbers_high[0x20];
1345
1346         u8         ether_stats_jabbers_low[0x20];
1347
1348         u8         ether_stats_collisions_high[0x20];
1349
1350         u8         ether_stats_collisions_low[0x20];
1351
1352         u8         ether_stats_pkts64octets_high[0x20];
1353
1354         u8         ether_stats_pkts64octets_low[0x20];
1355
1356         u8         ether_stats_pkts65to127octets_high[0x20];
1357
1358         u8         ether_stats_pkts65to127octets_low[0x20];
1359
1360         u8         ether_stats_pkts128to255octets_high[0x20];
1361
1362         u8         ether_stats_pkts128to255octets_low[0x20];
1363
1364         u8         ether_stats_pkts256to511octets_high[0x20];
1365
1366         u8         ether_stats_pkts256to511octets_low[0x20];
1367
1368         u8         ether_stats_pkts512to1023octets_high[0x20];
1369
1370         u8         ether_stats_pkts512to1023octets_low[0x20];
1371
1372         u8         ether_stats_pkts1024to1518octets_high[0x20];
1373
1374         u8         ether_stats_pkts1024to1518octets_low[0x20];
1375
1376         u8         ether_stats_pkts1519to2047octets_high[0x20];
1377
1378         u8         ether_stats_pkts1519to2047octets_low[0x20];
1379
1380         u8         ether_stats_pkts2048to4095octets_high[0x20];
1381
1382         u8         ether_stats_pkts2048to4095octets_low[0x20];
1383
1384         u8         ether_stats_pkts4096to8191octets_high[0x20];
1385
1386         u8         ether_stats_pkts4096to8191octets_low[0x20];
1387
1388         u8         ether_stats_pkts8192to10239octets_high[0x20];
1389
1390         u8         ether_stats_pkts8192to10239octets_low[0x20];
1391
1392         u8         reserved_0[0x280];
1393 };
1394
1395 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1396         u8         if_in_octets_high[0x20];
1397
1398         u8         if_in_octets_low[0x20];
1399
1400         u8         if_in_ucast_pkts_high[0x20];
1401
1402         u8         if_in_ucast_pkts_low[0x20];
1403
1404         u8         if_in_discards_high[0x20];
1405
1406         u8         if_in_discards_low[0x20];
1407
1408         u8         if_in_errors_high[0x20];
1409
1410         u8         if_in_errors_low[0x20];
1411
1412         u8         if_in_unknown_protos_high[0x20];
1413
1414         u8         if_in_unknown_protos_low[0x20];
1415
1416         u8         if_out_octets_high[0x20];
1417
1418         u8         if_out_octets_low[0x20];
1419
1420         u8         if_out_ucast_pkts_high[0x20];
1421
1422         u8         if_out_ucast_pkts_low[0x20];
1423
1424         u8         if_out_discards_high[0x20];
1425
1426         u8         if_out_discards_low[0x20];
1427
1428         u8         if_out_errors_high[0x20];
1429
1430         u8         if_out_errors_low[0x20];
1431
1432         u8         if_in_multicast_pkts_high[0x20];
1433
1434         u8         if_in_multicast_pkts_low[0x20];
1435
1436         u8         if_in_broadcast_pkts_high[0x20];
1437
1438         u8         if_in_broadcast_pkts_low[0x20];
1439
1440         u8         if_out_multicast_pkts_high[0x20];
1441
1442         u8         if_out_multicast_pkts_low[0x20];
1443
1444         u8         if_out_broadcast_pkts_high[0x20];
1445
1446         u8         if_out_broadcast_pkts_low[0x20];
1447
1448         u8         reserved_0[0x480];
1449 };
1450
1451 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1452         u8         a_frames_transmitted_ok_high[0x20];
1453
1454         u8         a_frames_transmitted_ok_low[0x20];
1455
1456         u8         a_frames_received_ok_high[0x20];
1457
1458         u8         a_frames_received_ok_low[0x20];
1459
1460         u8         a_frame_check_sequence_errors_high[0x20];
1461
1462         u8         a_frame_check_sequence_errors_low[0x20];
1463
1464         u8         a_alignment_errors_high[0x20];
1465
1466         u8         a_alignment_errors_low[0x20];
1467
1468         u8         a_octets_transmitted_ok_high[0x20];
1469
1470         u8         a_octets_transmitted_ok_low[0x20];
1471
1472         u8         a_octets_received_ok_high[0x20];
1473
1474         u8         a_octets_received_ok_low[0x20];
1475
1476         u8         a_multicast_frames_xmitted_ok_high[0x20];
1477
1478         u8         a_multicast_frames_xmitted_ok_low[0x20];
1479
1480         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1481
1482         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1483
1484         u8         a_multicast_frames_received_ok_high[0x20];
1485
1486         u8         a_multicast_frames_received_ok_low[0x20];
1487
1488         u8         a_broadcast_frames_received_ok_high[0x20];
1489
1490         u8         a_broadcast_frames_received_ok_low[0x20];
1491
1492         u8         a_in_range_length_errors_high[0x20];
1493
1494         u8         a_in_range_length_errors_low[0x20];
1495
1496         u8         a_out_of_range_length_field_high[0x20];
1497
1498         u8         a_out_of_range_length_field_low[0x20];
1499
1500         u8         a_frame_too_long_errors_high[0x20];
1501
1502         u8         a_frame_too_long_errors_low[0x20];
1503
1504         u8         a_symbol_error_during_carrier_high[0x20];
1505
1506         u8         a_symbol_error_during_carrier_low[0x20];
1507
1508         u8         a_mac_control_frames_transmitted_high[0x20];
1509
1510         u8         a_mac_control_frames_transmitted_low[0x20];
1511
1512         u8         a_mac_control_frames_received_high[0x20];
1513
1514         u8         a_mac_control_frames_received_low[0x20];
1515
1516         u8         a_unsupported_opcodes_received_high[0x20];
1517
1518         u8         a_unsupported_opcodes_received_low[0x20];
1519
1520         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1521
1522         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1523
1524         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1525
1526         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1527
1528         u8         reserved_0[0x300];
1529 };
1530
1531 struct mlx5_ifc_cmd_inter_comp_event_bits {
1532         u8         command_completion_vector[0x20];
1533
1534         u8         reserved_0[0xc0];
1535 };
1536
1537 struct mlx5_ifc_stall_vl_event_bits {
1538         u8         reserved_0[0x18];
1539         u8         port_num[0x1];
1540         u8         reserved_1[0x3];
1541         u8         vl[0x4];
1542
1543         u8         reserved_2[0xa0];
1544 };
1545
1546 struct mlx5_ifc_db_bf_congestion_event_bits {
1547         u8         event_subtype[0x8];
1548         u8         reserved_0[0x8];
1549         u8         congestion_level[0x8];
1550         u8         reserved_1[0x8];
1551
1552         u8         reserved_2[0xa0];
1553 };
1554
1555 struct mlx5_ifc_gpio_event_bits {
1556         u8         reserved_0[0x60];
1557
1558         u8         gpio_event_hi[0x20];
1559
1560         u8         gpio_event_lo[0x20];
1561
1562         u8         reserved_1[0x40];
1563 };
1564
1565 struct mlx5_ifc_port_state_change_event_bits {
1566         u8         reserved_0[0x40];
1567
1568         u8         port_num[0x4];
1569         u8         reserved_1[0x1c];
1570
1571         u8         reserved_2[0x80];
1572 };
1573
1574 struct mlx5_ifc_dropped_packet_logged_bits {
1575         u8         reserved_0[0xe0];
1576 };
1577
1578 enum {
1579         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1580         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1581 };
1582
1583 struct mlx5_ifc_cq_error_bits {
1584         u8         reserved_0[0x8];
1585         u8         cqn[0x18];
1586
1587         u8         reserved_1[0x20];
1588
1589         u8         reserved_2[0x18];
1590         u8         syndrome[0x8];
1591
1592         u8         reserved_3[0x80];
1593 };
1594
1595 struct mlx5_ifc_rdma_page_fault_event_bits {
1596         u8         bytes_committed[0x20];
1597
1598         u8         r_key[0x20];
1599
1600         u8         reserved_0[0x10];
1601         u8         packet_len[0x10];
1602
1603         u8         rdma_op_len[0x20];
1604
1605         u8         rdma_va[0x40];
1606
1607         u8         reserved_1[0x5];
1608         u8         rdma[0x1];
1609         u8         write[0x1];
1610         u8         requestor[0x1];
1611         u8         qp_number[0x18];
1612 };
1613
1614 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1615         u8         bytes_committed[0x20];
1616
1617         u8         reserved_0[0x10];
1618         u8         wqe_index[0x10];
1619
1620         u8         reserved_1[0x10];
1621         u8         len[0x10];
1622
1623         u8         reserved_2[0x60];
1624
1625         u8         reserved_3[0x5];
1626         u8         rdma[0x1];
1627         u8         write_read[0x1];
1628         u8         requestor[0x1];
1629         u8         qpn[0x18];
1630 };
1631
1632 struct mlx5_ifc_qp_events_bits {
1633         u8         reserved_0[0xa0];
1634
1635         u8         type[0x8];
1636         u8         reserved_1[0x18];
1637
1638         u8         reserved_2[0x8];
1639         u8         qpn_rqn_sqn[0x18];
1640 };
1641
1642 struct mlx5_ifc_dct_events_bits {
1643         u8         reserved_0[0xc0];
1644
1645         u8         reserved_1[0x8];
1646         u8         dct_number[0x18];
1647 };
1648
1649 struct mlx5_ifc_comp_event_bits {
1650         u8         reserved_0[0xc0];
1651
1652         u8         reserved_1[0x8];
1653         u8         cq_number[0x18];
1654 };
1655
1656 enum {
1657         MLX5_QPC_STATE_RST        = 0x0,
1658         MLX5_QPC_STATE_INIT       = 0x1,
1659         MLX5_QPC_STATE_RTR        = 0x2,
1660         MLX5_QPC_STATE_RTS        = 0x3,
1661         MLX5_QPC_STATE_SQER       = 0x4,
1662         MLX5_QPC_STATE_ERR        = 0x6,
1663         MLX5_QPC_STATE_SQD        = 0x7,
1664         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1665 };
1666
1667 enum {
1668         MLX5_QPC_ST_RC            = 0x0,
1669         MLX5_QPC_ST_UC            = 0x1,
1670         MLX5_QPC_ST_UD            = 0x2,
1671         MLX5_QPC_ST_XRC           = 0x3,
1672         MLX5_QPC_ST_DCI           = 0x5,
1673         MLX5_QPC_ST_QP0           = 0x7,
1674         MLX5_QPC_ST_QP1           = 0x8,
1675         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1676         MLX5_QPC_ST_REG_UMR       = 0xc,
1677 };
1678
1679 enum {
1680         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1681         MLX5_QPC_PM_STATE_REARM     = 0x1,
1682         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1683         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1684 };
1685
1686 enum {
1687         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1688         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1689 };
1690
1691 enum {
1692         MLX5_QPC_MTU_256_BYTES        = 0x1,
1693         MLX5_QPC_MTU_512_BYTES        = 0x2,
1694         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1695         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1696         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1697         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1698 };
1699
1700 enum {
1701         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1702         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1703         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1704         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1705         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1706         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1707         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1708         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1709 };
1710
1711 enum {
1712         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1713         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1714         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1715 };
1716
1717 enum {
1718         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1719         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1720         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1721 };
1722
1723 struct mlx5_ifc_qpc_bits {
1724         u8         state[0x4];
1725         u8         reserved_0[0x4];
1726         u8         st[0x8];
1727         u8         reserved_1[0x3];
1728         u8         pm_state[0x2];
1729         u8         reserved_2[0x7];
1730         u8         end_padding_mode[0x2];
1731         u8         reserved_3[0x2];
1732
1733         u8         wq_signature[0x1];
1734         u8         block_lb_mc[0x1];
1735         u8         atomic_like_write_en[0x1];
1736         u8         latency_sensitive[0x1];
1737         u8         reserved_4[0x1];
1738         u8         drain_sigerr[0x1];
1739         u8         reserved_5[0x2];
1740         u8         pd[0x18];
1741
1742         u8         mtu[0x3];
1743         u8         log_msg_max[0x5];
1744         u8         reserved_6[0x1];
1745         u8         log_rq_size[0x4];
1746         u8         log_rq_stride[0x3];
1747         u8         no_sq[0x1];
1748         u8         log_sq_size[0x4];
1749         u8         reserved_7[0x6];
1750         u8         rlky[0x1];
1751         u8         reserved_8[0x4];
1752
1753         u8         counter_set_id[0x8];
1754         u8         uar_page[0x18];
1755
1756         u8         reserved_9[0x8];
1757         u8         user_index[0x18];
1758
1759         u8         reserved_10[0x3];
1760         u8         log_page_size[0x5];
1761         u8         remote_qpn[0x18];
1762
1763         struct mlx5_ifc_ads_bits primary_address_path;
1764
1765         struct mlx5_ifc_ads_bits secondary_address_path;
1766
1767         u8         log_ack_req_freq[0x4];
1768         u8         reserved_11[0x4];
1769         u8         log_sra_max[0x3];
1770         u8         reserved_12[0x2];
1771         u8         retry_count[0x3];
1772         u8         rnr_retry[0x3];
1773         u8         reserved_13[0x1];
1774         u8         fre[0x1];
1775         u8         cur_rnr_retry[0x3];
1776         u8         cur_retry_count[0x3];
1777         u8         reserved_14[0x5];
1778
1779         u8         reserved_15[0x20];
1780
1781         u8         reserved_16[0x8];
1782         u8         next_send_psn[0x18];
1783
1784         u8         reserved_17[0x8];
1785         u8         cqn_snd[0x18];
1786
1787         u8         reserved_18[0x40];
1788
1789         u8         reserved_19[0x8];
1790         u8         last_acked_psn[0x18];
1791
1792         u8         reserved_20[0x8];
1793         u8         ssn[0x18];
1794
1795         u8         reserved_21[0x8];
1796         u8         log_rra_max[0x3];
1797         u8         reserved_22[0x1];
1798         u8         atomic_mode[0x4];
1799         u8         rre[0x1];
1800         u8         rwe[0x1];
1801         u8         rae[0x1];
1802         u8         reserved_23[0x1];
1803         u8         page_offset[0x6];
1804         u8         reserved_24[0x3];
1805         u8         cd_slave_receive[0x1];
1806         u8         cd_slave_send[0x1];
1807         u8         cd_master[0x1];
1808
1809         u8         reserved_25[0x3];
1810         u8         min_rnr_nak[0x5];
1811         u8         next_rcv_psn[0x18];
1812
1813         u8         reserved_26[0x8];
1814         u8         xrcd[0x18];
1815
1816         u8         reserved_27[0x8];
1817         u8         cqn_rcv[0x18];
1818
1819         u8         dbr_addr[0x40];
1820
1821         u8         q_key[0x20];
1822
1823         u8         reserved_28[0x5];
1824         u8         rq_type[0x3];
1825         u8         srqn_rmpn[0x18];
1826
1827         u8         reserved_29[0x8];
1828         u8         rmsn[0x18];
1829
1830         u8         hw_sq_wqebb_counter[0x10];
1831         u8         sw_sq_wqebb_counter[0x10];
1832
1833         u8         hw_rq_counter[0x20];
1834
1835         u8         sw_rq_counter[0x20];
1836
1837         u8         reserved_30[0x20];
1838
1839         u8         reserved_31[0xf];
1840         u8         cgs[0x1];
1841         u8         cs_req[0x8];
1842         u8         cs_res[0x8];
1843
1844         u8         dc_access_key[0x40];
1845
1846         u8         reserved_32[0xc0];
1847 };
1848
1849 struct mlx5_ifc_roce_addr_layout_bits {
1850         u8         source_l3_address[16][0x8];
1851
1852         u8         reserved_0[0x3];
1853         u8         vlan_valid[0x1];
1854         u8         vlan_id[0xc];
1855         u8         source_mac_47_32[0x10];
1856
1857         u8         source_mac_31_0[0x20];
1858
1859         u8         reserved_1[0x14];
1860         u8         roce_l3_type[0x4];
1861         u8         roce_version[0x8];
1862
1863         u8         reserved_2[0x20];
1864 };
1865
1866 union mlx5_ifc_hca_cap_union_bits {
1867         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1868         struct mlx5_ifc_odp_cap_bits odp_cap;
1869         struct mlx5_ifc_atomic_caps_bits atomic_caps;
1870         struct mlx5_ifc_roce_cap_bits roce_cap;
1871         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1872         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1873         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1874         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1875         u8         reserved_0[0x8000];
1876 };
1877
1878 enum {
1879         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1880         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1881         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1882 };
1883
1884 struct mlx5_ifc_flow_context_bits {
1885         u8         reserved_0[0x20];
1886
1887         u8         group_id[0x20];
1888
1889         u8         reserved_1[0x8];
1890         u8         flow_tag[0x18];
1891
1892         u8         reserved_2[0x10];
1893         u8         action[0x10];
1894
1895         u8         reserved_3[0x8];
1896         u8         destination_list_size[0x18];
1897
1898         u8         reserved_4[0x160];
1899
1900         struct mlx5_ifc_fte_match_param_bits match_value;
1901
1902         u8         reserved_5[0x600];
1903
1904         struct mlx5_ifc_dest_format_struct_bits destination[0];
1905 };
1906
1907 enum {
1908         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1909         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1910 };
1911
1912 struct mlx5_ifc_xrc_srqc_bits {
1913         u8         state[0x4];
1914         u8         log_xrc_srq_size[0x4];
1915         u8         reserved_0[0x18];
1916
1917         u8         wq_signature[0x1];
1918         u8         cont_srq[0x1];
1919         u8         reserved_1[0x1];
1920         u8         rlky[0x1];
1921         u8         basic_cyclic_rcv_wqe[0x1];
1922         u8         log_rq_stride[0x3];
1923         u8         xrcd[0x18];
1924
1925         u8         page_offset[0x6];
1926         u8         reserved_2[0x2];
1927         u8         cqn[0x18];
1928
1929         u8         reserved_3[0x20];
1930
1931         u8         user_index_equal_xrc_srqn[0x1];
1932         u8         reserved_4[0x1];
1933         u8         log_page_size[0x6];
1934         u8         user_index[0x18];
1935
1936         u8         reserved_5[0x20];
1937
1938         u8         reserved_6[0x8];
1939         u8         pd[0x18];
1940
1941         u8         lwm[0x10];
1942         u8         wqe_cnt[0x10];
1943
1944         u8         reserved_7[0x40];
1945
1946         u8         db_record_addr_h[0x20];
1947
1948         u8         db_record_addr_l[0x1e];
1949         u8         reserved_8[0x2];
1950
1951         u8         reserved_9[0x80];
1952 };
1953
1954 struct mlx5_ifc_traffic_counter_bits {
1955         u8         packets[0x40];
1956
1957         u8         octets[0x40];
1958 };
1959
1960 struct mlx5_ifc_tisc_bits {
1961         u8         reserved_0[0xc];
1962         u8         prio[0x4];
1963         u8         reserved_1[0x10];
1964
1965         u8         reserved_2[0x100];
1966
1967         u8         reserved_3[0x8];
1968         u8         transport_domain[0x18];
1969
1970         u8         reserved_4[0x3c0];
1971 };
1972
1973 enum {
1974         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
1975         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
1976 };
1977
1978 enum {
1979         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
1980         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
1981 };
1982
1983 enum {
1984         MLX5_RX_HASH_FN_NONE           = 0x0,
1985         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
1986         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
1987 };
1988
1989 enum {
1990         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
1991         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
1992 };
1993
1994 struct mlx5_ifc_tirc_bits {
1995         u8         reserved_0[0x20];
1996
1997         u8         disp_type[0x4];
1998         u8         reserved_1[0x1c];
1999
2000         u8         reserved_2[0x40];
2001
2002         u8         reserved_3[0x4];
2003         u8         lro_timeout_period_usecs[0x10];
2004         u8         lro_enable_mask[0x4];
2005         u8         lro_max_ip_payload_size[0x8];
2006
2007         u8         reserved_4[0x40];
2008
2009         u8         reserved_5[0x8];
2010         u8         inline_rqn[0x18];
2011
2012         u8         rx_hash_symmetric[0x1];
2013         u8         reserved_6[0x1];
2014         u8         tunneled_offload_en[0x1];
2015         u8         reserved_7[0x5];
2016         u8         indirect_table[0x18];
2017
2018         u8         rx_hash_fn[0x4];
2019         u8         reserved_8[0x2];
2020         u8         self_lb_block[0x2];
2021         u8         transport_domain[0x18];
2022
2023         u8         rx_hash_toeplitz_key[10][0x20];
2024
2025         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2026
2027         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2028
2029         u8         reserved_9[0x4c0];
2030 };
2031
2032 enum {
2033         MLX5_SRQC_STATE_GOOD   = 0x0,
2034         MLX5_SRQC_STATE_ERROR  = 0x1,
2035 };
2036
2037 struct mlx5_ifc_srqc_bits {
2038         u8         state[0x4];
2039         u8         log_srq_size[0x4];
2040         u8         reserved_0[0x18];
2041
2042         u8         wq_signature[0x1];
2043         u8         cont_srq[0x1];
2044         u8         reserved_1[0x1];
2045         u8         rlky[0x1];
2046         u8         reserved_2[0x1];
2047         u8         log_rq_stride[0x3];
2048         u8         xrcd[0x18];
2049
2050         u8         page_offset[0x6];
2051         u8         reserved_3[0x2];
2052         u8         cqn[0x18];
2053
2054         u8         reserved_4[0x20];
2055
2056         u8         reserved_5[0x2];
2057         u8         log_page_size[0x6];
2058         u8         reserved_6[0x18];
2059
2060         u8         reserved_7[0x20];
2061
2062         u8         reserved_8[0x8];
2063         u8         pd[0x18];
2064
2065         u8         lwm[0x10];
2066         u8         wqe_cnt[0x10];
2067
2068         u8         reserved_9[0x40];
2069
2070         u8         dbr_addr[0x40];
2071
2072         u8         reserved_10[0x80];
2073 };
2074
2075 enum {
2076         MLX5_SQC_STATE_RST  = 0x0,
2077         MLX5_SQC_STATE_RDY  = 0x1,
2078         MLX5_SQC_STATE_ERR  = 0x3,
2079 };
2080
2081 struct mlx5_ifc_sqc_bits {
2082         u8         rlky[0x1];
2083         u8         cd_master[0x1];
2084         u8         fre[0x1];
2085         u8         flush_in_error_en[0x1];
2086         u8         reserved_0[0x4];
2087         u8         state[0x4];
2088         u8         reserved_1[0x14];
2089
2090         u8         reserved_2[0x8];
2091         u8         user_index[0x18];
2092
2093         u8         reserved_3[0x8];
2094         u8         cqn[0x18];
2095
2096         u8         reserved_4[0xa0];
2097
2098         u8         tis_lst_sz[0x10];
2099         u8         reserved_5[0x10];
2100
2101         u8         reserved_6[0x40];
2102
2103         u8         reserved_7[0x8];
2104         u8         tis_num_0[0x18];
2105
2106         struct mlx5_ifc_wq_bits wq;
2107 };
2108
2109 struct mlx5_ifc_rqtc_bits {
2110         u8         reserved_0[0xa0];
2111
2112         u8         reserved_1[0x10];
2113         u8         rqt_max_size[0x10];
2114
2115         u8         reserved_2[0x10];
2116         u8         rqt_actual_size[0x10];
2117
2118         u8         reserved_3[0x6a0];
2119
2120         struct mlx5_ifc_rq_num_bits rq_num[0];
2121 };
2122
2123 enum {
2124         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2125         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2126 };
2127
2128 enum {
2129         MLX5_RQC_STATE_RST  = 0x0,
2130         MLX5_RQC_STATE_RDY  = 0x1,
2131         MLX5_RQC_STATE_ERR  = 0x3,
2132 };
2133
2134 struct mlx5_ifc_rqc_bits {
2135         u8         rlky[0x1];
2136         u8         reserved_0[0x2];
2137         u8         vsd[0x1];
2138         u8         mem_rq_type[0x4];
2139         u8         state[0x4];
2140         u8         reserved_1[0x1];
2141         u8         flush_in_error_en[0x1];
2142         u8         reserved_2[0x12];
2143
2144         u8         reserved_3[0x8];
2145         u8         user_index[0x18];
2146
2147         u8         reserved_4[0x8];
2148         u8         cqn[0x18];
2149
2150         u8         counter_set_id[0x8];
2151         u8         reserved_5[0x18];
2152
2153         u8         reserved_6[0x8];
2154         u8         rmpn[0x18];
2155
2156         u8         reserved_7[0xe0];
2157
2158         struct mlx5_ifc_wq_bits wq;
2159 };
2160
2161 enum {
2162         MLX5_RMPC_STATE_RDY  = 0x1,
2163         MLX5_RMPC_STATE_ERR  = 0x3,
2164 };
2165
2166 struct mlx5_ifc_rmpc_bits {
2167         u8         reserved_0[0x8];
2168         u8         state[0x4];
2169         u8         reserved_1[0x14];
2170
2171         u8         basic_cyclic_rcv_wqe[0x1];
2172         u8         reserved_2[0x1f];
2173
2174         u8         reserved_3[0x140];
2175
2176         struct mlx5_ifc_wq_bits wq;
2177 };
2178
2179 struct mlx5_ifc_nic_vport_context_bits {
2180         u8         reserved_0[0x1f];
2181         u8         roce_en[0x1];
2182
2183         u8         arm_change_event[0x1];
2184         u8         reserved_1[0x1a];
2185         u8         event_on_mtu[0x1];
2186         u8         event_on_promisc_change[0x1];
2187         u8         event_on_vlan_change[0x1];
2188         u8         event_on_mc_address_change[0x1];
2189         u8         event_on_uc_address_change[0x1];
2190
2191         u8         reserved_2[0xf0];
2192
2193         u8         mtu[0x10];
2194
2195         u8         reserved_3[0x640];
2196
2197         u8         promisc_uc[0x1];
2198         u8         promisc_mc[0x1];
2199         u8         promisc_all[0x1];
2200         u8         reserved_4[0x2];
2201         u8         allowed_list_type[0x3];
2202         u8         reserved_5[0xc];
2203         u8         allowed_list_size[0xc];
2204
2205         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2206
2207         u8         reserved_6[0x20];
2208
2209         u8         current_uc_mac_address[0][0x40];
2210 };
2211
2212 enum {
2213         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2214         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2215         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2216 };
2217
2218 struct mlx5_ifc_mkc_bits {
2219         u8         reserved_0[0x1];
2220         u8         free[0x1];
2221         u8         reserved_1[0xd];
2222         u8         small_fence_on_rdma_read_response[0x1];
2223         u8         umr_en[0x1];
2224         u8         a[0x1];
2225         u8         rw[0x1];
2226         u8         rr[0x1];
2227         u8         lw[0x1];
2228         u8         lr[0x1];
2229         u8         access_mode[0x2];
2230         u8         reserved_2[0x8];
2231
2232         u8         qpn[0x18];
2233         u8         mkey_7_0[0x8];
2234
2235         u8         reserved_3[0x20];
2236
2237         u8         length64[0x1];
2238         u8         bsf_en[0x1];
2239         u8         sync_umr[0x1];
2240         u8         reserved_4[0x2];
2241         u8         expected_sigerr_count[0x1];
2242         u8         reserved_5[0x1];
2243         u8         en_rinval[0x1];
2244         u8         pd[0x18];
2245
2246         u8         start_addr[0x40];
2247
2248         u8         len[0x40];
2249
2250         u8         bsf_octword_size[0x20];
2251
2252         u8         reserved_6[0x80];
2253
2254         u8         translations_octword_size[0x20];
2255
2256         u8         reserved_7[0x1b];
2257         u8         log_page_size[0x5];
2258
2259         u8         reserved_8[0x20];
2260 };
2261
2262 struct mlx5_ifc_pkey_bits {
2263         u8         reserved_0[0x10];
2264         u8         pkey[0x10];
2265 };
2266
2267 struct mlx5_ifc_array128_auto_bits {
2268         u8         array128_auto[16][0x8];
2269 };
2270
2271 struct mlx5_ifc_hca_vport_context_bits {
2272         u8         field_select[0x20];
2273
2274         u8         reserved_0[0xe0];
2275
2276         u8         sm_virt_aware[0x1];
2277         u8         has_smi[0x1];
2278         u8         has_raw[0x1];
2279         u8         grh_required[0x1];
2280         u8         reserved_1[0xc];
2281         u8         port_physical_state[0x4];
2282         u8         vport_state_policy[0x4];
2283         u8         port_state[0x4];
2284         u8         vport_state[0x4];
2285
2286         u8         reserved_2[0x20];
2287
2288         u8         system_image_guid[0x40];
2289
2290         u8         port_guid[0x40];
2291
2292         u8         node_guid[0x40];
2293
2294         u8         cap_mask1[0x20];
2295
2296         u8         cap_mask1_field_select[0x20];
2297
2298         u8         cap_mask2[0x20];
2299
2300         u8         cap_mask2_field_select[0x20];
2301
2302         u8         reserved_3[0x80];
2303
2304         u8         lid[0x10];
2305         u8         reserved_4[0x4];
2306         u8         init_type_reply[0x4];
2307         u8         lmc[0x3];
2308         u8         subnet_timeout[0x5];
2309
2310         u8         sm_lid[0x10];
2311         u8         sm_sl[0x4];
2312         u8         reserved_5[0xc];
2313
2314         u8         qkey_violation_counter[0x10];
2315         u8         pkey_violation_counter[0x10];
2316
2317         u8         reserved_6[0xca0];
2318 };
2319
2320 struct mlx5_ifc_esw_vport_context_bits {
2321         u8         reserved_0[0x3];
2322         u8         vport_svlan_strip[0x1];
2323         u8         vport_cvlan_strip[0x1];
2324         u8         vport_svlan_insert[0x1];
2325         u8         vport_cvlan_insert[0x2];
2326         u8         reserved_1[0x18];
2327
2328         u8         reserved_2[0x20];
2329
2330         u8         svlan_cfi[0x1];
2331         u8         svlan_pcp[0x3];
2332         u8         svlan_id[0xc];
2333         u8         cvlan_cfi[0x1];
2334         u8         cvlan_pcp[0x3];
2335         u8         cvlan_id[0xc];
2336
2337         u8         reserved_3[0x7a0];
2338 };
2339
2340 enum {
2341         MLX5_EQC_STATUS_OK                = 0x0,
2342         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2343 };
2344
2345 enum {
2346         MLX5_EQC_ST_ARMED  = 0x9,
2347         MLX5_EQC_ST_FIRED  = 0xa,
2348 };
2349
2350 struct mlx5_ifc_eqc_bits {
2351         u8         status[0x4];
2352         u8         reserved_0[0x9];
2353         u8         ec[0x1];
2354         u8         oi[0x1];
2355         u8         reserved_1[0x5];
2356         u8         st[0x4];
2357         u8         reserved_2[0x8];
2358
2359         u8         reserved_3[0x20];
2360
2361         u8         reserved_4[0x14];
2362         u8         page_offset[0x6];
2363         u8         reserved_5[0x6];
2364
2365         u8         reserved_6[0x3];
2366         u8         log_eq_size[0x5];
2367         u8         uar_page[0x18];
2368
2369         u8         reserved_7[0x20];
2370
2371         u8         reserved_8[0x18];
2372         u8         intr[0x8];
2373
2374         u8         reserved_9[0x3];
2375         u8         log_page_size[0x5];
2376         u8         reserved_10[0x18];
2377
2378         u8         reserved_11[0x60];
2379
2380         u8         reserved_12[0x8];
2381         u8         consumer_counter[0x18];
2382
2383         u8         reserved_13[0x8];
2384         u8         producer_counter[0x18];
2385
2386         u8         reserved_14[0x80];
2387 };
2388
2389 enum {
2390         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2391         MLX5_DCTC_STATE_DRAINING  = 0x1,
2392         MLX5_DCTC_STATE_DRAINED   = 0x2,
2393 };
2394
2395 enum {
2396         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2397         MLX5_DCTC_CS_RES_NA         = 0x1,
2398         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2399 };
2400
2401 enum {
2402         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2403         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2404         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2405         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2406         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2407 };
2408
2409 struct mlx5_ifc_dctc_bits {
2410         u8         reserved_0[0x4];
2411         u8         state[0x4];
2412         u8         reserved_1[0x18];
2413
2414         u8         reserved_2[0x8];
2415         u8         user_index[0x18];
2416
2417         u8         reserved_3[0x8];
2418         u8         cqn[0x18];
2419
2420         u8         counter_set_id[0x8];
2421         u8         atomic_mode[0x4];
2422         u8         rre[0x1];
2423         u8         rwe[0x1];
2424         u8         rae[0x1];
2425         u8         atomic_like_write_en[0x1];
2426         u8         latency_sensitive[0x1];
2427         u8         rlky[0x1];
2428         u8         free_ar[0x1];
2429         u8         reserved_4[0xd];
2430
2431         u8         reserved_5[0x8];
2432         u8         cs_res[0x8];
2433         u8         reserved_6[0x3];
2434         u8         min_rnr_nak[0x5];
2435         u8         reserved_7[0x8];
2436
2437         u8         reserved_8[0x8];
2438         u8         srqn[0x18];
2439
2440         u8         reserved_9[0x8];
2441         u8         pd[0x18];
2442
2443         u8         tclass[0x8];
2444         u8         reserved_10[0x4];
2445         u8         flow_label[0x14];
2446
2447         u8         dc_access_key[0x40];
2448
2449         u8         reserved_11[0x5];
2450         u8         mtu[0x3];
2451         u8         port[0x8];
2452         u8         pkey_index[0x10];
2453
2454         u8         reserved_12[0x8];
2455         u8         my_addr_index[0x8];
2456         u8         reserved_13[0x8];
2457         u8         hop_limit[0x8];
2458
2459         u8         dc_access_key_violation_count[0x20];
2460
2461         u8         reserved_14[0x14];
2462         u8         dei_cfi[0x1];
2463         u8         eth_prio[0x3];
2464         u8         ecn[0x2];
2465         u8         dscp[0x6];
2466
2467         u8         reserved_15[0x40];
2468 };
2469
2470 enum {
2471         MLX5_CQC_STATUS_OK             = 0x0,
2472         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2473         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2474 };
2475
2476 enum {
2477         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2478         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2479 };
2480
2481 enum {
2482         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2483         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2484         MLX5_CQC_ST_FIRED                                 = 0xa,
2485 };
2486
2487 struct mlx5_ifc_cqc_bits {
2488         u8         status[0x4];
2489         u8         reserved_0[0x4];
2490         u8         cqe_sz[0x3];
2491         u8         cc[0x1];
2492         u8         reserved_1[0x1];
2493         u8         scqe_break_moderation_en[0x1];
2494         u8         oi[0x1];
2495         u8         reserved_2[0x2];
2496         u8         cqe_zip_en[0x1];
2497         u8         mini_cqe_res_format[0x2];
2498         u8         st[0x4];
2499         u8         reserved_3[0x8];
2500
2501         u8         reserved_4[0x20];
2502
2503         u8         reserved_5[0x14];
2504         u8         page_offset[0x6];
2505         u8         reserved_6[0x6];
2506
2507         u8         reserved_7[0x3];
2508         u8         log_cq_size[0x5];
2509         u8         uar_page[0x18];
2510
2511         u8         reserved_8[0x4];
2512         u8         cq_period[0xc];
2513         u8         cq_max_count[0x10];
2514
2515         u8         reserved_9[0x18];
2516         u8         c_eqn[0x8];
2517
2518         u8         reserved_10[0x3];
2519         u8         log_page_size[0x5];
2520         u8         reserved_11[0x18];
2521
2522         u8         reserved_12[0x20];
2523
2524         u8         reserved_13[0x8];
2525         u8         last_notified_index[0x18];
2526
2527         u8         reserved_14[0x8];
2528         u8         last_solicit_index[0x18];
2529
2530         u8         reserved_15[0x8];
2531         u8         consumer_counter[0x18];
2532
2533         u8         reserved_16[0x8];
2534         u8         producer_counter[0x18];
2535
2536         u8         reserved_17[0x40];
2537
2538         u8         dbr_addr[0x40];
2539 };
2540
2541 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2542         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2543         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2544         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2545         u8         reserved_0[0x800];
2546 };
2547
2548 struct mlx5_ifc_query_adapter_param_block_bits {
2549         u8         reserved_0[0xc0];
2550
2551         u8         reserved_1[0x8];
2552         u8         ieee_vendor_id[0x18];
2553
2554         u8         reserved_2[0x10];
2555         u8         vsd_vendor_id[0x10];
2556
2557         u8         vsd[208][0x8];
2558
2559         u8         vsd_contd_psid[16][0x8];
2560 };
2561
2562 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2563         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2564         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2565         u8         reserved_0[0x20];
2566 };
2567
2568 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2569         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2570         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2571         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2572         u8         reserved_0[0x20];
2573 };
2574
2575 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2576         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2577         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2578         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2579         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2580         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2581         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2582         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2583         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2584         u8         reserved_0[0x7c0];
2585 };
2586
2587 union mlx5_ifc_event_auto_bits {
2588         struct mlx5_ifc_comp_event_bits comp_event;
2589         struct mlx5_ifc_dct_events_bits dct_events;
2590         struct mlx5_ifc_qp_events_bits qp_events;
2591         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2592         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2593         struct mlx5_ifc_cq_error_bits cq_error;
2594         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2595         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2596         struct mlx5_ifc_gpio_event_bits gpio_event;
2597         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2598         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2599         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2600         u8         reserved_0[0xe0];
2601 };
2602
2603 struct mlx5_ifc_health_buffer_bits {
2604         u8         reserved_0[0x100];
2605
2606         u8         assert_existptr[0x20];
2607
2608         u8         assert_callra[0x20];
2609
2610         u8         reserved_1[0x40];
2611
2612         u8         fw_version[0x20];
2613
2614         u8         hw_id[0x20];
2615
2616         u8         reserved_2[0x20];
2617
2618         u8         irisc_index[0x8];
2619         u8         synd[0x8];
2620         u8         ext_synd[0x10];
2621 };
2622
2623 struct mlx5_ifc_register_loopback_control_bits {
2624         u8         no_lb[0x1];
2625         u8         reserved_0[0x7];
2626         u8         port[0x8];
2627         u8         reserved_1[0x10];
2628
2629         u8         reserved_2[0x60];
2630 };
2631
2632 struct mlx5_ifc_teardown_hca_out_bits {
2633         u8         status[0x8];
2634         u8         reserved_0[0x18];
2635
2636         u8         syndrome[0x20];
2637
2638         u8         reserved_1[0x40];
2639 };
2640
2641 enum {
2642         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2643         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2644 };
2645
2646 struct mlx5_ifc_teardown_hca_in_bits {
2647         u8         opcode[0x10];
2648         u8         reserved_0[0x10];
2649
2650         u8         reserved_1[0x10];
2651         u8         op_mod[0x10];
2652
2653         u8         reserved_2[0x10];
2654         u8         profile[0x10];
2655
2656         u8         reserved_3[0x20];
2657 };
2658
2659 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2660         u8         status[0x8];
2661         u8         reserved_0[0x18];
2662
2663         u8         syndrome[0x20];
2664
2665         u8         reserved_1[0x40];
2666 };
2667
2668 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2669         u8         opcode[0x10];
2670         u8         reserved_0[0x10];
2671
2672         u8         reserved_1[0x10];
2673         u8         op_mod[0x10];
2674
2675         u8         reserved_2[0x8];
2676         u8         qpn[0x18];
2677
2678         u8         reserved_3[0x20];
2679
2680         u8         opt_param_mask[0x20];
2681
2682         u8         reserved_4[0x20];
2683
2684         struct mlx5_ifc_qpc_bits qpc;
2685
2686         u8         reserved_5[0x80];
2687 };
2688
2689 struct mlx5_ifc_sqd2rts_qp_out_bits {
2690         u8         status[0x8];
2691         u8         reserved_0[0x18];
2692
2693         u8         syndrome[0x20];
2694
2695         u8         reserved_1[0x40];
2696 };
2697
2698 struct mlx5_ifc_sqd2rts_qp_in_bits {
2699         u8         opcode[0x10];
2700         u8         reserved_0[0x10];
2701
2702         u8         reserved_1[0x10];
2703         u8         op_mod[0x10];
2704
2705         u8         reserved_2[0x8];
2706         u8         qpn[0x18];
2707
2708         u8         reserved_3[0x20];
2709
2710         u8         opt_param_mask[0x20];
2711
2712         u8         reserved_4[0x20];
2713
2714         struct mlx5_ifc_qpc_bits qpc;
2715
2716         u8         reserved_5[0x80];
2717 };
2718
2719 struct mlx5_ifc_set_roce_address_out_bits {
2720         u8         status[0x8];
2721         u8         reserved_0[0x18];
2722
2723         u8         syndrome[0x20];
2724
2725         u8         reserved_1[0x40];
2726 };
2727
2728 struct mlx5_ifc_set_roce_address_in_bits {
2729         u8         opcode[0x10];
2730         u8         reserved_0[0x10];
2731
2732         u8         reserved_1[0x10];
2733         u8         op_mod[0x10];
2734
2735         u8         roce_address_index[0x10];
2736         u8         reserved_2[0x10];
2737
2738         u8         reserved_3[0x20];
2739
2740         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2741 };
2742
2743 struct mlx5_ifc_set_mad_demux_out_bits {
2744         u8         status[0x8];
2745         u8         reserved_0[0x18];
2746
2747         u8         syndrome[0x20];
2748
2749         u8         reserved_1[0x40];
2750 };
2751
2752 enum {
2753         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2754         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2755 };
2756
2757 struct mlx5_ifc_set_mad_demux_in_bits {
2758         u8         opcode[0x10];
2759         u8         reserved_0[0x10];
2760
2761         u8         reserved_1[0x10];
2762         u8         op_mod[0x10];
2763
2764         u8         reserved_2[0x20];
2765
2766         u8         reserved_3[0x6];
2767         u8         demux_mode[0x2];
2768         u8         reserved_4[0x18];
2769 };
2770
2771 struct mlx5_ifc_set_l2_table_entry_out_bits {
2772         u8         status[0x8];
2773         u8         reserved_0[0x18];
2774
2775         u8         syndrome[0x20];
2776
2777         u8         reserved_1[0x40];
2778 };
2779
2780 struct mlx5_ifc_set_l2_table_entry_in_bits {
2781         u8         opcode[0x10];
2782         u8         reserved_0[0x10];
2783
2784         u8         reserved_1[0x10];
2785         u8         op_mod[0x10];
2786
2787         u8         reserved_2[0x60];
2788
2789         u8         reserved_3[0x8];
2790         u8         table_index[0x18];
2791
2792         u8         reserved_4[0x20];
2793
2794         u8         reserved_5[0x13];
2795         u8         vlan_valid[0x1];
2796         u8         vlan[0xc];
2797
2798         struct mlx5_ifc_mac_address_layout_bits mac_address;
2799
2800         u8         reserved_6[0xc0];
2801 };
2802
2803 struct mlx5_ifc_set_issi_out_bits {
2804         u8         status[0x8];
2805         u8         reserved_0[0x18];
2806
2807         u8         syndrome[0x20];
2808
2809         u8         reserved_1[0x40];
2810 };
2811
2812 struct mlx5_ifc_set_issi_in_bits {
2813         u8         opcode[0x10];
2814         u8         reserved_0[0x10];
2815
2816         u8         reserved_1[0x10];
2817         u8         op_mod[0x10];
2818
2819         u8         reserved_2[0x10];
2820         u8         current_issi[0x10];
2821
2822         u8         reserved_3[0x20];
2823 };
2824
2825 struct mlx5_ifc_set_hca_cap_out_bits {
2826         u8         status[0x8];
2827         u8         reserved_0[0x18];
2828
2829         u8         syndrome[0x20];
2830
2831         u8         reserved_1[0x40];
2832 };
2833
2834 struct mlx5_ifc_set_hca_cap_in_bits {
2835         u8         opcode[0x10];
2836         u8         reserved_0[0x10];
2837
2838         u8         reserved_1[0x10];
2839         u8         op_mod[0x10];
2840
2841         u8         reserved_2[0x40];
2842
2843         union mlx5_ifc_hca_cap_union_bits capability;
2844 };
2845
2846 struct mlx5_ifc_set_fte_out_bits {
2847         u8         status[0x8];
2848         u8         reserved_0[0x18];
2849
2850         u8         syndrome[0x20];
2851
2852         u8         reserved_1[0x40];
2853 };
2854
2855 struct mlx5_ifc_set_fte_in_bits {
2856         u8         opcode[0x10];
2857         u8         reserved_0[0x10];
2858
2859         u8         reserved_1[0x10];
2860         u8         op_mod[0x10];
2861
2862         u8         reserved_2[0x40];
2863
2864         u8         table_type[0x8];
2865         u8         reserved_3[0x18];
2866
2867         u8         reserved_4[0x8];
2868         u8         table_id[0x18];
2869
2870         u8         reserved_5[0x40];
2871
2872         u8         flow_index[0x20];
2873
2874         u8         reserved_6[0xe0];
2875
2876         struct mlx5_ifc_flow_context_bits flow_context;
2877 };
2878
2879 struct mlx5_ifc_rts2rts_qp_out_bits {
2880         u8         status[0x8];
2881         u8         reserved_0[0x18];
2882
2883         u8         syndrome[0x20];
2884
2885         u8         reserved_1[0x40];
2886 };
2887
2888 struct mlx5_ifc_rts2rts_qp_in_bits {
2889         u8         opcode[0x10];
2890         u8         reserved_0[0x10];
2891
2892         u8         reserved_1[0x10];
2893         u8         op_mod[0x10];
2894
2895         u8         reserved_2[0x8];
2896         u8         qpn[0x18];
2897
2898         u8         reserved_3[0x20];
2899
2900         u8         opt_param_mask[0x20];
2901
2902         u8         reserved_4[0x20];
2903
2904         struct mlx5_ifc_qpc_bits qpc;
2905
2906         u8         reserved_5[0x80];
2907 };
2908
2909 struct mlx5_ifc_rtr2rts_qp_out_bits {
2910         u8         status[0x8];
2911         u8         reserved_0[0x18];
2912
2913         u8         syndrome[0x20];
2914
2915         u8         reserved_1[0x40];
2916 };
2917
2918 struct mlx5_ifc_rtr2rts_qp_in_bits {
2919         u8         opcode[0x10];
2920         u8         reserved_0[0x10];
2921
2922         u8         reserved_1[0x10];
2923         u8         op_mod[0x10];
2924
2925         u8         reserved_2[0x8];
2926         u8         qpn[0x18];
2927
2928         u8         reserved_3[0x20];
2929
2930         u8         opt_param_mask[0x20];
2931
2932         u8         reserved_4[0x20];
2933
2934         struct mlx5_ifc_qpc_bits qpc;
2935
2936         u8         reserved_5[0x80];
2937 };
2938
2939 struct mlx5_ifc_rst2init_qp_out_bits {
2940         u8         status[0x8];
2941         u8         reserved_0[0x18];
2942
2943         u8         syndrome[0x20];
2944
2945         u8         reserved_1[0x40];
2946 };
2947
2948 struct mlx5_ifc_rst2init_qp_in_bits {
2949         u8         opcode[0x10];
2950         u8         reserved_0[0x10];
2951
2952         u8         reserved_1[0x10];
2953         u8         op_mod[0x10];
2954
2955         u8         reserved_2[0x8];
2956         u8         qpn[0x18];
2957
2958         u8         reserved_3[0x20];
2959
2960         u8         opt_param_mask[0x20];
2961
2962         u8         reserved_4[0x20];
2963
2964         struct mlx5_ifc_qpc_bits qpc;
2965
2966         u8         reserved_5[0x80];
2967 };
2968
2969 struct mlx5_ifc_query_xrc_srq_out_bits {
2970         u8         status[0x8];
2971         u8         reserved_0[0x18];
2972
2973         u8         syndrome[0x20];
2974
2975         u8         reserved_1[0x40];
2976
2977         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2978
2979         u8         reserved_2[0x600];
2980
2981         u8         pas[0][0x40];
2982 };
2983
2984 struct mlx5_ifc_query_xrc_srq_in_bits {
2985         u8         opcode[0x10];
2986         u8         reserved_0[0x10];
2987
2988         u8         reserved_1[0x10];
2989         u8         op_mod[0x10];
2990
2991         u8         reserved_2[0x8];
2992         u8         xrc_srqn[0x18];
2993
2994         u8         reserved_3[0x20];
2995 };
2996
2997 enum {
2998         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
2999         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3000 };
3001
3002 struct mlx5_ifc_query_vport_state_out_bits {
3003         u8         status[0x8];
3004         u8         reserved_0[0x18];
3005
3006         u8         syndrome[0x20];
3007
3008         u8         reserved_1[0x20];
3009
3010         u8         reserved_2[0x18];
3011         u8         admin_state[0x4];
3012         u8         state[0x4];
3013 };
3014
3015 enum {
3016         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3017         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3018 };
3019
3020 struct mlx5_ifc_query_vport_state_in_bits {
3021         u8         opcode[0x10];
3022         u8         reserved_0[0x10];
3023
3024         u8         reserved_1[0x10];
3025         u8         op_mod[0x10];
3026
3027         u8         other_vport[0x1];
3028         u8         reserved_2[0xf];
3029         u8         vport_number[0x10];
3030
3031         u8         reserved_3[0x20];
3032 };
3033
3034 struct mlx5_ifc_query_vport_counter_out_bits {
3035         u8         status[0x8];
3036         u8         reserved_0[0x18];
3037
3038         u8         syndrome[0x20];
3039
3040         u8         reserved_1[0x40];
3041
3042         struct mlx5_ifc_traffic_counter_bits received_errors;
3043
3044         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3045
3046         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3047
3048         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3049
3050         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3051
3052         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3053
3054         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3055
3056         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3057
3058         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3059
3060         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3061
3062         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3063
3064         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3065
3066         u8         reserved_2[0xa00];
3067 };
3068
3069 enum {
3070         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3071 };
3072
3073 struct mlx5_ifc_query_vport_counter_in_bits {
3074         u8         opcode[0x10];
3075         u8         reserved_0[0x10];
3076
3077         u8         reserved_1[0x10];
3078         u8         op_mod[0x10];
3079
3080         u8         other_vport[0x1];
3081         u8         reserved_2[0xf];
3082         u8         vport_number[0x10];
3083
3084         u8         reserved_3[0x60];
3085
3086         u8         clear[0x1];
3087         u8         reserved_4[0x1f];
3088
3089         u8         reserved_5[0x20];
3090 };
3091
3092 struct mlx5_ifc_query_tis_out_bits {
3093         u8         status[0x8];
3094         u8         reserved_0[0x18];
3095
3096         u8         syndrome[0x20];
3097
3098         u8         reserved_1[0x40];
3099
3100         struct mlx5_ifc_tisc_bits tis_context;
3101 };
3102
3103 struct mlx5_ifc_query_tis_in_bits {
3104         u8         opcode[0x10];
3105         u8         reserved_0[0x10];
3106
3107         u8         reserved_1[0x10];
3108         u8         op_mod[0x10];
3109
3110         u8         reserved_2[0x8];
3111         u8         tisn[0x18];
3112
3113         u8         reserved_3[0x20];
3114 };
3115
3116 struct mlx5_ifc_query_tir_out_bits {
3117         u8         status[0x8];
3118         u8         reserved_0[0x18];
3119
3120         u8         syndrome[0x20];
3121
3122         u8         reserved_1[0xc0];
3123
3124         struct mlx5_ifc_tirc_bits tir_context;
3125 };
3126
3127 struct mlx5_ifc_query_tir_in_bits {
3128         u8         opcode[0x10];
3129         u8         reserved_0[0x10];
3130
3131         u8         reserved_1[0x10];
3132         u8         op_mod[0x10];
3133
3134         u8         reserved_2[0x8];
3135         u8         tirn[0x18];
3136
3137         u8         reserved_3[0x20];
3138 };
3139
3140 struct mlx5_ifc_query_srq_out_bits {
3141         u8         status[0x8];
3142         u8         reserved_0[0x18];
3143
3144         u8         syndrome[0x20];
3145
3146         u8         reserved_1[0x40];
3147
3148         struct mlx5_ifc_srqc_bits srq_context_entry;
3149
3150         u8         reserved_2[0x600];
3151
3152         u8         pas[0][0x40];
3153 };
3154
3155 struct mlx5_ifc_query_srq_in_bits {
3156         u8         opcode[0x10];
3157         u8         reserved_0[0x10];
3158
3159         u8         reserved_1[0x10];
3160         u8         op_mod[0x10];
3161
3162         u8         reserved_2[0x8];
3163         u8         srqn[0x18];
3164
3165         u8         reserved_3[0x20];
3166 };
3167
3168 struct mlx5_ifc_query_sq_out_bits {
3169         u8         status[0x8];
3170         u8         reserved_0[0x18];
3171
3172         u8         syndrome[0x20];
3173
3174         u8         reserved_1[0xc0];
3175
3176         struct mlx5_ifc_sqc_bits sq_context;
3177 };
3178
3179 struct mlx5_ifc_query_sq_in_bits {
3180         u8         opcode[0x10];
3181         u8         reserved_0[0x10];
3182
3183         u8         reserved_1[0x10];
3184         u8         op_mod[0x10];
3185
3186         u8         reserved_2[0x8];
3187         u8         sqn[0x18];
3188
3189         u8         reserved_3[0x20];
3190 };
3191
3192 struct mlx5_ifc_query_special_contexts_out_bits {
3193         u8         status[0x8];
3194         u8         reserved_0[0x18];
3195
3196         u8         syndrome[0x20];
3197
3198         u8         reserved_1[0x20];
3199
3200         u8         resd_lkey[0x20];
3201 };
3202
3203 struct mlx5_ifc_query_special_contexts_in_bits {
3204         u8         opcode[0x10];
3205         u8         reserved_0[0x10];
3206
3207         u8         reserved_1[0x10];
3208         u8         op_mod[0x10];
3209
3210         u8         reserved_2[0x40];
3211 };
3212
3213 struct mlx5_ifc_query_rqt_out_bits {
3214         u8         status[0x8];
3215         u8         reserved_0[0x18];
3216
3217         u8         syndrome[0x20];
3218
3219         u8         reserved_1[0xc0];
3220
3221         struct mlx5_ifc_rqtc_bits rqt_context;
3222 };
3223
3224 struct mlx5_ifc_query_rqt_in_bits {
3225         u8         opcode[0x10];
3226         u8         reserved_0[0x10];
3227
3228         u8         reserved_1[0x10];
3229         u8         op_mod[0x10];
3230
3231         u8         reserved_2[0x8];
3232         u8         rqtn[0x18];
3233
3234         u8         reserved_3[0x20];
3235 };
3236
3237 struct mlx5_ifc_query_rq_out_bits {
3238         u8         status[0x8];
3239         u8         reserved_0[0x18];
3240
3241         u8         syndrome[0x20];
3242
3243         u8         reserved_1[0xc0];
3244
3245         struct mlx5_ifc_rqc_bits rq_context;
3246 };
3247
3248 struct mlx5_ifc_query_rq_in_bits {
3249         u8         opcode[0x10];
3250         u8         reserved_0[0x10];
3251
3252         u8         reserved_1[0x10];
3253         u8         op_mod[0x10];
3254
3255         u8         reserved_2[0x8];
3256         u8         rqn[0x18];
3257
3258         u8         reserved_3[0x20];
3259 };
3260
3261 struct mlx5_ifc_query_roce_address_out_bits {
3262         u8         status[0x8];
3263         u8         reserved_0[0x18];
3264
3265         u8         syndrome[0x20];
3266
3267         u8         reserved_1[0x40];
3268
3269         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3270 };
3271
3272 struct mlx5_ifc_query_roce_address_in_bits {
3273         u8         opcode[0x10];
3274         u8         reserved_0[0x10];
3275
3276         u8         reserved_1[0x10];
3277         u8         op_mod[0x10];
3278
3279         u8         roce_address_index[0x10];
3280         u8         reserved_2[0x10];
3281
3282         u8         reserved_3[0x20];
3283 };
3284
3285 struct mlx5_ifc_query_rmp_out_bits {
3286         u8         status[0x8];
3287         u8         reserved_0[0x18];
3288
3289         u8         syndrome[0x20];
3290
3291         u8         reserved_1[0xc0];
3292
3293         struct mlx5_ifc_rmpc_bits rmp_context;
3294 };
3295
3296 struct mlx5_ifc_query_rmp_in_bits {
3297         u8         opcode[0x10];
3298         u8         reserved_0[0x10];
3299
3300         u8         reserved_1[0x10];
3301         u8         op_mod[0x10];
3302
3303         u8         reserved_2[0x8];
3304         u8         rmpn[0x18];
3305
3306         u8         reserved_3[0x20];
3307 };
3308
3309 struct mlx5_ifc_query_qp_out_bits {
3310         u8         status[0x8];
3311         u8         reserved_0[0x18];
3312
3313         u8         syndrome[0x20];
3314
3315         u8         reserved_1[0x40];
3316
3317         u8         opt_param_mask[0x20];
3318
3319         u8         reserved_2[0x20];
3320
3321         struct mlx5_ifc_qpc_bits qpc;
3322
3323         u8         reserved_3[0x80];
3324
3325         u8         pas[0][0x40];
3326 };
3327
3328 struct mlx5_ifc_query_qp_in_bits {
3329         u8         opcode[0x10];
3330         u8         reserved_0[0x10];
3331
3332         u8         reserved_1[0x10];
3333         u8         op_mod[0x10];
3334
3335         u8         reserved_2[0x8];
3336         u8         qpn[0x18];
3337
3338         u8         reserved_3[0x20];
3339 };
3340
3341 struct mlx5_ifc_query_q_counter_out_bits {
3342         u8         status[0x8];
3343         u8         reserved_0[0x18];
3344
3345         u8         syndrome[0x20];
3346
3347         u8         reserved_1[0x40];
3348
3349         u8         rx_write_requests[0x20];
3350
3351         u8         reserved_2[0x20];
3352
3353         u8         rx_read_requests[0x20];
3354
3355         u8         reserved_3[0x20];
3356
3357         u8         rx_atomic_requests[0x20];
3358
3359         u8         reserved_4[0x20];
3360
3361         u8         rx_dct_connect[0x20];
3362
3363         u8         reserved_5[0x20];
3364
3365         u8         out_of_buffer[0x20];
3366
3367         u8         reserved_6[0x20];
3368
3369         u8         out_of_sequence[0x20];
3370
3371         u8         reserved_7[0x620];
3372 };
3373
3374 struct mlx5_ifc_query_q_counter_in_bits {
3375         u8         opcode[0x10];
3376         u8         reserved_0[0x10];
3377
3378         u8         reserved_1[0x10];
3379         u8         op_mod[0x10];
3380
3381         u8         reserved_2[0x80];
3382
3383         u8         clear[0x1];
3384         u8         reserved_3[0x1f];
3385
3386         u8         reserved_4[0x18];
3387         u8         counter_set_id[0x8];
3388 };
3389
3390 struct mlx5_ifc_query_pages_out_bits {
3391         u8         status[0x8];
3392         u8         reserved_0[0x18];
3393
3394         u8         syndrome[0x20];
3395
3396         u8         reserved_1[0x10];
3397         u8         function_id[0x10];
3398
3399         u8         num_pages[0x20];
3400 };
3401
3402 enum {
3403         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3404         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3405         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3406 };
3407
3408 struct mlx5_ifc_query_pages_in_bits {
3409         u8         opcode[0x10];
3410         u8         reserved_0[0x10];
3411
3412         u8         reserved_1[0x10];
3413         u8         op_mod[0x10];
3414
3415         u8         reserved_2[0x10];
3416         u8         function_id[0x10];
3417
3418         u8         reserved_3[0x20];
3419 };
3420
3421 struct mlx5_ifc_query_nic_vport_context_out_bits {
3422         u8         status[0x8];
3423         u8         reserved_0[0x18];
3424
3425         u8         syndrome[0x20];
3426
3427         u8         reserved_1[0x40];
3428
3429         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3430 };
3431
3432 struct mlx5_ifc_query_nic_vport_context_in_bits {
3433         u8         opcode[0x10];
3434         u8         reserved_0[0x10];
3435
3436         u8         reserved_1[0x10];
3437         u8         op_mod[0x10];
3438
3439         u8         other_vport[0x1];
3440         u8         reserved_2[0xf];
3441         u8         vport_number[0x10];
3442
3443         u8         reserved_3[0x5];
3444         u8         allowed_list_type[0x3];
3445         u8         reserved_4[0x18];
3446 };
3447
3448 struct mlx5_ifc_query_mkey_out_bits {
3449         u8         status[0x8];
3450         u8         reserved_0[0x18];
3451
3452         u8         syndrome[0x20];
3453
3454         u8         reserved_1[0x40];
3455
3456         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3457
3458         u8         reserved_2[0x600];
3459
3460         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3461
3462         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3463 };
3464
3465 struct mlx5_ifc_query_mkey_in_bits {
3466         u8         opcode[0x10];
3467         u8         reserved_0[0x10];
3468
3469         u8         reserved_1[0x10];
3470         u8         op_mod[0x10];
3471
3472         u8         reserved_2[0x8];
3473         u8         mkey_index[0x18];
3474
3475         u8         pg_access[0x1];
3476         u8         reserved_3[0x1f];
3477 };
3478
3479 struct mlx5_ifc_query_mad_demux_out_bits {
3480         u8         status[0x8];
3481         u8         reserved_0[0x18];
3482
3483         u8         syndrome[0x20];
3484
3485         u8         reserved_1[0x40];
3486
3487         u8         mad_dumux_parameters_block[0x20];
3488 };
3489
3490 struct mlx5_ifc_query_mad_demux_in_bits {
3491         u8         opcode[0x10];
3492         u8         reserved_0[0x10];
3493
3494         u8         reserved_1[0x10];
3495         u8         op_mod[0x10];
3496
3497         u8         reserved_2[0x40];
3498 };
3499
3500 struct mlx5_ifc_query_l2_table_entry_out_bits {
3501         u8         status[0x8];
3502         u8         reserved_0[0x18];
3503
3504         u8         syndrome[0x20];
3505
3506         u8         reserved_1[0xa0];
3507
3508         u8         reserved_2[0x13];
3509         u8         vlan_valid[0x1];
3510         u8         vlan[0xc];
3511
3512         struct mlx5_ifc_mac_address_layout_bits mac_address;
3513
3514         u8         reserved_3[0xc0];
3515 };
3516
3517 struct mlx5_ifc_query_l2_table_entry_in_bits {
3518         u8         opcode[0x10];
3519         u8         reserved_0[0x10];
3520
3521         u8         reserved_1[0x10];
3522         u8         op_mod[0x10];
3523
3524         u8         reserved_2[0x60];
3525
3526         u8         reserved_3[0x8];
3527         u8         table_index[0x18];
3528
3529         u8         reserved_4[0x140];
3530 };
3531
3532 struct mlx5_ifc_query_issi_out_bits {
3533         u8         status[0x8];
3534         u8         reserved_0[0x18];
3535
3536         u8         syndrome[0x20];
3537
3538         u8         reserved_1[0x10];
3539         u8         current_issi[0x10];
3540
3541         u8         reserved_2[0xa0];
3542
3543         u8         supported_issi_reserved[76][0x8];
3544         u8         supported_issi_dw0[0x20];
3545 };
3546
3547 struct mlx5_ifc_query_issi_in_bits {
3548         u8         opcode[0x10];
3549         u8         reserved_0[0x10];
3550
3551         u8         reserved_1[0x10];
3552         u8         op_mod[0x10];
3553
3554         u8         reserved_2[0x40];
3555 };
3556
3557 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3558         u8         status[0x8];
3559         u8         reserved_0[0x18];
3560
3561         u8         syndrome[0x20];
3562
3563         u8         reserved_1[0x40];
3564
3565         struct mlx5_ifc_pkey_bits pkey[0];
3566 };
3567
3568 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3569         u8         opcode[0x10];
3570         u8         reserved_0[0x10];
3571
3572         u8         reserved_1[0x10];
3573         u8         op_mod[0x10];
3574
3575         u8         other_vport[0x1];
3576         u8         reserved_2[0xb];
3577         u8         port_num[0x4];
3578         u8         vport_number[0x10];
3579
3580         u8         reserved_3[0x10];
3581         u8         pkey_index[0x10];
3582 };
3583
3584 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3585         u8         status[0x8];
3586         u8         reserved_0[0x18];
3587
3588         u8         syndrome[0x20];
3589
3590         u8         reserved_1[0x20];
3591
3592         u8         gids_num[0x10];
3593         u8         reserved_2[0x10];
3594
3595         struct mlx5_ifc_array128_auto_bits gid[0];
3596 };
3597
3598 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3599         u8         opcode[0x10];
3600         u8         reserved_0[0x10];
3601
3602         u8         reserved_1[0x10];
3603         u8         op_mod[0x10];
3604
3605         u8         other_vport[0x1];
3606         u8         reserved_2[0xb];
3607         u8         port_num[0x4];
3608         u8         vport_number[0x10];
3609
3610         u8         reserved_3[0x10];
3611         u8         gid_index[0x10];
3612 };
3613
3614 struct mlx5_ifc_query_hca_vport_context_out_bits {
3615         u8         status[0x8];
3616         u8         reserved_0[0x18];
3617
3618         u8         syndrome[0x20];
3619
3620         u8         reserved_1[0x40];
3621
3622         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3623 };
3624
3625 struct mlx5_ifc_query_hca_vport_context_in_bits {
3626         u8         opcode[0x10];
3627         u8         reserved_0[0x10];
3628
3629         u8         reserved_1[0x10];
3630         u8         op_mod[0x10];
3631
3632         u8         other_vport[0x1];
3633         u8         reserved_2[0xb];
3634         u8         port_num[0x4];
3635         u8         vport_number[0x10];
3636
3637         u8         reserved_3[0x20];
3638 };
3639
3640 struct mlx5_ifc_query_hca_cap_out_bits {
3641         u8         status[0x8];
3642         u8         reserved_0[0x18];
3643
3644         u8         syndrome[0x20];
3645
3646         u8         reserved_1[0x40];
3647
3648         union mlx5_ifc_hca_cap_union_bits capability;
3649 };
3650
3651 struct mlx5_ifc_query_hca_cap_in_bits {
3652         u8         opcode[0x10];
3653         u8         reserved_0[0x10];
3654
3655         u8         reserved_1[0x10];
3656         u8         op_mod[0x10];
3657
3658         u8         reserved_2[0x40];
3659 };
3660
3661 struct mlx5_ifc_query_flow_table_out_bits {
3662         u8         status[0x8];
3663         u8         reserved_0[0x18];
3664
3665         u8         syndrome[0x20];
3666
3667         u8         reserved_1[0x80];
3668
3669         u8         reserved_2[0x8];
3670         u8         level[0x8];
3671         u8         reserved_3[0x8];
3672         u8         log_size[0x8];
3673
3674         u8         reserved_4[0x120];
3675 };
3676
3677 struct mlx5_ifc_query_flow_table_in_bits {
3678         u8         opcode[0x10];
3679         u8         reserved_0[0x10];
3680
3681         u8         reserved_1[0x10];
3682         u8         op_mod[0x10];
3683
3684         u8         reserved_2[0x40];
3685
3686         u8         table_type[0x8];
3687         u8         reserved_3[0x18];
3688
3689         u8         reserved_4[0x8];
3690         u8         table_id[0x18];
3691
3692         u8         reserved_5[0x140];
3693 };
3694
3695 struct mlx5_ifc_query_fte_out_bits {
3696         u8         status[0x8];
3697         u8         reserved_0[0x18];
3698
3699         u8         syndrome[0x20];
3700
3701         u8         reserved_1[0x1c0];
3702
3703         struct mlx5_ifc_flow_context_bits flow_context;
3704 };
3705
3706 struct mlx5_ifc_query_fte_in_bits {
3707         u8         opcode[0x10];
3708         u8         reserved_0[0x10];
3709
3710         u8         reserved_1[0x10];
3711         u8         op_mod[0x10];
3712
3713         u8         reserved_2[0x40];
3714
3715         u8         table_type[0x8];
3716         u8         reserved_3[0x18];
3717
3718         u8         reserved_4[0x8];
3719         u8         table_id[0x18];
3720
3721         u8         reserved_5[0x40];
3722
3723         u8         flow_index[0x20];
3724
3725         u8         reserved_6[0xe0];
3726 };
3727
3728 enum {
3729         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3730         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3731         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3732 };
3733
3734 struct mlx5_ifc_query_flow_group_out_bits {
3735         u8         status[0x8];
3736         u8         reserved_0[0x18];
3737
3738         u8         syndrome[0x20];
3739
3740         u8         reserved_1[0xa0];
3741
3742         u8         start_flow_index[0x20];
3743
3744         u8         reserved_2[0x20];
3745
3746         u8         end_flow_index[0x20];
3747
3748         u8         reserved_3[0xa0];
3749
3750         u8         reserved_4[0x18];
3751         u8         match_criteria_enable[0x8];
3752
3753         struct mlx5_ifc_fte_match_param_bits match_criteria;
3754
3755         u8         reserved_5[0xe00];
3756 };
3757
3758 struct mlx5_ifc_query_flow_group_in_bits {
3759         u8         opcode[0x10];
3760         u8         reserved_0[0x10];
3761
3762         u8         reserved_1[0x10];
3763         u8         op_mod[0x10];
3764
3765         u8         reserved_2[0x40];
3766
3767         u8         table_type[0x8];
3768         u8         reserved_3[0x18];
3769
3770         u8         reserved_4[0x8];
3771         u8         table_id[0x18];
3772
3773         u8         group_id[0x20];
3774
3775         u8         reserved_5[0x120];
3776 };
3777
3778 struct mlx5_ifc_query_esw_vport_context_out_bits {
3779         u8         status[0x8];
3780         u8         reserved_0[0x18];
3781
3782         u8         syndrome[0x20];
3783
3784         u8         reserved_1[0x40];
3785
3786         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3787 };
3788
3789 struct mlx5_ifc_query_esw_vport_context_in_bits {
3790         u8         opcode[0x10];
3791         u8         reserved_0[0x10];
3792
3793         u8         reserved_1[0x10];
3794         u8         op_mod[0x10];
3795
3796         u8         other_vport[0x1];
3797         u8         reserved_2[0xf];
3798         u8         vport_number[0x10];
3799
3800         u8         reserved_3[0x20];
3801 };
3802
3803 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3804         u8         status[0x8];
3805         u8         reserved_0[0x18];
3806
3807         u8         syndrome[0x20];
3808
3809         u8         reserved_1[0x40];
3810 };
3811
3812 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3813         u8         reserved[0x1c];
3814         u8         vport_cvlan_insert[0x1];
3815         u8         vport_svlan_insert[0x1];
3816         u8         vport_cvlan_strip[0x1];
3817         u8         vport_svlan_strip[0x1];
3818 };
3819
3820 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3821         u8         opcode[0x10];
3822         u8         reserved_0[0x10];
3823
3824         u8         reserved_1[0x10];
3825         u8         op_mod[0x10];
3826
3827         u8         other_vport[0x1];
3828         u8         reserved_2[0xf];
3829         u8         vport_number[0x10];
3830
3831         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3832
3833         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3834 };
3835
3836 struct mlx5_ifc_query_eq_out_bits {
3837         u8         status[0x8];
3838         u8         reserved_0[0x18];
3839
3840         u8         syndrome[0x20];
3841
3842         u8         reserved_1[0x40];
3843
3844         struct mlx5_ifc_eqc_bits eq_context_entry;
3845
3846         u8         reserved_2[0x40];
3847
3848         u8         event_bitmask[0x40];
3849
3850         u8         reserved_3[0x580];
3851
3852         u8         pas[0][0x40];
3853 };
3854
3855 struct mlx5_ifc_query_eq_in_bits {
3856         u8         opcode[0x10];
3857         u8         reserved_0[0x10];
3858
3859         u8         reserved_1[0x10];
3860         u8         op_mod[0x10];
3861
3862         u8         reserved_2[0x18];
3863         u8         eq_number[0x8];
3864
3865         u8         reserved_3[0x20];
3866 };
3867
3868 struct mlx5_ifc_query_dct_out_bits {
3869         u8         status[0x8];
3870         u8         reserved_0[0x18];
3871
3872         u8         syndrome[0x20];
3873
3874         u8         reserved_1[0x40];
3875
3876         struct mlx5_ifc_dctc_bits dct_context_entry;
3877
3878         u8         reserved_2[0x180];
3879 };
3880
3881 struct mlx5_ifc_query_dct_in_bits {
3882         u8         opcode[0x10];
3883         u8         reserved_0[0x10];
3884
3885         u8         reserved_1[0x10];
3886         u8         op_mod[0x10];
3887
3888         u8         reserved_2[0x8];
3889         u8         dctn[0x18];
3890
3891         u8         reserved_3[0x20];
3892 };
3893
3894 struct mlx5_ifc_query_cq_out_bits {
3895         u8         status[0x8];
3896         u8         reserved_0[0x18];
3897
3898         u8         syndrome[0x20];
3899
3900         u8         reserved_1[0x40];
3901
3902         struct mlx5_ifc_cqc_bits cq_context;
3903
3904         u8         reserved_2[0x600];
3905
3906         u8         pas[0][0x40];
3907 };
3908
3909 struct mlx5_ifc_query_cq_in_bits {
3910         u8         opcode[0x10];
3911         u8         reserved_0[0x10];
3912
3913         u8         reserved_1[0x10];
3914         u8         op_mod[0x10];
3915
3916         u8         reserved_2[0x8];
3917         u8         cqn[0x18];
3918
3919         u8         reserved_3[0x20];
3920 };
3921
3922 struct mlx5_ifc_query_cong_status_out_bits {
3923         u8         status[0x8];
3924         u8         reserved_0[0x18];
3925
3926         u8         syndrome[0x20];
3927
3928         u8         reserved_1[0x20];
3929
3930         u8         enable[0x1];
3931         u8         tag_enable[0x1];
3932         u8         reserved_2[0x1e];
3933 };
3934
3935 struct mlx5_ifc_query_cong_status_in_bits {
3936         u8         opcode[0x10];
3937         u8         reserved_0[0x10];
3938
3939         u8         reserved_1[0x10];
3940         u8         op_mod[0x10];
3941
3942         u8         reserved_2[0x18];
3943         u8         priority[0x4];
3944         u8         cong_protocol[0x4];
3945
3946         u8         reserved_3[0x20];
3947 };
3948
3949 struct mlx5_ifc_query_cong_statistics_out_bits {
3950         u8         status[0x8];
3951         u8         reserved_0[0x18];
3952
3953         u8         syndrome[0x20];
3954
3955         u8         reserved_1[0x40];
3956
3957         u8         cur_flows[0x20];
3958
3959         u8         sum_flows[0x20];
3960
3961         u8         cnp_ignored_high[0x20];
3962
3963         u8         cnp_ignored_low[0x20];
3964
3965         u8         cnp_handled_high[0x20];
3966
3967         u8         cnp_handled_low[0x20];
3968
3969         u8         reserved_2[0x100];
3970
3971         u8         time_stamp_high[0x20];
3972
3973         u8         time_stamp_low[0x20];
3974
3975         u8         accumulators_period[0x20];
3976
3977         u8         ecn_marked_roce_packets_high[0x20];
3978
3979         u8         ecn_marked_roce_packets_low[0x20];
3980
3981         u8         cnps_sent_high[0x20];
3982
3983         u8         cnps_sent_low[0x20];
3984
3985         u8         reserved_3[0x560];
3986 };
3987
3988 struct mlx5_ifc_query_cong_statistics_in_bits {
3989         u8         opcode[0x10];
3990         u8         reserved_0[0x10];
3991
3992         u8         reserved_1[0x10];
3993         u8         op_mod[0x10];
3994
3995         u8         clear[0x1];
3996         u8         reserved_2[0x1f];
3997
3998         u8         reserved_3[0x20];
3999 };
4000
4001 struct mlx5_ifc_query_cong_params_out_bits {
4002         u8         status[0x8];
4003         u8         reserved_0[0x18];
4004
4005         u8         syndrome[0x20];
4006
4007         u8         reserved_1[0x40];
4008
4009         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4010 };
4011
4012 struct mlx5_ifc_query_cong_params_in_bits {
4013         u8         opcode[0x10];
4014         u8         reserved_0[0x10];
4015
4016         u8         reserved_1[0x10];
4017         u8         op_mod[0x10];
4018
4019         u8         reserved_2[0x1c];
4020         u8         cong_protocol[0x4];
4021
4022         u8         reserved_3[0x20];
4023 };
4024
4025 struct mlx5_ifc_query_adapter_out_bits {
4026         u8         status[0x8];
4027         u8         reserved_0[0x18];
4028
4029         u8         syndrome[0x20];
4030
4031         u8         reserved_1[0x40];
4032
4033         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4034 };
4035
4036 struct mlx5_ifc_query_adapter_in_bits {
4037         u8         opcode[0x10];
4038         u8         reserved_0[0x10];
4039
4040         u8         reserved_1[0x10];
4041         u8         op_mod[0x10];
4042
4043         u8         reserved_2[0x40];
4044 };
4045
4046 struct mlx5_ifc_qp_2rst_out_bits {
4047         u8         status[0x8];
4048         u8         reserved_0[0x18];
4049
4050         u8         syndrome[0x20];
4051
4052         u8         reserved_1[0x40];
4053 };
4054
4055 struct mlx5_ifc_qp_2rst_in_bits {
4056         u8         opcode[0x10];
4057         u8         reserved_0[0x10];
4058
4059         u8         reserved_1[0x10];
4060         u8         op_mod[0x10];
4061
4062         u8         reserved_2[0x8];
4063         u8         qpn[0x18];
4064
4065         u8         reserved_3[0x20];
4066 };
4067
4068 struct mlx5_ifc_qp_2err_out_bits {
4069         u8         status[0x8];
4070         u8         reserved_0[0x18];
4071
4072         u8         syndrome[0x20];
4073
4074         u8         reserved_1[0x40];
4075 };
4076
4077 struct mlx5_ifc_qp_2err_in_bits {
4078         u8         opcode[0x10];
4079         u8         reserved_0[0x10];
4080
4081         u8         reserved_1[0x10];
4082         u8         op_mod[0x10];
4083
4084         u8         reserved_2[0x8];
4085         u8         qpn[0x18];
4086
4087         u8         reserved_3[0x20];
4088 };
4089
4090 struct mlx5_ifc_page_fault_resume_out_bits {
4091         u8         status[0x8];
4092         u8         reserved_0[0x18];
4093
4094         u8         syndrome[0x20];
4095
4096         u8         reserved_1[0x40];
4097 };
4098
4099 struct mlx5_ifc_page_fault_resume_in_bits {
4100         u8         opcode[0x10];
4101         u8         reserved_0[0x10];
4102
4103         u8         reserved_1[0x10];
4104         u8         op_mod[0x10];
4105
4106         u8         error[0x1];
4107         u8         reserved_2[0x4];
4108         u8         rdma[0x1];
4109         u8         read_write[0x1];
4110         u8         req_res[0x1];
4111         u8         qpn[0x18];
4112
4113         u8         reserved_3[0x20];
4114 };
4115
4116 struct mlx5_ifc_nop_out_bits {
4117         u8         status[0x8];
4118         u8         reserved_0[0x18];
4119
4120         u8         syndrome[0x20];
4121
4122         u8         reserved_1[0x40];
4123 };
4124
4125 struct mlx5_ifc_nop_in_bits {
4126         u8         opcode[0x10];
4127         u8         reserved_0[0x10];
4128
4129         u8         reserved_1[0x10];
4130         u8         op_mod[0x10];
4131
4132         u8         reserved_2[0x40];
4133 };
4134
4135 struct mlx5_ifc_modify_vport_state_out_bits {
4136         u8         status[0x8];
4137         u8         reserved_0[0x18];
4138
4139         u8         syndrome[0x20];
4140
4141         u8         reserved_1[0x40];
4142 };
4143
4144 struct mlx5_ifc_modify_vport_state_in_bits {
4145         u8         opcode[0x10];
4146         u8         reserved_0[0x10];
4147
4148         u8         reserved_1[0x10];
4149         u8         op_mod[0x10];
4150
4151         u8         other_vport[0x1];
4152         u8         reserved_2[0xf];
4153         u8         vport_number[0x10];
4154
4155         u8         reserved_3[0x18];
4156         u8         admin_state[0x4];
4157         u8         reserved_4[0x4];
4158 };
4159
4160 struct mlx5_ifc_modify_tis_out_bits {
4161         u8         status[0x8];
4162         u8         reserved_0[0x18];
4163
4164         u8         syndrome[0x20];
4165
4166         u8         reserved_1[0x40];
4167 };
4168
4169 struct mlx5_ifc_modify_tis_in_bits {
4170         u8         opcode[0x10];
4171         u8         reserved_0[0x10];
4172
4173         u8         reserved_1[0x10];
4174         u8         op_mod[0x10];
4175
4176         u8         reserved_2[0x8];
4177         u8         tisn[0x18];
4178
4179         u8         reserved_3[0x20];
4180
4181         u8         modify_bitmask[0x40];
4182
4183         u8         reserved_4[0x40];
4184
4185         struct mlx5_ifc_tisc_bits ctx;
4186 };
4187
4188 struct mlx5_ifc_modify_tir_bitmask_bits {
4189         u8         reserved_0[0x20];
4190
4191         u8         reserved_1[0x1b];
4192         u8         self_lb_en[0x1];
4193         u8         reserved_2[0x3];
4194         u8         lro[0x1];
4195 };
4196
4197 struct mlx5_ifc_modify_tir_out_bits {
4198         u8         status[0x8];
4199         u8         reserved_0[0x18];
4200
4201         u8         syndrome[0x20];
4202
4203         u8         reserved_1[0x40];
4204 };
4205
4206 struct mlx5_ifc_modify_tir_in_bits {
4207         u8         opcode[0x10];
4208         u8         reserved_0[0x10];
4209
4210         u8         reserved_1[0x10];
4211         u8         op_mod[0x10];
4212
4213         u8         reserved_2[0x8];
4214         u8         tirn[0x18];
4215
4216         u8         reserved_3[0x20];
4217
4218         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4219
4220         u8         reserved_4[0x40];
4221
4222         struct mlx5_ifc_tirc_bits ctx;
4223 };
4224
4225 struct mlx5_ifc_modify_sq_out_bits {
4226         u8         status[0x8];
4227         u8         reserved_0[0x18];
4228
4229         u8         syndrome[0x20];
4230
4231         u8         reserved_1[0x40];
4232 };
4233
4234 struct mlx5_ifc_modify_sq_in_bits {
4235         u8         opcode[0x10];
4236         u8         reserved_0[0x10];
4237
4238         u8         reserved_1[0x10];
4239         u8         op_mod[0x10];
4240
4241         u8         sq_state[0x4];
4242         u8         reserved_2[0x4];
4243         u8         sqn[0x18];
4244
4245         u8         reserved_3[0x20];
4246
4247         u8         modify_bitmask[0x40];
4248
4249         u8         reserved_4[0x40];
4250
4251         struct mlx5_ifc_sqc_bits ctx;
4252 };
4253
4254 struct mlx5_ifc_modify_rqt_out_bits {
4255         u8         status[0x8];
4256         u8         reserved_0[0x18];
4257
4258         u8         syndrome[0x20];
4259
4260         u8         reserved_1[0x40];
4261 };
4262
4263 struct mlx5_ifc_rqt_bitmask_bits {
4264         u8         reserved[0x20];
4265
4266         u8         reserved1[0x1f];
4267         u8         rqn_list[0x1];
4268 };
4269
4270 struct mlx5_ifc_modify_rqt_in_bits {
4271         u8         opcode[0x10];
4272         u8         reserved_0[0x10];
4273
4274         u8         reserved_1[0x10];
4275         u8         op_mod[0x10];
4276
4277         u8         reserved_2[0x8];
4278         u8         rqtn[0x18];
4279
4280         u8         reserved_3[0x20];
4281
4282         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4283
4284         u8         reserved_4[0x40];
4285
4286         struct mlx5_ifc_rqtc_bits ctx;
4287 };
4288
4289 struct mlx5_ifc_modify_rq_out_bits {
4290         u8         status[0x8];
4291         u8         reserved_0[0x18];
4292
4293         u8         syndrome[0x20];
4294
4295         u8         reserved_1[0x40];
4296 };
4297
4298 struct mlx5_ifc_modify_rq_in_bits {
4299         u8         opcode[0x10];
4300         u8         reserved_0[0x10];
4301
4302         u8         reserved_1[0x10];
4303         u8         op_mod[0x10];
4304
4305         u8         rq_state[0x4];
4306         u8         reserved_2[0x4];
4307         u8         rqn[0x18];
4308
4309         u8         reserved_3[0x20];
4310
4311         u8         modify_bitmask[0x40];
4312
4313         u8         reserved_4[0x40];
4314
4315         struct mlx5_ifc_rqc_bits ctx;
4316 };
4317
4318 struct mlx5_ifc_modify_rmp_out_bits {
4319         u8         status[0x8];
4320         u8         reserved_0[0x18];
4321
4322         u8         syndrome[0x20];
4323
4324         u8         reserved_1[0x40];
4325 };
4326
4327 struct mlx5_ifc_rmp_bitmask_bits {
4328         u8         reserved[0x20];
4329
4330         u8         reserved1[0x1f];
4331         u8         lwm[0x1];
4332 };
4333
4334 struct mlx5_ifc_modify_rmp_in_bits {
4335         u8         opcode[0x10];
4336         u8         reserved_0[0x10];
4337
4338         u8         reserved_1[0x10];
4339         u8         op_mod[0x10];
4340
4341         u8         rmp_state[0x4];
4342         u8         reserved_2[0x4];
4343         u8         rmpn[0x18];
4344
4345         u8         reserved_3[0x20];
4346
4347         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4348
4349         u8         reserved_4[0x40];
4350
4351         struct mlx5_ifc_rmpc_bits ctx;
4352 };
4353
4354 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4355         u8         status[0x8];
4356         u8         reserved_0[0x18];
4357
4358         u8         syndrome[0x20];
4359
4360         u8         reserved_1[0x40];
4361 };
4362
4363 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4364         u8         reserved_0[0x19];
4365         u8         mtu[0x1];
4366         u8         change_event[0x1];
4367         u8         promisc[0x1];
4368         u8         permanent_address[0x1];
4369         u8         addresses_list[0x1];
4370         u8         roce_en[0x1];
4371         u8         reserved_1[0x1];
4372 };
4373
4374 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4375         u8         opcode[0x10];
4376         u8         reserved_0[0x10];
4377
4378         u8         reserved_1[0x10];
4379         u8         op_mod[0x10];
4380
4381         u8         other_vport[0x1];
4382         u8         reserved_2[0xf];
4383         u8         vport_number[0x10];
4384
4385         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4386
4387         u8         reserved_3[0x780];
4388
4389         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4390 };
4391
4392 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4393         u8         status[0x8];
4394         u8         reserved_0[0x18];
4395
4396         u8         syndrome[0x20];
4397
4398         u8         reserved_1[0x40];
4399 };
4400
4401 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4402         u8         opcode[0x10];
4403         u8         reserved_0[0x10];
4404
4405         u8         reserved_1[0x10];
4406         u8         op_mod[0x10];
4407
4408         u8         other_vport[0x1];
4409         u8         reserved_2[0xb];
4410         u8         port_num[0x4];
4411         u8         vport_number[0x10];
4412
4413         u8         reserved_3[0x20];
4414
4415         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4416 };
4417
4418 struct mlx5_ifc_modify_cq_out_bits {
4419         u8         status[0x8];
4420         u8         reserved_0[0x18];
4421
4422         u8         syndrome[0x20];
4423
4424         u8         reserved_1[0x40];
4425 };
4426
4427 enum {
4428         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4429         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4430 };
4431
4432 struct mlx5_ifc_modify_cq_in_bits {
4433         u8         opcode[0x10];
4434         u8         reserved_0[0x10];
4435
4436         u8         reserved_1[0x10];
4437         u8         op_mod[0x10];
4438
4439         u8         reserved_2[0x8];
4440         u8         cqn[0x18];
4441
4442         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4443
4444         struct mlx5_ifc_cqc_bits cq_context;
4445
4446         u8         reserved_3[0x600];
4447
4448         u8         pas[0][0x40];
4449 };
4450
4451 struct mlx5_ifc_modify_cong_status_out_bits {
4452         u8         status[0x8];
4453         u8         reserved_0[0x18];
4454
4455         u8         syndrome[0x20];
4456
4457         u8         reserved_1[0x40];
4458 };
4459
4460 struct mlx5_ifc_modify_cong_status_in_bits {
4461         u8         opcode[0x10];
4462         u8         reserved_0[0x10];
4463
4464         u8         reserved_1[0x10];
4465         u8         op_mod[0x10];
4466
4467         u8         reserved_2[0x18];
4468         u8         priority[0x4];
4469         u8         cong_protocol[0x4];
4470
4471         u8         enable[0x1];
4472         u8         tag_enable[0x1];
4473         u8         reserved_3[0x1e];
4474 };
4475
4476 struct mlx5_ifc_modify_cong_params_out_bits {
4477         u8         status[0x8];
4478         u8         reserved_0[0x18];
4479
4480         u8         syndrome[0x20];
4481
4482         u8         reserved_1[0x40];
4483 };
4484
4485 struct mlx5_ifc_modify_cong_params_in_bits {
4486         u8         opcode[0x10];
4487         u8         reserved_0[0x10];
4488
4489         u8         reserved_1[0x10];
4490         u8         op_mod[0x10];
4491
4492         u8         reserved_2[0x1c];
4493         u8         cong_protocol[0x4];
4494
4495         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4496
4497         u8         reserved_3[0x80];
4498
4499         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4500 };
4501
4502 struct mlx5_ifc_manage_pages_out_bits {
4503         u8         status[0x8];
4504         u8         reserved_0[0x18];
4505
4506         u8         syndrome[0x20];
4507
4508         u8         output_num_entries[0x20];
4509
4510         u8         reserved_1[0x20];
4511
4512         u8         pas[0][0x40];
4513 };
4514
4515 enum {
4516         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4517         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4518         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4519 };
4520
4521 struct mlx5_ifc_manage_pages_in_bits {
4522         u8         opcode[0x10];
4523         u8         reserved_0[0x10];
4524
4525         u8         reserved_1[0x10];
4526         u8         op_mod[0x10];
4527
4528         u8         reserved_2[0x10];
4529         u8         function_id[0x10];
4530
4531         u8         input_num_entries[0x20];
4532
4533         u8         pas[0][0x40];
4534 };
4535
4536 struct mlx5_ifc_mad_ifc_out_bits {
4537         u8         status[0x8];
4538         u8         reserved_0[0x18];
4539
4540         u8         syndrome[0x20];
4541
4542         u8         reserved_1[0x40];
4543
4544         u8         response_mad_packet[256][0x8];
4545 };
4546
4547 struct mlx5_ifc_mad_ifc_in_bits {
4548         u8         opcode[0x10];
4549         u8         reserved_0[0x10];
4550
4551         u8         reserved_1[0x10];
4552         u8         op_mod[0x10];
4553
4554         u8         remote_lid[0x10];
4555         u8         reserved_2[0x8];
4556         u8         port[0x8];
4557
4558         u8         reserved_3[0x20];
4559
4560         u8         mad[256][0x8];
4561 };
4562
4563 struct mlx5_ifc_init_hca_out_bits {
4564         u8         status[0x8];
4565         u8         reserved_0[0x18];
4566
4567         u8         syndrome[0x20];
4568
4569         u8         reserved_1[0x40];
4570 };
4571
4572 struct mlx5_ifc_init_hca_in_bits {
4573         u8         opcode[0x10];
4574         u8         reserved_0[0x10];
4575
4576         u8         reserved_1[0x10];
4577         u8         op_mod[0x10];
4578
4579         u8         reserved_2[0x40];
4580 };
4581
4582 struct mlx5_ifc_init2rtr_qp_out_bits {
4583         u8         status[0x8];
4584         u8         reserved_0[0x18];
4585
4586         u8         syndrome[0x20];
4587
4588         u8         reserved_1[0x40];
4589 };
4590
4591 struct mlx5_ifc_init2rtr_qp_in_bits {
4592         u8         opcode[0x10];
4593         u8         reserved_0[0x10];
4594
4595         u8         reserved_1[0x10];
4596         u8         op_mod[0x10];
4597
4598         u8         reserved_2[0x8];
4599         u8         qpn[0x18];
4600
4601         u8         reserved_3[0x20];
4602
4603         u8         opt_param_mask[0x20];
4604
4605         u8         reserved_4[0x20];
4606
4607         struct mlx5_ifc_qpc_bits qpc;
4608
4609         u8         reserved_5[0x80];
4610 };
4611
4612 struct mlx5_ifc_init2init_qp_out_bits {
4613         u8         status[0x8];
4614         u8         reserved_0[0x18];
4615
4616         u8         syndrome[0x20];
4617
4618         u8         reserved_1[0x40];
4619 };
4620
4621 struct mlx5_ifc_init2init_qp_in_bits {
4622         u8         opcode[0x10];
4623         u8         reserved_0[0x10];
4624
4625         u8         reserved_1[0x10];
4626         u8         op_mod[0x10];
4627
4628         u8         reserved_2[0x8];
4629         u8         qpn[0x18];
4630
4631         u8         reserved_3[0x20];
4632
4633         u8         opt_param_mask[0x20];
4634
4635         u8         reserved_4[0x20];
4636
4637         struct mlx5_ifc_qpc_bits qpc;
4638
4639         u8         reserved_5[0x80];
4640 };
4641
4642 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4643         u8         status[0x8];
4644         u8         reserved_0[0x18];
4645
4646         u8         syndrome[0x20];
4647
4648         u8         reserved_1[0x40];
4649
4650         u8         packet_headers_log[128][0x8];
4651
4652         u8         packet_syndrome[64][0x8];
4653 };
4654
4655 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4656         u8         opcode[0x10];
4657         u8         reserved_0[0x10];
4658
4659         u8         reserved_1[0x10];
4660         u8         op_mod[0x10];
4661
4662         u8         reserved_2[0x40];
4663 };
4664
4665 struct mlx5_ifc_gen_eqe_in_bits {
4666         u8         opcode[0x10];
4667         u8         reserved_0[0x10];
4668
4669         u8         reserved_1[0x10];
4670         u8         op_mod[0x10];
4671
4672         u8         reserved_2[0x18];
4673         u8         eq_number[0x8];
4674
4675         u8         reserved_3[0x20];
4676
4677         u8         eqe[64][0x8];
4678 };
4679
4680 struct mlx5_ifc_gen_eq_out_bits {
4681         u8         status[0x8];
4682         u8         reserved_0[0x18];
4683
4684         u8         syndrome[0x20];
4685
4686         u8         reserved_1[0x40];
4687 };
4688
4689 struct mlx5_ifc_enable_hca_out_bits {
4690         u8         status[0x8];
4691         u8         reserved_0[0x18];
4692
4693         u8         syndrome[0x20];
4694
4695         u8         reserved_1[0x20];
4696 };
4697
4698 struct mlx5_ifc_enable_hca_in_bits {
4699         u8         opcode[0x10];
4700         u8         reserved_0[0x10];
4701
4702         u8         reserved_1[0x10];
4703         u8         op_mod[0x10];
4704
4705         u8         reserved_2[0x10];
4706         u8         function_id[0x10];
4707
4708         u8         reserved_3[0x20];
4709 };
4710
4711 struct mlx5_ifc_drain_dct_out_bits {
4712         u8         status[0x8];
4713         u8         reserved_0[0x18];
4714
4715         u8         syndrome[0x20];
4716
4717         u8         reserved_1[0x40];
4718 };
4719
4720 struct mlx5_ifc_drain_dct_in_bits {
4721         u8         opcode[0x10];
4722         u8         reserved_0[0x10];
4723
4724         u8         reserved_1[0x10];
4725         u8         op_mod[0x10];
4726
4727         u8         reserved_2[0x8];
4728         u8         dctn[0x18];
4729
4730         u8         reserved_3[0x20];
4731 };
4732
4733 struct mlx5_ifc_disable_hca_out_bits {
4734         u8         status[0x8];
4735         u8         reserved_0[0x18];
4736
4737         u8         syndrome[0x20];
4738
4739         u8         reserved_1[0x20];
4740 };
4741
4742 struct mlx5_ifc_disable_hca_in_bits {
4743         u8         opcode[0x10];
4744         u8         reserved_0[0x10];
4745
4746         u8         reserved_1[0x10];
4747         u8         op_mod[0x10];
4748
4749         u8         reserved_2[0x10];
4750         u8         function_id[0x10];
4751
4752         u8         reserved_3[0x20];
4753 };
4754
4755 struct mlx5_ifc_detach_from_mcg_out_bits {
4756         u8         status[0x8];
4757         u8         reserved_0[0x18];
4758
4759         u8         syndrome[0x20];
4760
4761         u8         reserved_1[0x40];
4762 };
4763
4764 struct mlx5_ifc_detach_from_mcg_in_bits {
4765         u8         opcode[0x10];
4766         u8         reserved_0[0x10];
4767
4768         u8         reserved_1[0x10];
4769         u8         op_mod[0x10];
4770
4771         u8         reserved_2[0x8];
4772         u8         qpn[0x18];
4773
4774         u8         reserved_3[0x20];
4775
4776         u8         multicast_gid[16][0x8];
4777 };
4778
4779 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4780         u8         status[0x8];
4781         u8         reserved_0[0x18];
4782
4783         u8         syndrome[0x20];
4784
4785         u8         reserved_1[0x40];
4786 };
4787
4788 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4789         u8         opcode[0x10];
4790         u8         reserved_0[0x10];
4791
4792         u8         reserved_1[0x10];
4793         u8         op_mod[0x10];
4794
4795         u8         reserved_2[0x8];
4796         u8         xrc_srqn[0x18];
4797
4798         u8         reserved_3[0x20];
4799 };
4800
4801 struct mlx5_ifc_destroy_tis_out_bits {
4802         u8         status[0x8];
4803         u8         reserved_0[0x18];
4804
4805         u8         syndrome[0x20];
4806
4807         u8         reserved_1[0x40];
4808 };
4809
4810 struct mlx5_ifc_destroy_tis_in_bits {
4811         u8         opcode[0x10];
4812         u8         reserved_0[0x10];
4813
4814         u8         reserved_1[0x10];
4815         u8         op_mod[0x10];
4816
4817         u8         reserved_2[0x8];
4818         u8         tisn[0x18];
4819
4820         u8         reserved_3[0x20];
4821 };
4822
4823 struct mlx5_ifc_destroy_tir_out_bits {
4824         u8         status[0x8];
4825         u8         reserved_0[0x18];
4826
4827         u8         syndrome[0x20];
4828
4829         u8         reserved_1[0x40];
4830 };
4831
4832 struct mlx5_ifc_destroy_tir_in_bits {
4833         u8         opcode[0x10];
4834         u8         reserved_0[0x10];
4835
4836         u8         reserved_1[0x10];
4837         u8         op_mod[0x10];
4838
4839         u8         reserved_2[0x8];
4840         u8         tirn[0x18];
4841
4842         u8         reserved_3[0x20];
4843 };
4844
4845 struct mlx5_ifc_destroy_srq_out_bits {
4846         u8         status[0x8];
4847         u8         reserved_0[0x18];
4848
4849         u8         syndrome[0x20];
4850
4851         u8         reserved_1[0x40];
4852 };
4853
4854 struct mlx5_ifc_destroy_srq_in_bits {
4855         u8         opcode[0x10];
4856         u8         reserved_0[0x10];
4857
4858         u8         reserved_1[0x10];
4859         u8         op_mod[0x10];
4860
4861         u8         reserved_2[0x8];
4862         u8         srqn[0x18];
4863
4864         u8         reserved_3[0x20];
4865 };
4866
4867 struct mlx5_ifc_destroy_sq_out_bits {
4868         u8         status[0x8];
4869         u8         reserved_0[0x18];
4870
4871         u8         syndrome[0x20];
4872
4873         u8         reserved_1[0x40];
4874 };
4875
4876 struct mlx5_ifc_destroy_sq_in_bits {
4877         u8         opcode[0x10];
4878         u8         reserved_0[0x10];
4879
4880         u8         reserved_1[0x10];
4881         u8         op_mod[0x10];
4882
4883         u8         reserved_2[0x8];
4884         u8         sqn[0x18];
4885
4886         u8         reserved_3[0x20];
4887 };
4888
4889 struct mlx5_ifc_destroy_rqt_out_bits {
4890         u8         status[0x8];
4891         u8         reserved_0[0x18];
4892
4893         u8         syndrome[0x20];
4894
4895         u8         reserved_1[0x40];
4896 };
4897
4898 struct mlx5_ifc_destroy_rqt_in_bits {
4899         u8         opcode[0x10];
4900         u8         reserved_0[0x10];
4901
4902         u8         reserved_1[0x10];
4903         u8         op_mod[0x10];
4904
4905         u8         reserved_2[0x8];
4906         u8         rqtn[0x18];
4907
4908         u8         reserved_3[0x20];
4909 };
4910
4911 struct mlx5_ifc_destroy_rq_out_bits {
4912         u8         status[0x8];
4913         u8         reserved_0[0x18];
4914
4915         u8         syndrome[0x20];
4916
4917         u8         reserved_1[0x40];
4918 };
4919
4920 struct mlx5_ifc_destroy_rq_in_bits {
4921         u8         opcode[0x10];
4922         u8         reserved_0[0x10];
4923
4924         u8         reserved_1[0x10];
4925         u8         op_mod[0x10];
4926
4927         u8         reserved_2[0x8];
4928         u8         rqn[0x18];
4929
4930         u8         reserved_3[0x20];
4931 };
4932
4933 struct mlx5_ifc_destroy_rmp_out_bits {
4934         u8         status[0x8];
4935         u8         reserved_0[0x18];
4936
4937         u8         syndrome[0x20];
4938
4939         u8         reserved_1[0x40];
4940 };
4941
4942 struct mlx5_ifc_destroy_rmp_in_bits {
4943         u8         opcode[0x10];
4944         u8         reserved_0[0x10];
4945
4946         u8         reserved_1[0x10];
4947         u8         op_mod[0x10];
4948
4949         u8         reserved_2[0x8];
4950         u8         rmpn[0x18];
4951
4952         u8         reserved_3[0x20];
4953 };
4954
4955 struct mlx5_ifc_destroy_qp_out_bits {
4956         u8         status[0x8];
4957         u8         reserved_0[0x18];
4958
4959         u8         syndrome[0x20];
4960
4961         u8         reserved_1[0x40];
4962 };
4963
4964 struct mlx5_ifc_destroy_qp_in_bits {
4965         u8         opcode[0x10];
4966         u8         reserved_0[0x10];
4967
4968         u8         reserved_1[0x10];
4969         u8         op_mod[0x10];
4970
4971         u8         reserved_2[0x8];
4972         u8         qpn[0x18];
4973
4974         u8         reserved_3[0x20];
4975 };
4976
4977 struct mlx5_ifc_destroy_psv_out_bits {
4978         u8         status[0x8];
4979         u8         reserved_0[0x18];
4980
4981         u8         syndrome[0x20];
4982
4983         u8         reserved_1[0x40];
4984 };
4985
4986 struct mlx5_ifc_destroy_psv_in_bits {
4987         u8         opcode[0x10];
4988         u8         reserved_0[0x10];
4989
4990         u8         reserved_1[0x10];
4991         u8         op_mod[0x10];
4992
4993         u8         reserved_2[0x8];
4994         u8         psvn[0x18];
4995
4996         u8         reserved_3[0x20];
4997 };
4998
4999 struct mlx5_ifc_destroy_mkey_out_bits {
5000         u8         status[0x8];
5001         u8         reserved_0[0x18];
5002
5003         u8         syndrome[0x20];
5004
5005         u8         reserved_1[0x40];
5006 };
5007
5008 struct mlx5_ifc_destroy_mkey_in_bits {
5009         u8         opcode[0x10];
5010         u8         reserved_0[0x10];
5011
5012         u8         reserved_1[0x10];
5013         u8         op_mod[0x10];
5014
5015         u8         reserved_2[0x8];
5016         u8         mkey_index[0x18];
5017
5018         u8         reserved_3[0x20];
5019 };
5020
5021 struct mlx5_ifc_destroy_flow_table_out_bits {
5022         u8         status[0x8];
5023         u8         reserved_0[0x18];
5024
5025         u8         syndrome[0x20];
5026
5027         u8         reserved_1[0x40];
5028 };
5029
5030 struct mlx5_ifc_destroy_flow_table_in_bits {
5031         u8         opcode[0x10];
5032         u8         reserved_0[0x10];
5033
5034         u8         reserved_1[0x10];
5035         u8         op_mod[0x10];
5036
5037         u8         reserved_2[0x40];
5038
5039         u8         table_type[0x8];
5040         u8         reserved_3[0x18];
5041
5042         u8         reserved_4[0x8];
5043         u8         table_id[0x18];
5044
5045         u8         reserved_5[0x140];
5046 };
5047
5048 struct mlx5_ifc_destroy_flow_group_out_bits {
5049         u8         status[0x8];
5050         u8         reserved_0[0x18];
5051
5052         u8         syndrome[0x20];
5053
5054         u8         reserved_1[0x40];
5055 };
5056
5057 struct mlx5_ifc_destroy_flow_group_in_bits {
5058         u8         opcode[0x10];
5059         u8         reserved_0[0x10];
5060
5061         u8         reserved_1[0x10];
5062         u8         op_mod[0x10];
5063
5064         u8         reserved_2[0x40];
5065
5066         u8         table_type[0x8];
5067         u8         reserved_3[0x18];
5068
5069         u8         reserved_4[0x8];
5070         u8         table_id[0x18];
5071
5072         u8         group_id[0x20];
5073
5074         u8         reserved_5[0x120];
5075 };
5076
5077 struct mlx5_ifc_destroy_eq_out_bits {
5078         u8         status[0x8];
5079         u8         reserved_0[0x18];
5080
5081         u8         syndrome[0x20];
5082
5083         u8         reserved_1[0x40];
5084 };
5085
5086 struct mlx5_ifc_destroy_eq_in_bits {
5087         u8         opcode[0x10];
5088         u8         reserved_0[0x10];
5089
5090         u8         reserved_1[0x10];
5091         u8         op_mod[0x10];
5092
5093         u8         reserved_2[0x18];
5094         u8         eq_number[0x8];
5095
5096         u8         reserved_3[0x20];
5097 };
5098
5099 struct mlx5_ifc_destroy_dct_out_bits {
5100         u8         status[0x8];
5101         u8         reserved_0[0x18];
5102
5103         u8         syndrome[0x20];
5104
5105         u8         reserved_1[0x40];
5106 };
5107
5108 struct mlx5_ifc_destroy_dct_in_bits {
5109         u8         opcode[0x10];
5110         u8         reserved_0[0x10];
5111
5112         u8         reserved_1[0x10];
5113         u8         op_mod[0x10];
5114
5115         u8         reserved_2[0x8];
5116         u8         dctn[0x18];
5117
5118         u8         reserved_3[0x20];
5119 };
5120
5121 struct mlx5_ifc_destroy_cq_out_bits {
5122         u8         status[0x8];
5123         u8         reserved_0[0x18];
5124
5125         u8         syndrome[0x20];
5126
5127         u8         reserved_1[0x40];
5128 };
5129
5130 struct mlx5_ifc_destroy_cq_in_bits {
5131         u8         opcode[0x10];
5132         u8         reserved_0[0x10];
5133
5134         u8         reserved_1[0x10];
5135         u8         op_mod[0x10];
5136
5137         u8         reserved_2[0x8];
5138         u8         cqn[0x18];
5139
5140         u8         reserved_3[0x20];
5141 };
5142
5143 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5144         u8         status[0x8];
5145         u8         reserved_0[0x18];
5146
5147         u8         syndrome[0x20];
5148
5149         u8         reserved_1[0x40];
5150 };
5151
5152 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5153         u8         opcode[0x10];
5154         u8         reserved_0[0x10];
5155
5156         u8         reserved_1[0x10];
5157         u8         op_mod[0x10];
5158
5159         u8         reserved_2[0x20];
5160
5161         u8         reserved_3[0x10];
5162         u8         vxlan_udp_port[0x10];
5163 };
5164
5165 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5166         u8         status[0x8];
5167         u8         reserved_0[0x18];
5168
5169         u8         syndrome[0x20];
5170
5171         u8         reserved_1[0x40];
5172 };
5173
5174 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5175         u8         opcode[0x10];
5176         u8         reserved_0[0x10];
5177
5178         u8         reserved_1[0x10];
5179         u8         op_mod[0x10];
5180
5181         u8         reserved_2[0x60];
5182
5183         u8         reserved_3[0x8];
5184         u8         table_index[0x18];
5185
5186         u8         reserved_4[0x140];
5187 };
5188
5189 struct mlx5_ifc_delete_fte_out_bits {
5190         u8         status[0x8];
5191         u8         reserved_0[0x18];
5192
5193         u8         syndrome[0x20];
5194
5195         u8         reserved_1[0x40];
5196 };
5197
5198 struct mlx5_ifc_delete_fte_in_bits {
5199         u8         opcode[0x10];
5200         u8         reserved_0[0x10];
5201
5202         u8         reserved_1[0x10];
5203         u8         op_mod[0x10];
5204
5205         u8         reserved_2[0x40];
5206
5207         u8         table_type[0x8];
5208         u8         reserved_3[0x18];
5209
5210         u8         reserved_4[0x8];
5211         u8         table_id[0x18];
5212
5213         u8         reserved_5[0x40];
5214
5215         u8         flow_index[0x20];
5216
5217         u8         reserved_6[0xe0];
5218 };
5219
5220 struct mlx5_ifc_dealloc_xrcd_out_bits {
5221         u8         status[0x8];
5222         u8         reserved_0[0x18];
5223
5224         u8         syndrome[0x20];
5225
5226         u8         reserved_1[0x40];
5227 };
5228
5229 struct mlx5_ifc_dealloc_xrcd_in_bits {
5230         u8         opcode[0x10];
5231         u8         reserved_0[0x10];
5232
5233         u8         reserved_1[0x10];
5234         u8         op_mod[0x10];
5235
5236         u8         reserved_2[0x8];
5237         u8         xrcd[0x18];
5238
5239         u8         reserved_3[0x20];
5240 };
5241
5242 struct mlx5_ifc_dealloc_uar_out_bits {
5243         u8         status[0x8];
5244         u8         reserved_0[0x18];
5245
5246         u8         syndrome[0x20];
5247
5248         u8         reserved_1[0x40];
5249 };
5250
5251 struct mlx5_ifc_dealloc_uar_in_bits {
5252         u8         opcode[0x10];
5253         u8         reserved_0[0x10];
5254
5255         u8         reserved_1[0x10];
5256         u8         op_mod[0x10];
5257
5258         u8         reserved_2[0x8];
5259         u8         uar[0x18];
5260
5261         u8         reserved_3[0x20];
5262 };
5263
5264 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5265         u8         status[0x8];
5266         u8         reserved_0[0x18];
5267
5268         u8         syndrome[0x20];
5269
5270         u8         reserved_1[0x40];
5271 };
5272
5273 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5274         u8         opcode[0x10];
5275         u8         reserved_0[0x10];
5276
5277         u8         reserved_1[0x10];
5278         u8         op_mod[0x10];
5279
5280         u8         reserved_2[0x8];
5281         u8         transport_domain[0x18];
5282
5283         u8         reserved_3[0x20];
5284 };
5285
5286 struct mlx5_ifc_dealloc_q_counter_out_bits {
5287         u8         status[0x8];
5288         u8         reserved_0[0x18];
5289
5290         u8         syndrome[0x20];
5291
5292         u8         reserved_1[0x40];
5293 };
5294
5295 struct mlx5_ifc_dealloc_q_counter_in_bits {
5296         u8         opcode[0x10];
5297         u8         reserved_0[0x10];
5298
5299         u8         reserved_1[0x10];
5300         u8         op_mod[0x10];
5301
5302         u8         reserved_2[0x18];
5303         u8         counter_set_id[0x8];
5304
5305         u8         reserved_3[0x20];
5306 };
5307
5308 struct mlx5_ifc_dealloc_pd_out_bits {
5309         u8         status[0x8];
5310         u8         reserved_0[0x18];
5311
5312         u8         syndrome[0x20];
5313
5314         u8         reserved_1[0x40];
5315 };
5316
5317 struct mlx5_ifc_dealloc_pd_in_bits {
5318         u8         opcode[0x10];
5319         u8         reserved_0[0x10];
5320
5321         u8         reserved_1[0x10];
5322         u8         op_mod[0x10];
5323
5324         u8         reserved_2[0x8];
5325         u8         pd[0x18];
5326
5327         u8         reserved_3[0x20];
5328 };
5329
5330 struct mlx5_ifc_create_xrc_srq_out_bits {
5331         u8         status[0x8];
5332         u8         reserved_0[0x18];
5333
5334         u8         syndrome[0x20];
5335
5336         u8         reserved_1[0x8];
5337         u8         xrc_srqn[0x18];
5338
5339         u8         reserved_2[0x20];
5340 };
5341
5342 struct mlx5_ifc_create_xrc_srq_in_bits {
5343         u8         opcode[0x10];
5344         u8         reserved_0[0x10];
5345
5346         u8         reserved_1[0x10];
5347         u8         op_mod[0x10];
5348
5349         u8         reserved_2[0x40];
5350
5351         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5352
5353         u8         reserved_3[0x600];
5354
5355         u8         pas[0][0x40];
5356 };
5357
5358 struct mlx5_ifc_create_tis_out_bits {
5359         u8         status[0x8];
5360         u8         reserved_0[0x18];
5361
5362         u8         syndrome[0x20];
5363
5364         u8         reserved_1[0x8];
5365         u8         tisn[0x18];
5366
5367         u8         reserved_2[0x20];
5368 };
5369
5370 struct mlx5_ifc_create_tis_in_bits {
5371         u8         opcode[0x10];
5372         u8         reserved_0[0x10];
5373
5374         u8         reserved_1[0x10];
5375         u8         op_mod[0x10];
5376
5377         u8         reserved_2[0xc0];
5378
5379         struct mlx5_ifc_tisc_bits ctx;
5380 };
5381
5382 struct mlx5_ifc_create_tir_out_bits {
5383         u8         status[0x8];
5384         u8         reserved_0[0x18];
5385
5386         u8         syndrome[0x20];
5387
5388         u8         reserved_1[0x8];
5389         u8         tirn[0x18];
5390
5391         u8         reserved_2[0x20];
5392 };
5393
5394 struct mlx5_ifc_create_tir_in_bits {
5395         u8         opcode[0x10];
5396         u8         reserved_0[0x10];
5397
5398         u8         reserved_1[0x10];
5399         u8         op_mod[0x10];
5400
5401         u8         reserved_2[0xc0];
5402
5403         struct mlx5_ifc_tirc_bits ctx;
5404 };
5405
5406 struct mlx5_ifc_create_srq_out_bits {
5407         u8         status[0x8];
5408         u8         reserved_0[0x18];
5409
5410         u8         syndrome[0x20];
5411
5412         u8         reserved_1[0x8];
5413         u8         srqn[0x18];
5414
5415         u8         reserved_2[0x20];
5416 };
5417
5418 struct mlx5_ifc_create_srq_in_bits {
5419         u8         opcode[0x10];
5420         u8         reserved_0[0x10];
5421
5422         u8         reserved_1[0x10];
5423         u8         op_mod[0x10];
5424
5425         u8         reserved_2[0x40];
5426
5427         struct mlx5_ifc_srqc_bits srq_context_entry;
5428
5429         u8         reserved_3[0x600];
5430
5431         u8         pas[0][0x40];
5432 };
5433
5434 struct mlx5_ifc_create_sq_out_bits {
5435         u8         status[0x8];
5436         u8         reserved_0[0x18];
5437
5438         u8         syndrome[0x20];
5439
5440         u8         reserved_1[0x8];
5441         u8         sqn[0x18];
5442
5443         u8         reserved_2[0x20];
5444 };
5445
5446 struct mlx5_ifc_create_sq_in_bits {
5447         u8         opcode[0x10];
5448         u8         reserved_0[0x10];
5449
5450         u8         reserved_1[0x10];
5451         u8         op_mod[0x10];
5452
5453         u8         reserved_2[0xc0];
5454
5455         struct mlx5_ifc_sqc_bits ctx;
5456 };
5457
5458 struct mlx5_ifc_create_rqt_out_bits {
5459         u8         status[0x8];
5460         u8         reserved_0[0x18];
5461
5462         u8         syndrome[0x20];
5463
5464         u8         reserved_1[0x8];
5465         u8         rqtn[0x18];
5466
5467         u8         reserved_2[0x20];
5468 };
5469
5470 struct mlx5_ifc_create_rqt_in_bits {
5471         u8         opcode[0x10];
5472         u8         reserved_0[0x10];
5473
5474         u8         reserved_1[0x10];
5475         u8         op_mod[0x10];
5476
5477         u8         reserved_2[0xc0];
5478
5479         struct mlx5_ifc_rqtc_bits rqt_context;
5480 };
5481
5482 struct mlx5_ifc_create_rq_out_bits {
5483         u8         status[0x8];
5484         u8         reserved_0[0x18];
5485
5486         u8         syndrome[0x20];
5487
5488         u8         reserved_1[0x8];
5489         u8         rqn[0x18];
5490
5491         u8         reserved_2[0x20];
5492 };
5493
5494 struct mlx5_ifc_create_rq_in_bits {
5495         u8         opcode[0x10];
5496         u8         reserved_0[0x10];
5497
5498         u8         reserved_1[0x10];
5499         u8         op_mod[0x10];
5500
5501         u8         reserved_2[0xc0];
5502
5503         struct mlx5_ifc_rqc_bits ctx;
5504 };
5505
5506 struct mlx5_ifc_create_rmp_out_bits {
5507         u8         status[0x8];
5508         u8         reserved_0[0x18];
5509
5510         u8         syndrome[0x20];
5511
5512         u8         reserved_1[0x8];
5513         u8         rmpn[0x18];
5514
5515         u8         reserved_2[0x20];
5516 };
5517
5518 struct mlx5_ifc_create_rmp_in_bits {
5519         u8         opcode[0x10];
5520         u8         reserved_0[0x10];
5521
5522         u8         reserved_1[0x10];
5523         u8         op_mod[0x10];
5524
5525         u8         reserved_2[0xc0];
5526
5527         struct mlx5_ifc_rmpc_bits ctx;
5528 };
5529
5530 struct mlx5_ifc_create_qp_out_bits {
5531         u8         status[0x8];
5532         u8         reserved_0[0x18];
5533
5534         u8         syndrome[0x20];
5535
5536         u8         reserved_1[0x8];
5537         u8         qpn[0x18];
5538
5539         u8         reserved_2[0x20];
5540 };
5541
5542 struct mlx5_ifc_create_qp_in_bits {
5543         u8         opcode[0x10];
5544         u8         reserved_0[0x10];
5545
5546         u8         reserved_1[0x10];
5547         u8         op_mod[0x10];
5548
5549         u8         reserved_2[0x40];
5550
5551         u8         opt_param_mask[0x20];
5552
5553         u8         reserved_3[0x20];
5554
5555         struct mlx5_ifc_qpc_bits qpc;
5556
5557         u8         reserved_4[0x80];
5558
5559         u8         pas[0][0x40];
5560 };
5561
5562 struct mlx5_ifc_create_psv_out_bits {
5563         u8         status[0x8];
5564         u8         reserved_0[0x18];
5565
5566         u8         syndrome[0x20];
5567
5568         u8         reserved_1[0x40];
5569
5570         u8         reserved_2[0x8];
5571         u8         psv0_index[0x18];
5572
5573         u8         reserved_3[0x8];
5574         u8         psv1_index[0x18];
5575
5576         u8         reserved_4[0x8];
5577         u8         psv2_index[0x18];
5578
5579         u8         reserved_5[0x8];
5580         u8         psv3_index[0x18];
5581 };
5582
5583 struct mlx5_ifc_create_psv_in_bits {
5584         u8         opcode[0x10];
5585         u8         reserved_0[0x10];
5586
5587         u8         reserved_1[0x10];
5588         u8         op_mod[0x10];
5589
5590         u8         num_psv[0x4];
5591         u8         reserved_2[0x4];
5592         u8         pd[0x18];
5593
5594         u8         reserved_3[0x20];
5595 };
5596
5597 struct mlx5_ifc_create_mkey_out_bits {
5598         u8         status[0x8];
5599         u8         reserved_0[0x18];
5600
5601         u8         syndrome[0x20];
5602
5603         u8         reserved_1[0x8];
5604         u8         mkey_index[0x18];
5605
5606         u8         reserved_2[0x20];
5607 };
5608
5609 struct mlx5_ifc_create_mkey_in_bits {
5610         u8         opcode[0x10];
5611         u8         reserved_0[0x10];
5612
5613         u8         reserved_1[0x10];
5614         u8         op_mod[0x10];
5615
5616         u8         reserved_2[0x20];
5617
5618         u8         pg_access[0x1];
5619         u8         reserved_3[0x1f];
5620
5621         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5622
5623         u8         reserved_4[0x80];
5624
5625         u8         translations_octword_actual_size[0x20];
5626
5627         u8         reserved_5[0x560];
5628
5629         u8         klm_pas_mtt[0][0x20];
5630 };
5631
5632 struct mlx5_ifc_create_flow_table_out_bits {
5633         u8         status[0x8];
5634         u8         reserved_0[0x18];
5635
5636         u8         syndrome[0x20];
5637
5638         u8         reserved_1[0x8];
5639         u8         table_id[0x18];
5640
5641         u8         reserved_2[0x20];
5642 };
5643
5644 struct mlx5_ifc_create_flow_table_in_bits {
5645         u8         opcode[0x10];
5646         u8         reserved_0[0x10];
5647
5648         u8         reserved_1[0x10];
5649         u8         op_mod[0x10];
5650
5651         u8         reserved_2[0x40];
5652
5653         u8         table_type[0x8];
5654         u8         reserved_3[0x18];
5655
5656         u8         reserved_4[0x20];
5657
5658         u8         reserved_5[0x8];
5659         u8         level[0x8];
5660         u8         reserved_6[0x8];
5661         u8         log_size[0x8];
5662
5663         u8         reserved_7[0x120];
5664 };
5665
5666 struct mlx5_ifc_create_flow_group_out_bits {
5667         u8         status[0x8];
5668         u8         reserved_0[0x18];
5669
5670         u8         syndrome[0x20];
5671
5672         u8         reserved_1[0x8];
5673         u8         group_id[0x18];
5674
5675         u8         reserved_2[0x20];
5676 };
5677
5678 enum {
5679         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5680         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5681         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5682 };
5683
5684 struct mlx5_ifc_create_flow_group_in_bits {
5685         u8         opcode[0x10];
5686         u8         reserved_0[0x10];
5687
5688         u8         reserved_1[0x10];
5689         u8         op_mod[0x10];
5690
5691         u8         reserved_2[0x40];
5692
5693         u8         table_type[0x8];
5694         u8         reserved_3[0x18];
5695
5696         u8         reserved_4[0x8];
5697         u8         table_id[0x18];
5698
5699         u8         reserved_5[0x20];
5700
5701         u8         start_flow_index[0x20];
5702
5703         u8         reserved_6[0x20];
5704
5705         u8         end_flow_index[0x20];
5706
5707         u8         reserved_7[0xa0];
5708
5709         u8         reserved_8[0x18];
5710         u8         match_criteria_enable[0x8];
5711
5712         struct mlx5_ifc_fte_match_param_bits match_criteria;
5713
5714         u8         reserved_9[0xe00];
5715 };
5716
5717 struct mlx5_ifc_create_eq_out_bits {
5718         u8         status[0x8];
5719         u8         reserved_0[0x18];
5720
5721         u8         syndrome[0x20];
5722
5723         u8         reserved_1[0x18];
5724         u8         eq_number[0x8];
5725
5726         u8         reserved_2[0x20];
5727 };
5728
5729 struct mlx5_ifc_create_eq_in_bits {
5730         u8         opcode[0x10];
5731         u8         reserved_0[0x10];
5732
5733         u8         reserved_1[0x10];
5734         u8         op_mod[0x10];
5735
5736         u8         reserved_2[0x40];
5737
5738         struct mlx5_ifc_eqc_bits eq_context_entry;
5739
5740         u8         reserved_3[0x40];
5741
5742         u8         event_bitmask[0x40];
5743
5744         u8         reserved_4[0x580];
5745
5746         u8         pas[0][0x40];
5747 };
5748
5749 struct mlx5_ifc_create_dct_out_bits {
5750         u8         status[0x8];
5751         u8         reserved_0[0x18];
5752
5753         u8         syndrome[0x20];
5754
5755         u8         reserved_1[0x8];
5756         u8         dctn[0x18];
5757
5758         u8         reserved_2[0x20];
5759 };
5760
5761 struct mlx5_ifc_create_dct_in_bits {
5762         u8         opcode[0x10];
5763         u8         reserved_0[0x10];
5764
5765         u8         reserved_1[0x10];
5766         u8         op_mod[0x10];
5767
5768         u8         reserved_2[0x40];
5769
5770         struct mlx5_ifc_dctc_bits dct_context_entry;
5771
5772         u8         reserved_3[0x180];
5773 };
5774
5775 struct mlx5_ifc_create_cq_out_bits {
5776         u8         status[0x8];
5777         u8         reserved_0[0x18];
5778
5779         u8         syndrome[0x20];
5780
5781         u8         reserved_1[0x8];
5782         u8         cqn[0x18];
5783
5784         u8         reserved_2[0x20];
5785 };
5786
5787 struct mlx5_ifc_create_cq_in_bits {
5788         u8         opcode[0x10];
5789         u8         reserved_0[0x10];
5790
5791         u8         reserved_1[0x10];
5792         u8         op_mod[0x10];
5793
5794         u8         reserved_2[0x40];
5795
5796         struct mlx5_ifc_cqc_bits cq_context;
5797
5798         u8         reserved_3[0x600];
5799
5800         u8         pas[0][0x40];
5801 };
5802
5803 struct mlx5_ifc_config_int_moderation_out_bits {
5804         u8         status[0x8];
5805         u8         reserved_0[0x18];
5806
5807         u8         syndrome[0x20];
5808
5809         u8         reserved_1[0x4];
5810         u8         min_delay[0xc];
5811         u8         int_vector[0x10];
5812
5813         u8         reserved_2[0x20];
5814 };
5815
5816 enum {
5817         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
5818         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
5819 };
5820
5821 struct mlx5_ifc_config_int_moderation_in_bits {
5822         u8         opcode[0x10];
5823         u8         reserved_0[0x10];
5824
5825         u8         reserved_1[0x10];
5826         u8         op_mod[0x10];
5827
5828         u8         reserved_2[0x4];
5829         u8         min_delay[0xc];
5830         u8         int_vector[0x10];
5831
5832         u8         reserved_3[0x20];
5833 };
5834
5835 struct mlx5_ifc_attach_to_mcg_out_bits {
5836         u8         status[0x8];
5837         u8         reserved_0[0x18];
5838
5839         u8         syndrome[0x20];
5840
5841         u8         reserved_1[0x40];
5842 };
5843
5844 struct mlx5_ifc_attach_to_mcg_in_bits {
5845         u8         opcode[0x10];
5846         u8         reserved_0[0x10];
5847
5848         u8         reserved_1[0x10];
5849         u8         op_mod[0x10];
5850
5851         u8         reserved_2[0x8];
5852         u8         qpn[0x18];
5853
5854         u8         reserved_3[0x20];
5855
5856         u8         multicast_gid[16][0x8];
5857 };
5858
5859 struct mlx5_ifc_arm_xrc_srq_out_bits {
5860         u8         status[0x8];
5861         u8         reserved_0[0x18];
5862
5863         u8         syndrome[0x20];
5864
5865         u8         reserved_1[0x40];
5866 };
5867
5868 enum {
5869         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
5870 };
5871
5872 struct mlx5_ifc_arm_xrc_srq_in_bits {
5873         u8         opcode[0x10];
5874         u8         reserved_0[0x10];
5875
5876         u8         reserved_1[0x10];
5877         u8         op_mod[0x10];
5878
5879         u8         reserved_2[0x8];
5880         u8         xrc_srqn[0x18];
5881
5882         u8         reserved_3[0x10];
5883         u8         lwm[0x10];
5884 };
5885
5886 struct mlx5_ifc_arm_rq_out_bits {
5887         u8         status[0x8];
5888         u8         reserved_0[0x18];
5889
5890         u8         syndrome[0x20];
5891
5892         u8         reserved_1[0x40];
5893 };
5894
5895 enum {
5896         MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
5897 };
5898
5899 struct mlx5_ifc_arm_rq_in_bits {
5900         u8         opcode[0x10];
5901         u8         reserved_0[0x10];
5902
5903         u8         reserved_1[0x10];
5904         u8         op_mod[0x10];
5905
5906         u8         reserved_2[0x8];
5907         u8         srq_number[0x18];
5908
5909         u8         reserved_3[0x10];
5910         u8         lwm[0x10];
5911 };
5912
5913 struct mlx5_ifc_arm_dct_out_bits {
5914         u8         status[0x8];
5915         u8         reserved_0[0x18];
5916
5917         u8         syndrome[0x20];
5918
5919         u8         reserved_1[0x40];
5920 };
5921
5922 struct mlx5_ifc_arm_dct_in_bits {
5923         u8         opcode[0x10];
5924         u8         reserved_0[0x10];
5925
5926         u8         reserved_1[0x10];
5927         u8         op_mod[0x10];
5928
5929         u8         reserved_2[0x8];
5930         u8         dct_number[0x18];
5931
5932         u8         reserved_3[0x20];
5933 };
5934
5935 struct mlx5_ifc_alloc_xrcd_out_bits {
5936         u8         status[0x8];
5937         u8         reserved_0[0x18];
5938
5939         u8         syndrome[0x20];
5940
5941         u8         reserved_1[0x8];
5942         u8         xrcd[0x18];
5943
5944         u8         reserved_2[0x20];
5945 };
5946
5947 struct mlx5_ifc_alloc_xrcd_in_bits {
5948         u8         opcode[0x10];
5949         u8         reserved_0[0x10];
5950
5951         u8         reserved_1[0x10];
5952         u8         op_mod[0x10];
5953
5954         u8         reserved_2[0x40];
5955 };
5956
5957 struct mlx5_ifc_alloc_uar_out_bits {
5958         u8         status[0x8];
5959         u8         reserved_0[0x18];
5960
5961         u8         syndrome[0x20];
5962
5963         u8         reserved_1[0x8];
5964         u8         uar[0x18];
5965
5966         u8         reserved_2[0x20];
5967 };
5968
5969 struct mlx5_ifc_alloc_uar_in_bits {
5970         u8         opcode[0x10];
5971         u8         reserved_0[0x10];
5972
5973         u8         reserved_1[0x10];
5974         u8         op_mod[0x10];
5975
5976         u8         reserved_2[0x40];
5977 };
5978
5979 struct mlx5_ifc_alloc_transport_domain_out_bits {
5980         u8         status[0x8];
5981         u8         reserved_0[0x18];
5982
5983         u8         syndrome[0x20];
5984
5985         u8         reserved_1[0x8];
5986         u8         transport_domain[0x18];
5987
5988         u8         reserved_2[0x20];
5989 };
5990
5991 struct mlx5_ifc_alloc_transport_domain_in_bits {
5992         u8         opcode[0x10];
5993         u8         reserved_0[0x10];
5994
5995         u8         reserved_1[0x10];
5996         u8         op_mod[0x10];
5997
5998         u8         reserved_2[0x40];
5999 };
6000
6001 struct mlx5_ifc_alloc_q_counter_out_bits {
6002         u8         status[0x8];
6003         u8         reserved_0[0x18];
6004
6005         u8         syndrome[0x20];
6006
6007         u8         reserved_1[0x18];
6008         u8         counter_set_id[0x8];
6009
6010         u8         reserved_2[0x20];
6011 };
6012
6013 struct mlx5_ifc_alloc_q_counter_in_bits {
6014         u8         opcode[0x10];
6015         u8         reserved_0[0x10];
6016
6017         u8         reserved_1[0x10];
6018         u8         op_mod[0x10];
6019
6020         u8         reserved_2[0x40];
6021 };
6022
6023 struct mlx5_ifc_alloc_pd_out_bits {
6024         u8         status[0x8];
6025         u8         reserved_0[0x18];
6026
6027         u8         syndrome[0x20];
6028
6029         u8         reserved_1[0x8];
6030         u8         pd[0x18];
6031
6032         u8         reserved_2[0x20];
6033 };
6034
6035 struct mlx5_ifc_alloc_pd_in_bits {
6036         u8         opcode[0x10];
6037         u8         reserved_0[0x10];
6038
6039         u8         reserved_1[0x10];
6040         u8         op_mod[0x10];
6041
6042         u8         reserved_2[0x40];
6043 };
6044
6045 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6046         u8         status[0x8];
6047         u8         reserved_0[0x18];
6048
6049         u8         syndrome[0x20];
6050
6051         u8         reserved_1[0x40];
6052 };
6053
6054 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6055         u8         opcode[0x10];
6056         u8         reserved_0[0x10];
6057
6058         u8         reserved_1[0x10];
6059         u8         op_mod[0x10];
6060
6061         u8         reserved_2[0x20];
6062
6063         u8         reserved_3[0x10];
6064         u8         vxlan_udp_port[0x10];
6065 };
6066
6067 struct mlx5_ifc_access_register_out_bits {
6068         u8         status[0x8];
6069         u8         reserved_0[0x18];
6070
6071         u8         syndrome[0x20];
6072
6073         u8         reserved_1[0x40];
6074
6075         u8         register_data[0][0x20];
6076 };
6077
6078 enum {
6079         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6080         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6081 };
6082
6083 struct mlx5_ifc_access_register_in_bits {
6084         u8         opcode[0x10];
6085         u8         reserved_0[0x10];
6086
6087         u8         reserved_1[0x10];
6088         u8         op_mod[0x10];
6089
6090         u8         reserved_2[0x10];
6091         u8         register_id[0x10];
6092
6093         u8         argument[0x20];
6094
6095         u8         register_data[0][0x20];
6096 };
6097
6098 struct mlx5_ifc_sltp_reg_bits {
6099         u8         status[0x4];
6100         u8         version[0x4];
6101         u8         local_port[0x8];
6102         u8         pnat[0x2];
6103         u8         reserved_0[0x2];
6104         u8         lane[0x4];
6105         u8         reserved_1[0x8];
6106
6107         u8         reserved_2[0x20];
6108
6109         u8         reserved_3[0x7];
6110         u8         polarity[0x1];
6111         u8         ob_tap0[0x8];
6112         u8         ob_tap1[0x8];
6113         u8         ob_tap2[0x8];
6114
6115         u8         reserved_4[0xc];
6116         u8         ob_preemp_mode[0x4];
6117         u8         ob_reg[0x8];
6118         u8         ob_bias[0x8];
6119
6120         u8         reserved_5[0x20];
6121 };
6122
6123 struct mlx5_ifc_slrg_reg_bits {
6124         u8         status[0x4];
6125         u8         version[0x4];
6126         u8         local_port[0x8];
6127         u8         pnat[0x2];
6128         u8         reserved_0[0x2];
6129         u8         lane[0x4];
6130         u8         reserved_1[0x8];
6131
6132         u8         time_to_link_up[0x10];
6133         u8         reserved_2[0xc];
6134         u8         grade_lane_speed[0x4];
6135
6136         u8         grade_version[0x8];
6137         u8         grade[0x18];
6138
6139         u8         reserved_3[0x4];
6140         u8         height_grade_type[0x4];
6141         u8         height_grade[0x18];
6142
6143         u8         height_dz[0x10];
6144         u8         height_dv[0x10];
6145
6146         u8         reserved_4[0x10];
6147         u8         height_sigma[0x10];
6148
6149         u8         reserved_5[0x20];
6150
6151         u8         reserved_6[0x4];
6152         u8         phase_grade_type[0x4];
6153         u8         phase_grade[0x18];
6154
6155         u8         reserved_7[0x8];
6156         u8         phase_eo_pos[0x8];
6157         u8         reserved_8[0x8];
6158         u8         phase_eo_neg[0x8];
6159
6160         u8         ffe_set_tested[0x10];
6161         u8         test_errors_per_lane[0x10];
6162 };
6163
6164 struct mlx5_ifc_pvlc_reg_bits {
6165         u8         reserved_0[0x8];
6166         u8         local_port[0x8];
6167         u8         reserved_1[0x10];
6168
6169         u8         reserved_2[0x1c];
6170         u8         vl_hw_cap[0x4];
6171
6172         u8         reserved_3[0x1c];
6173         u8         vl_admin[0x4];
6174
6175         u8         reserved_4[0x1c];
6176         u8         vl_operational[0x4];
6177 };
6178
6179 struct mlx5_ifc_pude_reg_bits {
6180         u8         swid[0x8];
6181         u8         local_port[0x8];
6182         u8         reserved_0[0x4];
6183         u8         admin_status[0x4];
6184         u8         reserved_1[0x4];
6185         u8         oper_status[0x4];
6186
6187         u8         reserved_2[0x60];
6188 };
6189
6190 struct mlx5_ifc_ptys_reg_bits {
6191         u8         reserved_0[0x8];
6192         u8         local_port[0x8];
6193         u8         reserved_1[0xd];
6194         u8         proto_mask[0x3];
6195
6196         u8         reserved_2[0x40];
6197
6198         u8         eth_proto_capability[0x20];
6199
6200         u8         ib_link_width_capability[0x10];
6201         u8         ib_proto_capability[0x10];
6202
6203         u8         reserved_3[0x20];
6204
6205         u8         eth_proto_admin[0x20];
6206
6207         u8         ib_link_width_admin[0x10];
6208         u8         ib_proto_admin[0x10];
6209
6210         u8         reserved_4[0x20];
6211
6212         u8         eth_proto_oper[0x20];
6213
6214         u8         ib_link_width_oper[0x10];
6215         u8         ib_proto_oper[0x10];
6216
6217         u8         reserved_5[0x20];
6218
6219         u8         eth_proto_lp_advertise[0x20];
6220
6221         u8         reserved_6[0x60];
6222 };
6223
6224 struct mlx5_ifc_ptas_reg_bits {
6225         u8         reserved_0[0x20];
6226
6227         u8         algorithm_options[0x10];
6228         u8         reserved_1[0x4];
6229         u8         repetitions_mode[0x4];
6230         u8         num_of_repetitions[0x8];
6231
6232         u8         grade_version[0x8];
6233         u8         height_grade_type[0x4];
6234         u8         phase_grade_type[0x4];
6235         u8         height_grade_weight[0x8];
6236         u8         phase_grade_weight[0x8];
6237
6238         u8         gisim_measure_bits[0x10];
6239         u8         adaptive_tap_measure_bits[0x10];
6240
6241         u8         ber_bath_high_error_threshold[0x10];
6242         u8         ber_bath_mid_error_threshold[0x10];
6243
6244         u8         ber_bath_low_error_threshold[0x10];
6245         u8         one_ratio_high_threshold[0x10];
6246
6247         u8         one_ratio_high_mid_threshold[0x10];
6248         u8         one_ratio_low_mid_threshold[0x10];
6249
6250         u8         one_ratio_low_threshold[0x10];
6251         u8         ndeo_error_threshold[0x10];
6252
6253         u8         mixer_offset_step_size[0x10];
6254         u8         reserved_2[0x8];
6255         u8         mix90_phase_for_voltage_bath[0x8];
6256
6257         u8         mixer_offset_start[0x10];
6258         u8         mixer_offset_end[0x10];
6259
6260         u8         reserved_3[0x15];
6261         u8         ber_test_time[0xb];
6262 };
6263
6264 struct mlx5_ifc_pspa_reg_bits {
6265         u8         swid[0x8];
6266         u8         local_port[0x8];
6267         u8         sub_port[0x8];
6268         u8         reserved_0[0x8];
6269
6270         u8         reserved_1[0x20];
6271 };
6272
6273 struct mlx5_ifc_pqdr_reg_bits {
6274         u8         reserved_0[0x8];
6275         u8         local_port[0x8];
6276         u8         reserved_1[0x5];
6277         u8         prio[0x3];
6278         u8         reserved_2[0x6];
6279         u8         mode[0x2];
6280
6281         u8         reserved_3[0x20];
6282
6283         u8         reserved_4[0x10];
6284         u8         min_threshold[0x10];
6285
6286         u8         reserved_5[0x10];
6287         u8         max_threshold[0x10];
6288
6289         u8         reserved_6[0x10];
6290         u8         mark_probability_denominator[0x10];
6291
6292         u8         reserved_7[0x60];
6293 };
6294
6295 struct mlx5_ifc_ppsc_reg_bits {
6296         u8         reserved_0[0x8];
6297         u8         local_port[0x8];
6298         u8         reserved_1[0x10];
6299
6300         u8         reserved_2[0x60];
6301
6302         u8         reserved_3[0x1c];
6303         u8         wrps_admin[0x4];
6304
6305         u8         reserved_4[0x1c];
6306         u8         wrps_status[0x4];
6307
6308         u8         reserved_5[0x8];
6309         u8         up_threshold[0x8];
6310         u8         reserved_6[0x8];
6311         u8         down_threshold[0x8];
6312
6313         u8         reserved_7[0x20];
6314
6315         u8         reserved_8[0x1c];
6316         u8         srps_admin[0x4];
6317
6318         u8         reserved_9[0x1c];
6319         u8         srps_status[0x4];
6320
6321         u8         reserved_10[0x40];
6322 };
6323
6324 struct mlx5_ifc_pplr_reg_bits {
6325         u8         reserved_0[0x8];
6326         u8         local_port[0x8];
6327         u8         reserved_1[0x10];
6328
6329         u8         reserved_2[0x8];
6330         u8         lb_cap[0x8];
6331         u8         reserved_3[0x8];
6332         u8         lb_en[0x8];
6333 };
6334
6335 struct mlx5_ifc_pplm_reg_bits {
6336         u8         reserved_0[0x8];
6337         u8         local_port[0x8];
6338         u8         reserved_1[0x10];
6339
6340         u8         reserved_2[0x20];
6341
6342         u8         port_profile_mode[0x8];
6343         u8         static_port_profile[0x8];
6344         u8         active_port_profile[0x8];
6345         u8         reserved_3[0x8];
6346
6347         u8         retransmission_active[0x8];
6348         u8         fec_mode_active[0x18];
6349
6350         u8         reserved_4[0x20];
6351 };
6352
6353 struct mlx5_ifc_ppcnt_reg_bits {
6354         u8         swid[0x8];
6355         u8         local_port[0x8];
6356         u8         pnat[0x2];
6357         u8         reserved_0[0x8];
6358         u8         grp[0x6];
6359
6360         u8         clr[0x1];
6361         u8         reserved_1[0x1c];
6362         u8         prio_tc[0x3];
6363
6364         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6365 };
6366
6367 struct mlx5_ifc_ppad_reg_bits {
6368         u8         reserved_0[0x3];
6369         u8         single_mac[0x1];
6370         u8         reserved_1[0x4];
6371         u8         local_port[0x8];
6372         u8         mac_47_32[0x10];
6373
6374         u8         mac_31_0[0x20];
6375
6376         u8         reserved_2[0x40];
6377 };
6378
6379 struct mlx5_ifc_pmtu_reg_bits {
6380         u8         reserved_0[0x8];
6381         u8         local_port[0x8];
6382         u8         reserved_1[0x10];
6383
6384         u8         max_mtu[0x10];
6385         u8         reserved_2[0x10];
6386
6387         u8         admin_mtu[0x10];
6388         u8         reserved_3[0x10];
6389
6390         u8         oper_mtu[0x10];
6391         u8         reserved_4[0x10];
6392 };
6393
6394 struct mlx5_ifc_pmpr_reg_bits {
6395         u8         reserved_0[0x8];
6396         u8         module[0x8];
6397         u8         reserved_1[0x10];
6398
6399         u8         reserved_2[0x18];
6400         u8         attenuation_5g[0x8];
6401
6402         u8         reserved_3[0x18];
6403         u8         attenuation_7g[0x8];
6404
6405         u8         reserved_4[0x18];
6406         u8         attenuation_12g[0x8];
6407 };
6408
6409 struct mlx5_ifc_pmpe_reg_bits {
6410         u8         reserved_0[0x8];
6411         u8         module[0x8];
6412         u8         reserved_1[0xc];
6413         u8         module_status[0x4];
6414
6415         u8         reserved_2[0x60];
6416 };
6417
6418 struct mlx5_ifc_pmpc_reg_bits {
6419         u8         module_state_updated[32][0x8];
6420 };
6421
6422 struct mlx5_ifc_pmlpn_reg_bits {
6423         u8         reserved_0[0x4];
6424         u8         mlpn_status[0x4];
6425         u8         local_port[0x8];
6426         u8         reserved_1[0x10];
6427
6428         u8         e[0x1];
6429         u8         reserved_2[0x1f];
6430 };
6431
6432 struct mlx5_ifc_pmlp_reg_bits {
6433         u8         rxtx[0x1];
6434         u8         reserved_0[0x7];
6435         u8         local_port[0x8];
6436         u8         reserved_1[0x8];
6437         u8         width[0x8];
6438
6439         u8         lane0_module_mapping[0x20];
6440
6441         u8         lane1_module_mapping[0x20];
6442
6443         u8         lane2_module_mapping[0x20];
6444
6445         u8         lane3_module_mapping[0x20];
6446
6447         u8         reserved_2[0x160];
6448 };
6449
6450 struct mlx5_ifc_pmaos_reg_bits {
6451         u8         reserved_0[0x8];
6452         u8         module[0x8];
6453         u8         reserved_1[0x4];
6454         u8         admin_status[0x4];
6455         u8         reserved_2[0x4];
6456         u8         oper_status[0x4];
6457
6458         u8         ase[0x1];
6459         u8         ee[0x1];
6460         u8         reserved_3[0x1c];
6461         u8         e[0x2];
6462
6463         u8         reserved_4[0x40];
6464 };
6465
6466 struct mlx5_ifc_plpc_reg_bits {
6467         u8         reserved_0[0x4];
6468         u8         profile_id[0xc];
6469         u8         reserved_1[0x4];
6470         u8         proto_mask[0x4];
6471         u8         reserved_2[0x8];
6472
6473         u8         reserved_3[0x10];
6474         u8         lane_speed[0x10];
6475
6476         u8         reserved_4[0x17];
6477         u8         lpbf[0x1];
6478         u8         fec_mode_policy[0x8];
6479
6480         u8         retransmission_capability[0x8];
6481         u8         fec_mode_capability[0x18];
6482
6483         u8         retransmission_support_admin[0x8];
6484         u8         fec_mode_support_admin[0x18];
6485
6486         u8         retransmission_request_admin[0x8];
6487         u8         fec_mode_request_admin[0x18];
6488
6489         u8         reserved_5[0x80];
6490 };
6491
6492 struct mlx5_ifc_plib_reg_bits {
6493         u8         reserved_0[0x8];
6494         u8         local_port[0x8];
6495         u8         reserved_1[0x8];
6496         u8         ib_port[0x8];
6497
6498         u8         reserved_2[0x60];
6499 };
6500
6501 struct mlx5_ifc_plbf_reg_bits {
6502         u8         reserved_0[0x8];
6503         u8         local_port[0x8];
6504         u8         reserved_1[0xd];
6505         u8         lbf_mode[0x3];
6506
6507         u8         reserved_2[0x20];
6508 };
6509
6510 struct mlx5_ifc_pipg_reg_bits {
6511         u8         reserved_0[0x8];
6512         u8         local_port[0x8];
6513         u8         reserved_1[0x10];
6514
6515         u8         dic[0x1];
6516         u8         reserved_2[0x19];
6517         u8         ipg[0x4];
6518         u8         reserved_3[0x2];
6519 };
6520
6521 struct mlx5_ifc_pifr_reg_bits {
6522         u8         reserved_0[0x8];
6523         u8         local_port[0x8];
6524         u8         reserved_1[0x10];
6525
6526         u8         reserved_2[0xe0];
6527
6528         u8         port_filter[8][0x20];
6529
6530         u8         port_filter_update_en[8][0x20];
6531 };
6532
6533 struct mlx5_ifc_pfcc_reg_bits {
6534         u8         reserved_0[0x8];
6535         u8         local_port[0x8];
6536         u8         reserved_1[0x10];
6537
6538         u8         ppan[0x4];
6539         u8         reserved_2[0x4];
6540         u8         prio_mask_tx[0x8];
6541         u8         reserved_3[0x8];
6542         u8         prio_mask_rx[0x8];
6543
6544         u8         pptx[0x1];
6545         u8         aptx[0x1];
6546         u8         reserved_4[0x6];
6547         u8         pfctx[0x8];
6548         u8         reserved_5[0x10];
6549
6550         u8         pprx[0x1];
6551         u8         aprx[0x1];
6552         u8         reserved_6[0x6];
6553         u8         pfcrx[0x8];
6554         u8         reserved_7[0x10];
6555
6556         u8         reserved_8[0x80];
6557 };
6558
6559 struct mlx5_ifc_pelc_reg_bits {
6560         u8         op[0x4];
6561         u8         reserved_0[0x4];
6562         u8         local_port[0x8];
6563         u8         reserved_1[0x10];
6564
6565         u8         op_admin[0x8];
6566         u8         op_capability[0x8];
6567         u8         op_request[0x8];
6568         u8         op_active[0x8];
6569
6570         u8         admin[0x40];
6571
6572         u8         capability[0x40];
6573
6574         u8         request[0x40];
6575
6576         u8         active[0x40];
6577
6578         u8         reserved_2[0x80];
6579 };
6580
6581 struct mlx5_ifc_peir_reg_bits {
6582         u8         reserved_0[0x8];
6583         u8         local_port[0x8];
6584         u8         reserved_1[0x10];
6585
6586         u8         reserved_2[0xc];
6587         u8         error_count[0x4];
6588         u8         reserved_3[0x10];
6589
6590         u8         reserved_4[0xc];
6591         u8         lane[0x4];
6592         u8         reserved_5[0x8];
6593         u8         error_type[0x8];
6594 };
6595
6596 struct mlx5_ifc_pcap_reg_bits {
6597         u8         reserved_0[0x8];
6598         u8         local_port[0x8];
6599         u8         reserved_1[0x10];
6600
6601         u8         port_capability_mask[4][0x20];
6602 };
6603
6604 struct mlx5_ifc_paos_reg_bits {
6605         u8         swid[0x8];
6606         u8         local_port[0x8];
6607         u8         reserved_0[0x4];
6608         u8         admin_status[0x4];
6609         u8         reserved_1[0x4];
6610         u8         oper_status[0x4];
6611
6612         u8         ase[0x1];
6613         u8         ee[0x1];
6614         u8         reserved_2[0x1c];
6615         u8         e[0x2];
6616
6617         u8         reserved_3[0x40];
6618 };
6619
6620 struct mlx5_ifc_pamp_reg_bits {
6621         u8         reserved_0[0x8];
6622         u8         opamp_group[0x8];
6623         u8         reserved_1[0xc];
6624         u8         opamp_group_type[0x4];
6625
6626         u8         start_index[0x10];
6627         u8         reserved_2[0x4];
6628         u8         num_of_indices[0xc];
6629
6630         u8         index_data[18][0x10];
6631 };
6632
6633 struct mlx5_ifc_lane_2_module_mapping_bits {
6634         u8         reserved_0[0x6];
6635         u8         rx_lane[0x2];
6636         u8         reserved_1[0x6];
6637         u8         tx_lane[0x2];
6638         u8         reserved_2[0x8];
6639         u8         module[0x8];
6640 };
6641
6642 struct mlx5_ifc_bufferx_reg_bits {
6643         u8         reserved_0[0x6];
6644         u8         lossy[0x1];
6645         u8         epsb[0x1];
6646         u8         reserved_1[0xc];
6647         u8         size[0xc];
6648
6649         u8         xoff_threshold[0x10];
6650         u8         xon_threshold[0x10];
6651 };
6652
6653 struct mlx5_ifc_set_node_in_bits {
6654         u8         node_description[64][0x8];
6655 };
6656
6657 struct mlx5_ifc_register_power_settings_bits {
6658         u8         reserved_0[0x18];
6659         u8         power_settings_level[0x8];
6660
6661         u8         reserved_1[0x60];
6662 };
6663
6664 struct mlx5_ifc_register_host_endianness_bits {
6665         u8         he[0x1];
6666         u8         reserved_0[0x1f];
6667
6668         u8         reserved_1[0x60];
6669 };
6670
6671 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6672         u8         reserved_0[0x20];
6673
6674         u8         mkey[0x20];
6675
6676         u8         addressh_63_32[0x20];
6677
6678         u8         addressl_31_0[0x20];
6679 };
6680
6681 struct mlx5_ifc_ud_adrs_vector_bits {
6682         u8         dc_key[0x40];
6683
6684         u8         ext[0x1];
6685         u8         reserved_0[0x7];
6686         u8         destination_qp_dct[0x18];
6687
6688         u8         static_rate[0x4];
6689         u8         sl_eth_prio[0x4];
6690         u8         fl[0x1];
6691         u8         mlid[0x7];
6692         u8         rlid_udp_sport[0x10];
6693
6694         u8         reserved_1[0x20];
6695
6696         u8         rmac_47_16[0x20];
6697
6698         u8         rmac_15_0[0x10];
6699         u8         tclass[0x8];
6700         u8         hop_limit[0x8];
6701
6702         u8         reserved_2[0x1];
6703         u8         grh[0x1];
6704         u8         reserved_3[0x2];
6705         u8         src_addr_index[0x8];
6706         u8         flow_label[0x14];
6707
6708         u8         rgid_rip[16][0x8];
6709 };
6710
6711 struct mlx5_ifc_pages_req_event_bits {
6712         u8         reserved_0[0x10];
6713         u8         function_id[0x10];
6714
6715         u8         num_pages[0x20];
6716
6717         u8         reserved_1[0xa0];
6718 };
6719
6720 struct mlx5_ifc_eqe_bits {
6721         u8         reserved_0[0x8];
6722         u8         event_type[0x8];
6723         u8         reserved_1[0x8];
6724         u8         event_sub_type[0x8];
6725
6726         u8         reserved_2[0xe0];
6727
6728         union mlx5_ifc_event_auto_bits event_data;
6729
6730         u8         reserved_3[0x10];
6731         u8         signature[0x8];
6732         u8         reserved_4[0x7];
6733         u8         owner[0x1];
6734 };
6735
6736 enum {
6737         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6738 };
6739
6740 struct mlx5_ifc_cmd_queue_entry_bits {
6741         u8         type[0x8];
6742         u8         reserved_0[0x18];
6743
6744         u8         input_length[0x20];
6745
6746         u8         input_mailbox_pointer_63_32[0x20];
6747
6748         u8         input_mailbox_pointer_31_9[0x17];
6749         u8         reserved_1[0x9];
6750
6751         u8         command_input_inline_data[16][0x8];
6752
6753         u8         command_output_inline_data[16][0x8];
6754
6755         u8         output_mailbox_pointer_63_32[0x20];
6756
6757         u8         output_mailbox_pointer_31_9[0x17];
6758         u8         reserved_2[0x9];
6759
6760         u8         output_length[0x20];
6761
6762         u8         token[0x8];
6763         u8         signature[0x8];
6764         u8         reserved_3[0x8];
6765         u8         status[0x7];
6766         u8         ownership[0x1];
6767 };
6768
6769 struct mlx5_ifc_cmd_out_bits {
6770         u8         status[0x8];
6771         u8         reserved_0[0x18];
6772
6773         u8         syndrome[0x20];
6774
6775         u8         command_output[0x20];
6776 };
6777
6778 struct mlx5_ifc_cmd_in_bits {
6779         u8         opcode[0x10];
6780         u8         reserved_0[0x10];
6781
6782         u8         reserved_1[0x10];
6783         u8         op_mod[0x10];
6784
6785         u8         command[0][0x20];
6786 };
6787
6788 struct mlx5_ifc_cmd_if_box_bits {
6789         u8         mailbox_data[512][0x8];
6790
6791         u8         reserved_0[0x180];
6792
6793         u8         next_pointer_63_32[0x20];
6794
6795         u8         next_pointer_31_10[0x16];
6796         u8         reserved_1[0xa];
6797
6798         u8         block_number[0x20];
6799
6800         u8         reserved_2[0x8];
6801         u8         token[0x8];
6802         u8         ctrl_signature[0x8];
6803         u8         signature[0x8];
6804 };
6805
6806 struct mlx5_ifc_mtt_bits {
6807         u8         ptag_63_32[0x20];
6808
6809         u8         ptag_31_8[0x18];
6810         u8         reserved_0[0x6];
6811         u8         wr_en[0x1];
6812         u8         rd_en[0x1];
6813 };
6814
6815 enum {
6816         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
6817         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
6818         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
6819 };
6820
6821 enum {
6822         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
6823         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
6824         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
6825 };
6826
6827 enum {
6828         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
6829         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
6830         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
6831         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
6832         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
6833         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
6834         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
6835         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
6836         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
6837         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
6838         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
6839 };
6840
6841 struct mlx5_ifc_initial_seg_bits {
6842         u8         fw_rev_minor[0x10];
6843         u8         fw_rev_major[0x10];
6844
6845         u8         cmd_interface_rev[0x10];
6846         u8         fw_rev_subminor[0x10];
6847
6848         u8         reserved_0[0x40];
6849
6850         u8         cmdq_phy_addr_63_32[0x20];
6851
6852         u8         cmdq_phy_addr_31_12[0x14];
6853         u8         reserved_1[0x2];
6854         u8         nic_interface[0x2];
6855         u8         log_cmdq_size[0x4];
6856         u8         log_cmdq_stride[0x4];
6857
6858         u8         command_doorbell_vector[0x20];
6859
6860         u8         reserved_2[0xf00];
6861
6862         u8         initializing[0x1];
6863         u8         reserved_3[0x4];
6864         u8         nic_interface_supported[0x3];
6865         u8         reserved_4[0x18];
6866
6867         struct mlx5_ifc_health_buffer_bits health_buffer;
6868
6869         u8         no_dram_nic_offset[0x20];
6870
6871         u8         reserved_5[0x6e40];
6872
6873         u8         reserved_6[0x1f];
6874         u8         clear_int[0x1];
6875
6876         u8         health_syndrome[0x8];
6877         u8         health_counter[0x18];
6878
6879         u8         reserved_7[0x17fc0];
6880 };
6881
6882 union mlx5_ifc_ports_control_registers_document_bits {
6883         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6884         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6885         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6886         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6887         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6888         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6889         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6890         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6891         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6892         struct mlx5_ifc_pamp_reg_bits pamp_reg;
6893         struct mlx5_ifc_paos_reg_bits paos_reg;
6894         struct mlx5_ifc_pcap_reg_bits pcap_reg;
6895         struct mlx5_ifc_peir_reg_bits peir_reg;
6896         struct mlx5_ifc_pelc_reg_bits pelc_reg;
6897         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6898         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6899         struct mlx5_ifc_pifr_reg_bits pifr_reg;
6900         struct mlx5_ifc_pipg_reg_bits pipg_reg;
6901         struct mlx5_ifc_plbf_reg_bits plbf_reg;
6902         struct mlx5_ifc_plib_reg_bits plib_reg;
6903         struct mlx5_ifc_plpc_reg_bits plpc_reg;
6904         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6905         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6906         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6907         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6908         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6909         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6910         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6911         struct mlx5_ifc_ppad_reg_bits ppad_reg;
6912         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6913         struct mlx5_ifc_pplm_reg_bits pplm_reg;
6914         struct mlx5_ifc_pplr_reg_bits pplr_reg;
6915         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6916         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6917         struct mlx5_ifc_pspa_reg_bits pspa_reg;
6918         struct mlx5_ifc_ptas_reg_bits ptas_reg;
6919         struct mlx5_ifc_ptys_reg_bits ptys_reg;
6920         struct mlx5_ifc_pude_reg_bits pude_reg;
6921         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6922         struct mlx5_ifc_slrg_reg_bits slrg_reg;
6923         struct mlx5_ifc_sltp_reg_bits sltp_reg;
6924         u8         reserved_0[0x60e0];
6925 };
6926
6927 union mlx5_ifc_debug_enhancements_document_bits {
6928         struct mlx5_ifc_health_buffer_bits health_buffer;
6929         u8         reserved_0[0x200];
6930 };
6931
6932 union mlx5_ifc_uplink_pci_interface_document_bits {
6933         struct mlx5_ifc_initial_seg_bits initial_seg;
6934         u8         reserved_0[0x20060];
6935 };
6936
6937 #endif /* MLX5_IFC_H */