include/linux/qed/common_hsi.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef __COMMON_HSI__
  10 #define __COMMON_HSI__
  11
  12 #define CORE_SPQE_PAGE_SIZE_BYTES                       4096
  13
  14 #define X_FINAL_CLEANUP_AGG_INT 1
  15
  16 #define FW_MAJOR_VERSION        8
  17 #define FW_MINOR_VERSION        7
  18 #define FW_REVISION_VERSION     3
  19 #define FW_ENGINEERING_VERSION  0
  20
  21 /***********************/
  22 /* COMMON HW CONSTANTS */
  23 /***********************/
  24
  25 /* PCI functions */
  26 #define MAX_NUM_PORTS_K2        (4)
  27 #define MAX_NUM_PORTS_BB        (2)
  28 #define MAX_NUM_PORTS           (MAX_NUM_PORTS_K2)
  29
  30 #define MAX_NUM_PFS_K2  (16)
  31 #define MAX_NUM_PFS_BB  (8)
  32 #define MAX_NUM_PFS     (MAX_NUM_PFS_K2)
  33 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
  34
  35 #define MAX_NUM_VFS_K2  (192)
  36 #define MAX_NUM_VFS_BB  (120)
  37 #define MAX_NUM_VFS     (MAX_NUM_VFS_K2)
  38
  39 #define MAX_NUM_FUNCTIONS_BB    (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
  40 #define MAX_NUM_FUNCTIONS       (MAX_NUM_PFS + MAX_NUM_VFS)
  41
  42 #define MAX_FUNCTION_NUMBER_BB  (MAX_NUM_PFS + MAX_NUM_VFS_BB)
  43 #define MAX_FUNCTION_NUMBER     (MAX_NUM_PFS + MAX_NUM_VFS)
  44
  45 #define MAX_NUM_VPORTS_K2       (208)
  46 #define MAX_NUM_VPORTS_BB       (160)
  47 #define MAX_NUM_VPORTS          (MAX_NUM_VPORTS_K2)
  48
  49 #define MAX_NUM_L2_QUEUES_K2    (320)
  50 #define MAX_NUM_L2_QUEUES_BB    (256)
  51 #define MAX_NUM_L2_QUEUES       (MAX_NUM_L2_QUEUES_K2)
  52
  53 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
  54 #define NUM_PHYS_TCS_4PORT_K2   (4)
  55 #define NUM_OF_PHYS_TCS         (8)
  56
  57 #define NUM_TCS_4PORT_K2        (NUM_PHYS_TCS_4PORT_K2 + 1)
  58 #define NUM_OF_TCS              (NUM_OF_PHYS_TCS + 1)
  59
  60 #define LB_TC                   (NUM_OF_PHYS_TCS)
  61
  62 /* Num of possible traffic priority values */
  63 #define NUM_OF_PRIO             (8)
  64
  65 #define MAX_NUM_VOQS_K2         (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
  66 #define MAX_NUM_VOQS_BB         (NUM_OF_TCS * MAX_NUM_PORTS_BB)
  67 #define MAX_NUM_VOQS            (MAX_NUM_VOQS_K2)
  68 #define MAX_PHYS_VOQS           (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
  69
  70 /* CIDs */
  71 #define NUM_OF_CONNECTION_TYPES (8)
  72 #define NUM_OF_LCIDS            (320)
  73 #define NUM_OF_LTIDS            (320)
  74
  75 /*****************/
  76 /* CDU CONSTANTS */
  77 /*****************/
  78
  79 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT              (17)
  80 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK             (0x1ffff)
  81
  82 /*****************/
  83 /* DQ CONSTANTS  */
  84 /*****************/
  85
  86 /* DEMS */
  87 #define DQ_DEMS_LEGACY                  0
  88
  89 /* XCM agg val selection */
  90 #define DQ_XCM_AGG_VAL_SEL_WORD2  0
  91 #define DQ_XCM_AGG_VAL_SEL_WORD3  1
  92 #define DQ_XCM_AGG_VAL_SEL_WORD4  2
  93 #define DQ_XCM_AGG_VAL_SEL_WORD5  3
  94 #define DQ_XCM_AGG_VAL_SEL_REG3   4
  95 #define DQ_XCM_AGG_VAL_SEL_REG4   5
  96 #define DQ_XCM_AGG_VAL_SEL_REG5   6
  97 #define DQ_XCM_AGG_VAL_SEL_REG6   7
  98
  99 /* XCM agg val selection */
 100 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \
 101         DQ_XCM_AGG_VAL_SEL_WORD2
 102 #define DQ_XCM_ETH_TX_BD_CONS_CMD \
 103         DQ_XCM_AGG_VAL_SEL_WORD3
 104 #define DQ_XCM_CORE_TX_BD_CONS_CMD \
 105         DQ_XCM_AGG_VAL_SEL_WORD3
 106 #define DQ_XCM_ETH_TX_BD_PROD_CMD \
 107         DQ_XCM_AGG_VAL_SEL_WORD4
 108 #define DQ_XCM_CORE_TX_BD_PROD_CMD \
 109         DQ_XCM_AGG_VAL_SEL_WORD4
 110 #define DQ_XCM_CORE_SPQ_PROD_CMD \
 111         DQ_XCM_AGG_VAL_SEL_WORD4
 112 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD            DQ_XCM_AGG_VAL_SEL_WORD5
 113
 114 /* XCM agg counter flag selection */
 115 #define DQ_XCM_AGG_FLG_SHIFT_BIT14  0
 116 #define DQ_XCM_AGG_FLG_SHIFT_BIT15  1
 117 #define DQ_XCM_AGG_FLG_SHIFT_CF12   2
 118 #define DQ_XCM_AGG_FLG_SHIFT_CF13   3
 119 #define DQ_XCM_AGG_FLG_SHIFT_CF18   4
 120 #define DQ_XCM_AGG_FLG_SHIFT_CF19   5
 121 #define DQ_XCM_AGG_FLG_SHIFT_CF22   6
 122 #define DQ_XCM_AGG_FLG_SHIFT_CF23   7
 123
 124 /* XCM agg counter flag selection */
 125 #define DQ_XCM_ETH_DQ_CF_CMD            (1 << \
 126                                         DQ_XCM_AGG_FLG_SHIFT_CF18)
 127 #define DQ_XCM_CORE_DQ_CF_CMD           (1 << \
 128                                         DQ_XCM_AGG_FLG_SHIFT_CF18)
 129 #define DQ_XCM_ETH_TERMINATE_CMD        (1 << \
 130                                         DQ_XCM_AGG_FLG_SHIFT_CF19)
 131 #define DQ_XCM_CORE_TERMINATE_CMD       (1 << \
 132                                         DQ_XCM_AGG_FLG_SHIFT_CF19)
 133 #define DQ_XCM_ETH_SLOW_PATH_CMD        (1 << \
 134                                         DQ_XCM_AGG_FLG_SHIFT_CF22)
 135 #define DQ_XCM_CORE_SLOW_PATH_CMD       (1 << \
 136                                         DQ_XCM_AGG_FLG_SHIFT_CF22)
 137 #define DQ_XCM_ETH_TPH_EN_CMD           (1 << \
 138                                         DQ_XCM_AGG_FLG_SHIFT_CF23)
 139
 140 /*****************/
 141 /* QM CONSTANTS  */
 142 /*****************/
 143
 144 /* number of TX queues in the QM */
 145 #define MAX_QM_TX_QUEUES_K2     512
 146 #define MAX_QM_TX_QUEUES_BB     448
 147 #define MAX_QM_TX_QUEUES        MAX_QM_TX_QUEUES_K2
 148
 149 /* number of Other queues in the QM */
 150 #define MAX_QM_OTHER_QUEUES_BB  64
 151 #define MAX_QM_OTHER_QUEUES_K2  128
 152 #define MAX_QM_OTHER_QUEUES     MAX_QM_OTHER_QUEUES_K2
 153
 154 /* number of queues in a PF queue group */
 155 #define QM_PF_QUEUE_GROUP_SIZE  8
 156
 157 /* the size of a single queue element in bytes */
 158 #define QM_PQ_ELEMENT_SIZE                      4
 159
 160 /* base number of Tx PQs in the CM PQ representation.
 161  * should be used when storing PQ IDs in CM PQ registers and context
 162  */
 163 #define CM_TX_PQ_BASE   0x200
 164
 165 /* QM registers data */
 166 #define QM_LINE_CRD_REG_WIDTH           16
 167 #define QM_LINE_CRD_REG_SIGN_BIT        (1 << (QM_LINE_CRD_REG_WIDTH - 1))
 168 #define QM_BYTE_CRD_REG_WIDTH           24
 169 #define QM_BYTE_CRD_REG_SIGN_BIT        (1 << (QM_BYTE_CRD_REG_WIDTH - 1))
 170 #define QM_WFQ_CRD_REG_WIDTH            32
 171 #define QM_WFQ_CRD_REG_SIGN_BIT         (1 << (QM_WFQ_CRD_REG_WIDTH - 1))
 172 #define QM_RL_CRD_REG_WIDTH             32
 173 #define QM_RL_CRD_REG_SIGN_BIT          (1 << (QM_RL_CRD_REG_WIDTH - 1))
 174
 175 /*****************/
 176 /* CAU CONSTANTS */
 177 /*****************/
 178
 179 #define CAU_FSM_ETH_RX  0
 180 #define CAU_FSM_ETH_TX  1
 181
 182 /* Number of Protocol Indices per Status Block */
 183 #define PIS_PER_SB    12
 184
 185 #define CAU_HC_STOPPED_STATE    3
 186 #define CAU_HC_DISABLE_STATE    4
 187 #define CAU_HC_ENABLE_STATE     0
 188
 189 /*****************/
 190 /* IGU CONSTANTS */
 191 /*****************/
 192
 193 #define MAX_SB_PER_PATH_K2      (368)
 194 #define MAX_SB_PER_PATH_BB      (288)
 195 #define MAX_TOT_SB_PER_PATH \
 196         MAX_SB_PER_PATH_K2
 197
 198 #define MAX_SB_PER_PF_MIMD      129
 199 #define MAX_SB_PER_PF_SIMD      64
 200 #define MAX_SB_PER_VF           64
 201
 202 /* Memory addresses on the BAR for the IGU Sub Block */
 203 #define IGU_MEM_BASE                    0x0000
 204
 205 #define IGU_MEM_MSIX_BASE               0x0000
 206 #define IGU_MEM_MSIX_UPPER              0x0101
 207 #define IGU_MEM_MSIX_RESERVED_UPPER     0x01ff
 208
 209 #define IGU_MEM_PBA_MSIX_BASE           0x0200
 210 #define IGU_MEM_PBA_MSIX_UPPER          0x0202
 211 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
 212
 213 #define IGU_CMD_INT_ACK_BASE            0x0400
 214 #define IGU_CMD_INT_ACK_UPPER           (IGU_CMD_INT_ACK_BASE + \
 215                                          MAX_TOT_SB_PER_PATH -  \
 216                                          1)
 217 #define IGU_CMD_INT_ACK_RESERVED_UPPER  0x05ff
 218
 219 #define IGU_CMD_ATTN_BIT_UPD_UPPER      0x05f0
 220 #define IGU_CMD_ATTN_BIT_SET_UPPER      0x05f1
 221 #define IGU_CMD_ATTN_BIT_CLR_UPPER      0x05f2
 222
 223 #define IGU_REG_SISR_MDPC_WMASK_UPPER           0x05f3
 224 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER       0x05f4
 225 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER       0x05f5
 226 #define IGU_REG_SISR_MDPC_WOMASK_UPPER          0x05f6
 227
 228 #define IGU_CMD_PROD_UPD_BASE                   0x0600
 229 #define IGU_CMD_PROD_UPD_UPPER                  (IGU_CMD_PROD_UPD_BASE +\
 230                                                  MAX_TOT_SB_PER_PATH - \
 231                                                  1)
 232 #define IGU_CMD_PROD_UPD_RESERVED_UPPER         0x07ff
 233
 234 /*****************/
 235 /* PXP CONSTANTS */
 236 /*****************/
 237
 238 /* PTT and GTT */
 239 #define PXP_NUM_PF_WINDOWS              12
 240 #define PXP_PER_PF_ENTRY_SIZE           8
 241 #define PXP_NUM_GLOBAL_WINDOWS          243
 242 #define PXP_GLOBAL_ENTRY_SIZE           4
 243 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4
 244 #define PXP_PF_WINDOW_ADMIN_START       0
 245 #define PXP_PF_WINDOW_ADMIN_LENGTH      0x1000
 246 #define PXP_PF_WINDOW_ADMIN_END         (PXP_PF_WINDOW_ADMIN_START + \
 247                                          PXP_PF_WINDOW_ADMIN_LENGTH - 1)
 248 #define PXP_PF_WINDOW_ADMIN_PER_PF_START        0
 249 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH       (PXP_NUM_PF_WINDOWS * \
 250                                                  PXP_PER_PF_ENTRY_SIZE)
 251 #define PXP_PF_WINDOW_ADMIN_PER_PF_END  (PXP_PF_WINDOW_ADMIN_PER_PF_START + \
 252                                          PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
 253 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START        0x200
 254 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH       (PXP_NUM_GLOBAL_WINDOWS * \
 255                                                  PXP_GLOBAL_ENTRY_SIZE)
 256 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \
 257                 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \
 258                  PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
 259 #define PXP_PF_GLOBAL_PRETEND_ADDR      0x1f0
 260 #define PXP_PF_ME_OPAQUE_MASK_ADDR      0xf4
 261 #define PXP_PF_ME_OPAQUE_ADDR           0x1f8
 262 #define PXP_PF_ME_CONCRETE_ADDR         0x1fc
 263
 264 #define PXP_EXTERNAL_BAR_PF_WINDOW_START        0x1000
 265 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM          PXP_NUM_PF_WINDOWS
 266 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE  0x1000
 267 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \
 268         (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \
 269          PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)
 270 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \
 271         (PXP_EXTERNAL_BAR_PF_WINDOW_START + \
 272          PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)
 273
 274 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \
 275         (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)
 276 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM              PXP_NUM_GLOBAL_WINDOWS
 277 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE      0x1000
 278 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \
 279         (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \
 280          PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)
 281 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \
 282         (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
 283          PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
 284
 285 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN  12
 286 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
 287
 288 #define PXP_VF_BAR0_START_IGU                   0
 289 #define PXP_VF_BAR0_IGU_LENGTH                  0x3000
 290 #define PXP_VF_BAR0_END_IGU                     (PXP_VF_BAR0_START_IGU + \
 291                                                  PXP_VF_BAR0_IGU_LENGTH - 1)
 292
 293 #define PXP_VF_BAR0_START_DQ                    0x3000
 294 #define PXP_VF_BAR0_DQ_LENGTH                   0x200
 295 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET            0
 296 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS           (PXP_VF_BAR0_START_DQ + \
 297                                                  PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
 298 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS         (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
 299                                                  + 4)
 300 #define PXP_VF_BAR0_END_DQ                      (PXP_VF_BAR0_START_DQ + \
 301                                                  PXP_VF_BAR0_DQ_LENGTH - 1)
 302
 303 #define PXP_VF_BAR0_START_TSDM_ZONE_B           0x3200
 304 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B           0x200
 305 #define PXP_VF_BAR0_END_TSDM_ZONE_B             (PXP_VF_BAR0_START_TSDM_ZONE_B \
 306                                                  +                             \
 307                                                  PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
 308                                                  - 1)
 309
 310 #define PXP_VF_BAR0_START_MSDM_ZONE_B           0x3400
 311 #define PXP_VF_BAR0_END_MSDM_ZONE_B             (PXP_VF_BAR0_START_MSDM_ZONE_B \
 312                                                  +                             \
 313                                                  PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
 314                                                  - 1)
 315
 316 #define PXP_VF_BAR0_START_USDM_ZONE_B           0x3600
 317 #define PXP_VF_BAR0_END_USDM_ZONE_B             (PXP_VF_BAR0_START_USDM_ZONE_B \
 318                                                  +                             \
 319                                                  PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
 320                                                  - 1)
 321
 322 #define PXP_VF_BAR0_START_XSDM_ZONE_B           0x3800
 323 #define PXP_VF_BAR0_END_XSDM_ZONE_B             (PXP_VF_BAR0_START_XSDM_ZONE_B \
 324                                                  +                             \
 325                                                  PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
 326                                                  - 1)
 327
 328 #define PXP_VF_BAR0_START_YSDM_ZONE_B           0x3a00
 329 #define PXP_VF_BAR0_END_YSDM_ZONE_B             (PXP_VF_BAR0_START_YSDM_ZONE_B \
 330                                                  +                             \
 331                                                  PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
 332                                                  - 1)
 333
 334 #define PXP_VF_BAR0_START_PSDM_ZONE_B           0x3c00
 335 #define PXP_VF_BAR0_END_PSDM_ZONE_B             (PXP_VF_BAR0_START_PSDM_ZONE_B \
 336                                                  +                             \
 337                                                  PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
 338                                                  - 1)
 339
 340 #define PXP_VF_BAR0_START_SDM_ZONE_A            0x4000
 341 #define PXP_VF_BAR0_END_SDM_ZONE_A              0x10000
 342
 343 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH           32
 344
 345 /* ILT Records */
 346 #define PXP_NUM_ILT_RECORDS_BB 7600
 347 #define PXP_NUM_ILT_RECORDS_K2 11000
 348 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
 349
 350 #define SDM_COMP_TYPE_NONE              0
 351 #define SDM_COMP_TYPE_WAKE_THREAD       1
 352 #define SDM_COMP_TYPE_AGG_INT           2
 353 #define SDM_COMP_TYPE_CM                3
 354 #define SDM_COMP_TYPE_LOADER            4
 355 #define SDM_COMP_TYPE_PXP               5
 356 #define SDM_COMP_TYPE_INDICATE_ERROR    6
 357 #define SDM_COMP_TYPE_RELEASE_THREAD    7
 358 #define SDM_COMP_TYPE_RAM               8
 359
 360 /******************/
 361 /* PBF CONSTANTS  */
 362 /******************/
 363
 364 /* Number of PBF command queue lines. Each line is 32B. */
 365 #define PBF_MAX_CMD_LINES 3328
 366
 367 /* Number of BTB blocks. Each block is 256B. */
 368 #define BTB_MAX_BLOCKS 1440
 369
 370 /*****************/
 371 /* PRS CONSTANTS */
 372 /*****************/
 373
 374 /* Async data KCQ CQE */
 375 struct async_data {
 376         __le32  cid;
 377         __le16  itid;
 378         u8      error_code;
 379         u8      fw_debug_param;
 380 };
 381
 382 struct regpair {
 383         __le32  lo;
 384         __le32  hi;
 385 };
 386
 387 struct vf_pf_channel_eqe_data {
 388         struct regpair msg_addr;
 389 };
 390
 391 /* Event Data Union */
 392 union event_ring_data {
 393         u8                              bytes[8];
 394         struct vf_pf_channel_eqe_data   vf_pf_channel;
 395         struct async_data               async_info;
 396 };
 397
 398 /* Event Ring Entry */
 399 struct event_ring_entry {
 400         u8                      protocol_id;
 401         u8                      opcode;
 402         __le16                  reserved0;
 403         __le16                  echo;
 404         u8                      fw_return_code;
 405         u8                      flags;
 406 #define EVENT_RING_ENTRY_ASYNC_MASK      0x1
 407 #define EVENT_RING_ENTRY_ASYNC_SHIFT     0
 408 #define EVENT_RING_ENTRY_RESERVED1_MASK  0x7F
 409 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
 410         union event_ring_data   data;
 411 };
 412
 413 /* Multi function mode */
 414 enum mf_mode {
 415         ERROR_MODE /* Unsupported mode */,
 416         MF_OVLAN,
 417         MF_NPAR,
 418         MAX_MF_MODE
 419 };
 420
 421 /* Per-protocol connection types */
 422 enum protocol_type {
 423         PROTOCOLID_RESERVED1,
 424         PROTOCOLID_RESERVED2,
 425         PROTOCOLID_RESERVED3,
 426         PROTOCOLID_CORE,
 427         PROTOCOLID_ETH,
 428         PROTOCOLID_RESERVED4,
 429         PROTOCOLID_RESERVED5,
 430         PROTOCOLID_PREROCE,
 431         PROTOCOLID_COMMON,
 432         PROTOCOLID_RESERVED6,
 433         MAX_PROTOCOL_TYPE
 434 };
 435
 436 /* status block structure */
 437 struct cau_pi_entry {
 438         u32 prod;
 439 #define CAU_PI_ENTRY_PROD_VAL_MASK    0xFFFF
 440 #define CAU_PI_ENTRY_PROD_VAL_SHIFT   0
 441 #define CAU_PI_ENTRY_PI_TIMESET_MASK  0x7F
 442 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
 443 #define CAU_PI_ENTRY_FSM_SEL_MASK     0x1
 444 #define CAU_PI_ENTRY_FSM_SEL_SHIFT    23
 445 #define CAU_PI_ENTRY_RESERVED_MASK    0xFF
 446 #define CAU_PI_ENTRY_RESERVED_SHIFT   24
 447 };
 448
 449 /* status block structure */
 450 struct cau_sb_entry {
 451         u32 data;
 452 #define CAU_SB_ENTRY_SB_PROD_MASK      0xFFFFFF
 453 #define CAU_SB_ENTRY_SB_PROD_SHIFT     0
 454 #define CAU_SB_ENTRY_STATE0_MASK       0xF
 455 #define CAU_SB_ENTRY_STATE0_SHIFT      24
 456 #define CAU_SB_ENTRY_STATE1_MASK       0xF
 457 #define CAU_SB_ENTRY_STATE1_SHIFT      28
 458         u32 params;
 459 #define CAU_SB_ENTRY_SB_TIMESET0_MASK  0x7F
 460 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
 461 #define CAU_SB_ENTRY_SB_TIMESET1_MASK  0x7F
 462 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
 463 #define CAU_SB_ENTRY_TIMER_RES0_MASK   0x3
 464 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT  14
 465 #define CAU_SB_ENTRY_TIMER_RES1_MASK   0x3
 466 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT  16
 467 #define CAU_SB_ENTRY_VF_NUMBER_MASK    0xFF
 468 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT   18
 469 #define CAU_SB_ENTRY_VF_VALID_MASK     0x1
 470 #define CAU_SB_ENTRY_VF_VALID_SHIFT    26
 471 #define CAU_SB_ENTRY_PF_NUMBER_MASK    0xF
 472 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT   27
 473 #define CAU_SB_ENTRY_TPH_MASK          0x1
 474 #define CAU_SB_ENTRY_TPH_SHIFT         31
 475 };
 476
 477 /* core doorbell data */
 478 struct core_db_data {
 479         u8 params;
 480 #define CORE_DB_DATA_DEST_MASK         0x3
 481 #define CORE_DB_DATA_DEST_SHIFT        0
 482 #define CORE_DB_DATA_AGG_CMD_MASK      0x3
 483 #define CORE_DB_DATA_AGG_CMD_SHIFT     2
 484 #define CORE_DB_DATA_BYPASS_EN_MASK    0x1
 485 #define CORE_DB_DATA_BYPASS_EN_SHIFT   4
 486 #define CORE_DB_DATA_RESERVED_MASK     0x1
 487 #define CORE_DB_DATA_RESERVED_SHIFT    5
 488 #define CORE_DB_DATA_AGG_VAL_SEL_MASK  0x3
 489 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
 490         u8      agg_flags;
 491         __le16  spq_prod;
 492 };
 493
 494 /* Enum of doorbell aggregative command selection */
 495 enum db_agg_cmd_sel {
 496         DB_AGG_CMD_NOP,
 497         DB_AGG_CMD_SET,
 498         DB_AGG_CMD_ADD,
 499         DB_AGG_CMD_MAX,
 500         MAX_DB_AGG_CMD_SEL
 501 };
 502
 503 /* Enum of doorbell destination */
 504 enum db_dest {
 505         DB_DEST_XCM,
 506         DB_DEST_UCM,
 507         DB_DEST_TCM,
 508         DB_NUM_DESTINATIONS,
 509         MAX_DB_DEST
 510 };
 511
 512 /* Structure for doorbell address, in legacy mode */
 513 struct db_legacy_addr {
 514         __le32 addr;
 515 #define DB_LEGACY_ADDR_RESERVED0_MASK  0x3
 516 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
 517 #define DB_LEGACY_ADDR_DEMS_MASK       0x7
 518 #define DB_LEGACY_ADDR_DEMS_SHIFT      2
 519 #define DB_LEGACY_ADDR_ICID_MASK       0x7FFFFFF
 520 #define DB_LEGACY_ADDR_ICID_SHIFT      5
 521 };
 522
 523 /* Igu interrupt command */
 524 enum igu_int_cmd {
 525         IGU_INT_ENABLE  = 0,
 526         IGU_INT_DISABLE = 1,
 527         IGU_INT_NOP     = 2,
 528         IGU_INT_NOP2    = 3,
 529         MAX_IGU_INT_CMD
 530 };
 531
 532 /* IGU producer or consumer update command */
 533 struct igu_prod_cons_update {
 534         u32 sb_id_and_flags;
 535 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK        0xFFFFFF
 536 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT       0
 537 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK     0x1
 538 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT    24
 539 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK      0x3
 540 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT     25
 541 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK  0x1
 542 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
 543 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK      0x1
 544 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT     28
 545 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK       0x3
 546 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT      29
 547 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK    0x1
 548 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT   31
 549         u32 reserved1;
 550 };
 551
 552 /* Igu segments access for default status block only */
 553 enum igu_seg_access {
 554         IGU_SEG_ACCESS_REG      = 0,
 555         IGU_SEG_ACCESS_ATTN     = 1,
 556         MAX_IGU_SEG_ACCESS
 557 };
 558
 559 struct parsing_and_err_flags {
 560         __le16 flags;
 561 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK                      0x3
 562 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT                     0
 563 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK                  0x3
 564 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT                 2
 565 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK                    0x1
 566 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT                   4
 567 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK               0x1
 568 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT              5
 569 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK        0x1
 570 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT       6
 571 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK                 0x1
 572 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT                7
 573 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK           0x1
 574 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT          8
 575 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK                  0x1
 576 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT                 9
 577 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK                0x1
 578 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT               10
 579 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK                 0x1
 580 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT                11
 581 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK         0x1
 582 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT        12
 583 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK            0x1
 584 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT           13
 585 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK  0x1
 586 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
 587 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK          0x1
 588 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT         15
 589 };
 590
 591 /* Concrete Function ID. */
 592 struct pxp_concrete_fid {
 593         __le16 fid;
 594 #define PXP_CONCRETE_FID_PFID_MASK     0xF
 595 #define PXP_CONCRETE_FID_PFID_SHIFT    0
 596 #define PXP_CONCRETE_FID_PORT_MASK     0x3
 597 #define PXP_CONCRETE_FID_PORT_SHIFT    4
 598 #define PXP_CONCRETE_FID_PATH_MASK     0x1
 599 #define PXP_CONCRETE_FID_PATH_SHIFT    6
 600 #define PXP_CONCRETE_FID_VFVALID_MASK  0x1
 601 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7
 602 #define PXP_CONCRETE_FID_VFID_MASK     0xFF
 603 #define PXP_CONCRETE_FID_VFID_SHIFT    8
 604 };
 605
 606 struct pxp_pretend_concrete_fid {
 607         __le16 fid;
 608 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK      0xF
 609 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT     0
 610 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK  0x7
 611 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
 612 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK   0x1
 613 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT  7
 614 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK      0xFF
 615 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT     8
 616 };
 617
 618 union pxp_pretend_fid {
 619         struct pxp_pretend_concrete_fid concrete_fid;
 620         __le16                          opaque_fid;
 621 };
 622
 623 /* Pxp Pretend Command Register. */
 624 struct pxp_pretend_cmd {
 625         union pxp_pretend_fid   fid;
 626         __le16                  control;
 627 #define PXP_PRETEND_CMD_PATH_MASK              0x1
 628 #define PXP_PRETEND_CMD_PATH_SHIFT             0
 629 #define PXP_PRETEND_CMD_USE_PORT_MASK          0x1
 630 #define PXP_PRETEND_CMD_USE_PORT_SHIFT         1
 631 #define PXP_PRETEND_CMD_PORT_MASK              0x3
 632 #define PXP_PRETEND_CMD_PORT_SHIFT             2
 633 #define PXP_PRETEND_CMD_RESERVED0_MASK         0xF
 634 #define PXP_PRETEND_CMD_RESERVED0_SHIFT        4
 635 #define PXP_PRETEND_CMD_RESERVED1_MASK         0xF
 636 #define PXP_PRETEND_CMD_RESERVED1_SHIFT        8
 637 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK      0x1
 638 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT     12
 639 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK      0x1
 640 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT     13
 641 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK  0x1
 642 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
 643 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK       0x1
 644 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT      15
 645 };
 646
 647 /* PTT Record in PXP Admin Window. */
 648 struct pxp_ptt_entry {
 649         __le32                  offset;
 650 #define PXP_PTT_ENTRY_OFFSET_MASK     0x7FFFFF
 651 #define PXP_PTT_ENTRY_OFFSET_SHIFT    0
 652 #define PXP_PTT_ENTRY_RESERVED0_MASK  0x1FF
 653 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
 654         struct pxp_pretend_cmd  pretend;
 655 };
 656
 657 /* RSS hash type */
 658 enum rss_hash_type {
 659         RSS_HASH_TYPE_DEFAULT   = 0,
 660         RSS_HASH_TYPE_IPV4      = 1,
 661         RSS_HASH_TYPE_TCP_IPV4  = 2,
 662         RSS_HASH_TYPE_IPV6      = 3,
 663         RSS_HASH_TYPE_TCP_IPV6  = 4,
 664         RSS_HASH_TYPE_UDP_IPV4  = 5,
 665         RSS_HASH_TYPE_UDP_IPV6  = 6,
 666         MAX_RSS_HASH_TYPE
 667 };
 668
 669 /* status block structure */
 670 struct status_block {
 671         __le16  pi_array[PIS_PER_SB];
 672         __le32  sb_num;
 673 #define STATUS_BLOCK_SB_NUM_MASK      0x1FF
 674 #define STATUS_BLOCK_SB_NUM_SHIFT     0
 675 #define STATUS_BLOCK_ZERO_PAD_MASK    0x7F
 676 #define STATUS_BLOCK_ZERO_PAD_SHIFT   9
 677 #define STATUS_BLOCK_ZERO_PAD2_MASK   0xFFFF
 678 #define STATUS_BLOCK_ZERO_PAD2_SHIFT  16
 679         __le32 prod_index;
 680 #define STATUS_BLOCK_PROD_INDEX_MASK  0xFFFFFF
 681 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0
 682 #define STATUS_BLOCK_ZERO_PAD3_MASK   0xFF
 683 #define STATUS_BLOCK_ZERO_PAD3_SHIFT  24
 684 };
 685
 686 struct tunnel_parsing_flags {
 687         u8 flags;
 688 #define TUNNEL_PARSING_FLAGS_TYPE_MASK              0x3
 689 #define TUNNEL_PARSING_FLAGS_TYPE_SHIFT             0
 690 #define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK  0x1
 691 #define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
 692 #define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK     0x3
 693 #define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT    3
 694 #define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK   0x1
 695 #define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT  5
 696 #define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK     0x1
 697 #define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT    6
 698 #define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK      0x1
 699 #define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT     7
 700 };
 701 #endif /* __COMMON_HSI__ */