include/linux/qed/qed_if.h

   1 /* QLogic qed NIC Driver
   2  *
   3  * Copyright (c) 2015 QLogic Corporation
   4  *
   5  * This software is available under the terms of the GNU General Public License
   6  * (GPL) Version 2, available from the file COPYING in the main directory of
   7  * this source tree.
   8  */
   9
  10 #ifndef _QED_IF_H
  11 #define _QED_IF_H
  12
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/pci.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/types.h>
  19 #include <asm/byteorder.h>
  20 #include <linux/io.h>
  21 #include <linux/compiler.h>
  22 #include <linux/kernel.h>
  23 #include <linux/list.h>
  24 #include <linux/slab.h>
  25 #include <linux/qed/common_hsi.h>
  26 #include <linux/qed/qed_chain.h>
  27
  28 enum dcbx_protocol_type {
  29         DCBX_PROTOCOL_ISCSI,
  30         DCBX_PROTOCOL_FCOE,
  31         DCBX_PROTOCOL_ROCE,
  32         DCBX_PROTOCOL_ROCE_V2,
  33         DCBX_PROTOCOL_ETH,
  34         DCBX_MAX_PROTOCOL_TYPE
  35 };
  36
  37 #ifdef CONFIG_DCB
  38 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
  39 #define QED_LLDP_PORT_ID_STAT_LEN 4
  40 #define QED_DCBX_MAX_APP_PROTOCOL 32
  41 #define QED_MAX_PFC_PRIORITIES 8
  42 #define QED_DCBX_DSCP_SIZE 64
  43
  44 struct qed_dcbx_lldp_remote {
  45         u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
  46         u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
  47         bool enable_rx;
  48         bool enable_tx;
  49         u32 tx_interval;
  50         u32 max_credit;
  51 };
  52
  53 struct qed_dcbx_lldp_local {
  54         u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
  55         u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
  56 };
  57
  58 struct qed_dcbx_app_prio {
  59         u8 roce;
  60         u8 roce_v2;
  61         u8 fcoe;
  62         u8 iscsi;
  63         u8 eth;
  64 };
  65
  66 struct qed_dbcx_pfc_params {
  67         bool willing;
  68         bool enabled;
  69         u8 prio[QED_MAX_PFC_PRIORITIES];
  70         u8 max_tc;
  71 };
  72
  73 enum qed_dcbx_sf_ieee_type {
  74         QED_DCBX_SF_IEEE_ETHTYPE,
  75         QED_DCBX_SF_IEEE_TCP_PORT,
  76         QED_DCBX_SF_IEEE_UDP_PORT,
  77         QED_DCBX_SF_IEEE_TCP_UDP_PORT
  78 };
  79
  80 struct qed_app_entry {
  81         bool ethtype;
  82         enum qed_dcbx_sf_ieee_type sf_ieee;
  83         bool enabled;
  84         u8 prio;
  85         u16 proto_id;
  86         enum dcbx_protocol_type proto_type;
  87 };
  88
  89 struct qed_dcbx_params {
  90         struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
  91         u16 num_app_entries;
  92         bool app_willing;
  93         bool app_valid;
  94         bool app_error;
  95         bool ets_willing;
  96         bool ets_enabled;
  97         bool ets_cbs;
  98         bool valid;
  99         u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
 100         u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
 101         u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
 102         struct qed_dbcx_pfc_params pfc;
 103         u8 max_ets_tc;
 104 };
 105
 106 struct qed_dcbx_admin_params {
 107         struct qed_dcbx_params params;
 108         bool valid;
 109 };
 110
 111 struct qed_dcbx_remote_params {
 112         struct qed_dcbx_params params;
 113         bool valid;
 114 };
 115
 116 struct qed_dcbx_operational_params {
 117         struct qed_dcbx_app_prio app_prio;
 118         struct qed_dcbx_params params;
 119         bool valid;
 120         bool enabled;
 121         bool ieee;
 122         bool cee;
 123         u32 err;
 124 };
 125
 126 struct qed_dcbx_get {
 127         struct qed_dcbx_operational_params operational;
 128         struct qed_dcbx_lldp_remote lldp_remote;
 129         struct qed_dcbx_lldp_local lldp_local;
 130         struct qed_dcbx_remote_params remote;
 131         struct qed_dcbx_admin_params local;
 132 };
 133 #endif
 134
 135 enum qed_led_mode {
 136         QED_LED_MODE_OFF,
 137         QED_LED_MODE_ON,
 138         QED_LED_MODE_RESTORE
 139 };
 140
 141 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
 142                                             (void __iomem *)(reg_addr))
 143
 144 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
 145
 146 #define QED_COALESCE_MAX 0xFF
 147
 148 /* forward */
 149 struct qed_dev;
 150
 151 struct qed_eth_pf_params {
 152         /* The following parameters are used during HW-init
 153          * and these parameters need to be passed as arguments
 154          * to update_pf_params routine invoked before slowpath start
 155          */
 156         u16 num_cons;
 157 };
 158
 159 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
 160 struct qed_iscsi_pf_params {
 161         u64 glbl_q_params_addr;
 162         u64 bdq_pbl_base_addr[2];
 163         u32 max_cwnd;
 164         u16 cq_num_entries;
 165         u16 cmdq_num_entries;
 166         u16 dup_ack_threshold;
 167         u16 tx_sws_timer;
 168         u16 min_rto;
 169         u16 min_rto_rt;
 170         u16 max_rto;
 171
 172         /* The following parameters are used during HW-init
 173          * and these parameters need to be passed as arguments
 174          * to update_pf_params routine invoked before slowpath start
 175          */
 176         u16 num_cons;
 177         u16 num_tasks;
 178
 179         /* The following parameters are used during protocol-init */
 180         u16 half_way_close_timeout;
 181         u16 bdq_xoff_threshold[2];
 182         u16 bdq_xon_threshold[2];
 183         u16 cmdq_xoff_threshold;
 184         u16 cmdq_xon_threshold;
 185         u16 rq_buffer_size;
 186
 187         u8 num_sq_pages_in_ring;
 188         u8 num_r2tq_pages_in_ring;
 189         u8 num_uhq_pages_in_ring;
 190         u8 num_queues;
 191         u8 log_page_size;
 192         u8 rqe_log_size;
 193         u8 max_fin_rt;
 194         u8 gl_rq_pi;
 195         u8 gl_cmd_pi;
 196         u8 debug_mode;
 197         u8 ll2_ooo_queue_id;
 198         u8 ooo_enable;
 199
 200         u8 is_target;
 201         u8 bdq_pbl_num_entries[2];
 202 };
 203
 204 struct qed_rdma_pf_params {
 205         /* Supplied to QED during resource allocation (may affect the ILT and
 206          * the doorbell BAR).
 207          */
 208         u32 min_dpis;           /* number of requested DPIs */
 209         u32 num_mrs;            /* number of requested memory regions */
 210         u32 num_qps;            /* number of requested Queue Pairs */
 211         u32 num_srqs;           /* number of requested SRQ */
 212         u8 roce_edpm_mode;      /* see QED_ROCE_EDPM_MODE_ENABLE */
 213         u8 gl_pi;               /* protocol index */
 214
 215         /* Will allocate rate limiters to be used with QPs */
 216         u8 enable_dcqcn;
 217 };
 218
 219 struct qed_pf_params {
 220         struct qed_eth_pf_params eth_pf_params;
 221         struct qed_iscsi_pf_params iscsi_pf_params;
 222         struct qed_rdma_pf_params rdma_pf_params;
 223 };
 224
 225 enum qed_int_mode {
 226         QED_INT_MODE_INTA,
 227         QED_INT_MODE_MSIX,
 228         QED_INT_MODE_MSI,
 229         QED_INT_MODE_POLL,
 230 };
 231
 232 struct qed_sb_info {
 233         struct status_block     *sb_virt;
 234         dma_addr_t              sb_phys;
 235         u32                     sb_ack; /* Last given ack */
 236         u16                     igu_sb_id;
 237         void __iomem            *igu_addr;
 238         u8                      flags;
 239 #define QED_SB_INFO_INIT        0x1
 240 #define QED_SB_INFO_SETUP       0x2
 241
 242         struct qed_dev          *cdev;
 243 };
 244
 245 struct qed_dev_info {
 246         unsigned long   pci_mem_start;
 247         unsigned long   pci_mem_end;
 248         unsigned int    pci_irq;
 249         u8              num_hwfns;
 250
 251         u8              hw_mac[ETH_ALEN];
 252         bool            is_mf_default;
 253
 254         /* FW version */
 255         u16             fw_major;
 256         u16             fw_minor;
 257         u16             fw_rev;
 258         u16             fw_eng;
 259
 260         /* MFW version */
 261         u32             mfw_rev;
 262
 263         bool rdma_supported;
 264
 265         u32             flash_size;
 266         u8              mf_mode;
 267         bool            tx_switching;
 268 };
 269
 270 enum qed_sb_type {
 271         QED_SB_TYPE_L2_QUEUE,
 272 };
 273
 274 enum qed_protocol {
 275         QED_PROTOCOL_ETH,
 276         QED_PROTOCOL_ISCSI,
 277 };
 278
 279 enum qed_link_mode_bits {
 280         QED_LM_FIBRE_BIT = BIT(0),
 281         QED_LM_Autoneg_BIT = BIT(1),
 282         QED_LM_Asym_Pause_BIT = BIT(2),
 283         QED_LM_Pause_BIT = BIT(3),
 284         QED_LM_1000baseT_Half_BIT = BIT(4),
 285         QED_LM_1000baseT_Full_BIT = BIT(5),
 286         QED_LM_10000baseKR_Full_BIT = BIT(6),
 287         QED_LM_25000baseKR_Full_BIT = BIT(7),
 288         QED_LM_40000baseLR4_Full_BIT = BIT(8),
 289         QED_LM_50000baseKR2_Full_BIT = BIT(9),
 290         QED_LM_100000baseKR4_Full_BIT = BIT(10),
 291         QED_LM_COUNT = 11
 292 };
 293
 294 struct qed_link_params {
 295         bool    link_up;
 296
 297 #define QED_LINK_OVERRIDE_SPEED_AUTONEG         BIT(0)
 298 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS      BIT(1)
 299 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED    BIT(2)
 300 #define QED_LINK_OVERRIDE_PAUSE_CONFIG          BIT(3)
 301 #define QED_LINK_OVERRIDE_LOOPBACK_MODE         BIT(4)
 302         u32     override_flags;
 303         bool    autoneg;
 304         u32     adv_speeds;
 305         u32     forced_speed;
 306 #define QED_LINK_PAUSE_AUTONEG_ENABLE           BIT(0)
 307 #define QED_LINK_PAUSE_RX_ENABLE                BIT(1)
 308 #define QED_LINK_PAUSE_TX_ENABLE                BIT(2)
 309         u32     pause_config;
 310 #define QED_LINK_LOOPBACK_NONE                  BIT(0)
 311 #define QED_LINK_LOOPBACK_INT_PHY               BIT(1)
 312 #define QED_LINK_LOOPBACK_EXT_PHY               BIT(2)
 313 #define QED_LINK_LOOPBACK_EXT                   BIT(3)
 314 #define QED_LINK_LOOPBACK_MAC                   BIT(4)
 315         u32     loopback_mode;
 316 };
 317
 318 struct qed_link_output {
 319         bool    link_up;
 320
 321         /* In QED_LM_* defs */
 322         u32     supported_caps;
 323         u32     advertised_caps;
 324         u32     lp_caps;
 325
 326         u32     speed;                  /* In Mb/s */
 327         u8      duplex;                 /* In DUPLEX defs */
 328         u8      port;                   /* In PORT defs */
 329         bool    autoneg;
 330         u32     pause_config;
 331 };
 332
 333 struct qed_probe_params {
 334         enum qed_protocol protocol;
 335         u32 dp_module;
 336         u8 dp_level;
 337         bool is_vf;
 338 };
 339
 340 #define QED_DRV_VER_STR_SIZE 12
 341 struct qed_slowpath_params {
 342         u32     int_mode;
 343         u8      drv_major;
 344         u8      drv_minor;
 345         u8      drv_rev;
 346         u8      drv_eng;
 347         u8      name[QED_DRV_VER_STR_SIZE];
 348 };
 349
 350 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
 351
 352 struct qed_int_info {
 353         struct msix_entry       *msix;
 354         u8                      msix_cnt;
 355
 356         /* This should be updated by the protocol driver */
 357         u8                      used_cnt;
 358 };
 359
 360 struct qed_common_cb_ops {
 361         void    (*link_update)(void                     *dev,
 362                                struct qed_link_output   *link);
 363 };
 364
 365 struct qed_selftest_ops {
 366 /**
 367  * @brief selftest_interrupt - Perform interrupt test
 368  *
 369  * @param cdev
 370  *
 371  * @return 0 on success, error otherwise.
 372  */
 373         int (*selftest_interrupt)(struct qed_dev *cdev);
 374
 375 /**
 376  * @brief selftest_memory - Perform memory test
 377  *
 378  * @param cdev
 379  *
 380  * @return 0 on success, error otherwise.
 381  */
 382         int (*selftest_memory)(struct qed_dev *cdev);
 383
 384 /**
 385  * @brief selftest_register - Perform register test
 386  *
 387  * @param cdev
 388  *
 389  * @return 0 on success, error otherwise.
 390  */
 391         int (*selftest_register)(struct qed_dev *cdev);
 392
 393 /**
 394  * @brief selftest_clock - Perform clock test
 395  *
 396  * @param cdev
 397  *
 398  * @return 0 on success, error otherwise.
 399  */
 400         int (*selftest_clock)(struct qed_dev *cdev);
 401 };
 402
 403 struct qed_common_ops {
 404         struct qed_selftest_ops *selftest;
 405
 406         struct qed_dev* (*probe)(struct pci_dev *dev,
 407                                  struct qed_probe_params *params);
 408
 409         void            (*remove)(struct qed_dev *cdev);
 410
 411         int             (*set_power_state)(struct qed_dev *cdev,
 412                                            pci_power_t state);
 413
 414         void            (*set_id)(struct qed_dev *cdev,
 415                                   char name[],
 416                                   char ver_str[]);
 417
 418         /* Client drivers need to make this call before slowpath_start.
 419          * PF params required for the call before slowpath_start is
 420          * documented within the qed_pf_params structure definition.
 421          */
 422         void            (*update_pf_params)(struct qed_dev *cdev,
 423                                             struct qed_pf_params *params);
 424         int             (*slowpath_start)(struct qed_dev *cdev,
 425                                           struct qed_slowpath_params *params);
 426
 427         int             (*slowpath_stop)(struct qed_dev *cdev);
 428
 429         /* Requests to use `cnt' interrupts for fastpath.
 430          * upon success, returns number of interrupts allocated for fastpath.
 431          */
 432         int             (*set_fp_int)(struct qed_dev *cdev,
 433                                       u16 cnt);
 434
 435         /* Fills `info' with pointers required for utilizing interrupts */
 436         int             (*get_fp_int)(struct qed_dev *cdev,
 437                                       struct qed_int_info *info);
 438
 439         u32             (*sb_init)(struct qed_dev *cdev,
 440                                    struct qed_sb_info *sb_info,
 441                                    void *sb_virt_addr,
 442                                    dma_addr_t sb_phy_addr,
 443                                    u16 sb_id,
 444                                    enum qed_sb_type type);
 445
 446         u32             (*sb_release)(struct qed_dev *cdev,
 447                                       struct qed_sb_info *sb_info,
 448                                       u16 sb_id);
 449
 450         void            (*simd_handler_config)(struct qed_dev *cdev,
 451                                                void *token,
 452                                                int index,
 453                                                void (*handler)(void *));
 454
 455         void            (*simd_handler_clean)(struct qed_dev *cdev,
 456                                               int index);
 457
 458         int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
 459
 460         int (*dbg_all_data_size) (struct qed_dev *cdev);
 461
 462 /**
 463  * @brief can_link_change - can the instance change the link or not
 464  *
 465  * @param cdev
 466  *
 467  * @return true if link-change is allowed, false otherwise.
 468  */
 469         bool (*can_link_change)(struct qed_dev *cdev);
 470
 471 /**
 472  * @brief set_link - set links according to params
 473  *
 474  * @param cdev
 475  * @param params - values used to override the default link configuration
 476  *
 477  * @return 0 on success, error otherwise.
 478  */
 479         int             (*set_link)(struct qed_dev *cdev,
 480                                     struct qed_link_params *params);
 481
 482 /**
 483  * @brief get_link - returns the current link state.
 484  *
 485  * @param cdev
 486  * @param if_link - structure to be filled with current link configuration.
 487  */
 488         void            (*get_link)(struct qed_dev *cdev,
 489                                     struct qed_link_output *if_link);
 490
 491 /**
 492  * @brief - drains chip in case Tx completions fail to arrive due to pause.
 493  *
 494  * @param cdev
 495  */
 496         int             (*drain)(struct qed_dev *cdev);
 497
 498 /**
 499  * @brief update_msglvl - update module debug level
 500  *
 501  * @param cdev
 502  * @param dp_module
 503  * @param dp_level
 504  */
 505         void            (*update_msglvl)(struct qed_dev *cdev,
 506                                          u32 dp_module,
 507                                          u8 dp_level);
 508
 509         int             (*chain_alloc)(struct qed_dev *cdev,
 510                                        enum qed_chain_use_mode intended_use,
 511                                        enum qed_chain_mode mode,
 512                                        enum qed_chain_cnt_type cnt_type,
 513                                        u32 num_elems,
 514                                        size_t elem_size,
 515                                        struct qed_chain *p_chain);
 516
 517         void            (*chain_free)(struct qed_dev *cdev,
 518                                       struct qed_chain *p_chain);
 519
 520 /**
 521  * @brief get_coalesce - Get coalesce parameters in usec
 522  *
 523  * @param cdev
 524  * @param rx_coal - Rx coalesce value in usec
 525  * @param tx_coal - Tx coalesce value in usec
 526  *
 527  */
 528         void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal);
 529
 530 /**
 531  * @brief set_coalesce - Configure Rx coalesce value in usec
 532  *
 533  * @param cdev
 534  * @param rx_coal - Rx coalesce value in usec
 535  * @param tx_coal - Tx coalesce value in usec
 536  * @param qid - Queue index
 537  * @param sb_id - Status Block Id
 538  *
 539  * @return 0 on success, error otherwise.
 540  */
 541         int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
 542                             u8 qid, u16 sb_id);
 543
 544 /**
 545  * @brief set_led - Configure LED mode
 546  *
 547  * @param cdev
 548  * @param mode - LED mode
 549  *
 550  * @return 0 on success, error otherwise.
 551  */
 552         int (*set_led)(struct qed_dev *cdev,
 553                        enum qed_led_mode mode);
 554 };
 555
 556 #define MASK_FIELD(_name, _value) \
 557         ((_value) &= (_name ## _MASK))
 558
 559 #define FIELD_VALUE(_name, _value) \
 560         ((_value & _name ## _MASK) << _name ## _SHIFT)
 561
 562 #define SET_FIELD(value, name, flag)                           \
 563         do {                                                   \
 564                 (value) &= ~(name ## _MASK << name ## _SHIFT); \
 565                 (value) |= (((u64)flag) << (name ## _SHIFT));  \
 566         } while (0)
 567
 568 #define GET_FIELD(value, name) \
 569         (((value) >> (name ## _SHIFT)) & name ## _MASK)
 570
 571 /* Debug print definitions */
 572 #define DP_ERR(cdev, fmt, ...)                                               \
 573                 pr_err("[%s:%d(%s)]" fmt,                                    \
 574                        __func__, __LINE__,                                   \
 575                        DP_NAME(cdev) ? DP_NAME(cdev) : "",                   \
 576                        ## __VA_ARGS__)                                       \
 577
 578 #define DP_NOTICE(cdev, fmt, ...)                                     \
 579         do {                                                          \
 580                 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
 581                         pr_notice("[%s:%d(%s)]" fmt,                  \
 582                                   __func__, __LINE__,                 \
 583                                   DP_NAME(cdev) ? DP_NAME(cdev) : "", \
 584                                   ## __VA_ARGS__);                    \
 585                                                                       \
 586                 }                                                     \
 587         } while (0)
 588
 589 #define DP_INFO(cdev, fmt, ...)                                       \
 590         do {                                                          \
 591                 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) {   \
 592                         pr_notice("[%s:%d(%s)]" fmt,                  \
 593                                   __func__, __LINE__,                 \
 594                                   DP_NAME(cdev) ? DP_NAME(cdev) : "", \
 595                                   ## __VA_ARGS__);                    \
 596                 }                                                     \
 597         } while (0)
 598
 599 #define DP_VERBOSE(cdev, module, fmt, ...)                              \
 600         do {                                                            \
 601                 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
 602                              ((cdev)->dp_module & module))) {           \
 603                         pr_notice("[%s:%d(%s)]" fmt,                    \
 604                                   __func__, __LINE__,                   \
 605                                   DP_NAME(cdev) ? DP_NAME(cdev) : "",   \
 606                                   ## __VA_ARGS__);                      \
 607                 }                                                       \
 608         } while (0)
 609
 610 enum DP_LEVEL {
 611         QED_LEVEL_VERBOSE       = 0x0,
 612         QED_LEVEL_INFO          = 0x1,
 613         QED_LEVEL_NOTICE        = 0x2,
 614         QED_LEVEL_ERR           = 0x3,
 615 };
 616
 617 #define QED_LOG_LEVEL_SHIFT     (30)
 618 #define QED_LOG_VERBOSE_MASK    (0x3fffffff)
 619 #define QED_LOG_INFO_MASK       (0x40000000)
 620 #define QED_LOG_NOTICE_MASK     (0x80000000)
 621
 622 enum DP_MODULE {
 623         QED_MSG_SPQ     = 0x10000,
 624         QED_MSG_STATS   = 0x20000,
 625         QED_MSG_DCB     = 0x40000,
 626         QED_MSG_IOV     = 0x80000,
 627         QED_MSG_SP      = 0x100000,
 628         QED_MSG_STORAGE = 0x200000,
 629         QED_MSG_CXT     = 0x800000,
 630         QED_MSG_ILT     = 0x2000000,
 631         QED_MSG_ROCE    = 0x4000000,
 632         QED_MSG_DEBUG   = 0x8000000,
 633         /* to be added...up to 0x8000000 */
 634 };
 635
 636 enum qed_mf_mode {
 637         QED_MF_DEFAULT,
 638         QED_MF_OVLAN,
 639         QED_MF_NPAR,
 640 };
 641
 642 struct qed_eth_stats {
 643         u64     no_buff_discards;
 644         u64     packet_too_big_discard;
 645         u64     ttl0_discard;
 646         u64     rx_ucast_bytes;
 647         u64     rx_mcast_bytes;
 648         u64     rx_bcast_bytes;
 649         u64     rx_ucast_pkts;
 650         u64     rx_mcast_pkts;
 651         u64     rx_bcast_pkts;
 652         u64     mftag_filter_discards;
 653         u64     mac_filter_discards;
 654         u64     tx_ucast_bytes;
 655         u64     tx_mcast_bytes;
 656         u64     tx_bcast_bytes;
 657         u64     tx_ucast_pkts;
 658         u64     tx_mcast_pkts;
 659         u64     tx_bcast_pkts;
 660         u64     tx_err_drop_pkts;
 661         u64     tpa_coalesced_pkts;
 662         u64     tpa_coalesced_events;
 663         u64     tpa_aborts_num;
 664         u64     tpa_not_coalesced_pkts;
 665         u64     tpa_coalesced_bytes;
 666
 667         /* port */
 668         u64     rx_64_byte_packets;
 669         u64     rx_65_to_127_byte_packets;
 670         u64     rx_128_to_255_byte_packets;
 671         u64     rx_256_to_511_byte_packets;
 672         u64     rx_512_to_1023_byte_packets;
 673         u64     rx_1024_to_1518_byte_packets;
 674         u64     rx_1519_to_1522_byte_packets;
 675         u64     rx_1519_to_2047_byte_packets;
 676         u64     rx_2048_to_4095_byte_packets;
 677         u64     rx_4096_to_9216_byte_packets;
 678         u64     rx_9217_to_16383_byte_packets;
 679         u64     rx_crc_errors;
 680         u64     rx_mac_crtl_frames;
 681         u64     rx_pause_frames;
 682         u64     rx_pfc_frames;
 683         u64     rx_align_errors;
 684         u64     rx_carrier_errors;
 685         u64     rx_oversize_packets;
 686         u64     rx_jabbers;
 687         u64     rx_undersize_packets;
 688         u64     rx_fragments;
 689         u64     tx_64_byte_packets;
 690         u64     tx_65_to_127_byte_packets;
 691         u64     tx_128_to_255_byte_packets;
 692         u64     tx_256_to_511_byte_packets;
 693         u64     tx_512_to_1023_byte_packets;
 694         u64     tx_1024_to_1518_byte_packets;
 695         u64     tx_1519_to_2047_byte_packets;
 696         u64     tx_2048_to_4095_byte_packets;
 697         u64     tx_4096_to_9216_byte_packets;
 698         u64     tx_9217_to_16383_byte_packets;
 699         u64     tx_pause_frames;
 700         u64     tx_pfc_frames;
 701         u64     tx_lpi_entry_count;
 702         u64     tx_total_collisions;
 703         u64     brb_truncates;
 704         u64     brb_discards;
 705         u64     rx_mac_bytes;
 706         u64     rx_mac_uc_packets;
 707         u64     rx_mac_mc_packets;
 708         u64     rx_mac_bc_packets;
 709         u64     rx_mac_frames_ok;
 710         u64     tx_mac_bytes;
 711         u64     tx_mac_uc_packets;
 712         u64     tx_mac_mc_packets;
 713         u64     tx_mac_bc_packets;
 714         u64     tx_mac_ctrl_frames;
 715 };
 716
 717 #define QED_SB_IDX              0x0002
 718
 719 #define RX_PI           0
 720 #define TX_PI(tc)       (RX_PI + 1 + tc)
 721
 722 struct qed_sb_cnt_info {
 723         int     sb_cnt;
 724         int     sb_iov_cnt;
 725         int     sb_free_blk;
 726 };
 727
 728 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
 729 {
 730         u32 prod = 0;
 731         u16 rc = 0;
 732
 733         prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
 734                STATUS_BLOCK_PROD_INDEX_MASK;
 735         if (sb_info->sb_ack != prod) {
 736                 sb_info->sb_ack = prod;
 737                 rc |= QED_SB_IDX;
 738         }
 739
 740         /* Let SB update */
 741         mmiowb();
 742         return rc;
 743 }
 744
 745 /**
 746  *
 747  * @brief This function creates an update command for interrupts that is
 748  *        written to the IGU.
 749  *
 750  * @param sb_info       - This is the structure allocated and
 751  *                 initialized per status block. Assumption is
 752  *                 that it was initialized using qed_sb_init
 753  * @param int_cmd       - Enable/Disable/Nop
 754  * @param upd_flg       - whether igu consumer should be
 755  *                 updated.
 756  *
 757  * @return inline void
 758  */
 759 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
 760                               enum igu_int_cmd int_cmd,
 761                               u8 upd_flg)
 762 {
 763         struct igu_prod_cons_update igu_ack = { 0 };
 764
 765         igu_ack.sb_id_and_flags =
 766                 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
 767                  (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
 768                  (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
 769                  (IGU_SEG_ACCESS_REG <<
 770                   IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
 771
 772         DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
 773
 774         /* Both segments (interrupts & acks) are written to same place address;
 775          * Need to guarantee all commands will be received (in-order) by HW.
 776          */
 777         mmiowb();
 778         barrier();
 779 }
 780
 781 static inline void __internal_ram_wr(void *p_hwfn,
 782                                      void __iomem *addr,
 783                                      int size,
 784                                      u32 *data)
 785
 786 {
 787         unsigned int i;
 788
 789         for (i = 0; i < size / sizeof(*data); i++)
 790                 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
 791 }
 792
 793 static inline void internal_ram_wr(void __iomem *addr,
 794                                    int size,
 795                                    u32 *data)
 796 {
 797         __internal_ram_wr(NULL, addr, size, data);
 798 }
 799
 800 enum qed_rss_caps {
 801         QED_RSS_IPV4            = 0x1,
 802         QED_RSS_IPV6            = 0x2,
 803         QED_RSS_IPV4_TCP        = 0x4,
 804         QED_RSS_IPV6_TCP        = 0x8,
 805         QED_RSS_IPV4_UDP        = 0x10,
 806         QED_RSS_IPV6_UDP        = 0x20,
 807 };
 808
 809 #define QED_RSS_IND_TABLE_SIZE 128
 810 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
 811 #endif