1 /* QLogic qed NIC Driver
3 * Copyright (c) 2015 QLogic Corporation
5 * This software is available under the terms of the GNU General Public License
6 * (GPL) Version 2, available from the file COPYING in the main directory of
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/netdevice.h>
16 #include <linux/pci.h>
17 #include <linux/skbuff.h>
18 #include <linux/types.h>
19 #include <asm/byteorder.h>
21 #include <linux/compiler.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/slab.h>
25 #include <linux/qed/common_hsi.h>
26 #include <linux/qed/qed_chain.h>
28 enum dcbx_protocol_type {
32 DCBX_PROTOCOL_ROCE_V2,
34 DCBX_MAX_PROTOCOL_TYPE
38 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
39 #define QED_LLDP_PORT_ID_STAT_LEN 4
40 #define QED_DCBX_MAX_APP_PROTOCOL 32
41 #define QED_MAX_PFC_PRIORITIES 8
42 #define QED_DCBX_DSCP_SIZE 64
44 struct qed_dcbx_lldp_remote {
45 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
46 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
53 struct qed_dcbx_lldp_local {
54 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
55 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
58 struct qed_dcbx_app_prio {
66 struct qed_dbcx_pfc_params {
69 u8 prio[QED_MAX_PFC_PRIORITIES];
73 struct qed_app_entry {
78 enum dcbx_protocol_type proto_type;
81 struct qed_dcbx_params {
82 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
91 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
92 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
93 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
94 struct qed_dbcx_pfc_params pfc;
98 struct qed_dcbx_admin_params {
99 struct qed_dcbx_params params;
103 struct qed_dcbx_remote_params {
104 struct qed_dcbx_params params;
108 struct qed_dcbx_operational_params {
109 struct qed_dcbx_app_prio app_prio;
110 struct qed_dcbx_params params;
118 struct qed_dcbx_get {
119 struct qed_dcbx_operational_params operational;
120 struct qed_dcbx_lldp_remote lldp_remote;
121 struct qed_dcbx_lldp_local lldp_local;
122 struct qed_dcbx_remote_params remote;
123 struct qed_dcbx_admin_params local;
133 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
134 (void __iomem *)(reg_addr))
136 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
138 #define QED_COALESCE_MAX 0xFF
143 struct qed_eth_pf_params {
144 /* The following parameters are used during HW-init
145 * and these parameters need to be passed as arguments
146 * to update_pf_params routine invoked before slowpath start
151 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
152 struct qed_iscsi_pf_params {
153 u64 glbl_q_params_addr;
154 u64 bdq_pbl_base_addr[2];
157 u16 cmdq_num_entries;
158 u16 dup_ack_threshold;
164 /* The following parameters are used during HW-init
165 * and these parameters need to be passed as arguments
166 * to update_pf_params routine invoked before slowpath start
171 /* The following parameters are used during protocol-init */
172 u16 half_way_close_timeout;
173 u16 bdq_xoff_threshold[2];
174 u16 bdq_xon_threshold[2];
175 u16 cmdq_xoff_threshold;
176 u16 cmdq_xon_threshold;
179 u8 num_sq_pages_in_ring;
180 u8 num_r2tq_pages_in_ring;
181 u8 num_uhq_pages_in_ring;
193 u8 bdq_pbl_num_entries[2];
196 struct qed_rdma_pf_params {
197 /* Supplied to QED during resource allocation (may affect the ILT and
200 u32 min_dpis; /* number of requested DPIs */
201 u32 num_mrs; /* number of requested memory regions */
202 u32 num_qps; /* number of requested Queue Pairs */
203 u32 num_srqs; /* number of requested SRQ */
204 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
205 u8 gl_pi; /* protocol index */
207 /* Will allocate rate limiters to be used with QPs */
211 struct qed_pf_params {
212 struct qed_eth_pf_params eth_pf_params;
213 struct qed_iscsi_pf_params iscsi_pf_params;
214 struct qed_rdma_pf_params rdma_pf_params;
225 struct status_block *sb_virt;
227 u32 sb_ack; /* Last given ack */
229 void __iomem *igu_addr;
231 #define QED_SB_INFO_INIT 0x1
232 #define QED_SB_INFO_SETUP 0x2
234 struct qed_dev *cdev;
237 struct qed_dev_info {
238 unsigned long pci_mem_start;
239 unsigned long pci_mem_end;
240 unsigned int pci_irq;
263 QED_SB_TYPE_L2_QUEUE,
271 struct qed_link_params {
274 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
275 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
276 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
277 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
278 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
283 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
284 #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
285 #define QED_LINK_PAUSE_TX_ENABLE BIT(2)
287 #define QED_LINK_LOOPBACK_NONE BIT(0)
288 #define QED_LINK_LOOPBACK_INT_PHY BIT(1)
289 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
290 #define QED_LINK_LOOPBACK_EXT BIT(3)
291 #define QED_LINK_LOOPBACK_MAC BIT(4)
295 struct qed_link_output {
298 u32 supported_caps; /* In SUPPORTED defs */
299 u32 advertised_caps; /* In ADVERTISED defs */
300 u32 lp_caps; /* In ADVERTISED defs */
301 u32 speed; /* In Mb/s */
302 u8 duplex; /* In DUPLEX defs */
303 u8 port; /* In PORT defs */
308 struct qed_probe_params {
309 enum qed_protocol protocol;
315 #define QED_DRV_VER_STR_SIZE 12
316 struct qed_slowpath_params {
322 u8 name[QED_DRV_VER_STR_SIZE];
325 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
327 struct qed_int_info {
328 struct msix_entry *msix;
331 /* This should be updated by the protocol driver */
335 struct qed_common_cb_ops {
336 void (*link_update)(void *dev,
337 struct qed_link_output *link);
340 struct qed_selftest_ops {
342 * @brief selftest_interrupt - Perform interrupt test
346 * @return 0 on success, error otherwise.
348 int (*selftest_interrupt)(struct qed_dev *cdev);
351 * @brief selftest_memory - Perform memory test
355 * @return 0 on success, error otherwise.
357 int (*selftest_memory)(struct qed_dev *cdev);
360 * @brief selftest_register - Perform register test
364 * @return 0 on success, error otherwise.
366 int (*selftest_register)(struct qed_dev *cdev);
369 * @brief selftest_clock - Perform clock test
373 * @return 0 on success, error otherwise.
375 int (*selftest_clock)(struct qed_dev *cdev);
378 struct qed_common_ops {
379 struct qed_selftest_ops *selftest;
381 struct qed_dev* (*probe)(struct pci_dev *dev,
382 struct qed_probe_params *params);
384 void (*remove)(struct qed_dev *cdev);
386 int (*set_power_state)(struct qed_dev *cdev,
389 void (*set_id)(struct qed_dev *cdev,
393 /* Client drivers need to make this call before slowpath_start.
394 * PF params required for the call before slowpath_start is
395 * documented within the qed_pf_params structure definition.
397 void (*update_pf_params)(struct qed_dev *cdev,
398 struct qed_pf_params *params);
399 int (*slowpath_start)(struct qed_dev *cdev,
400 struct qed_slowpath_params *params);
402 int (*slowpath_stop)(struct qed_dev *cdev);
404 /* Requests to use `cnt' interrupts for fastpath.
405 * upon success, returns number of interrupts allocated for fastpath.
407 int (*set_fp_int)(struct qed_dev *cdev,
410 /* Fills `info' with pointers required for utilizing interrupts */
411 int (*get_fp_int)(struct qed_dev *cdev,
412 struct qed_int_info *info);
414 u32 (*sb_init)(struct qed_dev *cdev,
415 struct qed_sb_info *sb_info,
417 dma_addr_t sb_phy_addr,
419 enum qed_sb_type type);
421 u32 (*sb_release)(struct qed_dev *cdev,
422 struct qed_sb_info *sb_info,
425 void (*simd_handler_config)(struct qed_dev *cdev,
428 void (*handler)(void *));
430 void (*simd_handler_clean)(struct qed_dev *cdev,
434 * @brief can_link_change - can the instance change the link or not
438 * @return true if link-change is allowed, false otherwise.
440 bool (*can_link_change)(struct qed_dev *cdev);
443 * @brief set_link - set links according to params
446 * @param params - values used to override the default link configuration
448 * @return 0 on success, error otherwise.
450 int (*set_link)(struct qed_dev *cdev,
451 struct qed_link_params *params);
454 * @brief get_link - returns the current link state.
457 * @param if_link - structure to be filled with current link configuration.
459 void (*get_link)(struct qed_dev *cdev,
460 struct qed_link_output *if_link);
463 * @brief - drains chip in case Tx completions fail to arrive due to pause.
467 int (*drain)(struct qed_dev *cdev);
470 * @brief update_msglvl - update module debug level
476 void (*update_msglvl)(struct qed_dev *cdev,
480 int (*chain_alloc)(struct qed_dev *cdev,
481 enum qed_chain_use_mode intended_use,
482 enum qed_chain_mode mode,
483 enum qed_chain_cnt_type cnt_type,
486 struct qed_chain *p_chain);
488 void (*chain_free)(struct qed_dev *cdev,
489 struct qed_chain *p_chain);
492 * @brief get_coalesce - Get coalesce parameters in usec
495 * @param rx_coal - Rx coalesce value in usec
496 * @param tx_coal - Tx coalesce value in usec
499 void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal);
502 * @brief set_coalesce - Configure Rx coalesce value in usec
505 * @param rx_coal - Rx coalesce value in usec
506 * @param tx_coal - Tx coalesce value in usec
507 * @param qid - Queue index
508 * @param sb_id - Status Block Id
510 * @return 0 on success, error otherwise.
512 int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
516 * @brief set_led - Configure LED mode
519 * @param mode - LED mode
521 * @return 0 on success, error otherwise.
523 int (*set_led)(struct qed_dev *cdev,
524 enum qed_led_mode mode);
527 #define MASK_FIELD(_name, _value) \
528 ((_value) &= (_name ## _MASK))
530 #define FIELD_VALUE(_name, _value) \
531 ((_value & _name ## _MASK) << _name ## _SHIFT)
533 #define SET_FIELD(value, name, flag) \
535 (value) &= ~(name ## _MASK << name ## _SHIFT); \
536 (value) |= (((u64)flag) << (name ## _SHIFT)); \
539 #define GET_FIELD(value, name) \
540 (((value) >> (name ## _SHIFT)) & name ## _MASK)
542 /* Debug print definitions */
543 #define DP_ERR(cdev, fmt, ...) \
544 pr_err("[%s:%d(%s)]" fmt, \
545 __func__, __LINE__, \
546 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
549 #define DP_NOTICE(cdev, fmt, ...) \
551 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
552 pr_notice("[%s:%d(%s)]" fmt, \
553 __func__, __LINE__, \
554 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
560 #define DP_INFO(cdev, fmt, ...) \
562 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
563 pr_notice("[%s:%d(%s)]" fmt, \
564 __func__, __LINE__, \
565 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
570 #define DP_VERBOSE(cdev, module, fmt, ...) \
572 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
573 ((cdev)->dp_module & module))) { \
574 pr_notice("[%s:%d(%s)]" fmt, \
575 __func__, __LINE__, \
576 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
582 QED_LEVEL_VERBOSE = 0x0,
583 QED_LEVEL_INFO = 0x1,
584 QED_LEVEL_NOTICE = 0x2,
588 #define QED_LOG_LEVEL_SHIFT (30)
589 #define QED_LOG_VERBOSE_MASK (0x3fffffff)
590 #define QED_LOG_INFO_MASK (0x40000000)
591 #define QED_LOG_NOTICE_MASK (0x80000000)
594 QED_MSG_SPQ = 0x10000,
595 QED_MSG_STATS = 0x20000,
596 QED_MSG_DCB = 0x40000,
597 QED_MSG_IOV = 0x80000,
598 QED_MSG_SP = 0x100000,
599 QED_MSG_STORAGE = 0x200000,
600 QED_MSG_CXT = 0x800000,
601 QED_MSG_ILT = 0x2000000,
602 QED_MSG_ROCE = 0x4000000,
603 QED_MSG_DEBUG = 0x8000000,
604 /* to be added...up to 0x8000000 */
613 struct qed_eth_stats {
614 u64 no_buff_discards;
615 u64 packet_too_big_discard;
623 u64 mftag_filter_discards;
624 u64 mac_filter_discards;
631 u64 tx_err_drop_pkts;
632 u64 tpa_coalesced_pkts;
633 u64 tpa_coalesced_events;
635 u64 tpa_not_coalesced_pkts;
636 u64 tpa_coalesced_bytes;
639 u64 rx_64_byte_packets;
640 u64 rx_65_to_127_byte_packets;
641 u64 rx_128_to_255_byte_packets;
642 u64 rx_256_to_511_byte_packets;
643 u64 rx_512_to_1023_byte_packets;
644 u64 rx_1024_to_1518_byte_packets;
645 u64 rx_1519_to_1522_byte_packets;
646 u64 rx_1519_to_2047_byte_packets;
647 u64 rx_2048_to_4095_byte_packets;
648 u64 rx_4096_to_9216_byte_packets;
649 u64 rx_9217_to_16383_byte_packets;
651 u64 rx_mac_crtl_frames;
655 u64 rx_carrier_errors;
656 u64 rx_oversize_packets;
658 u64 rx_undersize_packets;
660 u64 tx_64_byte_packets;
661 u64 tx_65_to_127_byte_packets;
662 u64 tx_128_to_255_byte_packets;
663 u64 tx_256_to_511_byte_packets;
664 u64 tx_512_to_1023_byte_packets;
665 u64 tx_1024_to_1518_byte_packets;
666 u64 tx_1519_to_2047_byte_packets;
667 u64 tx_2048_to_4095_byte_packets;
668 u64 tx_4096_to_9216_byte_packets;
669 u64 tx_9217_to_16383_byte_packets;
672 u64 tx_lpi_entry_count;
673 u64 tx_total_collisions;
677 u64 rx_mac_uc_packets;
678 u64 rx_mac_mc_packets;
679 u64 rx_mac_bc_packets;
680 u64 rx_mac_frames_ok;
682 u64 tx_mac_uc_packets;
683 u64 tx_mac_mc_packets;
684 u64 tx_mac_bc_packets;
685 u64 tx_mac_ctrl_frames;
688 #define QED_SB_IDX 0x0002
691 #define TX_PI(tc) (RX_PI + 1 + tc)
693 struct qed_sb_cnt_info {
699 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
704 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
705 STATUS_BLOCK_PROD_INDEX_MASK;
706 if (sb_info->sb_ack != prod) {
707 sb_info->sb_ack = prod;
718 * @brief This function creates an update command for interrupts that is
719 * written to the IGU.
721 * @param sb_info - This is the structure allocated and
722 * initialized per status block. Assumption is
723 * that it was initialized using qed_sb_init
724 * @param int_cmd - Enable/Disable/Nop
725 * @param upd_flg - whether igu consumer should be
728 * @return inline void
730 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
731 enum igu_int_cmd int_cmd,
734 struct igu_prod_cons_update igu_ack = { 0 };
736 igu_ack.sb_id_and_flags =
737 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
738 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
739 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
740 (IGU_SEG_ACCESS_REG <<
741 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
743 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
745 /* Both segments (interrupts & acks) are written to same place address;
746 * Need to guarantee all commands will be received (in-order) by HW.
752 static inline void __internal_ram_wr(void *p_hwfn,
760 for (i = 0; i < size / sizeof(*data); i++)
761 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
764 static inline void internal_ram_wr(void __iomem *addr,
768 __internal_ram_wr(NULL, addr, size, data);
774 QED_RSS_IPV4_TCP = 0x4,
775 QED_RSS_IPV6_TCP = 0x8,
776 QED_RSS_IPV4_UDP = 0x10,
777 QED_RSS_IPV6_UDP = 0x20,
780 #define QED_RSS_IND_TABLE_SIZE 128
781 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */