sound/pci/hda/patch_ca0132.c

   1 /*
   2  * HD audio interface patch for Creative Sound Core3D chip
   3  *
   4  * Copyright (c) 2011, Creative Technology Ltd.
   5  *
   6  * Based on patch_ca0110.c
   7  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   8  *
   9  *  This driver is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License as published by
  11  *  the Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This driver is distributed in the hope that it will be useful,
  15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *  GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; if not, write to the Free Software
  21  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/pci.h>
  28 #include <linux/module.h>
  29 #include <linux/firmware.h>
  30 #include <sound/core.h>
  31 #include <sound/tlv.h>
  32 #include "hda_codec.h"
  33 #include "hda_local.h"
  34 #include "hda_jack.h"
  35
  36 #include "ca0132_regs.h"
  37
  38 /* Enable this to see more debug messages. */
  39 /*#define ENABLE_CA0132_DEBUG*/
  40 /* Enable this to see controls for tuning purpose. */
  41 /*#define ENABLE_TUNING_CONTROLS*/
  42
  43 #define FLOAT_ZERO      0x00000000
  44 #define FLOAT_ONE       0x3f800000
  45 #define FLOAT_TWO       0x40000000
  46 #define FLOAT_MINUS_5   0xc0a00000
  47 #define FLOAT_60        0x42700000;
  48
  49 #define UNSOL_TAG_HP    0x10
  50 #define UNSOL_TAG_AMIC1 0x12
  51 #define UNSOL_TAG_DSP   0x16
  52
  53 #define SUCCEEDED(_x)         (((int)(_x)) >= 0)
  54 #define FAILED(_x)            (((int)(_x)) < 0)
  55
  56 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  57 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  58
  59 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  60 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  61 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  62
  63 #define MASTERCONTROL                           0x80
  64 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
  65 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  66
  67 #define WIDGET_CHIP_CTRL      0x15
  68 #define WIDGET_DSP_CTRL       0x16
  69
  70 #define MEM_CONNID_MICIN1     3
  71 #define MEM_CONNID_MICIN2     5
  72 #define MEM_CONNID_MICOUT1    12
  73 #define MEM_CONNID_MICOUT2    14
  74 #define MEM_CONNID_WUH        10
  75 #define MEM_CONNID_DSP        16
  76 #define MEM_CONNID_DMIC       100
  77
  78 #define SCP_SET    0
  79 #define SCP_GET    1
  80
  81 #define SPEQ_FILE  "ctspeq.bin"
  82 #define EFX_FILE   "ctefx.bin"
  83
  84 MODULE_FIRMWARE(SPEQ_FILE);
  85 MODULE_FIRMWARE(EFX_FILE);
  86
  87 /* Debug message controls */
  88 #ifdef ENABLE_CA0132_DEBUG
  89
  90 #define CTASSERT(x) \
  91         { if (!(x)) snd_printdd(KERN_ERR "CTASSERT failed.\n"); }
  92
  93 #define CA0132_LOG(fmt, args...)    snd_printdd(fmt, ##args)
  94 #define CA0132_DSP_LOG(msg)         snd_printdd(KERN_INFO "[%s]\n", msg)
  95 #define FAIL_MSG(n, s)              fail_debug_out(n, s)
  96
  97 static int fail_debug_out(int status, const char *s)
  98 {
  99         snd_printdd(KERN_ERR "[%s]\n", s);
 100         return status;
 101 }
 102 #else
 103
 104 #define CTASSERT(x)                 do { } while (0)
 105 #define CA0132_LOG(fmt, args...)    do { } while (0)
 106 #define CA0132_DSP_LOG(msg)         do { } while (0)
 107 #define FAIL_MSG(n, s)              fail_debug_out(n, s)
 108
 109 static int fail_debug_out(int status, const char *s)
 110 {
 111         return status;
 112 }
 113 #endif
 114
 115 static char *dirstr[2] = { "Playback", "Capture" };
 116
 117 enum {
 118         SPEAKER_OUT,
 119         HEADPHONE_OUT
 120 };
 121
 122 enum {
 123         DIGITAL_MIC,
 124         LINE_MIC_IN
 125 };
 126
 127 enum {
 128 #define VNODE_START_NID    0x80
 129         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
 130         VNID_MIC,
 131         VNID_HP_SEL,
 132         VNID_AMIC1_SEL,
 133         VNID_HP_ASEL,
 134         VNID_AMIC1_ASEL,
 135         VNODE_END_NID,
 136 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 137
 138 #define EFFECT_START_NID    0x90
 139 #define OUT_EFFECT_START_NID    EFFECT_START_NID
 140         SURROUND = OUT_EFFECT_START_NID,
 141         CRYSTALIZER,
 142         DIALOG_PLUS,
 143         SMART_VOLUME,
 144         X_BASS,
 145         EQUALIZER,
 146         OUT_EFFECT_END_NID,
 147 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 148
 149 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 150         ECHO_CANCELLATION = IN_EFFECT_START_NID,
 151         VOICE_FOCUS,
 152         MIC_SVM,
 153         NOISE_REDUCTION,
 154         KEY_CLICK,
 155         IN_EFFECT_END_NID,
 156 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 157
 158         VOICEFX = IN_EFFECT_END_NID,
 159         PLAY_ENHANCEMENT,
 160         CRYSTAL_VOICE,
 161         EFFECT_END_NID
 162 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 163 };
 164
 165 /* Effects values size*/
 166 #define EFFECT_VALS_MAX_COUNT 12
 167
 168 #define DSP_CAPTURE_INIT_LATENCY        0
 169 #define DSP_CRYSTAL_VOICE_LATENCY       124
 170 #define DSP_PLAYBACK_INIT_LATENCY       13
 171 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
 172 #define DSP_SPEAKER_OUT_LATENCY         7
 173
 174 struct ct_effect {
 175         char name[44];
 176         hda_nid_t nid;
 177         int mid; /*effect module ID*/
 178         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 179         int direct; /* 0:output; 1:input*/
 180         int params; /* number of default non-on/off params */
 181         /*effect default values, 1st is on/off. */
 182         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 183 };
 184
 185 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 186         { "Surround",
 187                 SURROUND,
 188                 0x96,
 189                 {0, 1},
 190                 0,
 191                 1,
 192                 {0x3F800000, 0x3F2B851F}
 193         },
 194         { "Crystalizer",
 195                 CRYSTALIZER,
 196                 0x96,
 197                 {7, 8},
 198                 0,
 199                 1,
 200                 {0x3F800000, 0x3F266666}
 201         },
 202         { "Dialog Plus",
 203                 DIALOG_PLUS,
 204                 0x96,
 205                 {2, 3},
 206                 0,
 207                 1,
 208                 {0x00000000, 0x3F000000}
 209         },
 210         { "Smart Volume",
 211                 SMART_VOLUME,
 212                 0x96,
 213                 {4, 5, 6},
 214                 0,
 215                 2,
 216                 {0x3F800000, 0x3F3D70A4, 0x00000000}
 217         },
 218         { "X-Bass",
 219                 X_BASS,
 220                 0x96,
 221                 {24, 23, 25},
 222                 0,
 223                 2,
 224                 {0x3F800000, 0x42A00000, 0x3F000000}
 225         },
 226         { "Equalizer",
 227                 EQUALIZER,
 228                 0x96,
 229                 {9, 10, 11, 12, 13, 14,
 230                         15, 16, 17, 18, 19, 20},
 231                 0,
 232                 11,
 233                 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 234                  0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 235                  0x00000000, 0x00000000}
 236         },
 237         { "Echo Cancellation",
 238                 ECHO_CANCELLATION,
 239                 0x95,
 240                 {0, 1, 2, 3},
 241                 1,
 242                 3,
 243                 {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 244         },
 245         { "Voice Focus",
 246                 VOICE_FOCUS,
 247                 0x95,
 248                 {6, 7, 8, 9},
 249                 1,
 250                 3,
 251                 {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 252         },
 253         { "Mic SVM",
 254                 MIC_SVM,
 255                 0x95,
 256                 {44, 45},
 257                 1,
 258                 1,
 259                 {0x00000000, 0x3F3D70A4}
 260         },
 261         { "Noise Reduction",
 262                 NOISE_REDUCTION,
 263                 0x95,
 264                 {4, 5},
 265                 1,
 266                 1,
 267                 {0x3F800000, 0x3F000000}
 268         },
 269         { "Key-Click Reduction",
 270                 KEY_CLICK,
 271                 71,
 272                 {0},
 273                 1,
 274                 0,
 275                 {0x3F800000}
 276         },
 277         { "VoiceFX",
 278                 VOICEFX,
 279                 0x95,
 280                 {10, 11, 12, 13, 14, 15, 16, 17, 18},
 281                 1,
 282                 8,
 283                 {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 0x3F800000,
 284                  0x3F800000, 0x3F800000, 0x00000000, 0x00000000}
 285         }
 286 };
 287
 288
 289 /* Tuning controls */
 290 #ifdef ENABLE_TUNING_CONTROLS
 291
 292 enum {
 293 #define TUNING_CTL_START_NID  0xC0
 294         WEDGE_ANGLE = TUNING_CTL_START_NID,
 295         SVM_LEVEL,
 296         EQUALIZER_BAND_0,
 297         EQUALIZER_BAND_1,
 298         EQUALIZER_BAND_2,
 299         EQUALIZER_BAND_3,
 300         EQUALIZER_BAND_4,
 301         EQUALIZER_BAND_5,
 302         EQUALIZER_BAND_6,
 303         EQUALIZER_BAND_7,
 304         EQUALIZER_BAND_8,
 305         EQUALIZER_BAND_9,
 306         AEC_LEVEL,
 307         TUNING_CTL_END_NID
 308 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 309 };
 310
 311 struct ct_tuning_ctl {
 312         char name[44];
 313         hda_nid_t parent_nid;
 314         hda_nid_t nid;
 315         int mid; /*effect module ID*/
 316         int req; /*effect module request*/
 317         int direct; /* 0:output; 1:input*/
 318         unsigned int def_val;/*effect default values*/
 319 };
 320
 321 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 322         { "Wedge Angle",
 323                 VOICE_FOCUS,
 324                 WEDGE_ANGLE,
 325                 0x95,
 326                 8,
 327                 1,
 328                 0x41F00000
 329         },
 330         { "SVM Level",
 331                 MIC_SVM,
 332                 SVM_LEVEL,
 333                 0x95,
 334                 45,
 335                 1,
 336                 0x3F3D70A4
 337         },
 338         { "EQ Band0",
 339                 EQUALIZER,
 340                 EQUALIZER_BAND_0,
 341                 0x96,
 342                 11,
 343                 0,
 344                 0x00000000
 345         },
 346         { "EQ Band1",
 347                 EQUALIZER,
 348                 EQUALIZER_BAND_1,
 349                 0x96,
 350                 12,
 351                 0,
 352                 0x00000000
 353         },
 354         { "EQ Band2",
 355                 EQUALIZER,
 356                 EQUALIZER_BAND_2,
 357                 0x96,
 358                 13,
 359                 0,
 360                 0x00000000
 361         },
 362         { "EQ Band3",
 363                 EQUALIZER,
 364                 EQUALIZER_BAND_3,
 365                 0x96,
 366                 14,
 367                 0,
 368                 0x00000000
 369         },
 370         { "EQ Band4",
 371                 EQUALIZER,
 372                 EQUALIZER_BAND_4,
 373                 0x96,
 374                 15,
 375                 0,
 376                 0x00000000
 377         },
 378         { "EQ Band5",
 379                 EQUALIZER,
 380                 EQUALIZER_BAND_5,
 381                 0x96,
 382                 16,
 383                 0,
 384                 0x00000000
 385         },
 386         { "EQ Band6",
 387                 EQUALIZER,
 388                 EQUALIZER_BAND_6,
 389                 0x96,
 390                 17,
 391                 0,
 392                 0x00000000
 393         },
 394         { "EQ Band7",
 395                 EQUALIZER,
 396                 EQUALIZER_BAND_7,
 397                 0x96,
 398                 18,
 399                 0,
 400                 0x00000000
 401         },
 402         { "EQ Band8",
 403                 EQUALIZER,
 404                 EQUALIZER_BAND_8,
 405                 0x96,
 406                 19,
 407                 0,
 408                 0x00000000
 409         },
 410         { "EQ Band9",
 411                 EQUALIZER,
 412                 EQUALIZER_BAND_9,
 413                 0x96,
 414                 20,
 415                 0,
 416                 0x00000000
 417         },
 418         { "AEC Level",
 419                 ECHO_CANCELLATION,
 420                 AEC_LEVEL,
 421                 0x86,
 422                 5,
 423                 1,
 424                 0x41F00000
 425         }
 426 };
 427 #endif
 428
 429 /* Voice FX Presets */
 430 #define VOICEFX_MAX_PARAM_COUNT 9
 431
 432 struct ct_voicefx {
 433         char *name;
 434         hda_nid_t nid;
 435         int mid;
 436         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 437 };
 438
 439 struct ct_voicefx_preset {
 440         char *name; /*preset name*/
 441         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 442 };
 443
 444 struct ct_voicefx ca0132_voicefx = {
 445         "VoiceFX Capture Switch",
 446         VOICEFX,
 447         0x95,
 448         {10, 11, 12, 13, 14, 15, 16, 17, 18}
 449 };
 450
 451 struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 452         { "Neutral",
 453                 { 0x00000000, 0x43C80000, 0x44AF0000,
 454                   0x44FA0000, 0x3F800000, 0x3F800000,
 455                   0x3F800000, 0x00000000, 0x00000000 }
 456         },
 457         { "Female2Male",
 458                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 459                   0x44FA0000, 0x3F19999A, 0x3F866666,
 460                   0x3F800000, 0x00000000, 0x00000000 }
 461         },
 462         { "Male2Female",
 463                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 464                   0x450AC000, 0x4017AE14, 0x3F6B851F,
 465                   0x3F800000, 0x00000000, 0x00000000 }
 466         },
 467         { "ScrappyKid",
 468                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 469                   0x44FA0000, 0x40400000, 0x3F28F5C3,
 470                   0x3F800000, 0x00000000, 0x00000000 }
 471         },
 472         { "Elderly",
 473                 { 0x3F800000, 0x44324000, 0x44BB8000,
 474                   0x44E10000, 0x3FB33333, 0x3FB9999A,
 475                   0x3F800000, 0x3E3A2E43, 0x00000000 }
 476         },
 477         { "Orc",
 478                 { 0x3F800000, 0x43EA0000, 0x44A52000,
 479                   0x45098000, 0x3F266666, 0x3FC00000,
 480                   0x3F800000, 0x00000000, 0x00000000 }
 481         },
 482         { "Elf",
 483                 { 0x3F800000, 0x43C70000, 0x44AE6000,
 484                   0x45193000, 0x3F8E147B, 0x3F75C28F,
 485                   0x3F800000, 0x00000000, 0x00000000 }
 486         },
 487         { "Dwarf",
 488                 { 0x3F800000, 0x43930000, 0x44BEE000,
 489                   0x45007000, 0x3F451EB8, 0x3F7851EC,
 490                   0x3F800000, 0x00000000, 0x00000000 }
 491         },
 492         { "AlienBrute",
 493                 { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 494                   0x451F6000, 0x3F266666, 0x3FA7D945,
 495                   0x3F800000, 0x3CF5C28F, 0x00000000 }
 496         },
 497         { "Robot",
 498                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 499                   0x44FA0000, 0x3FB2718B, 0x3F800000,
 500                   0xBC07010E, 0x00000000, 0x00000000 }
 501         },
 502         { "Marine",
 503                 { 0x3F800000, 0x43C20000, 0x44906000,
 504                   0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 505                   0x3F0A3D71, 0x00000000, 0x00000000 }
 506         },
 507         { "Emo",
 508                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 509                   0x44FA0000, 0x3F800000, 0x3F800000,
 510                   0x3E4CCCCD, 0x00000000, 0x00000000 }
 511         },
 512         { "DeepVoice",
 513                 { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 514                   0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 515                   0x3F800000, 0x00000000, 0x00000000 }
 516         },
 517         { "Munchkin",
 518                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 519                   0x44FA0000, 0x3F800000, 0x3F1A043C,
 520                   0x3F800000, 0x00000000, 0x00000000 }
 521         }
 522 };
 523
 524 enum hda_cmd_vendor_io {
 525         /* for DspIO node */
 526         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 527         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 528
 529         VENDOR_DSPIO_STATUS                  = 0xF01,
 530         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 531         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 532         VENDOR_DSPIO_DSP_INIT                = 0x703,
 533         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 534         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 535
 536         /* for ChipIO node */
 537         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 538         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 539         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 540         VENDOR_CHIPIO_DATA_LOW               = 0x300,
 541         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 542
 543         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 544         VENDOR_CHIPIO_STATUS                 = 0xF01,
 545         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 546         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 547
 548         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 549         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 550
 551         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 552         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 553
 554         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 555         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 556         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 557         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 558         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 559         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 560         VENDOR_CHIPIO_PARAM_SET              = 0x710,
 561         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 562
 563         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 564         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 565         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 566         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 567
 568         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 569         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 570         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 571         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 572
 573         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 574         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 575         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 576         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 577         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 578         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 579
 580         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 581 };
 582
 583 enum control_flag_id {
 584         /* Connection manager stream setup is bypassed/enabled */
 585         CONTROL_FLAG_C_MGR                  = 0,
 586         /* DSP DMA is bypassed/enabled */
 587         CONTROL_FLAG_DMA                    = 1,
 588         /* 8051 'idle' mode is disabled/enabled */
 589         CONTROL_FLAG_IDLE_ENABLE            = 2,
 590         /* Tracker for the SPDIF-in path is bypassed/enabled */
 591         CONTROL_FLAG_TRACKER                = 3,
 592         /* DigitalOut to Spdif2Out connection is disabled/enabled */
 593         CONTROL_FLAG_SPDIF2OUT              = 4,
 594         /* Digital Microphone is disabled/enabled */
 595         CONTROL_FLAG_DMIC                   = 5,
 596         /* ADC_B rate is 48 kHz/96 kHz */
 597         CONTROL_FLAG_ADC_B_96KHZ            = 6,
 598         /* ADC_C rate is 48 kHz/96 kHz */
 599         CONTROL_FLAG_ADC_C_96KHZ            = 7,
 600         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 601         CONTROL_FLAG_DAC_96KHZ              = 8,
 602         /* DSP rate is 48 kHz/96 kHz */
 603         CONTROL_FLAG_DSP_96KHZ              = 9,
 604         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 605         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 606         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 607         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 608         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 609         CONTROL_FLAG_DECODE_LOOP            = 12,
 610         /* De-emphasis filter on DAC-1 disabled/enabled */
 611         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 612         /* De-emphasis filter on DAC-2 disabled/enabled */
 613         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 614         /* De-emphasis filter on DAC-3 disabled/enabled */
 615         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 616         /* High-pass filter on ADC_B disabled/enabled */
 617         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 618         /* High-pass filter on ADC_C disabled/enabled */
 619         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 620         /* Common mode on Port_A disabled/enabled */
 621         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 622         /* Common mode on Port_D disabled/enabled */
 623         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 624         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 625         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 626         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 627         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 628         /* ASI rate is 48kHz/96kHz */
 629         CONTROL_FLAG_ASI_96KHZ              = 22,
 630         /* DAC power settings able to control attached ports no/yes */
 631         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 632         /* Clock Stop OK reporting is disabled/enabled */
 633         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 634         /* Number of control flags */
 635         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 636 };
 637
 638 enum control_param_id {
 639         /* 0: None, 1: Mic1In*/
 640         CONTROL_PARAM_VIP_SOURCE               = 1,
 641         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 642         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 643         /* Port A output stage gain setting to use when 16 Ohm output
 644          * impedance is selected*/
 645         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 646         /* Port D output stage gain setting to use when 16 Ohm output
 647          * impedance is selected*/
 648         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 649
 650         /* Stream Control */
 651
 652         /* Select stream with the given ID */
 653         CONTROL_PARAM_STREAM_ID                = 24,
 654         /* Source connection point for the selected stream */
 655         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 656         /* Destination connection point for the selected stream */
 657         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 658         /* Number of audio channels in the selected stream */
 659         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 660         /*Enable control for the selected stream */
 661         CONTROL_PARAM_STREAM_CONTROL           = 28,
 662
 663         /* Connection Point Control */
 664
 665         /* Select connection point with the given ID */
 666         CONTROL_PARAM_CONN_POINT_ID            = 29,
 667         /* Connection point sample rate */
 668         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 669
 670         /* Node Control */
 671
 672         /* Select HDA node with the given ID */
 673         CONTROL_PARAM_NODE_ID                  = 31
 674 };
 675
 676 enum hda_vendor_status_dspio {
 677         /* Success */
 678         VENDOR_STATUS_DSPIO_OK                       = 0x00,
 679         /* Busy, unable to accept new command, the host must retry */
 680         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
 681         /* SCP command queue is full */
 682         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
 683         /* SCP response queue is empty */
 684         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
 685 };
 686
 687 enum hda_vendor_status_chipio {
 688         /* Success */
 689         VENDOR_STATUS_CHIPIO_OK   = 0x00,
 690         /* Busy, unable to accept new command, the host must retry */
 691         VENDOR_STATUS_CHIPIO_BUSY = 0x01
 692 };
 693
 694 enum ca0132_sample_rate {
 695         SR_6_000        = 0x00,
 696         SR_8_000        = 0x01,
 697         SR_9_600        = 0x02,
 698         SR_11_025       = 0x03,
 699         SR_16_000       = 0x04,
 700         SR_22_050       = 0x05,
 701         SR_24_000       = 0x06,
 702         SR_32_000       = 0x07,
 703         SR_44_100       = 0x08,
 704         SR_48_000       = 0x09,
 705         SR_88_200       = 0x0A,
 706         SR_96_000       = 0x0B,
 707         SR_144_000      = 0x0C,
 708         SR_176_400      = 0x0D,
 709         SR_192_000      = 0x0E,
 710         SR_384_000      = 0x0F,
 711
 712         SR_COUNT        = 0x10,
 713
 714         SR_RATE_UNKNOWN = 0x1F
 715 };
 716
 717 enum dsp_download_state {
 718         DSP_DOWNLOAD_FAILED = -1,
 719         DSP_DOWNLOAD_INIT   = 0,
 720         DSP_DOWNLOADING     = 1,
 721         DSP_DOWNLOADED      = 2
 722 };
 723
 724 struct hda_stream_format {
 725         unsigned int   sample_rate;
 726         unsigned short valid_bits_per_sample;
 727         unsigned short container_size;
 728         unsigned short number_channels;
 729 };
 730
 731 /* retrieve parameters from hda format */
 732 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
 733 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
 734 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
 735 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
 736
 737 struct ca0132_spec {
 738         struct snd_kcontrol_new *mixers[5];
 739         unsigned int num_mixers;
 740         const struct hda_verb *base_init_verbs;
 741         const struct hda_verb *base_exit_verbs;
 742         const struct hda_verb *init_verbs[5];
 743         unsigned int num_init_verbs;  /* exclude base init verbs */
 744         struct auto_pin_cfg autocfg;
 745
 746         /* Nodes configurations */
 747         struct hda_multi_out multiout;
 748         hda_nid_t out_pins[5];
 749         hda_nid_t dacs[5];
 750         unsigned int num_outputs;
 751         hda_nid_t input_pins[5];
 752         hda_nid_t adcs[5];
 753         unsigned int num_inputs;
 754         hda_nid_t shared_mic_nid;
 755         hda_nid_t shared_out_nid;
 756         struct hda_pcm pcm_rec[5];  /* PCM information */
 757
 758         /* chip access */
 759         struct mutex chipio_mutex; /* chip access mutex */
 760         u32 curr_chip_addx;
 761
 762         /* DSP download related */
 763         enum dsp_download_state dsp_state;
 764         unsigned int dsp_stream_id;
 765         unsigned int wait_scp;
 766         unsigned int wait_scp_header;
 767         unsigned int wait_num_data;
 768         unsigned int scp_resp_header;
 769         unsigned int scp_resp_data[4];
 770         unsigned int scp_resp_count;
 771
 772         /* mixer and effects related */
 773         unsigned char dmic_ctl;
 774         int cur_out_type;
 775         int cur_mic_type;
 776         long vnode_lvol[VNODES_COUNT];
 777         long vnode_rvol[VNODES_COUNT];
 778         long vnode_lswitch[VNODES_COUNT];
 779         long vnode_rswitch[VNODES_COUNT];
 780         long effects_switch[EFFECTS_COUNT];
 781         long voicefx_val;
 782         long cur_mic_boost;
 783
 784         struct hda_codec *codec;
 785         struct delayed_work unsol_hp_work;
 786
 787         #ifdef ENABLE_TUNING_CONTROLS
 788         long cur_ctl_vals[TUNING_CTLS_COUNT];
 789         #endif
 790 };
 791
 792 /*
 793  * CA0132 codec access
 794  */
 795 unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
 796                 unsigned int verb, unsigned int parm, unsigned int *res)
 797 {
 798         unsigned int response;
 799         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
 800         *res = response;
 801
 802         return ((response == -1) ? -1 : 0);
 803 }
 804
 805 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
 806                 unsigned short converter_format, unsigned int *res)
 807 {
 808         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
 809                                 converter_format & 0xffff, res);
 810 }
 811
 812 static int codec_set_converter_stream_channel(struct hda_codec *codec,
 813                                 hda_nid_t nid, unsigned char stream,
 814                                 unsigned char channel, unsigned int *res)
 815 {
 816         unsigned char converter_stream_channel = 0;
 817
 818         converter_stream_channel = (stream << 4) | (channel & 0x0f);
 819         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
 820                                 converter_stream_channel, res);
 821 }
 822
 823 /*
 824  * CA0132 chip access stuffs
 825  */
 826 static int chipio_send(struct hda_codec *codec,
 827                        unsigned int reg,
 828                        u32 data)
 829 {
 830         unsigned int res;
 831         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
 832
 833         /* send bits of data specified by reg */
 834         do {
 835                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
 836                                          reg, data);
 837                 if (res == VENDOR_STATUS_CHIPIO_OK)
 838                         return 0;
 839                 msleep(1);
 840         } while (time_before(jiffies, timeout));
 841
 842         CTASSERT(0);
 843         printk(KERN_ERR "CA0132 chipio timed out %x %x\n", reg, data);
 844         return -1;
 845 }
 846
 847 static int chipio_write_addx(struct hda_codec *codec, u32 chip_addx)
 848 {
 849         struct ca0132_spec *spec = codec->spec;
 850         int status = 0;
 851
 852         if (spec->curr_chip_addx == chip_addx)
 853                 return 0;
 854
 855         /* send low 16 bits of the address */
 856         status = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
 857                              chip_addx & 0xffff);
 858
 859         if (SUCCEEDED(status)) {
 860                 /* send high 16 bits of the address */
 861                 status = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
 862                                      chip_addx >> 16);
 863         }
 864
 865         CTASSERT(SUCCEEDED(status));
 866         spec->curr_chip_addx = SUCCEEDED(status) ? chip_addx : ~0UL;
 867
 868         return status;
 869 }
 870
 871 static int chipio_write_data(struct hda_codec *codec, u32 data)
 872 {
 873         struct ca0132_spec *spec = codec->spec;
 874         int status = 0;
 875
 876         /* send low 16 bits of the data */
 877         status = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
 878
 879         if (SUCCEEDED(status)) {
 880                 /* send high 16 bits of the data */
 881                 status = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
 882                                      data >> 16);
 883         }
 884
 885         CTASSERT(SUCCEEDED(status));
 886         spec->curr_chip_addx = SUCCEEDED(status) ?
 887                                         (spec->curr_chip_addx + 4) : ~0UL;
 888
 889         return status;
 890 }
 891
 892 static int chipio_write_data_multiple(struct hda_codec *codec,
 893                                       const u32 *data,
 894                                       unsigned int count)
 895 {
 896         int status = 0;
 897
 898         if (data == NULL)
 899                 return FAIL_MSG(-1, "chipio_write_data null ptr");
 900
 901         while ((count-- != 0) && (status == 0))
 902                 status = chipio_write_data(codec, *data++);
 903
 904         return status;
 905 }
 906
 907 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
 908 {
 909         struct ca0132_spec *spec = codec->spec;
 910         int status = 0;
 911
 912         /* post read */
 913         status = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
 914
 915         if (SUCCEEDED(status)) {
 916                 /* read status */
 917                 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
 918         }
 919
 920         if (SUCCEEDED(status)) {
 921                 /* read data */
 922                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
 923                                            VENDOR_CHIPIO_HIC_READ_DATA, 0);
 924         }
 925
 926         CTASSERT(SUCCEEDED(status));
 927         spec->curr_chip_addx = SUCCEEDED(status) ?
 928                                         (spec->curr_chip_addx + 4) : ~0UL;
 929
 930         return status;
 931 }
 932
 933 static int chipio_write(struct hda_codec *codec, u32 chip_addx,
 934                         const u32 data)
 935 {
 936         struct ca0132_spec *spec = codec->spec;
 937         int status;
 938
 939         mutex_lock(&spec->chipio_mutex);
 940         status = chipio_write_addx(codec, chip_addx);
 941         if (SUCCEEDED(status))
 942                 status = chipio_write_data(codec, data);
 943         mutex_unlock(&spec->chipio_mutex);
 944
 945         return status;
 946 }
 947
 948 static int chipio_write_multiple(struct hda_codec *codec,
 949                                  u32 chip_addx,
 950                                  const u32 *data,
 951                                  unsigned int count)
 952 {
 953         struct ca0132_spec *spec = codec->spec;
 954         int status;
 955
 956         mutex_lock(&spec->chipio_mutex);
 957         status = chipio_write_addx(codec, chip_addx);
 958         if (SUCCEEDED(status))
 959                 status = chipio_write_data_multiple(codec, data, count);
 960         mutex_unlock(&spec->chipio_mutex);
 961
 962         return status;
 963 }
 964
 965 static int chipio_read(struct hda_codec *codec, u32 chip_addx,
 966                        unsigned int *data)
 967 {
 968         struct ca0132_spec *spec = codec->spec;
 969         int status;
 970
 971         mutex_lock(&spec->chipio_mutex);
 972         status = chipio_write_addx(codec, chip_addx);
 973         if (SUCCEEDED(status))
 974                 status = chipio_read_data(codec, data);
 975         mutex_unlock(&spec->chipio_mutex);
 976
 977         return status;
 978 }
 979
 980 static void chipio_set_control_flag(struct hda_codec *codec,
 981                                     enum control_flag_id flag_id,
 982                                     bool flag_state)
 983 {
 984         unsigned int val;
 985         unsigned int flag_bit;
 986
 987         flag_bit = (flag_state ? 1 : 0);
 988         val = (flag_bit << 7) | (flag_id);
 989         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
 990                             VENDOR_CHIPIO_FLAG_SET, val);
 991 }
 992
 993 static void chipio_set_control_param(struct hda_codec *codec,
 994                 enum control_param_id param_id, int param_val)
 995 {
 996         struct ca0132_spec *spec = codec->spec;
 997         int val;
 998
 999         if ((param_id < 32) && (param_val < 8)) {
1000                 val = (param_val << 5) | (param_id);
1001                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1002                                     VENDOR_CHIPIO_PARAM_SET, val);
1003         } else {
1004                 mutex_lock(&spec->chipio_mutex);
1005                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1006                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1007                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1008                                             param_id);
1009                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1010                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1011                                             param_val);
1012                 } else
1013                         CA0132_LOG("set_control_param:FAIL! id=0x%x, val=%d\n",
1014                                    param_id, param_val);
1015                 mutex_unlock(&spec->chipio_mutex);
1016         }
1017 }
1018
1019 static void chipio_set_conn_rate(struct hda_codec *codec,
1020                                 int connid, enum ca0132_sample_rate rate)
1021 {
1022         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1023         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1024                                  rate);
1025 }
1026
1027 static void chipio_enable_clocks(struct hda_codec *codec)
1028 {
1029         struct ca0132_spec *spec = codec->spec;
1030
1031         mutex_lock(&spec->chipio_mutex);
1032         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1033                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1034         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1035                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1036         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1037                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1038         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1039                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1040         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1041                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1042         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1043                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1044         mutex_unlock(&spec->chipio_mutex);
1045 }
1046
1047
1048 /*
1049  * CA0132 DSP IO stuffs
1050  */
1051 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1052                       unsigned int data)
1053 {
1054         unsigned int res;
1055         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1056
1057         /* send bits of data specified by reg to dsp */
1058         do {
1059                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1060                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1061                         return res;
1062                 msleep(1);
1063         } while (time_before(jiffies, timeout));
1064
1065         CTASSERT(0);
1066         return -1;
1067 }
1068
1069 static void dspio_write_wait(struct hda_codec *codec)
1070 {
1071         int status;
1072         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1073
1074         do {
1075                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1076                                                 VENDOR_DSPIO_STATUS, 0);
1077                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1078                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1079                         break;
1080                 msleep(1);
1081         } while (time_before(jiffies, timeout));
1082 }
1083
1084 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1085 {
1086         struct ca0132_spec *spec = codec->spec;
1087         int status;
1088
1089         dspio_write_wait(codec);
1090
1091         mutex_lock(&spec->chipio_mutex);
1092         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1093                             scp_data & 0xffff);
1094         if (SUCCEEDED(status))
1095                 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1096                                     scp_data >> 16);
1097         mutex_unlock(&spec->chipio_mutex);
1098
1099         /* OK, now check if the write itself has executed*/
1100         if (SUCCEEDED(status))
1101                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1102                                             VENDOR_DSPIO_STATUS, 0);
1103
1104         if (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL)
1105                 CA0132_LOG("dspio_write: SCP_COMMAND_QUEUE_FULL!!!\n\n");
1106
1107         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1108                         -1 : 0;
1109 }
1110
1111 static int dspio_write_multiple(struct hda_codec *codec,
1112                                 unsigned int *buffer, unsigned int size)
1113 {
1114         int status = 0;
1115         unsigned int count;
1116
1117         if ((buffer == NULL))
1118                 return -1;
1119
1120         count = 0;
1121         while (count < size) {
1122                 status = dspio_write(codec, *buffer++);
1123                 if (status != 0)
1124                         break;
1125                 count++;
1126         }
1127
1128         return status;
1129 }
1130
1131 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1132 {
1133         int status;
1134
1135         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1136         if (SUCCEEDED(status))
1137                 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1138
1139         if (FAILED(status) ||
1140             (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1141                 return -1;
1142
1143         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1144                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
1145
1146         return 0;
1147 }
1148
1149 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1150                                unsigned int *buf_size, unsigned int size_count)
1151 {
1152         int status = 0;
1153         unsigned int size = *buf_size;
1154         unsigned int count;
1155         unsigned int skip_count;
1156         unsigned int dummy;
1157
1158         if ((buffer == NULL))
1159                 return -1;
1160
1161         count = 0;
1162         while (count < size && count < size_count) {
1163                 status = dspio_read(codec, buffer++);
1164                 if (status != 0)
1165                         break;
1166                 count++;
1167         }
1168
1169         skip_count = count;
1170         if (SUCCEEDED(status)) {
1171                 while (skip_count < size) {
1172                         status = dspio_read(codec, &dummy);
1173                         if (status != 0)
1174                                 break;
1175                         skip_count++;
1176                 }
1177         }
1178         *buf_size = count;
1179
1180         return status;
1181 }
1182
1183 static inline unsigned int
1184 make_scp_header(unsigned int target_id, unsigned int source_id,
1185                 unsigned int get_flag, unsigned int req,
1186                 unsigned int device_flag, unsigned int resp_flag,
1187                 unsigned int error_flag, unsigned int data_size)
1188 {
1189         unsigned int header = 0;
1190
1191         header = (data_size & 0x1f) << 27;
1192         header |= (error_flag & 0x01) << 26;
1193         header |= (resp_flag & 0x01) << 25;
1194         header |= (device_flag & 0x01) << 24;
1195         header |= (req & 0x7f) << 17;
1196         header |= (get_flag & 0x01) << 16;
1197         header |= (source_id & 0xff) << 8;
1198         header |= target_id & 0xff;
1199
1200         return header;
1201 }
1202
1203 static inline void
1204 extract_scp_header(unsigned int header,
1205                    unsigned int *target_id, unsigned int *source_id,
1206                    unsigned int *get_flag, unsigned int *req,
1207                    unsigned int *device_flag, unsigned int *resp_flag,
1208                    unsigned int *error_flag, unsigned int *data_size)
1209 {
1210         if (data_size)
1211                 *data_size = (header >> 27) & 0x1f;
1212         if (error_flag)
1213                 *error_flag = (header >> 26) & 0x01;
1214         if (resp_flag)
1215                 *resp_flag = (header >> 25) & 0x01;
1216         if (device_flag)
1217                 *device_flag = (header >> 24) & 0x01;
1218         if (req)
1219                 *req = (header >> 17) & 0x7f;
1220         if (get_flag)
1221                 *get_flag = (header >> 16) & 0x01;
1222         if (source_id)
1223                 *source_id = (header >> 8) & 0xff;
1224         if (target_id)
1225                 *target_id = header & 0xff;
1226 }
1227
1228 #define SCP_MAX_DATA_WORDS  (16)
1229
1230 /* Structure to contain any SCP message */
1231 struct scp_msg {
1232         unsigned int hdr;
1233         unsigned int data[SCP_MAX_DATA_WORDS];
1234 };
1235
1236 static void dspio_clear_response_queue(struct hda_codec *codec)
1237 {
1238         unsigned int dummy = 0;
1239         int status = -1;
1240
1241         /* clear all from the response queue */
1242         do {
1243                 status = dspio_read(codec, &dummy);
1244         } while (status == 0);
1245 }
1246
1247 static int dspio_get_response_data(struct hda_codec *codec)
1248 {
1249         struct ca0132_spec *spec = codec->spec;
1250         unsigned int data = 0;
1251         unsigned int count;
1252
1253         if (FAILED(dspio_read(codec, &data)))
1254                 return -1;
1255
1256         CA0132_LOG("dspio_get_response_data: 0x%08x\n", data);
1257         if ((data & 0x00ffffff) == spec->wait_scp_header) {
1258                 spec->scp_resp_header = data;
1259                 spec->scp_resp_count = data >> 27;
1260                 count = spec->wait_num_data;
1261                 dspio_read_multiple(codec, spec->scp_resp_data,
1262                                     &spec->scp_resp_count, count);
1263                 return 0;
1264         }
1265
1266         return -1;
1267 }
1268
1269 static int dspio_send_scp_message(struct hda_codec *codec,
1270                                   unsigned char *send_buf,
1271                                   unsigned int send_buf_size,
1272                                   unsigned char *return_buf,
1273                                   unsigned int return_buf_size,
1274                                   unsigned int *bytes_returned)
1275 {
1276         struct ca0132_spec *spec = codec->spec;
1277         int status = -1;
1278         unsigned int scp_send_size = 0;
1279         unsigned int total_size;
1280         bool waiting_for_resp = false;
1281         unsigned int header;
1282         struct scp_msg *ret_msg;
1283         unsigned int resp_src_id, resp_target_id;
1284         unsigned int data_size, src_id, target_id, get_flag, device_flag;
1285
1286         if (bytes_returned)
1287                 *bytes_returned = 0;
1288
1289         /* get scp header from buffer */
1290         header = *((unsigned int *)send_buf);
1291         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1292                            &device_flag, NULL, NULL, &data_size);
1293         scp_send_size = data_size + 1;
1294         total_size = (scp_send_size * 4);
1295
1296         CTASSERT(send_buf_size >= total_size);
1297         if (send_buf_size < total_size)
1298                 return -1;
1299
1300         if (get_flag || device_flag) {
1301                 if (!return_buf || return_buf_size < 4 || !bytes_returned) {
1302                         CTASSERT(0);
1303                         return -1;
1304                 }
1305                 spec->wait_scp_header = *((unsigned int *)send_buf);
1306
1307                 /* swap source id with target id */
1308                 resp_target_id = src_id;
1309                 resp_src_id = target_id;
1310                 spec->wait_scp_header &= 0xffff0000;
1311                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1312                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1313                 spec->wait_scp = 1;
1314                 waiting_for_resp = true;
1315         }
1316
1317         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1318                                       scp_send_size);
1319         if (FAILED(status)) {
1320                 CTASSERT(0);
1321                 spec->wait_scp = 0;
1322                 return status;
1323         }
1324
1325         if (waiting_for_resp) {
1326                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1327                 memset(return_buf, 0, return_buf_size);
1328                 do {
1329                         msleep(1);
1330                 } while (spec->wait_scp && time_before(jiffies, timeout));
1331                 waiting_for_resp = false;
1332                 if (!spec->wait_scp) {
1333                         ret_msg = (struct scp_msg *)return_buf;
1334                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1335                         memcpy(&ret_msg->data, spec->scp_resp_data,
1336                                spec->wait_num_data);
1337                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
1338                         status = 0;
1339                 } else {
1340                         CTASSERT(*bytes_returned == 0);
1341                         status = -1;
1342                 }
1343                 spec->wait_scp = 0;
1344         }
1345
1346         return status;
1347 }
1348
1349 static int dspio_scp(struct hda_codec *codec,
1350                 int mod_id, int req, int dir, void *data, unsigned int len,
1351                 void *reply, unsigned int *reply_len)
1352 {
1353         int status = 0;
1354         struct scp_msg scp_send, scp_reply;
1355         unsigned int ret_bytes, send_size, ret_size;
1356         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1357         unsigned int reply_data_size;
1358
1359         memset(&scp_send, 0, sizeof(scp_send));
1360         memset(&scp_reply, 0, sizeof(scp_reply));
1361
1362         CTASSERT((len == 0 || data != NULL) && len <= SCP_MAX_DATA_WORDS);
1363         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1364                 return -1;
1365
1366         CTASSERT(dir != SCP_GET || reply != NULL);
1367         if (dir == SCP_GET && reply == NULL)
1368                 return FAIL_MSG(-1, "dspio_scp get but has no buffer");
1369
1370         CTASSERT((reply == NULL) || (reply_len != NULL && (*reply_len > 0)));
1371         if (reply != NULL && (reply_len == NULL || (*reply_len == 0)))
1372                 return FAIL_MSG(-1, "dspio_scp bad resp buf len parms");
1373
1374         scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1375                                        0, 0, 0, len/sizeof(unsigned int));
1376         if (data != NULL && len > 0) {
1377                 len = min((unsigned int)(sizeof(scp_send.data)), len);
1378                 memcpy(scp_send.data, data, len);
1379         }
1380
1381         ret_bytes = 0;
1382         send_size = sizeof(unsigned int) + len;
1383         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1384                                         send_size, (unsigned char *)&scp_reply,
1385                                         sizeof(scp_reply), &ret_bytes);
1386
1387 /* for debugging */
1388 #ifdef ENABLE_CA0132_DEBUG
1389 {
1390         unsigned int x, *p, i;
1391         unsigned int source_id;
1392         unsigned int target_id;
1393         unsigned int req;
1394         unsigned int get_flag;
1395         unsigned int resp_flag;
1396         unsigned int device_flag;
1397         unsigned int error_flag;
1398         unsigned int data_size;
1399
1400         memcpy(&x, &scp_send.hdr, sizeof(unsigned int));
1401         extract_scp_header(x, &target_id, &source_id,
1402                            &get_flag, &req, &device_flag, &resp_flag,
1403                            &error_flag, &data_size);
1404
1405         snd_printdd(
1406                 "ScpDispatch ----- REQ: "
1407                 "HDR=0x%08x "
1408                 "SID=%04x "
1409                 "TID=%04x "
1410                 "Req=%04x "
1411                 "GRDE=%d %d %d %d "
1412                 "Siz=%d [ ",
1413                 x,
1414                 source_id,
1415                 target_id,
1416                 req,
1417                 get_flag,
1418                 resp_flag,
1419                 device_flag,
1420                 error_flag,
1421                 data_size);
1422
1423         for (x = 0; x < data_size; x++)
1424                 snd_printdd("0x%08x ", scp_send.data[x].ui);
1425
1426         snd_printdd("]\n");
1427
1428         if (get_flag) {
1429                 if (ret_bytes >= sizeof(scp_reply.hdr)) {
1430                         memcpy(&x, &scp_reply.hdr, sizeof(unsigned int));
1431                         extract_scp_header(x, &target_id, &source_id,
1432                                            &get_flag, &req, &device_flag,
1433                                            &resp_flag, &error_flag, &data_size);
1434
1435                         snd_printdd(
1436                                 "            ----- REP: "
1437                                 "HDR=0x%08x "
1438                                 "SID=%04x "
1439                                 "TID=%04x "
1440                                 "Req=%04x "
1441                                 "GRDE=%d %d %d %d "
1442                                 "Siz=%d [ ",
1443                                 x,
1444                                 source_id,
1445                                 target_id,
1446                                 req,
1447                                 get_flag,
1448                                 resp_flag,
1449                                 device_flag,
1450                                 error_flag,
1451                                 data_size);
1452
1453                         for (x = 0; x < data_size; x++)
1454                                 snd_printdd("0x%08x ", scp_reply.data[x].ui);
1455                 } else {
1456                         snd_printdd("REP: (too short,nbytes=%d) [", ret_bytes);
1457
1458                         for (p = (unsigned int *)&scp_reply, i = 0;
1459                                 i < ret_bytes; p++, i++) {
1460                                 snd_printdd("0x%04x ", *p);
1461                         }
1462                 }
1463                 snd_printdd("]\n");
1464         }
1465 }
1466 #endif
1467
1468         if (FAILED(status))
1469                 return FAIL_MSG(status, "dspio_scp: send scp msg failed");
1470
1471         /* extract send and reply headers members */
1472         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1473                            NULL, NULL, NULL, NULL, NULL);
1474         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1475                            &reply_resp_flag, &reply_error_flag,
1476                            &reply_data_size);
1477
1478         if (!send_get_flag)
1479                 return 0;
1480
1481         if (reply_resp_flag && !reply_error_flag) {
1482                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1483                                         / sizeof(unsigned int);
1484
1485                 CTASSERT(dir == SCP_GET && reply != NULL && reply_len != NULL);
1486
1487                 if (*reply_len < ret_size*sizeof(unsigned int)) {
1488                         status = FAIL_MSG(-1, "reply too long for buf");
1489                 } else if (ret_size != reply_data_size) {
1490                         status = FAIL_MSG(-1, "RetLen and HdrLen .NE.");
1491                 } else {
1492                         *reply_len = ret_size*sizeof(unsigned int);
1493                         memcpy(reply, scp_reply.data, *reply_len);
1494                 }
1495         } else {
1496                 status = FAIL_MSG(-1, "reply ill-formed or errflag set");
1497         }
1498
1499         return status;
1500 }
1501
1502 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1503                         int req, void *data, unsigned int len)
1504 {
1505         return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1506 }
1507
1508 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1509 {
1510         int status = 0;
1511         unsigned int size = sizeof(dma_chan);
1512
1513         CA0132_DSP_LOG("     dspio_alloc_dma_chan() -- begin");
1514         status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1515                         SCP_GET, NULL, 0, dma_chan, &size);
1516
1517         if (FAILED(status)) {
1518                 CA0132_DSP_LOG("dspio_alloc_dma_chan: SCP Failed");
1519                 return -1;
1520         }
1521
1522         if ((*dma_chan + 1) == 0) {
1523                 CA0132_DSP_LOG("no free dma channels to allocate");
1524                 return -1;
1525         }
1526
1527         CA0132_LOG("dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1528         CA0132_DSP_LOG("     dspio_alloc_dma_chan() -- complete");
1529
1530         return status;
1531 }
1532
1533 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1534 {
1535         int status = 0;
1536         unsigned int dummy = 0;
1537
1538         CA0132_DSP_LOG("     dspio_free_dma_chan() -- begin");
1539         CA0132_LOG("dspio_free_dma_chan: chan=%d\n", dma_chan);
1540
1541         status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1542                            SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1543
1544         if (FAILED(status)) {
1545                 CA0132_DSP_LOG("dspio_free_dma_chan: SCP Failed");
1546                 return -1;
1547         }
1548
1549         CA0132_DSP_LOG("     dspio_free_dma_chan() -- complete");
1550
1551         return status;
1552 }
1553
1554 /*
1555  * CA0132 DSP access stuffs
1556  */
1557 static int dsp_set_run_state(struct hda_codec *codec)
1558 {
1559         unsigned int dbg_ctrl_reg;
1560         unsigned int halt_state;
1561         int err;
1562
1563         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1564         if (err < 0)
1565                 return err;
1566
1567         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1568                       DSP_DBGCNTL_STATE_LOBIT;
1569
1570         if (halt_state != 0) {
1571                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1572                                   DSP_DBGCNTL_SS_MASK);
1573                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1574                                    dbg_ctrl_reg);
1575                 if (err < 0)
1576                         return err;
1577
1578                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1579                                 DSP_DBGCNTL_EXEC_MASK;
1580                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1581                                    dbg_ctrl_reg);
1582                 if (err < 0)
1583                         return err;
1584         }
1585
1586         return 0;
1587 }
1588
1589 static int dsp_reset(struct hda_codec *codec)
1590 {
1591         unsigned int res;
1592         int retry = 20;
1593
1594         CA0132_LOG("dsp_reset\n");
1595         do {
1596                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1597                 retry--;
1598         } while (res == -1 && retry);
1599
1600         if (!retry) {
1601                 CA0132_LOG("dsp_reset timeout\n");
1602                 return -1;
1603         }
1604
1605         return 0;
1606 }
1607
1608 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1609                                         bool *code, bool *yram)
1610 {
1611         *code = *yram = false;
1612
1613         if (UC_RANGE(chip_addx, 1)) {
1614                 *code = true;
1615                 return UC_OFF(chip_addx);
1616         } else if (X_RANGE_ALL(chip_addx, 1)) {
1617                 return X_OFF(chip_addx);
1618         } else if (Y_RANGE_ALL(chip_addx, 1)) {
1619                 *yram = true;
1620                 return Y_OFF(chip_addx);
1621         }
1622
1623         return (unsigned int)INVALID_CHIP_ADDRESS;
1624 }
1625
1626 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1627 {
1628         unsigned int dma_chnlstart_reg;
1629
1630         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1631
1632         return ((dma_chnlstart_reg & (1 <<
1633                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1634 }
1635
1636 static int dsp_dma_setup_common(struct hda_codec *codec,
1637                                 unsigned int chip_addx,
1638                                 unsigned int dma_chan,
1639                                 unsigned int port_map_mask,
1640                                 bool ovly)
1641 {
1642         int status = 0;
1643         unsigned int chnl_prop;
1644         unsigned int dsp_addx;
1645         unsigned int active;
1646         bool code, yram;
1647
1648         CA0132_DSP_LOG("-- dsp_dma_setup_common() -- Begin ---------");
1649
1650         CTASSERT(dma_chan < DSPDMAC_DMA_CFG_CHANNEL_COUNT);
1651         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT)
1652                 return FAIL_MSG(-1, "dma chan num invalid");
1653
1654         if (dsp_is_dma_active(codec, dma_chan))
1655                 return FAIL_MSG(-1, "dma already active");
1656
1657         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1658
1659         if (dsp_addx == INVALID_CHIP_ADDRESS)
1660                 return FAIL_MSG(-1, "invalid chip addr");
1661
1662         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1663         active = 0;
1664
1665         CA0132_DSP_LOG("   dsp_dma_setup_common()    start reg pgm");
1666
1667         if (ovly) {
1668                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1669                                      &chnl_prop);
1670
1671                 if (FAILED(status))
1672                         return FAIL_MSG(-1, "read CHNLPROP Reg fail");
1673
1674                 CA0132_DSP_LOG("   dsp_dma_setup_common()    Read CHNLPROP");
1675         }
1676
1677         if (!code)
1678                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1679         else
1680                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1681
1682         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1683
1684         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1685         if (FAILED(status))
1686                 return FAIL_MSG(-1, "write CHNLPROP Reg fail");
1687
1688         CA0132_DSP_LOG("   dsp_dma_setup_common()    Write CHNLPROP");
1689
1690         if (ovly) {
1691                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1692                                      &active);
1693
1694                 if (FAILED(status))
1695                         return FAIL_MSG(-1, "read ACTIVE Reg fail");
1696
1697                 CA0132_DSP_LOG("   dsp_dma_setup_common()    Read ACTIVE");
1698         }
1699
1700         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1701                 DSPDMAC_ACTIVE_AAR_MASK;
1702
1703         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1704         if (FAILED(status))
1705                 return FAIL_MSG(-1, "write ACTIVE Reg fail");
1706
1707         CA0132_DSP_LOG("   dsp_dma_setup_common()    Write ACTIVE");
1708
1709         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1710                               port_map_mask);
1711         if (FAILED(status))
1712                 return FAIL_MSG(-1, "write AUDCHSEL Reg fail");
1713
1714         CA0132_DSP_LOG("   dsp_dma_setup_common()    Write AUDCHSEL");
1715
1716         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1717                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1718         if (FAILED(status))
1719                 return FAIL_MSG(-1, "write IRQCNT Reg fail");
1720
1721         CA0132_DSP_LOG("   dsp_dma_setup_common()    Write IRQCNT");
1722
1723         CA0132_LOG(
1724                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1725                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1726                    chip_addx, dsp_addx, dma_chan,
1727                    port_map_mask, chnl_prop, active);
1728
1729         CA0132_DSP_LOG("-- dsp_dma_setup_common() -- Complete ---------");
1730
1731         return 0;
1732 }
1733
1734 static int dsp_dma_setup(struct hda_codec *codec,
1735                         unsigned int chip_addx,
1736                         unsigned int count,
1737                         unsigned int dma_chan)
1738 {
1739         int status = 0;
1740         bool code, yram;
1741         unsigned int dsp_addx;
1742         unsigned int addr_field;
1743         unsigned int incr_field;
1744         unsigned int base_cnt;
1745         unsigned int cur_cnt;
1746         unsigned int dma_cfg = 0;
1747         unsigned int adr_ofs = 0;
1748         unsigned int xfr_cnt = 0;
1749         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1750                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1751
1752         CA0132_DSP_LOG("-- dsp_dma_setup() -- Begin ---------");
1753
1754         CTASSERT(count <= max_dma_count);
1755         if (count > max_dma_count)
1756                 return FAIL_MSG(-1, "count too big");
1757
1758         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1759         if (dsp_addx == INVALID_CHIP_ADDRESS)
1760                 return FAIL_MSG(-1, "invalid chip addr");
1761
1762         CA0132_DSP_LOG("   dsp_dma_setup()    start reg pgm");
1763
1764         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1765         incr_field   = 0;
1766
1767         if (!code) {
1768                 addr_field <<= 1;
1769                 if (yram)
1770                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1771
1772                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1773         }
1774
1775         CTASSERT((addr_field & DSPDMAC_DMACFG_DBADR_MASK) == addr_field);
1776         dma_cfg = addr_field + incr_field;
1777         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1778                                 dma_cfg);
1779         if (FAILED(status))
1780                 return FAIL_MSG(-1, "write DMACFG Reg fail");
1781
1782         CA0132_DSP_LOG("   dsp_dma_setup()    Write DMACFG");
1783
1784         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1785                                                         (code ? 0 : 1));
1786         CTASSERT((adr_ofs & DSPDMAC_DSPADROFS_BOFS_MASK) == adr_ofs);
1787
1788         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1789                                 adr_ofs);
1790         if (FAILED(status))
1791                 return FAIL_MSG(-1, "write DSPADROFS Reg fail");
1792
1793         CA0132_DSP_LOG("   dsp_dma_setup()    Write DSPADROFS");
1794
1795         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1796         CTASSERT((base_cnt & DSPDMAC_XFRCNT_BCNT_MASK) == base_cnt);
1797
1798         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1799         CTASSERT((cur_cnt  & DSPDMAC_XFRCNT_CCNT_MASK) == cur_cnt);
1800
1801         xfr_cnt = base_cnt | cur_cnt;
1802
1803         status = chipio_write(codec,
1804                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1805         if (FAILED(status))
1806                 return FAIL_MSG(-1, "write XFRCNT Reg fail");
1807
1808         CA0132_DSP_LOG("   dsp_dma_setup()    Write XFRCNT");
1809
1810         CA0132_LOG(
1811                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1812                    "ADROFS=0x%x, XFRCNT=0x%x\n",
1813                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1814
1815         CA0132_DSP_LOG("-- dsp_dma_setup() -- Complete ---------");
1816
1817         return 0;
1818 }
1819
1820 static int dsp_dma_start(struct hda_codec *codec,
1821                          unsigned int dma_chan, bool ovly)
1822 {
1823         unsigned int reg = 0;
1824         int status = 0;
1825
1826         CA0132_DSP_LOG("-- dsp_dma_start() -- Begin ---------");
1827
1828         if (ovly) {
1829                 status = chipio_read(codec,
1830                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1831
1832                 if (FAILED(status))
1833                         return FAIL_MSG(-1, "read CHNLSTART reg fail");
1834
1835                 CA0132_DSP_LOG("-- dsp_dma_start()    Read CHNLSTART");
1836
1837                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1838                                 DSPDMAC_CHNLSTART_DIS_MASK);
1839         }
1840
1841         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1842                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1843         if (FAILED(status))
1844                 return FAIL_MSG(-1, "write CHNLSTART reg fail");
1845
1846         CA0132_DSP_LOG("-- dsp_dma_start() -- Complete ---------");
1847
1848         return status;
1849 }
1850
1851 static int dsp_dma_stop(struct hda_codec *codec,
1852                         unsigned int dma_chan, bool ovly)
1853 {
1854         unsigned int reg = 0;
1855         int status = 0;
1856
1857         CA0132_DSP_LOG("-- dsp_dma_stop() -- Begin ---------");
1858
1859         if (ovly) {
1860                 status = chipio_read(codec,
1861                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1862
1863                 if (FAILED(status))
1864                         return FAIL_MSG(-1, "read CHNLSTART reg fail");
1865
1866                 CA0132_DSP_LOG("-- dsp_dma_stop()    Read CHNLSTART");
1867                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1868                                 DSPDMAC_CHNLSTART_DIS_MASK);
1869         }
1870
1871         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1872                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1873         if (FAILED(status))
1874                 return FAIL_MSG(-1, "write CHNLSTART reg fail");
1875
1876         CA0132_DSP_LOG("-- dsp_dma_stop() -- Complete ---------");
1877
1878         return status;
1879 }
1880
1881 static int dsp_allocate_router_ports(struct hda_codec *codec,
1882                                      unsigned int num_chans,
1883                                      unsigned int ports_per_channel,
1884                                      unsigned int start_device,
1885                                      unsigned int *port_map)
1886 {
1887         int status = 0;
1888         int res;
1889         u8 val;
1890
1891         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1892         if (FAILED(status))
1893                 return status;
1894
1895         val = start_device << 6;
1896         val |= (ports_per_channel - 1) << 4;
1897         val |= num_chans - 1;
1898
1899         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1900                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1901                             val);
1902
1903         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1904                             VENDOR_CHIPIO_PORT_ALLOC_SET,
1905                             MEM_CONNID_DSP);
1906
1907         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1908         if (FAILED(status))
1909                 return status;
1910
1911         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1912                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1913
1914         *port_map = res;
1915
1916         return (res < 0) ? -1 : 0;
1917 }
1918
1919 static int dsp_free_router_ports(struct hda_codec *codec)
1920 {
1921         int status = 0;
1922
1923         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1924         if (FAILED(status))
1925                 return status;
1926
1927         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1928                             VENDOR_CHIPIO_PORT_FREE_SET,
1929                             MEM_CONNID_DSP);
1930
1931         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1932
1933         return status;
1934 }
1935
1936 static int dsp_allocate_ports(struct hda_codec *codec,
1937                         unsigned int num_chans,
1938                         unsigned int rate_multi, unsigned int *port_map)
1939 {
1940         int status = -1;
1941
1942         CA0132_DSP_LOG("     dsp_allocate_ports() -- begin");
1943
1944         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4))
1945                 return FAIL_MSG(status, "bad rate multiple");
1946
1947         status = dsp_allocate_router_ports(codec, num_chans,
1948                                            rate_multi, 0, port_map);
1949
1950         CA0132_DSP_LOG("     dsp_allocate_ports() -- complete");
1951
1952         return status;
1953 }
1954
1955 static int dsp_free_ports(struct hda_codec *codec)
1956 {
1957         int status;
1958
1959         CA0132_DSP_LOG("     dsp_free_ports() -- begin");
1960
1961         status = dsp_free_router_ports(codec);
1962         if (FAILED(status))
1963                 return FAIL_MSG(-1, "free router ports fail");
1964
1965         CA0132_DSP_LOG("     dsp_free_ports() -- complete");
1966
1967         return status;
1968 }
1969
1970 static int dsp_allocate_ports_format(struct hda_codec *codec,
1971                         const unsigned short fmt,
1972                         unsigned int *port_map)
1973 {
1974         int status = -1;
1975         unsigned int num_chans;
1976
1977         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
1978         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
1979         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
1980
1981         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4))
1982                 return FAIL_MSG(-1, "bad rate multiple");
1983
1984         num_chans = get_hdafmt_chs(fmt) + 1;
1985
1986         status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
1987
1988         return status;
1989 }
1990
1991 /*
1992  *  HDA DMA engine stuffs for DSP code download
1993  */
1994 struct dma_engine {
1995         struct hda_codec *codec;
1996         unsigned short m_converter_format;
1997         struct snd_dma_buffer *dmab;
1998         unsigned int buf_size;
1999 };
2000
2001 enum dma_state {
2002         DMA_STATE_STOP  = 0,
2003         DMA_STATE_RUN   = 1
2004 };
2005
2006 static int dma_convert_to_hda_format(
2007                 struct hda_stream_format *stream_format,
2008                 unsigned short *hda_format)
2009 {
2010         unsigned int format_val;
2011
2012         format_val = snd_hda_calc_stream_format(
2013                                 stream_format->sample_rate,
2014                                 stream_format->number_channels,
2015                                 SNDRV_PCM_FORMAT_S32_LE,
2016                                 stream_format->container_size, 0);
2017
2018         if (hda_format)
2019                 *hda_format = (unsigned short)format_val;
2020
2021         return 0;
2022 }
2023
2024 static int dma_reset(struct dma_engine *dma)
2025 {
2026         struct hda_codec *codec = dma->codec;
2027         struct ca0132_spec *spec = codec->spec;
2028         int status;
2029
2030         snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2031
2032         status = snd_hda_codec_load_dsp_prepare(codec,
2033                         dma->m_converter_format,
2034                         dma->buf_size,
2035                         dma->dmab);
2036         if (FAILED(status))
2037                 return status;
2038         spec->dsp_stream_id = status;
2039
2040         return 0;
2041 }
2042
2043 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2044 {
2045         bool cmd;
2046
2047         CA0132_LOG("dma_set_state state=%d\n", state);
2048
2049         switch (state) {
2050         case DMA_STATE_STOP:
2051                 cmd = false;
2052                 break;
2053         case DMA_STATE_RUN:
2054                 cmd = true;
2055                 break;
2056         default:
2057                 return 0;
2058         }
2059
2060         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2061         return 0;
2062 }
2063
2064 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2065 {
2066         return dma->dmab->bytes;
2067 }
2068
2069 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2070 {
2071         return dma->dmab->area;
2072 }
2073
2074 static int dma_xfer(struct dma_engine *dma,
2075                 const unsigned int *data,
2076                 unsigned int count)
2077 {
2078         memcpy(dma->dmab->area, data, count);
2079         return 0;
2080 }
2081
2082 static void dma_get_converter_format(
2083                 struct dma_engine *dma,
2084                 unsigned short *format)
2085 {
2086         if (format)
2087                 *format = dma->m_converter_format;
2088 }
2089
2090 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2091 {
2092         struct ca0132_spec *spec = dma->codec->spec;
2093
2094         return spec->dsp_stream_id;
2095 }
2096
2097
2098 /*
2099  * CA0132 chip DSP image segment stuffs
2100  */
2101 struct dsp_image_seg {
2102         u32 magic;
2103         u32 chip_addr;
2104         u32 count;
2105         u32 data[0];
2106 };
2107
2108 static const u32 g_magic_value = 0x4c46584d;
2109 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2110
2111 static bool is_valid(const struct dsp_image_seg *p)
2112 {
2113         return p->magic == g_magic_value;
2114 }
2115
2116 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2117 {
2118         return g_chip_addr_magic_value == p->chip_addr;
2119 }
2120
2121 static bool is_last(const struct dsp_image_seg *p)
2122 {
2123         return p->count == 0;
2124 }
2125
2126 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2127 {
2128         return sizeof(*p) + p->count*sizeof(u32);
2129 }
2130
2131 static const struct dsp_image_seg *get_next_seg_ptr(
2132                                 const struct dsp_image_seg *p)
2133 {
2134         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2135 }
2136
2137 /*
2138  * CA0132 chip DSP trannsfer stuffs.  For DSP download.
2139  */
2140 #define INVALID_DMA_CHANNEL (~0UL)
2141
2142 static int dspxfr_hci_write(struct hda_codec *codec,
2143                         const struct dsp_image_seg *fls)
2144 {
2145         int status = 0;
2146         const u32 *data;
2147         unsigned int count;
2148
2149         CTASSERT(fls != NULL && fls->chip_addr == g_chip_addr_magic_value);
2150         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value)
2151                 return FAIL_MSG(-1, "hci_write invalid params");
2152
2153         count = fls->count;
2154         data = (u32 *)(fls->data);
2155         while (SUCCEEDED(status) && count >= 2) {
2156                 status = chipio_write(codec, data[0], data[1]);
2157                 if (FAILED(status))
2158                         status = FAIL_MSG(status, "hci_write chipio failed");
2159                 count -= 2;
2160                 data  += 2;
2161         }
2162         return status;
2163 }
2164
2165 static int dspxfr_one_seg(struct hda_codec *codec,
2166                         const struct dsp_image_seg *fls,
2167                         unsigned int reloc,
2168                         struct dma_engine *dma_engine,
2169                         unsigned int dma_chan,
2170                         unsigned int port_map_mask,
2171                         bool ovly)
2172 {
2173         int status = 0;
2174         bool comm_dma_setup_done = false;
2175         const unsigned int *data;
2176         unsigned int chip_addx;
2177         unsigned int words_to_write;
2178         unsigned int buffer_size_words;
2179         unsigned char *buffer_addx;
2180         unsigned short hda_format;
2181         unsigned int sample_rate_div;
2182         unsigned int sample_rate_mul;
2183         unsigned int num_chans;
2184         unsigned int hda_frame_size_words;
2185         unsigned int remainder_words;
2186         const u32 *data_remainder;
2187         u32 chip_addx_remainder;
2188         unsigned int run_size_words;
2189         const struct dsp_image_seg *hci_write = NULL;
2190         unsigned long timeout;
2191         bool dma_active;
2192
2193         CTASSERT(fls != NULL);
2194         if (fls == NULL)
2195                 return -1;
2196         if (is_hci_prog_list_seg(fls)) {
2197                 hci_write = fls;
2198                 fls = get_next_seg_ptr(fls);
2199         }
2200
2201         if (hci_write && (!fls || is_last(fls))) {
2202                 CA0132_LOG("hci_write\n");
2203                 return dspxfr_hci_write(codec, hci_write);
2204         }
2205
2206         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2207                 CA0132_LOG("Invalid Params\n");
2208                 return -1;
2209         }
2210
2211         data = fls->data;
2212         chip_addx = fls->chip_addr,
2213         words_to_write = fls->count;
2214
2215         if (!words_to_write)
2216                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2217         if (reloc)
2218                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2219
2220         if (!UC_RANGE(chip_addx, words_to_write) &&
2221             !X_RANGE_ALL(chip_addx, words_to_write) &&
2222             !Y_RANGE_ALL(chip_addx, words_to_write)) {
2223                 CA0132_LOG("Invalid chip_addx Params\n");
2224                 return -1;
2225         }
2226
2227         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2228                                         sizeof(u32);
2229
2230         buffer_addx = dma_get_buffer_addr(dma_engine);
2231
2232         if (buffer_addx == NULL)
2233                 status = FAIL_MSG(-1, "dma_engine buffer NULL");
2234
2235         dma_get_converter_format(dma_engine, &hda_format);
2236         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2237         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2238         num_chans = get_hdafmt_chs(hda_format) + 1;
2239
2240         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2241                         (num_chans * sample_rate_mul / sample_rate_div));
2242
2243         if (hda_frame_size_words == 0) {
2244                 snd_printdd(KERN_ERR "frmsz zero\n");
2245                 return -EINVAL;
2246         }
2247
2248         buffer_size_words = min(buffer_size_words,
2249                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2250                                 65536 : 32768));
2251         buffer_size_words -= buffer_size_words % hda_frame_size_words;
2252         CA0132_LOG(
2253                    "chpadr=0x%08x frmsz=%u nchan=%u "
2254                    "rate_mul=%u div=%u bufsz=%u\n",
2255                    chip_addx, hda_frame_size_words, num_chans,
2256                    sample_rate_mul, sample_rate_div, buffer_size_words);
2257
2258         CTASSERT(SUCCEEDED(status));
2259         CTASSERT(buffer_addx != NULL);
2260         CTASSERT(buffer_size_words >= hda_frame_size_words);
2261
2262         if (buffer_addx == NULL || buffer_size_words < hda_frame_size_words) {
2263                 status = FAIL_MSG(-1, "dspxfr_one_seg:failed");
2264         }
2265
2266         if (FAILED(status))
2267                 return status;
2268
2269         remainder_words = words_to_write % hda_frame_size_words;
2270         data_remainder = data;
2271         chip_addx_remainder = chip_addx;
2272
2273         data += remainder_words;
2274         chip_addx += remainder_words*sizeof(u32);
2275         words_to_write -= remainder_words;
2276
2277         while ((words_to_write != 0) && SUCCEEDED(status)) {
2278                 run_size_words = min(buffer_size_words, words_to_write);
2279                 CA0132_LOG("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2280                            words_to_write, run_size_words, remainder_words);
2281                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2282                 if (!comm_dma_setup_done && SUCCEEDED(status)) {
2283                         status = dsp_dma_stop(codec, dma_chan, ovly);
2284                         if (SUCCEEDED(status))
2285                                 status = dsp_dma_setup_common(codec, chip_addx,
2286                                                 dma_chan, port_map_mask, ovly);
2287                         comm_dma_setup_done = true;
2288                 }
2289
2290                 if (SUCCEEDED(status))
2291                         status = dsp_dma_setup(codec, chip_addx,
2292                                                 run_size_words, dma_chan);
2293                 if (SUCCEEDED(status))
2294                         status = dsp_dma_start(codec, dma_chan, ovly);
2295                 if (SUCCEEDED(status) && !dsp_is_dma_active(codec, dma_chan))
2296                         status = FAIL_MSG(-1, "dspxfr:DMA did not start");
2297                 if (SUCCEEDED(status))
2298                         status = dma_set_state(dma_engine, DMA_STATE_RUN);
2299                 if (SUCCEEDED(status)) {
2300                         if (remainder_words != 0) {
2301                                 status = chipio_write_multiple(codec,
2302                                                         chip_addx_remainder,
2303                                                         data_remainder,
2304                                                         remainder_words);
2305                                 remainder_words = 0;
2306                         }
2307                         if (hci_write) {
2308                                 status = dspxfr_hci_write(codec, hci_write);
2309                                 hci_write = NULL;
2310                         }
2311
2312                         timeout = jiffies + msecs_to_jiffies(2000);
2313                         do {
2314                                 dma_active = dsp_is_dma_active(codec, dma_chan);
2315                                 if (!dma_active)
2316                                         break;
2317                                 msleep(1);
2318                         } while (time_before(jiffies, timeout));
2319                         if (dma_active)
2320                                 break;
2321                         CA0132_DSP_LOG("+++++ DMA complete");
2322                         dma_set_state(dma_engine, DMA_STATE_STOP);
2323                         status = dma_reset(dma_engine);
2324                         if (FAILED(status))
2325                                 break;
2326                 }
2327
2328                 CTASSERT(run_size_words <= words_to_write);
2329                 data += run_size_words;
2330                 chip_addx += run_size_words*sizeof(u32);
2331                 words_to_write -= run_size_words;
2332         }
2333
2334         if (SUCCEEDED(status) && (remainder_words != 0)) {
2335                 status = chipio_write_multiple(codec, chip_addx_remainder,
2336                                         data_remainder, remainder_words);
2337         }
2338
2339         return status;
2340 }
2341
2342 static int dspxfr_image(struct hda_codec *codec,
2343                         const struct dsp_image_seg *fls_data,
2344                         unsigned int reloc, struct hda_stream_format *format,
2345                         bool ovly)
2346 {
2347         struct ca0132_spec *spec = codec->spec;
2348         int status = 0;
2349         unsigned short hda_format = 0;
2350         unsigned int response;
2351         unsigned char stream_id = 0;
2352         struct dma_engine *dma_engine;
2353         unsigned int dma_chan;
2354         unsigned int port_map_mask;
2355
2356         CTASSERT(fls_data != NULL);
2357         if (fls_data == NULL)
2358                 return -1;
2359
2360         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2361         if (!dma_engine) {
2362                 status = -ENOMEM;
2363                 goto exit;
2364         }
2365
2366         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2367         if (!dma_engine->dmab) {
2368                 status = -ENOMEM;
2369                 goto free_dma_engine;
2370         }
2371
2372         dma_engine->codec = codec;
2373         dma_convert_to_hda_format(format, &hda_format);
2374         dma_engine->m_converter_format = hda_format;
2375         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2376                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2377
2378         dma_chan = 0;
2379         do {
2380                 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2381                                                 hda_format, &response);
2382
2383                 if (FAILED(status)) {
2384                         status = FAIL_MSG(status, "set converter format fail");
2385                         goto free_dma_engine_and_dmab;
2386                 }
2387
2388                 status = snd_hda_codec_load_dsp_prepare(codec,
2389                                         dma_engine->m_converter_format,
2390                                         dma_engine->buf_size,
2391                                         dma_engine->dmab);
2392                 if (FAILED(status))
2393                         break;
2394                 spec->dsp_stream_id = status;
2395
2396                 if (ovly) {
2397                         status = dspio_alloc_dma_chan(codec, &dma_chan);
2398                         if (FAILED(status)) {
2399                                 status = FAIL_MSG(status, "alloc dmachan fail");
2400                                 dma_chan = (unsigned int)INVALID_DMA_CHANNEL;
2401                                 break;
2402                         }
2403                 }
2404
2405                 port_map_mask = 0;
2406                 status = dsp_allocate_ports_format(codec, hda_format,
2407                                                 &port_map_mask);
2408                 if (FAILED(status)) {
2409                         status = FAIL_MSG(status, "alloc parts fail");
2410                         break;
2411                 }
2412
2413                 stream_id = dma_get_stream_id(dma_engine);
2414                 status = codec_set_converter_stream_channel(codec,
2415                                 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2416                 if (FAILED(status)) {
2417                         status = FAIL_MSG(status, "set stream chan fail");
2418                         break;
2419                 }
2420
2421                 while (SUCCEEDED(status) && (fls_data != NULL) &&
2422                                         !is_last(fls_data)) {
2423                         if (!is_valid(fls_data)) {
2424                                 status = FAIL_MSG(-1, "FLS check fail");
2425                                 break;
2426                         }
2427                         status = dspxfr_one_seg(codec, fls_data, reloc,
2428                                                 dma_engine, dma_chan,
2429                                                 port_map_mask, ovly);
2430                         if (is_hci_prog_list_seg(fls_data))
2431                                 fls_data = get_next_seg_ptr(fls_data);
2432
2433                         CTASSERT(fls_data != NULL);
2434                         if ((fls_data != NULL) && !is_last(fls_data))
2435                                 fls_data = get_next_seg_ptr(fls_data);
2436
2437                         CTASSERT(fls_data != NULL);
2438                 }
2439
2440                 if (port_map_mask != 0)
2441                         status = dsp_free_ports(codec);
2442
2443                 if (FAILED(status))
2444                         break;
2445
2446                 status = codec_set_converter_stream_channel(codec,
2447                                         WIDGET_CHIP_CTRL, 0, 0, &response);
2448         } while (0);
2449
2450         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2451                 status = dspio_free_dma_chan(codec, dma_chan);
2452
2453         snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2454 free_dma_engine_and_dmab:
2455         kfree(dma_engine->dmab);
2456 free_dma_engine:
2457         kfree(dma_engine);
2458 exit:
2459         return status;
2460 }
2461
2462 /*
2463  * CA0132 DSP download stuffs.
2464  */
2465 static void dspload_post_setup(struct hda_codec *codec)
2466 {
2467         CA0132_DSP_LOG("---- dspload_post_setup ------");
2468
2469         /*set DSP speaker to 2.0 configuration*/
2470         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2471         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2472
2473         /*update write pointer*/
2474         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2475 }
2476
2477 static int dspload_image(struct hda_codec *codec,
2478                         const struct dsp_image_seg *fls,
2479                         bool ovly,
2480                         unsigned int reloc,
2481                         bool autostart,
2482                         int router_chans)
2483 {
2484         int status = 0;
2485         struct hda_stream_format stream_format;
2486
2487         CA0132_DSP_LOG("---- dspload_image begin ------");
2488         if (router_chans == 0) {
2489                 if (!ovly)
2490                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2491                 else
2492                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2493         }
2494
2495         stream_format.sample_rate = 48000;
2496         stream_format.number_channels = (unsigned short)router_chans;
2497
2498         while (stream_format.number_channels > 16) {
2499                 stream_format.sample_rate *= 2;
2500                 stream_format.number_channels /= 2;
2501         }
2502
2503         stream_format.container_size = 32;
2504         stream_format.valid_bits_per_sample = 32;
2505
2506         do {
2507                 CA0132_DSP_LOG("Ready to program DMA");
2508                 if (!ovly)
2509                         status = dsp_reset(codec);
2510
2511                 if (FAILED(status))
2512                         break;
2513
2514                 CA0132_DSP_LOG("dsp_reset() complete");
2515                 status = dspxfr_image(codec, fls, reloc, &stream_format, ovly);
2516
2517                 if (FAILED(status))
2518                         break;
2519
2520                 CA0132_DSP_LOG("dspxfr_image() complete");
2521                 if (autostart && !ovly) {
2522                         dspload_post_setup(codec);
2523                         status = dsp_set_run_state(codec);
2524                 }
2525
2526                 CA0132_DSP_LOG("LOAD FINISHED");
2527         } while (0);
2528
2529         return status;
2530 }
2531
2532 static int dspload_get_speakereq_addx(struct hda_codec *codec,
2533                                 unsigned int *x,
2534                                 unsigned int *y)
2535 {
2536         int status = 0;
2537         struct { unsigned short y, x; } speakereq_info;
2538         unsigned int size = sizeof(speakereq_info);
2539
2540         CA0132_DSP_LOG("dspload_get_speakereq_addx() -- begin");
2541         status = dspio_scp(codec, MASTERCONTROL,
2542                         MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS,
2543                         SCP_GET, NULL, 0, &speakereq_info, &size);
2544
2545         if (FAILED(status)) {
2546                 CA0132_DSP_LOG("dspload_get_speakereq_addx: SCP Failed");
2547                 return -1;
2548         }
2549
2550         *x = speakereq_info.x;
2551         *y = speakereq_info.y;
2552         CA0132_LOG("dspload_get_speakereq_addx: X=0x%x Y=0x%x\n", *x, *y);
2553
2554         CA0132_DSP_LOG("dspload_get_speakereq_addx() -- complete");
2555
2556         return status;
2557 }
2558
2559 static const struct firmware *fw_speq;
2560 static const struct firmware *fw_efx;
2561
2562 static int request_firmware_cached(const struct firmware **firmware_p,
2563         const char *name, struct device *device)
2564 {
2565         if (*firmware_p)
2566                 return 0;  /* already loaded */
2567         return request_firmware(firmware_p, name, device);
2568 }
2569
2570 static void release_cached_firmware(void)
2571 {
2572         if (fw_speq) {
2573                 release_firmware(fw_speq);
2574                 fw_speq = NULL;
2575         }
2576         if (fw_efx) {
2577                 release_firmware(fw_efx);
2578                 fw_efx = NULL;
2579         }
2580 }
2581
2582 static int dspload_speakereq(struct hda_codec *codec)
2583 {
2584         int status = 0;
2585         const struct dsp_image_seg *image;
2586         unsigned int x, y;
2587
2588         CA0132_DSP_LOG("dspload_speakereq() -- begin");
2589
2590         if (request_firmware_cached(&fw_speq, SPEQ_FILE,
2591                                     codec->bus->card->dev) != 0)
2592                 return -1;
2593
2594         image = (struct dsp_image_seg *)(fw_speq->data);
2595
2596         status = dspload_get_speakereq_addx(codec, &x, &y);
2597         if (FAILED(status))
2598                 goto done;
2599
2600         status = dspload_image(codec, image, 1, y, 0, 8);
2601
2602 done:
2603         CA0132_DSP_LOG("dspload_speakereq() -- complete");
2604
2605         return status;
2606 }
2607
2608 static bool dspload_is_loaded(struct hda_codec *codec)
2609 {
2610         unsigned int data = 0;
2611         int status = 0;
2612
2613         status = chipio_read(codec, 0x40004, &data);
2614         if (FAILED(status) || (data != 1))
2615                 return false;
2616
2617         return true;
2618 }
2619
2620 static bool dspload_wait_loaded(struct hda_codec *codec)
2621 {
2622         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2623
2624         do {
2625                 if (dspload_is_loaded(codec)) {
2626                         pr_info("DOWNLOAD OK :-) DSP IS RUNNING.\n");
2627                         return true;
2628                 }
2629                 msleep(1);
2630         } while (time_before(jiffies, timeout));
2631
2632         pr_err("DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2633         return false;
2634 }
2635
2636 /*
2637  * PCM stuffs.
2638  */
2639 static void ca0132_setup_stream(struct hda_codec *codec, hda_nid_t nid,
2640                                 u32 stream_tag,
2641                                 int channel_id, int format)
2642 {
2643         unsigned int oldval, newval;
2644
2645         if (!nid)
2646                 return;
2647
2648         CA0132_LOG(
2649                    "ca0132_setup_stream: NID=0x%x, stream=0x%x, "
2650                    "channel=%d, format=0x%x\n",
2651                    nid, stream_tag, channel_id, format);
2652
2653         /* update the format-id if changed */
2654         oldval = snd_hda_codec_read(codec, nid, 0,
2655                                     AC_VERB_GET_STREAM_FORMAT, 0);
2656         if (oldval != format) {
2657                 msleep(20);
2658                 snd_hda_codec_write(codec, nid, 0,
2659                                     AC_VERB_SET_STREAM_FORMAT,
2660                                     format);
2661         }
2662
2663         oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2664         newval = (stream_tag << 4) | channel_id;
2665         if (oldval != newval) {
2666                 snd_hda_codec_write(codec, nid, 0,
2667                                     AC_VERB_SET_CHANNEL_STREAMID,
2668                                     newval);
2669         }
2670 }
2671
2672 static void ca0132_cleanup_stream(struct hda_codec *codec, hda_nid_t nid)
2673 {
2674         unsigned int val;
2675
2676         if (!nid)
2677                 return;
2678
2679         CA0132_LOG("ca0132_cleanup_stream: NID=0x%x\n", nid);
2680
2681         val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2682         if (!val)
2683                 return;
2684
2685         snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0);
2686         snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2687 }
2688
2689 /*
2690  * PCM playbacks
2691  */
2692 static unsigned int ca0132_get_playback_latency(struct hda_codec *codec)
2693 {
2694         struct ca0132_spec *spec = codec->spec;
2695         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2696
2697         if (!dspload_is_loaded(codec))
2698                 return 0;
2699
2700         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2701                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2702                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2703                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2704         }
2705
2706         if (spec->cur_out_type == SPEAKER_OUT)
2707                 latency += DSP_SPEAKER_OUT_LATENCY;
2708         return latency;
2709 }
2710
2711 /* Toggles the audio format to serial and back to parallel. Needed to make sure
2712  * the codec does what we tell it. */
2713 static void ca0132_toggle_dac_format(struct hda_codec *codec)
2714 {
2715         unsigned int aicr;
2716         chipio_read(codec, 0x18B008, &aicr);
2717         aicr = aicr | 0x8;
2718         chipio_write(codec, 0x18B008, aicr);
2719         aicr = aicr & ~0x8;
2720         chipio_write(codec, 0x18B008, aicr);
2721 }
2722
2723 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2724                                        struct hda_codec *codec,
2725                                        unsigned int stream_tag,
2726                                        unsigned int format,
2727                                        struct snd_pcm_substream *substream)
2728 {
2729         struct ca0132_spec *spec = codec->spec;
2730         struct snd_pcm_runtime *runtime = substream->runtime;
2731         unsigned int latency = ca0132_get_playback_latency(codec);
2732
2733         if (spec->dsp_state == DSP_DOWNLOADING) {
2734                 spec->dsp_stream_id = stream_tag;
2735                 return 0;
2736         }
2737
2738         runtime->delay = bytes_to_frames(runtime, (latency * runtime->rate *
2739                                         runtime->byte_align) / 1000);
2740
2741         ca0132_toggle_dac_format(codec);
2742
2743         ca0132_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2744
2745         return 0;
2746 }
2747
2748 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2749                                        struct hda_codec *codec,
2750                                        struct snd_pcm_substream *substream)
2751 {
2752         struct ca0132_spec *spec = codec->spec;
2753
2754         if (spec->dsp_state == DSP_DOWNLOADING)
2755                 return 0;
2756
2757         /*Allow stream some time to flush effects tail*/
2758         msleep(50);
2759
2760         ca0132_cleanup_stream(codec, spec->dacs[0]);
2761         return 0;
2762 }
2763
2764 /*
2765  * PCM capture
2766  */
2767
2768 static unsigned int ca0132_get_capture_latency(struct hda_codec *codec)
2769 {
2770         struct ca0132_spec *spec = codec->spec;
2771         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2772
2773         if (!dspload_is_loaded(codec))
2774                 return 0;
2775
2776         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2777                 latency += DSP_CRYSTAL_VOICE_LATENCY;
2778         return latency;
2779 }
2780
2781 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2782                                       struct hda_codec *codec,
2783                                       unsigned int stream_tag,
2784                                       unsigned int format,
2785                                       struct snd_pcm_substream *substream)
2786 {
2787         struct ca0132_spec *spec = codec->spec;
2788         struct snd_pcm_runtime *runtime = substream->runtime;
2789         unsigned int latency = ca0132_get_capture_latency(codec);
2790
2791         if (spec->dsp_state == DSP_DOWNLOADING)
2792                 return 0;
2793
2794         runtime->delay = bytes_to_frames(runtime, (latency * runtime->rate *
2795                                         runtime->byte_align) / 1000);
2796
2797         ca0132_setup_stream(codec, hinfo->nid, stream_tag, 0, format);
2798         return 0;
2799 }
2800
2801 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2802                                       struct hda_codec *codec,
2803                                       struct snd_pcm_substream *substream)
2804 {
2805         struct ca0132_spec *spec = codec->spec;
2806
2807         if (spec->dsp_state == DSP_DOWNLOADING)
2808                 return 0;
2809
2810         ca0132_cleanup_stream(codec, hinfo->nid);
2811         return 0;
2812 }
2813
2814
2815 /*
2816  * Controls stuffs.
2817  */
2818
2819 /*
2820  * Mixer controls helpers.
2821  */
2822 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2823         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2824           .name = xname, \
2825           .subdevice = HDA_SUBDEV_AMP_FLAG, \
2826           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2827                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2828                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2829           .info = ca0132_volume_info, \
2830           .get = ca0132_volume_get, \
2831           .put = ca0132_volume_put, \
2832           .tlv = { .c = ca0132_volume_tlv }, \
2833           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2834
2835 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2836         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2837           .name = xname, \
2838           .subdevice = HDA_SUBDEV_AMP_FLAG, \
2839           .info = snd_hda_mixer_amp_switch_info, \
2840           .get = ca0132_switch_get, \
2841           .put = ca0132_switch_put, \
2842           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2843
2844 /* stereo */
2845 #define CA0132_CODEC_VOL(xname, nid, dir) \
2846         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2847 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2848         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2849
2850
2851 /* The followings are for tuning of products */
2852 #ifdef ENABLE_TUNING_CONTROLS
2853
2854 static unsigned int voice_focus_vals_lookup[] = {
2855 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2856 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2857 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2858 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2859 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2860 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2861 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2862 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2863 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2864 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2865 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2866 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2867 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2868 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2869 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2870 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2871 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2872 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2873 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2874 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2875 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2876 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2877 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2878 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2879 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2880 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2881 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2882 };
2883
2884 static unsigned int mic_svm_vals_lookup[] = {
2885 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2886 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2887 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2888 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2889 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2890 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2891 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2892 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2893 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2894 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2895 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2896 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2897 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2898 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2899 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2900 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2901 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2902 };
2903
2904 static unsigned int equalizer_vals_lookup[] = {
2905 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2906 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2907 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2908 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2909 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2910 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2911 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2912 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2913 0x41C00000
2914 };
2915
2916 static unsigned int aec_vals_lookup[] = {
2917 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2918 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2919 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2920 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2921 0x41C00000, 0x41C80000, 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000,
2922 0x41F00000, 0x41F80000, 0x42000000, 0x42040000, 0x42080000, 0x420C0000,
2923 0x42100000, 0x42140000, 0x42180000, 0x421C0000, 0x42200000, 0x42240000,
2924 0x42280000, 0x422C0000, 0x42300000, 0x42340000, 0x42380000, 0x423C0000,
2925 0x42400000, 0x42440000, 0x42480000, 0x424C0000, 0x42500000, 0x42540000,
2926 0x42580000, 0x425C0000, 0x42600000, 0x42640000, 0x42680000, 0x426C0000,
2927 0x42700000
2928 };
2929
2930 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2931                           unsigned int *lookup, int idx)
2932 {
2933         int i = 0;
2934
2935         for (i = 0; i < TUNING_CTLS_COUNT; i++)
2936                 if (nid == ca0132_tuning_ctls[i].nid)
2937                         break;
2938
2939         snd_hda_power_up(codec);
2940         dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2941                         ca0132_tuning_ctls[i].req,
2942                         &(lookup[idx]), sizeof(unsigned int));
2943         snd_hda_power_down(codec);
2944
2945         return 1;
2946 }
2947
2948 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2949                           struct snd_ctl_elem_value *ucontrol)
2950 {
2951         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2952         struct ca0132_spec *spec = codec->spec;
2953         hda_nid_t nid = get_amp_nid(kcontrol);
2954         long *valp = ucontrol->value.integer.value;
2955         int idx = nid - TUNING_CTL_START_NID;
2956
2957         *valp = spec->cur_ctl_vals[idx];
2958         return 0;
2959 }
2960
2961 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2962                               struct snd_ctl_elem_info *uinfo)
2963 {
2964         int chs = get_amp_channels(kcontrol);
2965         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2966         uinfo->count = chs == 3 ? 2 : 1;
2967         uinfo->value.integer.min = 20;
2968         uinfo->value.integer.max = 180;
2969         uinfo->value.integer.step = 1;
2970
2971         return 0;
2972 }
2973
2974 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2975                                 struct snd_ctl_elem_value *ucontrol)
2976 {
2977         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2978         struct ca0132_spec *spec = codec->spec;
2979         hda_nid_t nid = get_amp_nid(kcontrol);
2980         long *valp = ucontrol->value.integer.value;
2981         int idx;
2982
2983         idx = nid - TUNING_CTL_START_NID;
2984         /* any change? */
2985         if (spec->cur_ctl_vals[idx] == *valp)
2986                 return 0;
2987
2988         spec->cur_ctl_vals[idx] = *valp;
2989
2990         idx = *valp - 20;
2991         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2992
2993         return 1;
2994 }
2995
2996 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2997                               struct snd_ctl_elem_info *uinfo)
2998 {
2999         int chs = get_amp_channels(kcontrol);
3000         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3001         uinfo->count = chs == 3 ? 2 : 1;
3002         uinfo->value.integer.min = 0;
3003         uinfo->value.integer.max = 100;
3004         uinfo->value.integer.step = 1;
3005
3006         return 0;
3007 }
3008
3009 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3010                                 struct snd_ctl_elem_value *ucontrol)
3011 {
3012         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3013         struct ca0132_spec *spec = codec->spec;
3014         hda_nid_t nid = get_amp_nid(kcontrol);
3015         long *valp = ucontrol->value.integer.value;
3016         int idx;
3017
3018         idx = nid - TUNING_CTL_START_NID;
3019         /* any change? */
3020         if (spec->cur_ctl_vals[idx] == *valp)
3021                 return 0;
3022
3023         spec->cur_ctl_vals[idx] = *valp;
3024
3025         idx = *valp;
3026         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3027
3028         return 0;
3029 }
3030
3031 static int aec_ctl_info(struct snd_kcontrol *kcontrol,
3032                               struct snd_ctl_elem_info *uinfo)
3033 {
3034         int chs = get_amp_channels(kcontrol);
3035         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3036         uinfo->count = chs == 3 ? 2 : 1;
3037         uinfo->value.integer.min = 0;
3038         uinfo->value.integer.max = 60;
3039         uinfo->value.integer.step = 1;
3040
3041         return 0;
3042 }
3043
3044 static int aec_ctl_put(struct snd_kcontrol *kcontrol,
3045                                 struct snd_ctl_elem_value *ucontrol)
3046 {
3047         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3048         struct ca0132_spec *spec = codec->spec;
3049         hda_nid_t nid = get_amp_nid(kcontrol);
3050         long *valp = ucontrol->value.integer.value;
3051         int idx;
3052
3053         idx = nid - TUNING_CTL_START_NID;
3054         /* any change? */
3055         if (spec->cur_ctl_vals[idx] == *valp)
3056                 return 0;
3057
3058         spec->cur_ctl_vals[idx] = *valp;
3059
3060         idx = *valp;
3061         tuning_ctl_set(codec, nid, aec_vals_lookup, idx);
3062
3063         return 0;
3064 }
3065
3066 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3067                               struct snd_ctl_elem_info *uinfo)
3068 {
3069         int chs = get_amp_channels(kcontrol);
3070         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3071         uinfo->count = chs == 3 ? 2 : 1;
3072         uinfo->value.integer.min = 0;
3073         uinfo->value.integer.max = 48;
3074         uinfo->value.integer.step = 1;
3075
3076         return 0;
3077 }
3078
3079 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3080                                 struct snd_ctl_elem_value *ucontrol)
3081 {
3082         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3083         struct ca0132_spec *spec = codec->spec;
3084         hda_nid_t nid = get_amp_nid(kcontrol);
3085         long *valp = ucontrol->value.integer.value;
3086         int idx;
3087
3088         idx = nid - TUNING_CTL_START_NID;
3089         /* any change? */
3090         if (spec->cur_ctl_vals[idx] == *valp)
3091                 return 0;
3092
3093         spec->cur_ctl_vals[idx] = *valp;
3094
3095         idx = *valp;
3096         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3097
3098         return 1;
3099 }
3100
3101 DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3102 DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3103
3104 static int add_tuning_control(struct hda_codec *codec,
3105                                 hda_nid_t pnid, hda_nid_t nid,
3106                                 const char *name, int dir)
3107 {
3108         char namestr[44];
3109         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3110         struct snd_kcontrol_new knew =
3111                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3112
3113         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3114                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3115         knew.tlv.c = 0;
3116         knew.tlv.p = 0;
3117         switch (pnid) {
3118         case VOICE_FOCUS:
3119                 knew.info = voice_focus_ctl_info;
3120                 knew.get = tuning_ctl_get;
3121                 knew.put = voice_focus_ctl_put;
3122                 knew.tlv.p = voice_focus_db_scale;
3123                 break;
3124         case MIC_SVM:
3125                 knew.info = mic_svm_ctl_info;
3126                 knew.get = tuning_ctl_get;
3127                 knew.put = mic_svm_ctl_put;
3128                 break;
3129         case EQUALIZER:
3130                 knew.info = equalizer_ctl_info;
3131                 knew.get = tuning_ctl_get;
3132                 knew.put = equalizer_ctl_put;
3133                 knew.tlv.p = eq_db_scale;
3134                 break;
3135         case ECHO_CANCELLATION:
3136                 knew.info = aec_ctl_info;
3137                 knew.get = tuning_ctl_get;
3138                 knew.put = aec_ctl_put;
3139                 break;
3140         default:
3141                 return 0;
3142         }
3143         knew.private_value =
3144                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3145         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3146         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3147 }
3148
3149 static int add_tuning_ctls(struct hda_codec *codec)
3150 {
3151         int i;
3152         int err;
3153
3154         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3155                 err = add_tuning_control(codec,
3156                                         ca0132_tuning_ctls[i].parent_nid,
3157                                         ca0132_tuning_ctls[i].nid,
3158                                         ca0132_tuning_ctls[i].name,
3159                                         ca0132_tuning_ctls[i].direct);
3160                 if (err < 0)
3161                         return err;
3162         }
3163
3164         return 0;
3165 }
3166
3167 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3168 {
3169         struct ca0132_spec *spec = codec->spec;
3170         int i;
3171
3172         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
3173         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3174         /* SVM level defaults to 0.74. */
3175         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3176
3177         /* EQ defaults to 0dB. */
3178         for (i = 2; i < TUNING_CTLS_COUNT; i++)
3179                 spec->cur_ctl_vals[i] = 24;
3180 }
3181 #endif
3182
3183 static int ca0132_select_out(struct hda_codec *codec)
3184 {
3185         struct ca0132_spec *spec = codec->spec;
3186         unsigned int pin_ctl;
3187         int jack_present;
3188         int auto_jack;
3189         unsigned int tmp;
3190         int err;
3191
3192         CA0132_LOG("ca0132_select_out\n");
3193
3194         snd_hda_power_up(codec);
3195
3196         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3197
3198         if (auto_jack)
3199                 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3200         else
3201                 jack_present =
3202                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3203
3204         if (jack_present)
3205                 spec->cur_out_type = HEADPHONE_OUT;
3206         else
3207                 spec->cur_out_type = SPEAKER_OUT;
3208
3209         if (spec->cur_out_type == SPEAKER_OUT) {
3210                 CA0132_LOG("ca0132_select_out speaker\n");
3211                 /*speaker out config*/
3212                 tmp = FLOAT_ONE;
3213                 err = dspio_set_param(codec, 0x80, 0x04,
3214                                         &tmp, sizeof(unsigned int));
3215                 if (err < 0)
3216                         goto exit;
3217                 /*enable speaker EQ*/
3218                 tmp = FLOAT_ONE;
3219                 err = dspio_set_param(codec, 0x8f, 0x00,
3220                                         &tmp, sizeof(unsigned int));
3221                 if (err < 0)
3222                         goto exit;
3223
3224                 /* Setup EAPD */
3225                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3226                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3227                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3228                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3229                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3230                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3231                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3232                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3233
3234                 /* disable headphone node */
3235                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3236                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3237                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3238                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
3239                                     pin_ctl & 0xBF);
3240                 /* enable speaker node */
3241                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3242                                              AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3243                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3244                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
3245                                     pin_ctl | 0x40);
3246         } else {
3247                 CA0132_LOG("ca0132_select_out hp\n");
3248                 /*headphone out config*/
3249                 tmp = FLOAT_ZERO;
3250                 err = dspio_set_param(codec, 0x80, 0x04,
3251                                         &tmp, sizeof(unsigned int));
3252                 if (err < 0)
3253                         goto exit;
3254                 /*disable speaker EQ*/
3255                 tmp = FLOAT_ZERO;
3256                 err = dspio_set_param(codec, 0x8f, 0x00,
3257                                         &tmp, sizeof(unsigned int));
3258                 if (err < 0)
3259                         goto exit;
3260
3261                 /* Setup EAPD */
3262                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3263                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3264                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3265                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3266                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3267                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3268                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3269                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3270
3271                 /* disable speaker*/
3272                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3273                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3274                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3275                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
3276                                     pin_ctl & 0xBF);
3277                 /* enable headphone*/
3278                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3279                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3280                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3281                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
3282                                     pin_ctl | 0x40);
3283         }
3284
3285 exit:
3286         snd_hda_power_down(codec);
3287
3288         return err < 0 ? err : 0;
3289 }
3290
3291 static void ca0132_unsol_hp_delayed(struct work_struct *work)
3292 {
3293         struct ca0132_spec *spec = container_of(
3294                 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3295         ca0132_select_out(spec->codec);
3296         snd_hda_jack_report_sync(spec->codec);
3297 }
3298
3299 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3300 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3301 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3302
3303 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3304 {
3305         struct ca0132_spec *spec = codec->spec;
3306         unsigned int tmp;
3307
3308         if (!dspload_is_loaded(codec))
3309                 return 0;
3310
3311         /* if CrystalVoice if off, vipsource should be 0 */
3312         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]
3313                         || (val == 0)) {
3314                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3315                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3316                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3317                 if (spec->cur_mic_type == DIGITAL_MIC)
3318                         tmp = FLOAT_TWO;
3319                 else
3320                         tmp = FLOAT_ONE;
3321                 dspio_set_param(codec, 0x80, 0x00, &tmp, sizeof(unsigned int));
3322                 tmp = FLOAT_ZERO;
3323                 dspio_set_param(codec, 0x80, 0x05, &tmp, sizeof(unsigned int));
3324         } else {
3325                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3326                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3327                 if (spec->cur_mic_type == DIGITAL_MIC)
3328                         tmp = FLOAT_TWO;
3329                 else
3330                         tmp = FLOAT_ONE;
3331                 dspio_set_param(codec, 0x80, 0x00, &tmp, sizeof(unsigned int));
3332                 tmp = FLOAT_ONE;
3333                 dspio_set_param(codec, 0x80, 0x05, &tmp, sizeof(unsigned int));
3334                 msleep(20);
3335                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3336         }
3337
3338         return 1;
3339 }
3340
3341 static int ca0132_select_mic(struct hda_codec *codec)
3342 {
3343         struct ca0132_spec *spec = codec->spec;
3344         int jack_present;
3345         int auto_jack;
3346
3347         CA0132_LOG("ca0132_select_mic\n");
3348
3349         snd_hda_power_up(codec);
3350
3351         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3352
3353         if (auto_jack)
3354                 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3355         else
3356                 jack_present =
3357                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3358
3359         if (jack_present)
3360                 spec->cur_mic_type = LINE_MIC_IN;
3361         else
3362                 spec->cur_mic_type = DIGITAL_MIC;
3363
3364         if (spec->cur_mic_type == DIGITAL_MIC) {
3365                 /* enable digital Mic */
3366                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3367                 ca0132_set_dmic(codec, 1);
3368                 ca0132_mic_boost_set(codec, 0);
3369                 /* set voice focus */
3370                 ca0132_effects_set(codec, VOICE_FOCUS,
3371                                    spec->effects_switch
3372                                    [VOICE_FOCUS - EFFECT_START_NID]);
3373         } else {
3374                 /* disable digital Mic */
3375                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3376                 ca0132_set_dmic(codec, 0);
3377                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3378                 /* disable voice focus */
3379                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3380         }
3381
3382         snd_hda_power_down(codec);
3383
3384         return 0;
3385 }
3386
3387 /*
3388  * Check if VNODE settings take effect immediately.
3389  */
3390 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3391                                      hda_nid_t vnid,
3392                                      hda_nid_t *shared_nid)
3393 {
3394         struct ca0132_spec *spec = codec->spec;
3395         hda_nid_t nid;
3396         bool effective = false;
3397
3398         switch (vnid) {
3399         case VNID_SPK:
3400                 nid = spec->shared_out_nid;
3401                 effective = true;
3402                 break;
3403         case VNID_MIC:
3404                 nid = spec->shared_mic_nid;
3405                 effective = true;
3406                 break;
3407         default:
3408                 break;
3409         }
3410
3411         if (effective && shared_nid)
3412                 *shared_nid = nid;
3413
3414         return effective;
3415 }
3416
3417 /*
3418  * The following functions are control change helpers.
3419  * They return 0 if no changed.  Return 1 if changed.
3420  */
3421 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3422 {
3423         struct ca0132_spec *spec = codec->spec;
3424         unsigned int tmp;
3425
3426         /* based on CrystalVoice state to enable VoiceFX. */
3427         if (enable) {
3428                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3429                         FLOAT_ONE : FLOAT_ZERO;
3430         } else {
3431                 tmp = FLOAT_ZERO;
3432         }
3433
3434         dspio_set_param(codec, ca0132_voicefx.mid,
3435                         ca0132_voicefx.reqs[0], &tmp, sizeof(unsigned int));
3436
3437         return 1;
3438 }
3439
3440 static void ca0132_update_latency(struct hda_codec *codec,
3441                                   unsigned int direction)
3442 {
3443         struct ca0132_spec *spec = codec->spec;
3444         unsigned int latency;
3445         struct snd_pcm_substream *substr;
3446         struct snd_pcm_runtime *runtime;
3447
3448         if (spec->dsp_state == DSP_DOWNLOADING)
3449                 return;
3450
3451         latency = (direction == SNDRV_PCM_STREAM_PLAYBACK)
3452                         ? ca0132_get_playback_latency(codec)
3453                         : ca0132_get_capture_latency(codec);
3454
3455         substr = codec->pcm_info->pcm->streams[direction].substream;
3456         while (substr) {
3457                 runtime = substr->runtime;
3458                 /* update latency only when runtime is setup */
3459                 if (runtime && runtime->frame_bits)
3460                         runtime->delay = bytes_to_frames(runtime,
3461                                         (latency * runtime->rate *
3462                                         runtime->byte_align) / 1000);
3463                 substr = substr->next;
3464         }
3465 }
3466
3467 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3468 {
3469         struct ca0132_spec *spec = codec->spec;
3470         unsigned int on;
3471         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3472         int err = 0;
3473         int idx = nid - EFFECT_START_NID;
3474
3475         if ((idx < 0) || (idx >= num_fx))
3476                 return 0; /* no changed */
3477
3478         /* for out effect, qualify with PE */
3479         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3480                 /* if PE if off, turn off out effects. */
3481                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3482                         val = 0;
3483         }
3484
3485         /* for in effect, qualify with CrystalVoice */
3486         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3487                 /* if CrystalVoice if off, turn off in effects. */
3488                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3489                         val = 0;
3490
3491                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3492                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3493                         val = 0;
3494         }
3495
3496         CA0132_LOG("ca0132_effect_set: nid=0x%x, val=%ld\n", nid, val);
3497
3498         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3499         err = dspio_set_param(codec, ca0132_effects[idx].mid,
3500                                 ca0132_effects[idx].reqs[0],
3501                                 &on, sizeof(unsigned int));
3502
3503         ca0132_update_latency(codec, SNDRV_PCM_STREAM_PLAYBACK);
3504         ca0132_update_latency(codec, SNDRV_PCM_STREAM_CAPTURE);
3505
3506         if (err < 0)
3507                 return 0; /* no changed */
3508
3509         return 1;
3510 }
3511
3512 static int ca0132_pe_switch_set(struct hda_codec *codec)
3513 {
3514         struct ca0132_spec *spec = codec->spec;
3515         hda_nid_t nid;
3516         int i, ret = 0;
3517
3518         CA0132_LOG("ca0132_pe_switch_set: val=%ld\n",
3519                    spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3520
3521         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3522         nid = OUT_EFFECT_START_NID;
3523         /* PE affects all out effects */
3524         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3525                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3526
3527         return ret;
3528 }
3529
3530 /* Check if Mic1 is streaming, if so, stop streaming */
3531 static int stop_mic1(struct hda_codec *codec)
3532 {
3533         struct ca0132_spec *spec = codec->spec;
3534         unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3535                                                  AC_VERB_GET_CONV, 0);
3536         if (oldval != 0)
3537                 snd_hda_codec_write(codec, spec->adcs[0], 0,
3538                                     AC_VERB_SET_CHANNEL_STREAMID,
3539                                     0);
3540         return oldval;
3541 }
3542
3543 /* Resume Mic1 streaming if it was stopped. */
3544 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3545 {
3546         struct ca0132_spec *spec = codec->spec;
3547         /* Restore the previous stream and channel */
3548         if (oldval != 0)
3549                 snd_hda_codec_write(codec, spec->adcs[0], 0,
3550                                     AC_VERB_SET_CHANNEL_STREAMID,
3551                                     oldval);
3552 }
3553
3554 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3555 {
3556         struct ca0132_spec *spec = codec->spec;
3557         hda_nid_t nid;
3558         int i, ret = 0;
3559         unsigned int oldval;
3560
3561         CA0132_LOG("ca0132_cvoice_switch_set: val=%ld\n",
3562                    spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3563
3564         i = IN_EFFECT_START_NID - EFFECT_START_NID;
3565         nid = IN_EFFECT_START_NID;
3566         /* CrystalVoice affects all in effects */
3567         for (; nid < IN_EFFECT_END_NID; nid++, i++)
3568                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3569
3570         /* including VoiceFX */
3571         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3572
3573         /* set correct vipsource */
3574         oldval = stop_mic1(codec);
3575         ret |= ca0132_set_vipsource(codec, 1);
3576         resume_mic1(codec, oldval);
3577         return ret;
3578 }
3579
3580 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3581 {
3582         struct ca0132_spec *spec = codec->spec;
3583         int ret = 0;
3584
3585         if (val) /* on */
3586                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3587                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3588         else /* off */
3589                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3590                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3591
3592         return ret;
3593 }
3594
3595 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3596                                 struct snd_ctl_elem_value *ucontrol)
3597 {
3598         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3599         hda_nid_t nid = get_amp_nid(kcontrol);
3600         hda_nid_t shared_nid = 0;
3601         bool effective;
3602         int ret = 0;
3603         struct ca0132_spec *spec = codec->spec;
3604         int auto_jack;
3605
3606         if (nid == VNID_HP_SEL) {
3607                 auto_jack =
3608                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3609                 if (!auto_jack)
3610                         ca0132_select_out(codec);
3611                 return 1;
3612         }
3613
3614         if (nid == VNID_AMIC1_SEL) {
3615                 auto_jack =
3616                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3617                 if (!auto_jack)
3618                         ca0132_select_mic(codec);
3619                 return 1;
3620         }
3621
3622         if (nid == VNID_HP_ASEL) {
3623                 ca0132_select_out(codec);
3624                 return 1;
3625         }
3626
3627         if (nid == VNID_AMIC1_ASEL) {
3628                 ca0132_select_mic(codec);
3629                 return 1;
3630         }
3631
3632         /* if effective conditions, then update hw immediately. */
3633         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3634         if (effective) {
3635                 int dir = get_amp_direction(kcontrol);
3636                 int ch = get_amp_channels(kcontrol);
3637                 unsigned long pval;
3638
3639                 mutex_lock(&codec->control_mutex);
3640                 pval = kcontrol->private_value;
3641                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3642                                                                 0, dir);
3643                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3644                 kcontrol->private_value = pval;
3645                 mutex_unlock(&codec->control_mutex);
3646         }
3647
3648         return ret;
3649 }
3650 /* End of control change helpers. */
3651
3652 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3653                                  struct snd_ctl_elem_info *uinfo)
3654 {
3655         unsigned int items = sizeof(ca0132_voicefx_presets)
3656                                 / sizeof(struct ct_voicefx_preset);
3657
3658         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3659         uinfo->count = 1;
3660         uinfo->value.enumerated.items = items;
3661         if (uinfo->value.enumerated.item >= items)
3662                 uinfo->value.enumerated.item = items - 1;
3663         strcpy(uinfo->value.enumerated.name,
3664                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3665         return 0;
3666 }
3667
3668 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3669                                 struct snd_ctl_elem_value *ucontrol)
3670 {
3671         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3672         struct ca0132_spec *spec = codec->spec;
3673
3674         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3675         return 0;
3676 }
3677
3678 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3679                                 struct snd_ctl_elem_value *ucontrol)
3680 {
3681         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3682         struct ca0132_spec *spec = codec->spec;
3683         int i, err = 0;
3684         int sel = ucontrol->value.enumerated.item[0];
3685         unsigned int items = sizeof(ca0132_voicefx_presets)
3686                                 / sizeof(struct ct_voicefx_preset);
3687
3688         if (sel >= items)
3689                 return 0;
3690
3691         CA0132_LOG("ca0132_voicefx_put: sel=%d, preset=%s\n",
3692                    sel, ca0132_voicefx_presets[sel].name);
3693
3694         /*
3695          * Idx 0 is default.
3696          * Default needs to qualify with CrystalVoice state.
3697          */
3698         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3699                 err = dspio_set_param(codec, ca0132_voicefx.mid,
3700                                 ca0132_voicefx.reqs[i],
3701                                 &(ca0132_voicefx_presets[sel].vals[i]),
3702                                 sizeof(unsigned int));
3703                 if (err < 0)
3704                         break;
3705         }
3706
3707         if (err >= 0) {
3708                 spec->voicefx_val = sel;
3709                 /* enable voice fx */
3710                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3711         }
3712
3713         return 1;
3714 }
3715
3716 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3717                                 struct snd_ctl_elem_value *ucontrol)
3718 {
3719         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3720         struct ca0132_spec *spec = codec->spec;
3721         hda_nid_t nid = get_amp_nid(kcontrol);
3722         int ch = get_amp_channels(kcontrol);
3723         long *valp = ucontrol->value.integer.value;
3724
3725         /* vnode */
3726         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3727                 if (ch & 1) {
3728                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3729                         valp++;
3730                 }
3731                 if (ch & 2) {
3732                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3733                         valp++;
3734                 }
3735                 return 0;
3736         }
3737
3738         /* effects, include PE and CrystalVoice */
3739         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3740                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3741                 return 0;
3742         }
3743
3744         /* mic boost */
3745         if (nid == spec->input_pins[0]) {
3746                 *valp = spec->cur_mic_boost;
3747                 return 0;
3748         }
3749
3750         return 0;
3751 }
3752
3753 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3754                              struct snd_ctl_elem_value *ucontrol)
3755 {
3756         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3757         struct ca0132_spec *spec = codec->spec;
3758         hda_nid_t nid = get_amp_nid(kcontrol);
3759         int ch = get_amp_channels(kcontrol);
3760         long *valp = ucontrol->value.integer.value;
3761         int changed = 1;
3762
3763         CA0132_LOG("ca0132_switch_put: nid=0x%x, val=%ld\n", nid, *valp);
3764
3765         snd_hda_power_up(codec);
3766         /* vnode */
3767         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3768                 if (ch & 1) {
3769                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3770                         valp++;
3771                 }
3772                 if (ch & 2) {
3773                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3774                         valp++;
3775                 }
3776                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3777                 goto exit;
3778         }
3779
3780         /* PE */
3781         if (nid == PLAY_ENHANCEMENT) {
3782                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3783                 changed = ca0132_pe_switch_set(codec);
3784                 goto exit;
3785         }
3786
3787         /* CrystalVoice */
3788         if (nid == CRYSTAL_VOICE) {
3789                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3790                 changed = ca0132_cvoice_switch_set(codec);
3791                 goto exit;
3792         }
3793
3794         /* out and in effects */
3795         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3796             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3797                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3798                 changed = ca0132_effects_set(codec, nid, *valp);
3799                 goto exit;
3800         }
3801
3802         /* mic boost */
3803         if (nid == spec->input_pins[0]) {
3804                 spec->cur_mic_boost = *valp;
3805
3806                 /* Mic boost does not apply to Digital Mic */
3807                 if (spec->cur_mic_type != DIGITAL_MIC)
3808                         changed = ca0132_mic_boost_set(codec, *valp);
3809                 goto exit;
3810         }
3811
3812 exit:
3813         snd_hda_power_down(codec);
3814         return changed;
3815 }
3816
3817 /*
3818  * Volume related
3819  */
3820 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3821                               struct snd_ctl_elem_info *uinfo)
3822 {
3823         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3824         struct ca0132_spec *spec = codec->spec;
3825         hda_nid_t nid = get_amp_nid(kcontrol);
3826         int ch = get_amp_channels(kcontrol);
3827         int dir = get_amp_direction(kcontrol);
3828         unsigned long pval;
3829         int err;
3830
3831         switch (nid) {
3832         case VNID_SPK:
3833                 /* follow shared_out info */
3834                 nid = spec->shared_out_nid;
3835                 mutex_lock(&codec->control_mutex);
3836                 pval = kcontrol->private_value;
3837                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3838                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3839                 kcontrol->private_value = pval;
3840                 mutex_unlock(&codec->control_mutex);
3841                 break;
3842         case VNID_MIC:
3843                 /* follow shared_mic info */
3844                 nid = spec->shared_mic_nid;
3845                 mutex_lock(&codec->control_mutex);
3846                 pval = kcontrol->private_value;
3847                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3848                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3849                 kcontrol->private_value = pval;
3850                 mutex_unlock(&codec->control_mutex);
3851                 break;
3852         default:
3853                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3854         }
3855         return err;
3856 }
3857
3858 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3859                                 struct snd_ctl_elem_value *ucontrol)
3860 {
3861         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3862         struct ca0132_spec *spec = codec->spec;
3863         hda_nid_t nid = get_amp_nid(kcontrol);
3864         int ch = get_amp_channels(kcontrol);
3865         long *valp = ucontrol->value.integer.value;
3866
3867         /* store the left and right volume */
3868         if (ch & 1) {
3869                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3870                 valp++;
3871         }
3872         if (ch & 2) {
3873                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3874                 valp++;
3875         }
3876         return 0;
3877 }
3878
3879 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3880                                 struct snd_ctl_elem_value *ucontrol)
3881 {
3882         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3883         struct ca0132_spec *spec = codec->spec;
3884         hda_nid_t nid = get_amp_nid(kcontrol);
3885         int ch = get_amp_channels(kcontrol);
3886         long *valp = ucontrol->value.integer.value;
3887         hda_nid_t shared_nid = 0;
3888         bool effective;
3889         int changed = 1;
3890
3891         /* store the left and right volume */
3892         if (ch & 1) {
3893                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3894                 valp++;
3895         }
3896         if (ch & 2) {
3897                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3898                 valp++;
3899         }
3900
3901         /* if effective conditions, then update hw immediately. */
3902         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3903         if (effective) {
3904                 int dir = get_amp_direction(kcontrol);
3905                 unsigned long pval;
3906
3907                 snd_hda_power_up(codec);
3908                 mutex_lock(&codec->control_mutex);
3909                 pval = kcontrol->private_value;
3910                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3911                                                                 0, dir);
3912                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3913                 kcontrol->private_value = pval;
3914                 mutex_unlock(&codec->control_mutex);
3915                 snd_hda_power_down(codec);
3916         }
3917
3918         return changed;
3919 }
3920
3921 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3922                              unsigned int size, unsigned int __user *tlv)
3923 {
3924         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3925         struct ca0132_spec *spec = codec->spec;
3926         hda_nid_t nid = get_amp_nid(kcontrol);
3927         int ch = get_amp_channels(kcontrol);
3928         int dir = get_amp_direction(kcontrol);
3929         unsigned long pval;
3930         int err;
3931
3932         switch (nid) {
3933         case VNID_SPK:
3934                 /* follow shared_out tlv */
3935                 nid = spec->shared_out_nid;
3936                 mutex_lock(&codec->control_mutex);
3937                 pval = kcontrol->private_value;
3938                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3939                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3940                 kcontrol->private_value = pval;
3941                 mutex_unlock(&codec->control_mutex);
3942                 break;
3943         case VNID_MIC:
3944                 /* follow shared_mic tlv */
3945                 nid = spec->shared_mic_nid;
3946                 mutex_lock(&codec->control_mutex);
3947                 pval = kcontrol->private_value;
3948                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3949                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3950                 kcontrol->private_value = pval;
3951                 mutex_unlock(&codec->control_mutex);
3952                 break;
3953         default:
3954                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3955         }
3956         return err;
3957 }
3958
3959 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3960                          const char *pfx, int dir)
3961 {
3962         char namestr[44];
3963         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3964         struct snd_kcontrol_new knew =
3965                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3966         sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3967         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3968 }
3969
3970 static int add_voicefx(struct hda_codec *codec)
3971 {
3972         struct snd_kcontrol_new knew =
3973                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3974                                     VOICEFX, 1, 0, HDA_INPUT);
3975         knew.info = ca0132_voicefx_info;
3976         knew.get = ca0132_voicefx_get;
3977         knew.put = ca0132_voicefx_put;
3978         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3979 }
3980
3981 /*
3982  * When changing Node IDs for Mixer Controls below, make sure to update
3983  * Node IDs in ca0132_config() as well.
3984  */
3985 static struct snd_kcontrol_new ca0132_mixer[] = {
3986         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3987         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3988         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3989         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3990         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3991         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3992         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3993         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3994         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3995                                0x12, 1, HDA_INPUT),
3996         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3997                                VNID_HP_SEL, 1, HDA_OUTPUT),
3998         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3999                                VNID_AMIC1_SEL, 1, HDA_INPUT),
4000         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
4001                                VNID_HP_ASEL, 1, HDA_OUTPUT),
4002         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
4003                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
4004         { } /* end */
4005 };
4006
4007 static int ca0132_build_controls(struct hda_codec *codec)
4008 {
4009         struct ca0132_spec *spec = codec->spec;
4010         int i, num_fx;
4011         int err = 0;
4012
4013         /* Add Mixer controls */
4014         for (i = 0; i < spec->num_mixers; i++) {
4015                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
4016                 if (err < 0)
4017                         return err;
4018         }
4019
4020         /* Add in and out effects controls.
4021          * VoiceFX, PE and CrystalVoice are added separately.
4022          */
4023         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4024         for (i = 0; i < num_fx; i++) {
4025                 err = add_fx_switch(codec, ca0132_effects[i].nid,
4026                                     ca0132_effects[i].name,
4027                                     ca0132_effects[i].direct);
4028                 if (err < 0)
4029                         return err;
4030         }
4031
4032         err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
4033         if (err < 0)
4034                 return err;
4035
4036         err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
4037         if (err < 0)
4038                 return err;
4039
4040         add_voicefx(codec);
4041
4042         #ifdef ENABLE_TUNING_CONTROLS
4043         add_tuning_ctls(codec);
4044         #endif
4045
4046         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
4047         if (err < 0)
4048                 return err;
4049
4050         return 0;
4051 }
4052
4053 /*
4054  * PCM
4055  */
4056 static struct hda_pcm_stream ca0132_pcm_analog_playback = {
4057         .substreams = 1,
4058         .channels_min = 2,
4059         .channels_max = 6,
4060         .ops = {
4061                 .prepare = ca0132_playback_pcm_prepare,
4062                 .cleanup = ca0132_playback_pcm_cleanup
4063         },
4064 };
4065
4066 static struct hda_pcm_stream ca0132_pcm_analog_capture = {
4067         .substreams = 1,
4068         .channels_min = 2,
4069         .channels_max = 2,
4070         .ops = {
4071                 .prepare = ca0132_capture_pcm_prepare,
4072                 .cleanup = ca0132_capture_pcm_cleanup
4073         },
4074 };
4075
4076 static int ca0132_build_pcms(struct hda_codec *codec)
4077 {
4078         struct ca0132_spec *spec = codec->spec;
4079         struct hda_pcm *info = spec->pcm_rec;
4080
4081         codec->pcm_info = info;
4082         codec->num_pcms = 0;
4083
4084         info->name = "CA0132 Analog";
4085         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4086         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4087         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4088                                                 spec->multiout.max_channels;
4089         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4090         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4091         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4092         codec->num_pcms++;
4093
4094         info++;
4095         info->name = "CA0132 Analog Mic-In2";
4096         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4097         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4098         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4099         codec->num_pcms++;
4100
4101         info++;
4102         info->name = "CA0132 What U Hear";
4103         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4104         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4105         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4106         codec->num_pcms++;
4107
4108         return 0;
4109 }
4110
4111 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4112 {
4113         if (pin) {
4114                 snd_hda_codec_write(codec, pin, 0,
4115                                     AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP);
4116                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4117                         snd_hda_codec_write(codec, pin, 0,
4118                                             AC_VERB_SET_AMP_GAIN_MUTE,
4119                                             AMP_OUT_UNMUTE);
4120         }
4121         if (dac)
4122                 snd_hda_codec_write(codec, dac, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4123                                     AMP_OUT_ZERO);
4124 }
4125
4126 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4127 {
4128         if (pin) {
4129                 snd_hda_codec_write(codec, pin, 0,
4130                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
4131                                     PIN_VREF80);
4132                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4133                         snd_hda_codec_write(codec, pin, 0,
4134                                             AC_VERB_SET_AMP_GAIN_MUTE,
4135                                             AMP_IN_UNMUTE(0));
4136         }
4137         if (adc) {
4138                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4139                                     AMP_IN_UNMUTE(0));
4140
4141                 /* init to 0 dB and unmute. */
4142                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4143                                          HDA_AMP_VOLMASK, 0x5a);
4144                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4145                                          HDA_AMP_MUTE, 0);
4146         }
4147 }
4148
4149 static void ca0132_init_unsol(struct hda_codec *codec)
4150 {
4151         snd_hda_jack_detect_enable(codec, UNSOL_TAG_HP, UNSOL_TAG_HP);
4152         snd_hda_jack_detect_enable(codec, UNSOL_TAG_AMIC1, UNSOL_TAG_AMIC1);
4153 }
4154
4155 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4156 {
4157         unsigned int caps;
4158
4159         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4160                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4161         snd_hda_override_amp_caps(codec, nid, dir, caps);
4162 }
4163
4164 static void ca0132_set_dmic_gain(struct hda_codec *codec, unsigned int gain)
4165 {
4166         unsigned int mic_gain_reg;
4167         chipio_read(codec, 0x18B098, &mic_gain_reg);
4168         mic_gain_reg = (mic_gain_reg & ~0x1F) | gain;
4169         chipio_write(codec, 0x18B098, mic_gain_reg);
4170
4171         chipio_read(codec, 0x18B09C, &mic_gain_reg);
4172         mic_gain_reg = (mic_gain_reg & ~0x1F) | gain;
4173         chipio_write(codec, 0x18B09C, mic_gain_reg);
4174 }
4175
4176 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4177 {
4178         struct ca0132_spec *spec = codec->spec;
4179         unsigned int tmp;
4180         u8 val;
4181         unsigned int oldval;
4182
4183         CA0132_LOG("ca0132_set_dmic: enable=%d\n", enable);
4184
4185         oldval = stop_mic1(codec);
4186         ca0132_set_vipsource(codec, 0);
4187         if (enable) {
4188                 /* set DMic input as 2-ch */
4189                 tmp = FLOAT_TWO;
4190                 dspio_set_param(codec, 0x80, 0x00, &tmp, sizeof(unsigned int));
4191
4192                 val = spec->dmic_ctl;
4193                 val |= 0x80;
4194                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4195                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
4196
4197                 if (!(spec->dmic_ctl & 0x20))
4198                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4199
4200                 ca0132_set_dmic_gain(codec, 0x14);
4201         } else {
4202                 /* set AMic input as mono */
4203                 tmp = FLOAT_ONE;
4204                 dspio_set_param(codec, 0x80, 0x00, &tmp, sizeof(unsigned int));
4205
4206                 val = spec->dmic_ctl;
4207                 /* clear bit7 and bit5 to disable dmic */
4208                 val &= 0x5f;
4209                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4210                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
4211
4212                 if (!(spec->dmic_ctl & 0x20))
4213                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4214
4215                 ca0132_set_dmic_gain(codec, 0x0);
4216         }
4217         ca0132_set_vipsource(codec, 1);
4218         resume_mic1(codec, oldval);
4219 }
4220
4221 static void ca0132_init_dmic(struct hda_codec *codec)
4222 {
4223         struct ca0132_spec *spec = codec->spec;
4224         u8 val;
4225
4226         /* Setup Digital Mic here, but don't enable.
4227          * Enable based on jack detect.
4228          */
4229
4230         /* MCLK uses MPIO1, set to enable.
4231          * Bit 2-0: MPIO select
4232          * Bit   3: set to disable
4233          * Bit 7-4: reserved
4234          */
4235         val = 0x01;
4236         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4237                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4238
4239         /* Data1 uses MPIO3. Data2 not use
4240          * Bit 2-0: Data1 MPIO select
4241          * Bit   3: set disable Data1
4242          * Bit 6-4: Data2 MPIO select
4243          * Bit   7: set disable Data2
4244          */
4245         val = 0x83;
4246         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4247                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
4248
4249         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4250          * Bit 3-0: Channel mask
4251          * Bit   4: set for 48KHz, clear for 32KHz
4252          * Bit   5: mode
4253          * Bit   6: set to select Data2, clear for Data1
4254          * Bit   7: set to enable DMic, clear for AMic
4255          */
4256         val = 0x23;
4257         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4258         spec->dmic_ctl = val;
4259         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4260                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
4261 }
4262
4263 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4264 {
4265         struct ca0132_spec *spec = codec->spec;
4266
4267         mutex_lock(&spec->chipio_mutex);
4268         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4269                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4270         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4271                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4272         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4273                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4274         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4275                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4276         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4277                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4278         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4279                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4280         mutex_unlock(&spec->chipio_mutex);
4281 }
4282
4283 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4284 {
4285         struct ca0132_spec *spec = codec->spec;
4286         int i;
4287         hda_nid_t nid;
4288
4289         CA0132_LOG("ca0132_refresh_widget_caps.\n");
4290         nid = codec->start_nid;
4291         for (i = 0; i < codec->num_nodes; i++, nid++)
4292                 codec->wcaps[i] = snd_hda_param_read(codec, nid,
4293                                                      AC_PAR_AUDIO_WIDGET_CAP);
4294
4295         for (i = 0; i < spec->multiout.num_dacs; i++)
4296                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4297
4298         for (i = 0; i < spec->num_outputs; i++)
4299                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4300
4301         for (i = 0; i < spec->num_inputs; i++) {
4302                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4303                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4304         }
4305 }
4306
4307 static void ca0132_setup_defaults(struct hda_codec *codec)
4308 {
4309         unsigned int tmp;
4310         int num_fx;
4311         int idx, i;
4312
4313         if (!dspload_is_loaded(codec))
4314                 return;
4315
4316         /* out, in effects + voicefx */
4317         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4318         for (idx = 0; idx < num_fx; idx++) {
4319                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4320                         dspio_set_param(codec, ca0132_effects[idx].mid,
4321                                         ca0132_effects[idx].reqs[i],
4322                                         &(ca0132_effects[idx].def_vals[i]),
4323                                         sizeof(unsigned int));
4324                 }
4325         }
4326
4327         /*remove DSP headroom*/
4328         tmp = FLOAT_ZERO;
4329         dspio_set_param(codec, 0x96, 0x3C, &tmp, sizeof(unsigned int));
4330
4331         /*set speaker EQ bypass attenuation*/
4332         dspio_set_param(codec, 0x8f, 0x01, &tmp, sizeof(unsigned int));
4333
4334         /* set AMic1 and AMic2 as mono mic */
4335         tmp = FLOAT_ONE;
4336         dspio_set_param(codec, 0x80, 0x00, &tmp, sizeof(unsigned int));
4337         dspio_set_param(codec, 0x80, 0x01, &tmp, sizeof(unsigned int));
4338
4339         /* set AMic1 as CrystalVoice input */
4340         tmp = FLOAT_ONE;
4341         dspio_set_param(codec, 0x80, 0x05, &tmp, sizeof(unsigned int));
4342
4343         /* set WUH source */
4344         tmp = FLOAT_TWO;
4345         dspio_set_param(codec, 0x31, 0x00, &tmp, sizeof(unsigned int));
4346
4347         /* set AEC level */
4348         tmp = FLOAT_60;
4349         dspio_set_param(codec, 0x86, 0x05, &tmp, sizeof(unsigned int));
4350 }
4351
4352 static void ca0132_init_flags(struct hda_codec *codec)
4353 {
4354         chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4355         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4356         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4357         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4358         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4359         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4360 }
4361
4362 static void ca0132_init_params(struct hda_codec *codec)
4363 {
4364         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4365         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4366 }
4367
4368 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4369 {
4370         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4371         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4372         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4373         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4374         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4375         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4376
4377         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4378         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4379         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4380 }
4381
4382 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4383 {
4384         bool dsp_loaded = false;
4385         const struct dsp_image_seg *dsp_os_image;
4386
4387         if (request_firmware_cached(&fw_efx, EFX_FILE,
4388                                     codec->bus->card->dev) != 0)
4389                 return false;
4390
4391         dsp_os_image = (struct dsp_image_seg *)(fw_efx->data);
4392         dspload_image(codec, dsp_os_image, 0, 0, true, 0);
4393         dsp_loaded = dspload_wait_loaded(codec);
4394
4395         if (dsp_loaded)
4396                 dspload_speakereq(codec);
4397
4398         return dsp_loaded;
4399 }
4400
4401 static void ca0132_download_dsp(struct hda_codec *codec)
4402 {
4403         struct ca0132_spec *spec = codec->spec;
4404
4405         spec->dsp_state = DSP_DOWNLOAD_INIT;
4406
4407         if (spec->dsp_state == DSP_DOWNLOAD_INIT) {
4408                 chipio_enable_clocks(codec);
4409                 spec->dsp_state = DSP_DOWNLOADING;
4410                 if (!ca0132_download_dsp_images(codec))
4411                         spec->dsp_state = DSP_DOWNLOAD_FAILED;
4412                 else
4413                         spec->dsp_state = DSP_DOWNLOADED;
4414         }
4415
4416         if (spec->dsp_state == DSP_DOWNLOADED)
4417                 ca0132_set_dsp_msr(codec, true);
4418 }
4419
4420 static void ca0132_process_dsp_response(struct hda_codec *codec)
4421 {
4422         struct ca0132_spec *spec = codec->spec;
4423
4424         CA0132_LOG("ca0132_process_dsp_response\n");
4425         if (spec->wait_scp) {
4426                 if (dspio_get_response_data(codec) >= 0)
4427                         spec->wait_scp = 0;
4428         }
4429
4430         dspio_clear_response_queue(codec);
4431 }
4432
4433 static void ca0132_unsol_event(struct hda_codec *codec, unsigned int res)
4434 {
4435         struct ca0132_spec *spec = codec->spec;
4436         CA0132_LOG("ca0132_unsol_event: 0x%x\n", res);
4437
4438
4439         if (((res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f) == UNSOL_TAG_DSP) {
4440                 ca0132_process_dsp_response(codec);
4441         } else {
4442                 res = snd_hda_jack_get_action(codec,
4443                                 (res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f);
4444
4445                 CA0132_LOG("snd_hda_jack_get_action: 0x%x\n", res);
4446
4447                 switch (res) {
4448                 case UNSOL_TAG_HP:
4449                         cancel_delayed_work_sync(&spec->unsol_hp_work);
4450                         queue_delayed_work(codec->bus->workq,
4451                                            &spec->unsol_hp_work,
4452                                            msecs_to_jiffies(250));
4453                         break;
4454                 case UNSOL_TAG_AMIC1:
4455                         ca0132_select_mic(codec);
4456                         snd_hda_jack_report_sync(codec);
4457                         break;
4458                 default:
4459                         break;
4460                 }
4461         }
4462 }
4463
4464 /*
4465  * Verbs tables.
4466  */
4467
4468 /* Sends before DSP download. */
4469 static struct hda_verb ca0132_base_init_verbs[] = {
4470         /*enable ct extension*/
4471         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4472         /*enable DSP node unsol, needed for DSP download*/
4473         {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP},
4474         {}
4475 };
4476
4477 /* Send at exit. */
4478 static struct hda_verb ca0132_base_exit_verbs[] = {
4479         /*set afg to D3*/
4480         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4481         /*disable ct extension*/
4482         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4483         {}
4484 };
4485
4486 /* Other verbs tables.  Sends after DSP download. */
4487 static struct hda_verb ca0132_init_verbs0[] = {
4488         /* chip init verbs */
4489         {0x15, 0x70D, 0xF0},
4490         {0x15, 0x70E, 0xFE},
4491         {0x15, 0x707, 0x75},
4492         {0x15, 0x707, 0xD3},
4493         {0x15, 0x707, 0x09},
4494         {0x15, 0x707, 0x53},
4495         {0x15, 0x707, 0xD4},
4496         {0x15, 0x707, 0xEF},
4497         {0x15, 0x707, 0x75},
4498         {0x15, 0x707, 0xD3},
4499         {0x15, 0x707, 0x09},
4500         {0x15, 0x707, 0x02},
4501         {0x15, 0x707, 0x37},
4502         {0x15, 0x707, 0x78},
4503         {0x15, 0x53C, 0xCE},
4504         {0x15, 0x575, 0xC9},
4505         {0x15, 0x53D, 0xCE},
4506         {0x15, 0x5B7, 0xC9},
4507         {0x15, 0x70D, 0xE8},
4508         {0x15, 0x70E, 0xFE},
4509         {0x15, 0x707, 0x02},
4510         {0x15, 0x707, 0x68},
4511         {0x15, 0x707, 0x62},
4512         {0x15, 0x53A, 0xCE},
4513         {0x15, 0x546, 0xC9},
4514         {0x15, 0x53B, 0xCE},
4515         {0x15, 0x5E8, 0xC9},
4516         {0x15, 0x717, 0x0D},
4517         {0x15, 0x718, 0x20},
4518         {}
4519 };
4520
4521 static struct hda_verb ca0132_init_verbs1[] = {
4522         {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP},
4523         {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1},
4524         /* Set the default configuration for the mic pin because the
4525          * value set in BIOS will be reset after ct extension is enabled.
4526          */
4527         {0x12, AC_VERB_SET_CONFIG_DEFAULT_BYTES_0, 0xf0},
4528         {0x12, AC_VERB_SET_CONFIG_DEFAULT_BYTES_1, 0x10},
4529         {0x12, AC_VERB_SET_CONFIG_DEFAULT_BYTES_2, 0xa1},
4530         {0x12, AC_VERB_SET_CONFIG_DEFAULT_BYTES_3, 0x03},
4531         /* config EAPD */
4532         {0x0b, 0x78D, 0x00},
4533         /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4534         /*{0x10, 0x78D, 0x02},*/
4535         /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4536         {}
4537 };
4538
4539 static void ca0132_init_chip(struct hda_codec *codec)
4540 {
4541         struct ca0132_spec *spec = codec->spec;
4542         int num_fx;
4543         int i;
4544         unsigned int on;
4545
4546         mutex_init(&spec->chipio_mutex);
4547
4548         spec->cur_out_type = SPEAKER_OUT;
4549         spec->cur_mic_type = DIGITAL_MIC;
4550         spec->cur_mic_boost = 0;
4551
4552         for (i = 0; i < VNODES_COUNT; i++) {
4553                 spec->vnode_lvol[i] = 0x5a;
4554                 spec->vnode_rvol[i] = 0x5a;
4555                 spec->vnode_lswitch[i] = 0;
4556                 spec->vnode_rswitch[i] = 0;
4557         }
4558
4559         /*
4560          * Default states for effects are in ca0132_effects[].
4561          */
4562         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4563         for (i = 0; i < num_fx; i++) {
4564                 on = (unsigned int)ca0132_effects[i].reqs[0];
4565                 spec->effects_switch[i] = on ? 1 : 0;
4566         }
4567
4568         spec->voicefx_val = 0;
4569         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4570         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4571
4572         #ifdef ENABLE_TUNING_CONTROLS
4573         ca0132_init_tuning_defaults(codec);
4574         #endif
4575 }
4576
4577 static void ca0132_exit_chip(struct hda_codec *codec)
4578 {
4579         /* put any chip cleanup stuffs here. */
4580
4581         if (dspload_is_loaded(codec))
4582                 dsp_reset(codec);
4583 }
4584
4585 static int xdata_read(struct hda_codec *codec, u16 addr)
4586 {
4587         struct ca0132_spec *spec = codec->spec;
4588         int data;
4589
4590         mutex_lock(&spec->chipio_mutex);
4591         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4592                             VENDOR_CHIPIO_8051_ADDRESS_LOW, addr & 0xFF);
4593         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4594                             VENDOR_CHIPIO_8051_ADDRESS_HIGH,
4595                             (addr >> 8) & 0xFF);
4596         data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
4597                             VENDOR_CHIPIO_8051_DATA_READ, 0);
4598         mutex_unlock(&spec->chipio_mutex);
4599
4600         return data;
4601 }
4602
4603 static int xdata_write(struct hda_codec *codec, u16 addr, u8 value)
4604 {
4605         struct ca0132_spec *spec = codec->spec;
4606
4607         mutex_lock(&spec->chipio_mutex);
4608         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4609                             VENDOR_CHIPIO_8051_ADDRESS_LOW, addr & 0xFF);
4610         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4611                             VENDOR_CHIPIO_8051_ADDRESS_HIGH,
4612                             (addr >> 8) & 0xFF);
4613         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4614                             VENDOR_CHIPIO_8051_DATA_WRITE, value);
4615         mutex_unlock(&spec->chipio_mutex);
4616
4617         return 0;
4618 }
4619
4620 static int idata_write(struct hda_codec *codec, u16 addr, u8 value)
4621 {
4622         struct ca0132_spec *spec = codec->spec;
4623
4624         mutex_lock(&spec->chipio_mutex);
4625         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4626                             VENDOR_CHIPIO_8051_ADDRESS_LOW, addr & 0xFF);
4627         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4628                             VENDOR_CHIPIO_8051_ADDRESS_HIGH,
4629                             (addr >> 8) & 0xFF);
4630         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4631                             0x709, value);
4632         mutex_unlock(&spec->chipio_mutex);
4633
4634         return 0;
4635 }
4636
4637 static int pmu_read(struct hda_codec *codec, u8 addr)
4638 {
4639         struct ca0132_spec *spec = codec->spec;
4640         int data;
4641
4642         mutex_lock(&spec->chipio_mutex);
4643         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4644                             VENDOR_CHIPIO_8051_ADDRESS_LOW, addr);
4645         data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
4646                             VENDOR_CHIPIO_PLL_PMU_READ, 0);
4647         mutex_unlock(&spec->chipio_mutex);
4648
4649         return data;
4650 }
4651
4652 static int pmu_write(struct hda_codec *codec, u8 addr, u8 value)
4653 {
4654         struct ca0132_spec *spec = codec->spec;
4655
4656         mutex_lock(&spec->chipio_mutex);
4657         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4658                             VENDOR_CHIPIO_8051_ADDRESS_LOW, addr);
4659         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4660                             VENDOR_CHIPIO_PLL_PMU_WRITE, value);
4661         mutex_unlock(&spec->chipio_mutex);
4662
4663         return 0;
4664 }
4665
4666 static int ca0132_init_codec(struct hda_codec *codec)
4667 {
4668         u8 codecDevices[] = {
4669                 1, 2, 3, 6, 8, 10, 11
4670         };
4671         bool codec_ready = true;
4672         int retryCount = 3;
4673         int tryCount = 5;
4674         int i;
4675         int codecStateAddr = 0x18BE;
4676         int addr;
4677         int data;
4678
4679         do {
4680                 codec_ready = true;
4681                 for (i = 0; i < ARRAY_SIZE(codecDevices); i++) {
4682                         addr = codecStateAddr + 13 * codecDevices[i] + 8;
4683                         data = xdata_read(codec, addr);
4684                         if ((data > 0) && (data & 0x4))
4685                                 codec_ready = false;
4686                 }
4687
4688                 if (!codec_ready) {
4689                         snd_hda_codec_write(codec, 1, 0,
4690                                             AC_VERB_SET_POWER_STATE, 4);
4691
4692                         data = pmu_read(codec, 0xF);
4693                         pmu_write(codec, 0xF, data & ~0x88);
4694                         msleep(100);
4695                         pmu_write(codec, 0xF, data | 0x88);
4696                         msleep(100);
4697                         xdata_write(codec, 0xB6, 0x1);
4698                         xdata_write(codec, 0x1F07, 0xF9);
4699                         xdata_write(codec, 0x1F08, 0x72);
4700                         idata_write(codec, 0x7D, 0x40);
4701
4702                         do {
4703                                 data = xdata_read(codec, 0xB6);
4704                                 msleep(100);
4705                         } while (data != 0 && --tryCount);
4706
4707                         snd_hda_codec_write(codec, 1, 0,
4708                                             AC_VERB_SET_POWER_STATE, 0);
4709                         msleep(500);
4710                 }
4711         } while (!codec_ready && --retryCount);
4712
4713         return 0;
4714 }
4715
4716 static int ca0132_init(struct hda_codec *codec)
4717 {
4718         struct ca0132_spec *spec = codec->spec;
4719         int i;
4720
4721         spec->dsp_state = DSP_DOWNLOAD_INIT;
4722         spec->curr_chip_addx = (unsigned int)INVALID_CHIP_ADDRESS;
4723
4724         snd_hda_power_up(codec);
4725
4726         snd_hda_sequence_write(codec, spec->base_init_verbs);
4727         ca0132_init_codec(codec);
4728         ca0132_init_params(codec);
4729         ca0132_init_flags(codec);
4730         ca0132_download_dsp(codec);
4731         ca0132_refresh_widget_caps(codec);
4732         ca0132_setup_defaults(codec);
4733         ca0132_pe_switch_set(codec);
4734         ca0132_cvoice_switch_set(codec);
4735         ca0132_init_analog_mic2(codec);
4736         ca0132_init_dmic(codec);
4737
4738         for (i = 0; i < spec->num_outputs; i++)
4739                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4740
4741         for (i = 0; i < spec->num_inputs; i++)
4742                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4743
4744         for (i = 0; i < spec->num_init_verbs; i++)
4745                 snd_hda_sequence_write(codec, spec->init_verbs[i]);
4746
4747         ca0132_init_unsol(codec);
4748
4749         ca0132_select_out(codec);
4750         ca0132_select_mic(codec);
4751
4752         snd_hda_jack_report_sync(codec);
4753
4754         snd_hda_power_down(codec);
4755
4756         return 0;
4757 }
4758
4759 static void ca0132_free(struct hda_codec *codec)
4760 {
4761         struct ca0132_spec *spec = codec->spec;
4762
4763         cancel_delayed_work_sync(&spec->unsol_hp_work);
4764         snd_hda_power_up(codec);
4765         snd_hda_sequence_write(codec, spec->base_exit_verbs);
4766         ca0132_exit_chip(codec);
4767         snd_hda_power_down(codec);
4768         kfree(codec->spec);
4769 }
4770
4771
4772 static struct hda_codec_ops ca0132_patch_ops = {
4773         .build_controls = ca0132_build_controls,
4774         .build_pcms = ca0132_build_pcms,
4775         .init = ca0132_init,
4776         .free = ca0132_free,
4777         .unsol_event = ca0132_unsol_event,
4778 };
4779
4780 static void ca0132_config(struct hda_codec *codec)
4781 {
4782         struct ca0132_spec *spec = codec->spec;
4783
4784         spec->dacs[0] = 0x2;
4785         spec->dacs[1] = 0x3;
4786         spec->dacs[2] = 0x4;
4787
4788         spec->multiout.dac_nids = spec->dacs;
4789         spec->multiout.num_dacs = 3;
4790         spec->multiout.max_channels = 2;
4791
4792         spec->num_outputs = 2;
4793         spec->out_pins[0] = 0x0b; /* speaker out */
4794         spec->out_pins[1] = 0x10; /* headphone out */
4795         spec->shared_out_nid = 0x2;
4796
4797         spec->num_inputs = 3;
4798         spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4799         spec->adcs[1] = 0x8; /* analog mic2 */
4800         spec->adcs[2] = 0xa; /* what u hear */
4801         spec->shared_mic_nid = 0x7;
4802
4803         spec->input_pins[0] = 0x12;
4804         spec->input_pins[1] = 0x11;
4805         spec->input_pins[2] = 0x13;
4806 }
4807
4808 static int patch_ca0132(struct hda_codec *codec)
4809 {
4810         struct ca0132_spec *spec;
4811         int err;
4812
4813         snd_printdd("patch_ca0132\n");
4814
4815         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4816         if (!spec)
4817                 return -ENOMEM;
4818         codec->spec = spec;
4819         spec->codec = codec;
4820
4821         spec->num_mixers = 1;
4822         spec->mixers[0] = ca0132_mixer;
4823
4824         spec->base_init_verbs = ca0132_base_init_verbs;
4825         spec->base_exit_verbs = ca0132_base_exit_verbs;
4826         spec->init_verbs[0] = ca0132_init_verbs0;
4827         spec->init_verbs[1] = ca0132_init_verbs1;
4828         spec->num_init_verbs = 2;
4829
4830         INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4831
4832         ca0132_init_chip(codec);
4833
4834         ca0132_config(codec);
4835
4836         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4837         if (err < 0)
4838                 return err;
4839
4840         codec->patch_ops = ca0132_patch_ops;
4841
4842         return 0;
4843 }
4844
4845
4846 /*
4847  * patch entries
4848  */
4849 static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4850         { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4851         {} /* terminator */
4852 };
4853
4854 MODULE_ALIAS("snd-hda-codec-id:11020011");
4855
4856 MODULE_LICENSE("GPL");
4857 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4858
4859 static struct hda_codec_preset_list ca0132_list = {
4860         .preset = snd_hda_preset_ca0132,
4861         .owner = THIS_MODULE,
4862 };
4863
4864 static int __init patch_ca0132_init(void)
4865 {
4866         return snd_hda_add_codec_preset(&ca0132_list);
4867 }
4868
4869 static void __exit patch_ca0132_exit(void)
4870 {
4871         release_cached_firmware();
4872         snd_hda_delete_codec_preset(&ca0132_list);
4873 }
4874
4875 module_init(patch_ca0132_init)
4876 module_exit(patch_ca0132_exit)