sound/pci/hda/patch_ca0132.c

   1 /*
   2  * HD audio interface patch for Creative Sound Core3D chip
   3  *
   4  * Copyright (c) 2011, Creative Technology Ltd.
   5  *
   6  * Based on patch_ca0110.c
   7  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   8  *
   9  *  This driver is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License as published by
  11  *  the Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This driver is distributed in the hope that it will be useful,
  15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *  GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; if not, write to the Free Software
  21  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/pci.h>
  28 #include <linux/module.h>
  29 #include <linux/firmware.h>
  30 #include <sound/core.h>
  31 #include <sound/tlv.h>
  32 #include "hda_codec.h"
  33 #include "hda_local.h"
  34 #include "hda_jack.h"
  35
  36 #include "ca0132_regs.h"
  37
  38 /* Enable this to see more debug messages. */
  39 /*#define ENABLE_CA0132_DEBUG*/
  40 /* Enable this to see controls for tuning purpose. */
  41 /*#define ENABLE_TUNING_CONTROLS*/
  42
  43 #define FLOAT_ZERO      0x00000000
  44 #define FLOAT_ONE       0x3f800000
  45 #define FLOAT_TWO       0x40000000
  46 #define FLOAT_MINUS_5   0xc0a00000
  47
  48 #define UNSOL_TAG_HP    0x10
  49 #define UNSOL_TAG_AMIC1 0x12
  50 #define UNSOL_TAG_DSP   0x16
  51
  52 #define SUCCEEDED(_x)         (((int)(_x)) >= 0)
  53 #define FAILED(_x)            (((int)(_x)) < 0)
  54
  55 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  56 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  57
  58 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  59 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  60 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  61
  62 #define MASTERCONTROL                           0x80
  63 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
  64 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  65
  66 #define WIDGET_CHIP_CTRL      0x15
  67 #define WIDGET_DSP_CTRL       0x16
  68
  69 #define MEM_CONNID_MICIN1     3
  70 #define MEM_CONNID_MICIN2     5
  71 #define MEM_CONNID_MICOUT1    12
  72 #define MEM_CONNID_MICOUT2    14
  73 #define MEM_CONNID_WUH        10
  74 #define MEM_CONNID_DSP        16
  75 #define MEM_CONNID_DMIC       100
  76
  77 #define SCP_SET    0
  78 #define SCP_GET    1
  79
  80 #define SPEQ_FILE  "ctspeq.bin"
  81 #define EFX_FILE   "ctefx.bin"
  82
  83 MODULE_FIRMWARE(SPEQ_FILE);
  84 MODULE_FIRMWARE(EFX_FILE);
  85
  86 /* Debug message controls */
  87 #ifdef ENABLE_CA0132_DEBUG
  88
  89 #define CTASSERT(x) \
  90         { if (!(x)) snd_printdd(KERN_ERR "CTASSERT failed.\n"); }
  91
  92 #define CA0132_LOG(fmt, args...)    snd_printdd(fmt, ##args)
  93 #define CA0132_DSP_LOG(msg)         snd_printdd(KERN_INFO "[%s]\n", msg)
  94 #define FAIL_MSG(n, s)              fail_debug_out(n, s)
  95
  96 static int fail_debug_out(int status, const char *s)
  97 {
  98         snd_printdd(KERN_ERR "[%s]\n", s);
  99         return status;
 100 }
 101 #else
 102
 103 #define CTASSERT(x)                 do { } while (0)
 104 #define CA0132_LOG(fmt, args...)    do { } while (0)
 105 #define CA0132_DSP_LOG(msg)         do { } while (0)
 106 #define FAIL_MSG(n, s)              fail_debug_out(n, s)
 107
 108 static int fail_debug_out(int status, const char *s)
 109 {
 110         return status;
 111 }
 112 #endif
 113
 114 static char *dirstr[2] = { "Playback", "Capture" };
 115
 116 enum {
 117         SPEAKER_OUT,
 118         HEADPHONE_OUT
 119 };
 120
 121 enum {
 122         DIGITAL_MIC,
 123         LINE_MIC_IN
 124 };
 125
 126 enum {
 127 #define VNODE_START_NID    0x80
 128         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
 129         VNID_MIC,
 130         VNID_HP_SEL,
 131         VNID_AMIC1_SEL,
 132         VNID_HP_ASEL,
 133         VNID_AMIC1_ASEL,
 134         VNODE_END_NID,
 135 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 136
 137 #define EFFECT_START_NID    0x90
 138 #define OUT_EFFECT_START_NID    EFFECT_START_NID
 139         SURROUND = OUT_EFFECT_START_NID,
 140         CRYSTALIZER,
 141         DIALOG_PLUS,
 142         SMART_VOLUME,
 143         X_BASS,
 144         EQUALIZER,
 145         OUT_EFFECT_END_NID,
 146 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 147
 148 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 149         ECHO_CANCELLATION = IN_EFFECT_START_NID,
 150         VOICE_FOCUS,
 151         MIC_SVM,
 152         NOISE_REDUCTION,
 153         IN_EFFECT_END_NID,
 154 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 155
 156         VOICEFX = IN_EFFECT_END_NID,
 157         PLAY_ENHANCEMENT,
 158         CRYSTAL_VOICE,
 159         EFFECT_END_NID
 160 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 161 };
 162
 163 /* Effects values size*/
 164 #define EFFECT_VALS_MAX_COUNT 12
 165
 166 #define DSP_CAPTURE_INIT_LATENCY        0
 167 #define DSP_CRYSTAL_VOICE_LATENCY       124
 168 #define DSP_PLAYBACK_INIT_LATENCY       13
 169 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
 170 #define DSP_SPEAKER_OUT_LATENCY         7
 171
 172 struct ct_effect {
 173         char name[44];
 174         hda_nid_t nid;
 175         int mid; /*effect module ID*/
 176         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 177         int direct; /* 0:output; 1:input*/
 178         int params; /* number of default non-on/off params */
 179         /*effect default values, 1st is on/off. */
 180         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 181 };
 182
 183 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 184         { "Surround",
 185                 SURROUND,
 186                 0x96,
 187                 {0, 1},
 188                 0,
 189                 1,
 190                 {0x3F800000, 0x3F2B851F}
 191         },
 192         { "Crystalizer",
 193                 CRYSTALIZER,
 194                 0x96,
 195                 {7, 8},
 196                 0,
 197                 1,
 198                 {0x3F800000, 0x3F266666}
 199         },
 200         { "Dialog Plus",
 201                 DIALOG_PLUS,
 202                 0x96,
 203                 {2, 3},
 204                 0,
 205                 1,
 206                 {0x00000000, 0x3F000000}
 207         },
 208         { "Smart Volume",
 209                 SMART_VOLUME,
 210                 0x96,
 211                 {4, 5, 6},
 212                 0,
 213                 2,
 214                 {0x3F800000, 0x3F3D70A4, 0x00000000}
 215         },
 216         { "X-Bass",
 217                 X_BASS,
 218                 0x96,
 219                 {24, 23, 25},
 220                 0,
 221                 2,
 222                 {0x3F800000, 0x42A00000, 0x3F000000}
 223         },
 224         { "Equalizer",
 225                 EQUALIZER,
 226                 0x96,
 227                 {9, 10, 11, 12, 13, 14,
 228                         15, 16, 17, 18, 19, 20},
 229                 0,
 230                 11,
 231                 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 232                  0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 233                  0x00000000, 0x00000000}
 234         },
 235         { "Echo Cancellation",
 236                 ECHO_CANCELLATION,
 237                 0x95,
 238                 {0, 1, 2, 3},
 239                 1,
 240                 3,
 241                 {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 242         },
 243         { "Voice Focus",
 244                 VOICE_FOCUS,
 245                 0x95,
 246                 {6, 7, 8, 9},
 247                 1,
 248                 3,
 249                 {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 250         },
 251         { "Mic SVM",
 252                 MIC_SVM,
 253                 0x95,
 254                 {44, 45},
 255                 1,
 256                 1,
 257                 {0x00000000, 0x3F3D70A4}
 258         },
 259         { "Noise Reduction",
 260                 NOISE_REDUCTION,
 261                 0x95,
 262                 {4, 5},
 263                 1,
 264                 1,
 265                 {0x3F800000, 0x3F000000}
 266         },
 267         { "VoiceFX",
 268                 VOICEFX,
 269                 0x95,
 270                 {10, 11, 12, 13, 14, 15, 16, 17, 18},
 271                 1,
 272                 8,
 273                 {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 0x3F800000,
 274                  0x3F800000, 0x3F800000, 0x00000000, 0x00000000}
 275         }
 276 };
 277
 278
 279 /* Tuning controls */
 280 #ifdef ENABLE_TUNING_CONTROLS
 281
 282 enum {
 283 #define TUNING_CTL_START_NID  0xC0
 284         WEDGE_ANGLE = TUNING_CTL_START_NID,
 285         SVM_LEVEL,
 286         EQUALIZER_BAND_0,
 287         EQUALIZER_BAND_1,
 288         EQUALIZER_BAND_2,
 289         EQUALIZER_BAND_3,
 290         EQUALIZER_BAND_4,
 291         EQUALIZER_BAND_5,
 292         EQUALIZER_BAND_6,
 293         EQUALIZER_BAND_7,
 294         EQUALIZER_BAND_8,
 295         EQUALIZER_BAND_9,
 296         TUNING_CTL_END_NID
 297 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 298 };
 299
 300 struct ct_tuning_ctl {
 301         char name[44];
 302         hda_nid_t parent_nid;
 303         hda_nid_t nid;
 304         int mid; /*effect module ID*/
 305         int req; /*effect module request*/
 306         int direct; /* 0:output; 1:input*/
 307         unsigned int def_val;/*effect default values*/
 308 };
 309
 310 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 311         { "Wedge Angle",
 312                 VOICE_FOCUS,
 313                 WEDGE_ANGLE,
 314                 0x95,
 315                 8,
 316                 1,
 317                 0x41F00000
 318         },
 319         { "SVM Level",
 320                 MIC_SVM,
 321                 SVM_LEVEL,
 322                 0x95,
 323                 45,
 324                 1,
 325                 0x3F3D70A4
 326         },
 327         { "EQ Band0",
 328                 EQUALIZER,
 329                 EQUALIZER_BAND_0,
 330                 0x96,
 331                 11,
 332                 0,
 333                 0x00000000
 334         },
 335         { "EQ Band1",
 336                 EQUALIZER,
 337                 EQUALIZER_BAND_1,
 338                 0x96,
 339                 12,
 340                 0,
 341                 0x00000000
 342         },
 343         { "EQ Band2",
 344                 EQUALIZER,
 345                 EQUALIZER_BAND_2,
 346                 0x96,
 347                 13,
 348                 0,
 349                 0x00000000
 350         },
 351         { "EQ Band3",
 352                 EQUALIZER,
 353                 EQUALIZER_BAND_3,
 354                 0x96,
 355                 14,
 356                 0,
 357                 0x00000000
 358         },
 359         { "EQ Band4",
 360                 EQUALIZER,
 361                 EQUALIZER_BAND_4,
 362                 0x96,
 363                 15,
 364                 0,
 365                 0x00000000
 366         },
 367         { "EQ Band5",
 368                 EQUALIZER,
 369                 EQUALIZER_BAND_5,
 370                 0x96,
 371                 16,
 372                 0,
 373                 0x00000000
 374         },
 375         { "EQ Band6",
 376                 EQUALIZER,
 377                 EQUALIZER_BAND_6,
 378                 0x96,
 379                 17,
 380                 0,
 381                 0x00000000
 382         },
 383         { "EQ Band7",
 384                 EQUALIZER,
 385                 EQUALIZER_BAND_7,
 386                 0x96,
 387                 18,
 388                 0,
 389                 0x00000000
 390         },
 391         { "EQ Band8",
 392                 EQUALIZER,
 393                 EQUALIZER_BAND_8,
 394                 0x96,
 395                 19,
 396                 0,
 397                 0x00000000
 398         },
 399         { "EQ Band9",
 400                 EQUALIZER,
 401                 EQUALIZER_BAND_9,
 402                 0x96,
 403                 20,
 404                 0,
 405                 0x00000000
 406         }
 407 };
 408 #endif
 409
 410 /* Voice FX Presets */
 411 #define VOICEFX_MAX_PARAM_COUNT 9
 412
 413 struct ct_voicefx {
 414         char *name;
 415         hda_nid_t nid;
 416         int mid;
 417         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 418 };
 419
 420 struct ct_voicefx_preset {
 421         char *name; /*preset name*/
 422         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 423 };
 424
 425 struct ct_voicefx ca0132_voicefx = {
 426         "VoiceFX Capture Switch",
 427         VOICEFX,
 428         0x95,
 429         {10, 11, 12, 13, 14, 15, 16, 17, 18}
 430 };
 431
 432 struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 433         { "Neutral",
 434                 { 0x00000000, 0x43C80000, 0x44AF0000,
 435                   0x44FA0000, 0x3F800000, 0x3F800000,
 436                   0x3F800000, 0x00000000, 0x00000000 }
 437         },
 438         { "Female2Male",
 439                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 440                   0x44FA0000, 0x3F19999A, 0x3F866666,
 441                   0x3F800000, 0x00000000, 0x00000000 }
 442         },
 443         { "Male2Female",
 444                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 445                   0x450AC000, 0x4017AE14, 0x3F6B851F,
 446                   0x3F800000, 0x00000000, 0x00000000 }
 447         },
 448         { "ScrappyKid",
 449                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 450                   0x44FA0000, 0x40400000, 0x3F28F5C3,
 451                   0x3F800000, 0x00000000, 0x00000000 }
 452         },
 453         { "Elderly",
 454                 { 0x3F800000, 0x44324000, 0x44BB8000,
 455                   0x44E10000, 0x3FB33333, 0x3FB9999A,
 456                   0x3F800000, 0x3E3A2E43, 0x00000000 }
 457         },
 458         { "Org",
 459                 { 0x3F800000, 0x43EA0000, 0x44A52000,
 460                   0x45098000, 0x3F266666, 0x3FC00000,
 461                   0x3F800000, 0x00000000, 0x00000000 }
 462         },
 463         { "Elf",
 464                 { 0x3F800000, 0x43C70000, 0x44AE6000,
 465                   0x45193000, 0x3F8E147B, 0x3F75C28F,
 466                   0x3F800000, 0x00000000, 0x00000000 }
 467         },
 468         { "Dwarf",
 469                 { 0x3F800000, 0x43930000, 0x44BEE000,
 470                   0x45007000, 0x3F451EB8, 0x3F7851EC,
 471                   0x3F800000, 0x00000000, 0x00000000 }
 472         },
 473         { "AlienBrute",
 474                 { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 475                   0x451F6000, 0x3F266666, 0x3FA7D945,
 476                   0x3F800000, 0x3CF5C28F, 0x00000000 }
 477         },
 478         { "Robot",
 479                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 480                   0x44FA0000, 0x3FB2718B, 0x3F800000,
 481                   0xBC07010E, 0x00000000, 0x00000000 }
 482         },
 483         { "Marine",
 484                 { 0x3F800000, 0x43C20000, 0x44906000,
 485                   0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 486                   0x3F0A3D71, 0x00000000, 0x00000000 }
 487         },
 488         { "Emo",
 489                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 490                   0x44FA0000, 0x3F800000, 0x3F800000,
 491                   0x3E4CCCCD, 0x00000000, 0x00000000 }
 492         },
 493         { "DeepVoice",
 494                 { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 495                   0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 496                   0x3F800000, 0x00000000, 0x00000000 }
 497         },
 498         { "Munchkin",
 499                 { 0x3F800000, 0x43C80000, 0x44AF0000,
 500                   0x44FA0000, 0x3F1A043C, 0x3F800000,
 501                   0x3F800000, 0x00000000, 0x00000000 }
 502         }
 503 };
 504
 505 enum hda_cmd_vendor_io {
 506         /* for DspIO node */
 507         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 508         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 509
 510         VENDOR_DSPIO_STATUS                  = 0xF01,
 511         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 512         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 513         VENDOR_DSPIO_DSP_INIT                = 0x703,
 514         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 515         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 516
 517         /* for ChipIO node */
 518         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 519         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 520         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 521         VENDOR_CHIPIO_DATA_LOW               = 0x300,
 522         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 523
 524         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 525         VENDOR_CHIPIO_STATUS                 = 0xF01,
 526         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 527         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 528
 529         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 530         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 531
 532         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 533         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 534
 535         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 536         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 537         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 538         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 539         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 540         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 541         VENDOR_CHIPIO_PARAM_SET              = 0x710,
 542         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 543
 544         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 545         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 546         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 547         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 548
 549         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 550         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 551         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 552         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 553
 554         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 555         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 556         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 557         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 558         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 559         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 560
 561         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 562 };
 563
 564 enum control_flag_id {
 565         /* Connection manager stream setup is bypassed/enabled */
 566         CONTROL_FLAG_C_MGR                  = 0,
 567         /* DSP DMA is bypassed/enabled */
 568         CONTROL_FLAG_DMA                    = 1,
 569         /* 8051 'idle' mode is disabled/enabled */
 570         CONTROL_FLAG_IDLE_ENABLE            = 2,
 571         /* Tracker for the SPDIF-in path is bypassed/enabled */
 572         CONTROL_FLAG_TRACKER                = 3,
 573         /* DigitalOut to Spdif2Out connection is disabled/enabled */
 574         CONTROL_FLAG_SPDIF2OUT              = 4,
 575         /* Digital Microphone is disabled/enabled */
 576         CONTROL_FLAG_DMIC                   = 5,
 577         /* ADC_B rate is 48 kHz/96 kHz */
 578         CONTROL_FLAG_ADC_B_96KHZ            = 6,
 579         /* ADC_C rate is 48 kHz/96 kHz */
 580         CONTROL_FLAG_ADC_C_96KHZ            = 7,
 581         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 582         CONTROL_FLAG_DAC_96KHZ              = 8,
 583         /* DSP rate is 48 kHz/96 kHz */
 584         CONTROL_FLAG_DSP_96KHZ              = 9,
 585         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 586         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 587         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 588         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 589         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 590         CONTROL_FLAG_DECODE_LOOP            = 12,
 591         /* De-emphasis filter on DAC-1 disabled/enabled */
 592         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 593         /* De-emphasis filter on DAC-2 disabled/enabled */
 594         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 595         /* De-emphasis filter on DAC-3 disabled/enabled */
 596         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 597         /* High-pass filter on ADC_B disabled/enabled */
 598         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 599         /* High-pass filter on ADC_C disabled/enabled */
 600         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 601         /* Common mode on Port_A disabled/enabled */
 602         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 603         /* Common mode on Port_D disabled/enabled */
 604         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 605         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 606         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 607         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 608         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 609         /* ASI rate is 48kHz/96kHz */
 610         CONTROL_FLAG_ASI_96KHZ              = 22,
 611         /* DAC power settings able to control attached ports no/yes */
 612         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 613         /* Clock Stop OK reporting is disabled/enabled */
 614         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 615         /* Number of control flags */
 616         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 617 };
 618
 619 enum control_param_id {
 620         /* 0: None, 1: Mic1In*/
 621         CONTROL_PARAM_VIP_SOURCE               = 1,
 622         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 623         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 624         /* Port A output stage gain setting to use when 16 Ohm output
 625          * impedance is selected*/
 626         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 627         /* Port D output stage gain setting to use when 16 Ohm output
 628          * impedance is selected*/
 629         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 630
 631         /* Stream Control */
 632
 633         /* Select stream with the given ID */
 634         CONTROL_PARAM_STREAM_ID                = 24,
 635         /* Source connection point for the selected stream */
 636         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 637         /* Destination connection point for the selected stream */
 638         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 639         /* Number of audio channels in the selected stream */
 640         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 641         /*Enable control for the selected stream */
 642         CONTROL_PARAM_STREAM_CONTROL           = 28,
 643
 644         /* Connection Point Control */
 645
 646         /* Select connection point with the given ID */
 647         CONTROL_PARAM_CONN_POINT_ID            = 29,
 648         /* Connection point sample rate */
 649         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 650
 651         /* Node Control */
 652
 653         /* Select HDA node with the given ID */
 654         CONTROL_PARAM_NODE_ID                  = 31
 655 };
 656
 657 enum hda_vendor_status_dspio {
 658         /* Success */
 659         VENDOR_STATUS_DSPIO_OK                       = 0x00,
 660         /* Busy, unable to accept new command, the host must retry */
 661         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
 662         /* SCP command queue is full */
 663         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
 664         /* SCP response queue is empty */
 665         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
 666 };
 667
 668 enum hda_vendor_status_chipio {
 669         /* Success */
 670         VENDOR_STATUS_CHIPIO_OK   = 0x00,
 671         /* Busy, unable to accept new command, the host must retry */
 672         VENDOR_STATUS_CHIPIO_BUSY = 0x01
 673 };
 674
 675 enum ca0132_sample_rate {
 676         SR_6_000        = 0x00,
 677         SR_8_000        = 0x01,
 678         SR_9_600        = 0x02,
 679         SR_11_025       = 0x03,
 680         SR_16_000       = 0x04,
 681         SR_22_050       = 0x05,
 682         SR_24_000       = 0x06,
 683         SR_32_000       = 0x07,
 684         SR_44_100       = 0x08,
 685         SR_48_000       = 0x09,
 686         SR_88_200       = 0x0A,
 687         SR_96_000       = 0x0B,
 688         SR_144_000      = 0x0C,
 689         SR_176_400      = 0x0D,
 690         SR_192_000      = 0x0E,
 691         SR_384_000      = 0x0F,
 692
 693         SR_COUNT        = 0x10,
 694
 695         SR_RATE_UNKNOWN = 0x1F
 696 };
 697
 698 enum dsp_download_state {
 699         DSP_DOWNLOAD_FAILED = -1,
 700         DSP_DOWNLOAD_INIT   = 0,
 701         DSP_DOWNLOADING     = 1,
 702         DSP_DOWNLOADED      = 2
 703 };
 704
 705 struct hda_stream_format {
 706         unsigned int   sample_rate;
 707         unsigned short valid_bits_per_sample;
 708         unsigned short container_size;
 709         unsigned short number_channels;
 710 };
 711
 712 /* retrieve parameters from hda format */
 713 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
 714 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
 715 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
 716 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
 717
 718 struct ca0132_spec {
 719         struct snd_kcontrol_new *mixers[5];
 720         unsigned int num_mixers;
 721         const struct hda_verb *base_init_verbs;
 722         const struct hda_verb *base_exit_verbs;
 723         const struct hda_verb *init_verbs[5];
 724         unsigned int num_init_verbs;  /* exclude base init verbs */
 725         struct auto_pin_cfg autocfg;
 726
 727         /* Nodes configurations */
 728         struct hda_multi_out multiout;
 729         hda_nid_t out_pins[5];
 730         hda_nid_t dacs[5];
 731         unsigned int num_outputs;
 732         hda_nid_t input_pins[5];
 733         hda_nid_t adcs[5];
 734         unsigned int num_inputs;
 735         hda_nid_t shared_mic_nid;
 736         hda_nid_t shared_out_nid;
 737         struct hda_pcm pcm_rec[5];  /* PCM information */
 738
 739         /* chip access */
 740         struct mutex chipio_mutex; /* chip access mutex */
 741         u32 curr_chip_addx;
 742
 743         /* DSP download related */
 744         enum dsp_download_state dsp_state;
 745         unsigned int dsp_stream_id;
 746         unsigned int wait_scp;
 747         unsigned int wait_scp_header;
 748         unsigned int wait_num_data;
 749         unsigned int scp_resp_header;
 750         unsigned int scp_resp_data[4];
 751         unsigned int scp_resp_count;
 752
 753         /* mixer and effects related */
 754         unsigned char dmic_ctl;
 755         int cur_out_type;
 756         int cur_mic_type;
 757         long vnode_lvol[VNODES_COUNT];
 758         long vnode_rvol[VNODES_COUNT];
 759         long vnode_lswitch[VNODES_COUNT];
 760         long vnode_rswitch[VNODES_COUNT];
 761         long effects_switch[EFFECTS_COUNT];
 762         long voicefx_val;
 763         long cur_mic_boost;
 764
 765         #ifdef ENABLE_TUNING_CONTROLS
 766         long cur_ctl_vals[TUNING_CTLS_COUNT];
 767         #endif
 768 };
 769
 770 /*
 771  * CA0132 codec access
 772  */
 773 unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
 774                 unsigned int verb, unsigned int parm, unsigned int *res)
 775 {
 776         unsigned int response;
 777         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
 778         *res = response;
 779
 780         return ((response == -1) ? -1 : 0);
 781 }
 782
 783 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
 784                 unsigned short converter_format, unsigned int *res)
 785 {
 786         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
 787                                 converter_format & 0xffff, res);
 788 }
 789
 790 static int codec_set_converter_stream_channel(struct hda_codec *codec,
 791                                 hda_nid_t nid, unsigned char stream,
 792                                 unsigned char channel, unsigned int *res)
 793 {
 794         unsigned char converter_stream_channel = 0;
 795
 796         converter_stream_channel = (stream << 4) | (channel & 0x0f);
 797         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
 798                                 converter_stream_channel, res);
 799 }
 800
 801 /*
 802  * CA0132 chip access stuffs
 803  */
 804 static int chipio_send(struct hda_codec *codec,
 805                        unsigned int reg,
 806                        u32 data)
 807 {
 808         unsigned int res;
 809         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 810
 811         /* send bits of data specified by reg */
 812         do {
 813                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
 814                                          reg, data);
 815                 if (res == VENDOR_STATUS_CHIPIO_OK)
 816                         return 0;
 817                 msleep(1);
 818         } while (time_before(jiffies, timeout));
 819
 820         CTASSERT(0);
 821         return -1;
 822 }
 823
 824 static int chipio_write_addx(struct hda_codec *codec, u32 chip_addx)
 825 {
 826         struct ca0132_spec *spec = codec->spec;
 827         int status = 0;
 828
 829         if (spec->curr_chip_addx == chip_addx)
 830                 return 0;
 831
 832         /* send low 16 bits of the address */
 833         status = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
 834                              chip_addx & 0xffff);
 835
 836         if (SUCCEEDED(status)) {
 837                 /* send high 16 bits of the address */
 838                 status = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
 839                                      chip_addx >> 16);
 840         }
 841
 842         CTASSERT(SUCCEEDED(status));
 843         spec->curr_chip_addx = SUCCEEDED(status) ? chip_addx : ~0UL;
 844
 845         return status;
 846 }
 847
 848 static int chipio_write_data(struct hda_codec *codec, u32 data)
 849 {
 850         struct ca0132_spec *spec = codec->spec;
 851         int status = 0;
 852
 853         /* send low 16 bits of the data */
 854         status = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
 855
 856         if (SUCCEEDED(status)) {
 857                 /* send high 16 bits of the data */
 858                 status = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
 859                                      data >> 16);
 860         }
 861
 862         CTASSERT(SUCCEEDED(status));
 863         spec->curr_chip_addx = SUCCEEDED(status) ?
 864                                         (spec->curr_chip_addx + 4) : ~0UL;
 865
 866         return status;
 867 }
 868
 869 static int chipio_write_data_multiple(struct hda_codec *codec,
 870                                       const u32 *data,
 871                                       unsigned int count)
 872 {
 873         int status = 0;
 874
 875         if (data == NULL)
 876                 return FAIL_MSG(-1, "chipio_write_data null ptr");
 877
 878         while ((count-- != 0) && (status == 0))
 879                 status = chipio_write_data(codec, *data++);
 880
 881         return status;
 882 }
 883
 884 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
 885 {
 886         struct ca0132_spec *spec = codec->spec;
 887         int status = 0;
 888
 889         /* post read */
 890         status = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
 891
 892         if (SUCCEEDED(status)) {
 893                 /* read status */
 894                 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
 895         }
 896
 897         if (SUCCEEDED(status)) {
 898                 /* read data */
 899                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
 900                                            VENDOR_CHIPIO_HIC_READ_DATA, 0);
 901         }
 902
 903         CTASSERT(SUCCEEDED(status));
 904         spec->curr_chip_addx = SUCCEEDED(status) ?
 905                                         (spec->curr_chip_addx + 4) : ~0UL;
 906
 907         return status;
 908 }
 909
 910 static int chipio_write(struct hda_codec *codec, u32 chip_addx,
 911                         const u32 data)
 912 {
 913         struct ca0132_spec *spec = codec->spec;
 914         int status;
 915
 916         mutex_lock(&spec->chipio_mutex);
 917         status = chipio_write_addx(codec, chip_addx);
 918         if (SUCCEEDED(status))
 919                 status = chipio_write_data(codec, data);
 920         mutex_unlock(&spec->chipio_mutex);
 921
 922         return status;
 923 }
 924
 925 static int chipio_write_multiple(struct hda_codec *codec,
 926                                  u32 chip_addx,
 927                                  const u32 *data,
 928                                  unsigned int count)
 929 {
 930         struct ca0132_spec *spec = codec->spec;
 931         int status;
 932
 933         mutex_lock(&spec->chipio_mutex);
 934         status = chipio_write_addx(codec, chip_addx);
 935         if (SUCCEEDED(status))
 936                 status = chipio_write_data_multiple(codec, data, count);
 937         mutex_unlock(&spec->chipio_mutex);
 938
 939         return status;
 940 }
 941
 942 static int chipio_read(struct hda_codec *codec, u32 chip_addx,
 943                        unsigned int *data)
 944 {
 945         struct ca0132_spec *spec = codec->spec;
 946         int status;
 947
 948         mutex_lock(&spec->chipio_mutex);
 949         status = chipio_write_addx(codec, chip_addx);
 950         if (SUCCEEDED(status))
 951                 status = chipio_read_data(codec, data);
 952         mutex_unlock(&spec->chipio_mutex);
 953
 954         return status;
 955 }
 956
 957 static void chipio_set_control_flag(struct hda_codec *codec,
 958                                     enum control_flag_id flag_id,
 959                                     bool flag_state)
 960 {
 961         unsigned int val;
 962         unsigned int flag_bit;
 963
 964         flag_bit = (flag_state ? 1 : 0);
 965         val = (flag_bit << 7) | (flag_id);
 966         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
 967                             VENDOR_CHIPIO_FLAG_SET, val);
 968 }
 969
 970 static void chipio_set_control_param(struct hda_codec *codec,
 971                 enum control_param_id param_id, int param_val)
 972 {
 973         struct ca0132_spec *spec = codec->spec;
 974         int val;
 975
 976         if ((param_id < 32) && (param_val < 8)) {
 977                 val = (param_val << 5) | (param_id);
 978                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
 979                                     VENDOR_CHIPIO_PARAM_SET, val);
 980         } else {
 981                 mutex_lock(&spec->chipio_mutex);
 982                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
 983                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
 984                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
 985                                             param_id);
 986                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
 987                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
 988                                             param_val);
 989                 } else
 990                         CA0132_LOG("set_control_param:FAIL! id=0x%x, val=%d\n",
 991                                    param_id, param_val);
 992                 mutex_unlock(&spec->chipio_mutex);
 993         }
 994 }
 995
 996 static void chipio_set_conn_rate(struct hda_codec *codec,
 997                                 int connid, enum ca0132_sample_rate rate)
 998 {
 999         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1000         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1001                                  rate);
1002 }
1003
1004 static void chipio_enable_clocks(struct hda_codec *codec)
1005 {
1006         struct ca0132_spec *spec = codec->spec;
1007
1008         mutex_lock(&spec->chipio_mutex);
1009         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1010                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1011         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1012                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1013         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1014                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1015         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1016                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1017         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1018                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1019         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1020                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1021         mutex_unlock(&spec->chipio_mutex);
1022 }
1023
1024
1025 /*
1026  * CA0132 DSP IO stuffs
1027  */
1028 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1029                       unsigned int data)
1030 {
1031         unsigned int res;
1032         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1033
1034         /* send bits of data specified by reg to dsp */
1035         do {
1036                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1037                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1038                         return res;
1039                 msleep(1);
1040         } while (time_before(jiffies, timeout));
1041
1042         CTASSERT(0);
1043         return -1;
1044 }
1045
1046 static void dspio_write_wait(struct hda_codec *codec)
1047 {
1048         int status;
1049         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1050
1051         do {
1052                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1053                                                 VENDOR_DSPIO_STATUS, 0);
1054                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1055                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1056                         break;
1057                 msleep(1);
1058         } while (time_before(jiffies, timeout));
1059 }
1060
1061 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1062 {
1063         struct ca0132_spec *spec = codec->spec;
1064         int status;
1065
1066         dspio_write_wait(codec);
1067
1068         mutex_lock(&spec->chipio_mutex);
1069         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1070                             scp_data & 0xffff);
1071         if (SUCCEEDED(status))
1072                 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1073                                     scp_data >> 16);
1074         mutex_unlock(&spec->chipio_mutex);
1075
1076         /* OK, now check if the write itself has executed*/
1077         if (SUCCEEDED(status))
1078                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1079                                             VENDOR_DSPIO_STATUS, 0);
1080
1081         if (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL)
1082                 CA0132_LOG("dspio_write: SCP_COMMAND_QUEUE_FULL!!!\n\n");
1083
1084         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1085                         -1 : 0;
1086 }
1087
1088 static int dspio_write_multiple(struct hda_codec *codec,
1089                                 unsigned int *buffer, unsigned int size)
1090 {
1091         int status = 0;
1092         unsigned int count;
1093
1094         if ((buffer == NULL))
1095                 return -1;
1096
1097         count = 0;
1098         while (count < size) {
1099                 status = dspio_write(codec, *buffer++);
1100                 if (status != 0)
1101                         break;
1102                 count++;
1103         }
1104
1105         return status;
1106 }
1107
1108 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1109 {
1110         int status;
1111
1112         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1113         if (SUCCEEDED(status))
1114                 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1115
1116         if (FAILED(status) ||
1117             (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1118                 return -1;
1119
1120         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1121                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
1122
1123         return 0;
1124 }
1125
1126 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1127                                unsigned int *buf_size, unsigned int size_count)
1128 {
1129         int status = 0;
1130         unsigned int size = *buf_size;
1131         unsigned int count;
1132         unsigned int skip_count;
1133         unsigned int dummy;
1134
1135         if ((buffer == NULL))
1136                 return -1;
1137
1138         count = 0;
1139         while (count < size && count < size_count) {
1140                 status = dspio_read(codec, buffer++);
1141                 if (status != 0)
1142                         break;
1143                 count++;
1144         }
1145
1146         skip_count = count;
1147         if (SUCCEEDED(status)) {
1148                 while (skip_count < size) {
1149                         status = dspio_read(codec, &dummy);
1150                         if (status != 0)
1151                                 break;
1152                         skip_count++;
1153                 }
1154         }
1155         *buf_size = count;
1156
1157         return status;
1158 }
1159
1160 static inline unsigned int
1161 make_scp_header(unsigned int target_id, unsigned int source_id,
1162                 unsigned int get_flag, unsigned int req,
1163                 unsigned int device_flag, unsigned int resp_flag,
1164                 unsigned int error_flag, unsigned int data_size)
1165 {
1166         unsigned int header = 0;
1167
1168         header = (data_size & 0x1f) << 27;
1169         header |= (error_flag & 0x01) << 26;
1170         header |= (resp_flag & 0x01) << 25;
1171         header |= (device_flag & 0x01) << 24;
1172         header |= (req & 0x7f) << 17;
1173         header |= (get_flag & 0x01) << 16;
1174         header |= (source_id & 0xff) << 8;
1175         header |= target_id & 0xff;
1176
1177         return header;
1178 }
1179
1180 static inline void
1181 extract_scp_header(unsigned int header,
1182                    unsigned int *target_id, unsigned int *source_id,
1183                    unsigned int *get_flag, unsigned int *req,
1184                    unsigned int *device_flag, unsigned int *resp_flag,
1185                    unsigned int *error_flag, unsigned int *data_size)
1186 {
1187         if (data_size)
1188                 *data_size = (header >> 27) & 0x1f;
1189         if (error_flag)
1190                 *error_flag = (header >> 26) & 0x01;
1191         if (resp_flag)
1192                 *resp_flag = (header >> 25) & 0x01;
1193         if (device_flag)
1194                 *device_flag = (header >> 24) & 0x01;
1195         if (req)
1196                 *req = (header >> 17) & 0x7f;
1197         if (get_flag)
1198                 *get_flag = (header >> 16) & 0x01;
1199         if (source_id)
1200                 *source_id = (header >> 8) & 0xff;
1201         if (target_id)
1202                 *target_id = header & 0xff;
1203 }
1204
1205 #define SCP_MAX_DATA_WORDS  (16)
1206
1207 /* Structure to contain any SCP message */
1208 struct scp_msg {
1209         unsigned int hdr;
1210         unsigned int data[SCP_MAX_DATA_WORDS];
1211 };
1212
1213 static void dspio_clear_response_queue(struct hda_codec *codec)
1214 {
1215         unsigned int dummy = 0;
1216         int status = -1;
1217
1218         /* clear all from the response queue */
1219         do {
1220                 status = dspio_read(codec, &dummy);
1221         } while (status == 0);
1222 }
1223
1224 static int dspio_get_response_data(struct hda_codec *codec)
1225 {
1226         struct ca0132_spec *spec = codec->spec;
1227         unsigned int data = 0;
1228         unsigned int count;
1229
1230         if (FAILED(dspio_read(codec, &data)))
1231                 return -1;
1232
1233         CA0132_LOG("dspio_get_response_data: 0x%08x\n", data);
1234         if ((data & 0x00ffffff) == spec->wait_scp_header) {
1235                 spec->scp_resp_header = data;
1236                 spec->scp_resp_count = data >> 27;
1237                 count = spec->wait_num_data;
1238                 dspio_read_multiple(codec, spec->scp_resp_data,
1239                                     &spec->scp_resp_count, count);
1240                 return 0;
1241         }
1242
1243         return -1;
1244 }
1245
1246 static int dspio_send_scp_message(struct hda_codec *codec,
1247                                   unsigned char *send_buf,
1248                                   unsigned int send_buf_size,
1249                                   unsigned char *return_buf,
1250                                   unsigned int return_buf_size,
1251                                   unsigned int *bytes_returned)
1252 {
1253         struct ca0132_spec *spec = codec->spec;
1254         int retry;
1255         int status = -1;
1256         unsigned int scp_send_size = 0;
1257         unsigned int total_size;
1258         bool waiting_for_resp = false;
1259         unsigned int header;
1260         struct scp_msg *ret_msg;
1261         unsigned int resp_src_id, resp_target_id;
1262         unsigned int data_size, src_id, target_id, get_flag, device_flag;
1263
1264         if (bytes_returned)
1265                 *bytes_returned = 0;
1266
1267         /* get scp header from buffer */
1268         header = *((unsigned int *)send_buf);
1269         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1270                            &device_flag, NULL, NULL, &data_size);
1271         scp_send_size = data_size + 1;
1272         total_size = (scp_send_size * 4);
1273
1274         CTASSERT(send_buf_size >= total_size);
1275         if (send_buf_size < total_size)
1276                 return -1;
1277
1278         if (get_flag || device_flag) {
1279                 if (!return_buf || return_buf_size < 4 || !bytes_returned) {
1280                         CTASSERT(0);
1281                         return -1;
1282                 }
1283                 spec->wait_scp_header = *((unsigned int *)send_buf);
1284
1285                 /* swap source id with target id */
1286                 resp_target_id = src_id;
1287                 resp_src_id = target_id;
1288                 spec->wait_scp_header &= 0xffff0000;
1289                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1290                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1291                 spec->wait_scp = 1;
1292                 waiting_for_resp = true;
1293         }
1294
1295         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1296                                       scp_send_size);
1297         if (FAILED(status)) {
1298                 CTASSERT(0);
1299                 spec->wait_scp = 0;
1300                 return status;
1301         }
1302
1303         if (waiting_for_resp) {
1304                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1305                 memset(return_buf, 0, return_buf_size);
1306                 do {
1307                         msleep(1);
1308                 } while (spec->wait_scp && time_before(jiffies, timeout));
1309                 waiting_for_resp = false;
1310                 if (!spec->wait_scp) {
1311                         ret_msg = (struct scp_msg *)return_buf;
1312                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1313                         memcpy(&ret_msg->data, spec->scp_resp_data,
1314                                spec->wait_num_data);
1315                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
1316                         status = 0;
1317                 } else {
1318                         CTASSERT(*bytes_returned == 0);
1319                         status = -1;
1320                 }
1321                 spec->wait_scp = 0;
1322         }
1323
1324         return status;
1325 }
1326
1327 static int dspio_scp(struct hda_codec *codec,
1328                 int mod_id, int req, int dir, void *data, unsigned int len,
1329                 void *reply, unsigned int *reply_len)
1330 {
1331         int status = 0;
1332         struct scp_msg scp_send, scp_reply;
1333         unsigned int ret_bytes, send_size, ret_size;
1334         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1335         unsigned int reply_data_size;
1336
1337         memset(&scp_send, 0, sizeof(scp_send));
1338         memset(&scp_reply, 0, sizeof(scp_reply));
1339
1340         CTASSERT((len == 0 || data != NULL) && len <= SCP_MAX_DATA_WORDS);
1341         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1342                 return -1;
1343
1344         CTASSERT(dir != SCP_GET || reply != NULL);
1345         if (dir == SCP_GET && reply == NULL)
1346                 return FAIL_MSG(-1, "dspio_scp get but has no buffer");
1347
1348         CTASSERT((reply == NULL) || (reply_len != NULL && (*reply_len > 0)));
1349         if (reply != NULL && (reply_len == NULL || (*reply_len == 0)))
1350                 return FAIL_MSG(-1, "dspio_scp bad resp buf len parms");
1351
1352         scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1353                                        0, 0, 0, len/sizeof(unsigned int));
1354         if (data != NULL && len > 0) {
1355                 len = min((unsigned int)(sizeof(scp_send.data)), len);
1356                 memcpy(scp_send.data, data, len);
1357         }
1358
1359         ret_bytes = 0;
1360         send_size = sizeof(unsigned int) + len;
1361         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1362                                         send_size, (unsigned char *)&scp_reply,
1363                                         sizeof(scp_reply), &ret_bytes);
1364
1365 /* for debugging */
1366 #ifdef ENABLE_CA0132_DEBUG
1367 {
1368         unsigned int x, *p, i;
1369         unsigned int source_id;
1370         unsigned int target_id;
1371         unsigned int req;
1372         unsigned int get_flag;
1373         unsigned int resp_flag;
1374         unsigned int device_flag;
1375         unsigned int error_flag;
1376         unsigned int data_size;
1377
1378         memcpy(&x, &scp_send.hdr, sizeof(unsigned int));
1379         extract_scp_header(x, &target_id, &source_id,
1380                            &get_flag, &req, &device_flag, &resp_flag,
1381                            &error_flag, &data_size);
1382
1383         snd_printdd(
1384                 "ScpDispatch ----- REQ: "
1385                 "HDR=0x%08x "
1386                 "SID=%04x "
1387                 "TID=%04x "
1388                 "Req=%04x "
1389                 "GRDE=%d %d %d %d "
1390                 "Siz=%d [ ",
1391                 x,
1392                 source_id,
1393                 target_id,
1394                 req,
1395                 get_flag,
1396                 resp_flag,
1397                 device_flag,
1398                 error_flag,
1399                 data_size);
1400
1401         for (x = 0; x < data_size; x++)
1402                 snd_printdd("0x%08x ", scp_send.data[x].ui);
1403
1404         snd_printdd("]\n");
1405
1406         if (get_flag) {
1407                 if (ret_bytes >= sizeof(scp_reply.hdr)) {
1408                         memcpy(&x, &scp_reply.hdr, sizeof(unsigned int));
1409                         extract_scp_header(x, &target_id, &source_id,
1410                                            &get_flag, &req, &device_flag,
1411                                            &resp_flag, &error_flag, &data_size);
1412
1413                         snd_printdd(
1414                                 "            ----- REP: "
1415                                 "HDR=0x%08x "
1416                                 "SID=%04x "
1417                                 "TID=%04x "
1418                                 "Req=%04x "
1419                                 "GRDE=%d %d %d %d "
1420                                 "Siz=%d [ ",
1421                                 x,
1422                                 source_id,
1423                                 target_id,
1424                                 req,
1425                                 get_flag,
1426                                 resp_flag,
1427                                 device_flag,
1428                                 error_flag,
1429                                 data_size);
1430
1431                         for (x = 0; x < data_size; x++)
1432                                 snd_printdd("0x%08x ", scp_reply.data[x].ui);
1433                 } else {
1434                         snd_printdd("REP: (too short,nbytes=%d) [", ret_bytes);
1435
1436                         for (p = (unsigned int *)&scp_reply, i = 0;
1437                                 i < ret_bytes; p++, i++) {
1438                                 snd_printdd("0x%04x ", *p);
1439                         }
1440                 }
1441                 snd_printdd("]\n");
1442         }
1443 }
1444 #endif
1445
1446         if (FAILED(status))
1447                 return FAIL_MSG(status, "dspio_scp: send scp msg failed");
1448
1449         /* extract send and reply headers members */
1450         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1451                            NULL, NULL, NULL, NULL, NULL);
1452         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1453                            &reply_resp_flag, &reply_error_flag,
1454                            &reply_data_size);
1455
1456         if (!send_get_flag)
1457                 return 0;
1458
1459         if (reply_resp_flag && !reply_error_flag) {
1460                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1461                                         / sizeof(unsigned int);
1462
1463                 CTASSERT(dir == SCP_GET && reply != NULL && reply_len != NULL);
1464
1465                 if (*reply_len < ret_size*sizeof(unsigned int)) {
1466                         status = FAIL_MSG(-1, "reply too long for buf");
1467                 } else if (ret_size != reply_data_size) {
1468                         status = FAIL_MSG(-1, "RetLen and HdrLen .NE.");
1469                 } else {
1470                         *reply_len = ret_size*sizeof(unsigned int);
1471                         memcpy(reply, scp_reply.data, *reply_len);
1472                 }
1473         } else {
1474                 status = FAIL_MSG(-1, "reply ill-formed or errflag set");
1475         }
1476
1477         return status;
1478 }
1479
1480 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1481                         int req, void *data, unsigned int len)
1482 {
1483         return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1484 }
1485
1486 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1487 {
1488         int status = 0;
1489         unsigned int size = sizeof(dma_chan);
1490
1491         CA0132_DSP_LOG("     dspio_alloc_dma_chan() -- begin");
1492         status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1493                         SCP_GET, NULL, 0, dma_chan, &size);
1494
1495         if (FAILED(status)) {
1496                 CA0132_DSP_LOG("dspio_alloc_dma_chan: SCP Failed");
1497                 return -1;
1498         }
1499
1500         if ((*dma_chan + 1) == 0) {
1501                 CA0132_DSP_LOG("no free dma channels to allocate");
1502                 return -1;
1503         }
1504
1505         CA0132_LOG("dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1506         CA0132_DSP_LOG("     dspio_alloc_dma_chan() -- complete");
1507
1508         return status;
1509 }
1510
1511 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1512 {
1513         int status = 0;
1514         unsigned int dummy = 0;
1515
1516         CA0132_DSP_LOG("     dspio_free_dma_chan() -- begin");
1517         CA0132_LOG("dspio_free_dma_chan: chan=%d\n", dma_chan);
1518
1519         status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1520                            SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1521
1522         if (FAILED(status)) {
1523                 CA0132_DSP_LOG("dspio_free_dma_chan: SCP Failed");
1524                 return -1;
1525         }
1526
1527         CA0132_DSP_LOG("     dspio_free_dma_chan() -- complete");
1528
1529         return status;
1530 }
1531
1532 /*
1533  * CA0132 DSP access stuffs
1534  */
1535 static int dsp_set_run_state(struct hda_codec *codec)
1536 {
1537         unsigned int dbg_ctrl_reg;
1538         unsigned int halt_state;
1539         int err;
1540
1541         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1542         if (err < 0)
1543                 return err;
1544
1545         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1546                       DSP_DBGCNTL_STATE_LOBIT;
1547
1548         if (halt_state != 0) {
1549                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1550                                   DSP_DBGCNTL_SS_MASK);
1551                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1552                                    dbg_ctrl_reg);
1553                 if (err < 0)
1554                         return err;
1555
1556                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1557                                 DSP_DBGCNTL_EXEC_MASK;
1558                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1559                                    dbg_ctrl_reg);
1560                 if (err < 0)
1561                         return err;
1562         }
1563
1564         return 0;
1565 }
1566
1567 static int dsp_reset(struct hda_codec *codec)
1568 {
1569         unsigned int res;
1570         int retry = 20;
1571
1572         CA0132_LOG("dsp_reset\n");
1573         do {
1574                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1575                 retry--;
1576         } while (res == -1 && retry);
1577
1578         if (!retry) {
1579                 CA0132_LOG("dsp_reset timeout\n");
1580                 return -1;
1581         }
1582
1583         return 0;
1584 }
1585
1586 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1587                                         bool *code, bool *yram)
1588 {
1589         *code = *yram = false;
1590
1591         if (UC_RANGE(chip_addx, 1)) {
1592                 *code = true;
1593                 return UC_OFF(chip_addx);
1594         } else if (X_RANGE_ALL(chip_addx, 1)) {
1595                 return X_OFF(chip_addx);
1596         } else if (Y_RANGE_ALL(chip_addx, 1)) {
1597                 *yram = true;
1598                 return Y_OFF(chip_addx);
1599         }
1600
1601         return (unsigned int)INVALID_CHIP_ADDRESS;
1602 }
1603
1604 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1605 {
1606         unsigned int dma_chnlstart_reg;
1607
1608         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1609
1610         return ((dma_chnlstart_reg & (1 <<
1611                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1612 }
1613
1614 static int dsp_dma_setup_common(struct hda_codec *codec,
1615                                 unsigned int chip_addx,
1616                                 unsigned int dma_chan,
1617                                 unsigned int port_map_mask,
1618                                 bool ovly)
1619 {
1620         int status = 0;
1621         unsigned int chnl_prop;
1622         unsigned int dsp_addx;
1623         unsigned int active;
1624         bool code, yram;
1625
1626         CA0132_DSP_LOG("-- dsp_dma_setup_common() -- Begin ---------");
1627
1628         CTASSERT(dma_chan < DSPDMAC_DMA_CFG_CHANNEL_COUNT);
1629         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT)
1630                 return FAIL_MSG(-1, "dma chan num invalid");
1631
1632         if (dsp_is_dma_active(codec, dma_chan))
1633                 return FAIL_MSG(-1, "dma already active");
1634
1635         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1636
1637         if (dsp_addx == INVALID_CHIP_ADDRESS)
1638                 return FAIL_MSG(-1, "invalid chip addr");
1639
1640         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1641         active = 0;
1642
1643         CA0132_DSP_LOG("   dsp_dma_setup_common()    start reg pgm");
1644
1645         if (ovly) {
1646                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1647                                      &chnl_prop);
1648
1649                 if (FAILED(status))
1650                         return FAIL_MSG(-1, "read CHNLPROP Reg fail");
1651
1652                 CA0132_DSP_LOG("   dsp_dma_setup_common()    Read CHNLPROP");
1653         }
1654
1655         if (!code)
1656                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1657         else
1658                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1659
1660         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1661
1662         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1663         if (FAILED(status))
1664                 return FAIL_MSG(-1, "write CHNLPROP Reg fail");
1665
1666         CA0132_DSP_LOG("   dsp_dma_setup_common()    Write CHNLPROP");
1667
1668         if (ovly) {
1669                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1670                                      &active);
1671
1672                 if (FAILED(status))
1673                         return FAIL_MSG(-1, "read ACTIVE Reg fail");
1674
1675                 CA0132_DSP_LOG("   dsp_dma_setup_common()    Read ACTIVE");
1676         }
1677
1678         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1679                 DSPDMAC_ACTIVE_AAR_MASK;
1680
1681         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1682         if (FAILED(status))
1683                 return FAIL_MSG(-1, "write ACTIVE Reg fail");
1684
1685         CA0132_DSP_LOG("   dsp_dma_setup_common()    Write ACTIVE");
1686
1687         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1688                               port_map_mask);
1689         if (FAILED(status))
1690                 return FAIL_MSG(-1, "write AUDCHSEL Reg fail");
1691
1692         CA0132_DSP_LOG("   dsp_dma_setup_common()    Write AUDCHSEL");
1693
1694         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1695                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1696         if (FAILED(status))
1697                 return FAIL_MSG(-1, "write IRQCNT Reg fail");
1698
1699         CA0132_DSP_LOG("   dsp_dma_setup_common()    Write IRQCNT");
1700
1701         CA0132_LOG(
1702                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1703                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1704                    chip_addx, dsp_addx, dma_chan,
1705                    port_map_mask, chnl_prop, active);
1706
1707         CA0132_DSP_LOG("-- dsp_dma_setup_common() -- Complete ---------");
1708
1709         return 0;
1710 }
1711
1712 static int dsp_dma_setup(struct hda_codec *codec,
1713                         unsigned int chip_addx,
1714                         unsigned int count,
1715                         unsigned int dma_chan)
1716 {
1717         int status = 0;
1718         bool code, yram;
1719         unsigned int dsp_addx;
1720         unsigned int addr_field;
1721         unsigned int incr_field;
1722         unsigned int base_cnt;
1723         unsigned int cur_cnt;
1724         unsigned int dma_cfg = 0;
1725         unsigned int adr_ofs = 0;
1726         unsigned int xfr_cnt = 0;
1727         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1728                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1729
1730         CA0132_DSP_LOG("-- dsp_dma_setup() -- Begin ---------");
1731
1732         CTASSERT(count <= max_dma_count);
1733         if (count > max_dma_count)
1734                 return FAIL_MSG(-1, "count too big");
1735
1736         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1737         if (dsp_addx == INVALID_CHIP_ADDRESS)
1738                 return FAIL_MSG(-1, "invalid chip addr");
1739
1740         CA0132_DSP_LOG("   dsp_dma_setup()    start reg pgm");
1741
1742         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1743         incr_field   = 0;
1744
1745         if (!code) {
1746                 addr_field <<= 1;
1747                 if (yram)
1748                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1749
1750                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1751         }
1752
1753         CTASSERT((addr_field & DSPDMAC_DMACFG_DBADR_MASK) == addr_field);
1754         dma_cfg = addr_field + incr_field;
1755         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1756                                 dma_cfg);
1757         if (FAILED(status))
1758                 return FAIL_MSG(-1, "write DMACFG Reg fail");
1759
1760         CA0132_DSP_LOG("   dsp_dma_setup()    Write DMACFG");
1761
1762         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1763                                                         (code ? 0 : 1));
1764         CTASSERT((adr_ofs & DSPDMAC_DSPADROFS_BOFS_MASK) == adr_ofs);
1765
1766         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1767                                 adr_ofs);
1768         if (FAILED(status))
1769                 return FAIL_MSG(-1, "write DSPADROFS Reg fail");
1770
1771         CA0132_DSP_LOG("   dsp_dma_setup()    Write DSPADROFS");
1772
1773         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1774         CTASSERT((base_cnt & DSPDMAC_XFRCNT_BCNT_MASK) == base_cnt);
1775
1776         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1777         CTASSERT((cur_cnt  & DSPDMAC_XFRCNT_CCNT_MASK) == cur_cnt);
1778
1779         xfr_cnt = base_cnt | cur_cnt;
1780
1781         status = chipio_write(codec,
1782                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1783         if (FAILED(status))
1784                 return FAIL_MSG(-1, "write XFRCNT Reg fail");
1785
1786         CA0132_DSP_LOG("   dsp_dma_setup()    Write XFRCNT");
1787
1788         CA0132_LOG(
1789                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1790                    "ADROFS=0x%x, XFRCNT=0x%x\n",
1791                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1792
1793         CA0132_DSP_LOG("-- dsp_dma_setup() -- Complete ---------");
1794
1795         return 0;
1796 }
1797
1798 static int dsp_dma_start(struct hda_codec *codec,
1799                          unsigned int dma_chan, bool ovly)
1800 {
1801         unsigned int reg = 0;
1802         int status = 0;
1803
1804         CA0132_DSP_LOG("-- dsp_dma_start() -- Begin ---------");
1805
1806         if (ovly) {
1807                 status = chipio_read(codec,
1808                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1809
1810                 if (FAILED(status))
1811                         return FAIL_MSG(-1, "read CHNLSTART reg fail");
1812
1813                 CA0132_DSP_LOG("-- dsp_dma_start()    Read CHNLSTART");
1814
1815                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1816                                 DSPDMAC_CHNLSTART_DIS_MASK);
1817         }
1818
1819         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1820                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1821         if (FAILED(status))
1822                 return FAIL_MSG(-1, "write CHNLSTART reg fail");
1823
1824         CA0132_DSP_LOG("-- dsp_dma_start() -- Complete ---------");
1825
1826         return status;
1827 }
1828
1829 static int dsp_dma_stop(struct hda_codec *codec,
1830                         unsigned int dma_chan, bool ovly)
1831 {
1832         unsigned int reg = 0;
1833         int status = 0;
1834
1835         CA0132_DSP_LOG("-- dsp_dma_stop() -- Begin ---------");
1836
1837         if (ovly) {
1838                 status = chipio_read(codec,
1839                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1840
1841                 if (FAILED(status))
1842                         return FAIL_MSG(-1, "read CHNLSTART reg fail");
1843
1844                 CA0132_DSP_LOG("-- dsp_dma_stop()    Read CHNLSTART");
1845                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1846                                 DSPDMAC_CHNLSTART_DIS_MASK);
1847         }
1848
1849         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1850                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1851         if (FAILED(status))
1852                 return FAIL_MSG(-1, "write CHNLSTART reg fail");
1853
1854         CA0132_DSP_LOG("-- dsp_dma_stop() -- Complete ---------");
1855
1856         return status;
1857 }
1858
1859 static int dsp_allocate_router_ports(struct hda_codec *codec,
1860                                      unsigned int num_chans,
1861                                      unsigned int ports_per_channel,
1862                                      unsigned int start_device,
1863                                      unsigned int *port_map)
1864 {
1865         int status = 0;
1866         int res;
1867         u8 val;
1868
1869         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1870         if (FAILED(status))
1871                 return status;
1872
1873         val = start_device << 6;
1874         val |= (ports_per_channel - 1) << 4;
1875         val |= num_chans - 1;
1876
1877         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1878                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1879                             val);
1880
1881         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1882                             VENDOR_CHIPIO_PORT_ALLOC_SET,
1883                             MEM_CONNID_DSP);
1884
1885         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1886         if (FAILED(status))
1887                 return status;
1888
1889         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1890                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1891
1892         *port_map = res;
1893
1894         return (res < 0) ? -1 : 0;
1895 }
1896
1897 static int dsp_free_router_ports(struct hda_codec *codec)
1898 {
1899         int status = 0;
1900
1901         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1902         if (FAILED(status))
1903                 return status;
1904
1905         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1906                             VENDOR_CHIPIO_PORT_FREE_SET,
1907                             MEM_CONNID_DSP);
1908
1909         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1910
1911         return status;
1912 }
1913
1914 static int dsp_allocate_ports(struct hda_codec *codec,
1915                         unsigned int num_chans,
1916                         unsigned int rate_multi, unsigned int *port_map)
1917 {
1918         int status = -1;
1919
1920         CA0132_DSP_LOG("     dsp_allocate_ports() -- begin");
1921
1922         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4))
1923                 return FAIL_MSG(status, "bad rate multiple");
1924
1925         status = dsp_allocate_router_ports(codec, num_chans,
1926                                            rate_multi, 0, port_map);
1927
1928         CA0132_DSP_LOG("     dsp_allocate_ports() -- complete");
1929
1930         return status;
1931 }
1932
1933 static int dsp_free_ports(struct hda_codec *codec)
1934 {
1935         int status;
1936
1937         CA0132_DSP_LOG("     dsp_free_ports() -- begin");
1938
1939         status = dsp_free_router_ports(codec);
1940         if (FAILED(status))
1941                 return FAIL_MSG(-1, "free router ports fail");
1942
1943         CA0132_DSP_LOG("     dsp_free_ports() -- complete");
1944
1945         return status;
1946 }
1947
1948 static int dsp_allocate_ports_format(struct hda_codec *codec,
1949                         const unsigned short fmt,
1950                         unsigned int *port_map)
1951 {
1952         int status = -1;
1953         unsigned int num_chans;
1954
1955         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
1956         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
1957         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
1958
1959         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4))
1960                 return FAIL_MSG(-1, "bad rate multiple");
1961
1962         num_chans = get_hdafmt_chs(fmt) + 1;
1963
1964         status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
1965
1966         return status;
1967 }
1968
1969 /*
1970  *  HDA DMA engine stuffs for DSP code download
1971  */
1972 struct dma_engine {
1973         struct hda_codec *codec;
1974         unsigned short m_converter_format;
1975         struct snd_dma_buffer *dmab;
1976         unsigned int buf_size;
1977 };
1978
1979 enum dma_state {
1980         DMA_STATE_STOP  = 0,
1981         DMA_STATE_RUN   = 1
1982 };
1983
1984 static int dma_convert_to_hda_format(
1985                 struct hda_stream_format *stream_format,
1986                 unsigned short *hda_format)
1987 {
1988         unsigned int format_val;
1989
1990         format_val = snd_hda_calc_stream_format(
1991                                 stream_format->sample_rate,
1992                                 stream_format->number_channels,
1993                                 SNDRV_PCM_FORMAT_S32_LE,
1994                                 stream_format->container_size, 0);
1995
1996         if (hda_format)
1997                 *hda_format = (unsigned short)format_val;
1998
1999         return 0;
2000 }
2001
2002 static int dma_reset(struct dma_engine *dma)
2003 {
2004         struct hda_codec *codec = dma->codec;
2005         struct ca0132_spec *spec = codec->spec;
2006         int status;
2007
2008         snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2009
2010         status = snd_hda_codec_load_dsp_prepare(codec,
2011                         dma->m_converter_format,
2012                         dma->buf_size,
2013                         dma->dmab);
2014         if (FAILED(status))
2015                 return status;
2016         spec->dsp_stream_id = status;
2017
2018         return 0;
2019 }
2020
2021 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2022 {
2023         bool cmd;
2024
2025         CA0132_LOG("dma_set_state state=%d\n", state);
2026
2027         switch (state) {
2028         case DMA_STATE_STOP:
2029                 cmd = false;
2030                 break;
2031         case DMA_STATE_RUN:
2032                 cmd = true;
2033                 break;
2034         default:
2035                 return 0;
2036         }
2037
2038         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2039         return 0;
2040 }
2041
2042 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2043 {
2044         return dma->dmab->bytes;
2045 }
2046
2047 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2048 {
2049         return dma->dmab->area;
2050 }
2051
2052 static int dma_xfer(struct dma_engine *dma,
2053                 const unsigned int *data,
2054                 unsigned int count)
2055 {
2056         memcpy(dma->dmab->area, data, count);
2057         return 0;
2058 }
2059
2060 static void dma_get_converter_format(
2061                 struct dma_engine *dma,
2062                 unsigned short *format)
2063 {
2064         if (format)
2065                 *format = dma->m_converter_format;
2066 }
2067
2068 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2069 {
2070         struct ca0132_spec *spec = dma->codec->spec;
2071
2072         return spec->dsp_stream_id;
2073 }
2074
2075
2076 /*
2077  * CA0132 chip DSP image segment stuffs
2078  */
2079 struct dsp_image_seg {
2080         u32 magic;
2081         u32 chip_addr;
2082         u32 count;
2083         u32 data[0];
2084 };
2085
2086 static const u32 g_magic_value = 0x4c46584d;
2087 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2088
2089 static bool is_valid(const struct dsp_image_seg *p)
2090 {
2091         return p->magic == g_magic_value;
2092 }
2093
2094 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2095 {
2096         return g_chip_addr_magic_value == p->chip_addr;
2097 }
2098
2099 static bool is_last(const struct dsp_image_seg *p)
2100 {
2101         return p->count == 0;
2102 }
2103
2104 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2105 {
2106         return sizeof(*p) + p->count*sizeof(u32);
2107 }
2108
2109 static const struct dsp_image_seg *get_next_seg_ptr(
2110                                 const struct dsp_image_seg *p)
2111 {
2112         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2113 }
2114
2115 /*
2116  * CA0132 chip DSP trannsfer stuffs.  For DSP download.
2117  */
2118 #define INVALID_DMA_CHANNEL (~0UL)
2119
2120 static int dspxfr_hci_write(struct hda_codec *codec,
2121                         const struct dsp_image_seg *fls)
2122 {
2123         int status = 0;
2124         const u32 *data;
2125         unsigned int count;
2126
2127         CTASSERT(fls != NULL && fls->chip_addr == g_chip_addr_magic_value);
2128         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value)
2129                 return FAIL_MSG(-1, "hci_write invalid params");
2130
2131         count = fls->count;
2132         data = (u32 *)(fls->data);
2133         while (SUCCEEDED(status) && count >= 2) {
2134                 status = chipio_write(codec, data[0], data[1]);
2135                 if (FAILED(status))
2136                         status = FAIL_MSG(status, "hci_write chipio failed");
2137                 count -= 2;
2138                 data  += 2;
2139         }
2140         return status;
2141 }
2142
2143 static int dspxfr_one_seg(struct hda_codec *codec,
2144                         const struct dsp_image_seg *fls,
2145                         unsigned int reloc,
2146                         struct dma_engine *dma_engine,
2147                         unsigned int dma_chan,
2148                         unsigned int port_map_mask,
2149                         bool ovly)
2150 {
2151         int status = 0;
2152         bool comm_dma_setup_done = false;
2153         const unsigned int *data;
2154         unsigned int chip_addx;
2155         unsigned int words_to_write;
2156         unsigned int buffer_size_words;
2157         unsigned char *buffer_addx;
2158         unsigned short hda_format;
2159         unsigned int sample_rate_div;
2160         unsigned int sample_rate_mul;
2161         unsigned int num_chans;
2162         unsigned int hda_frame_size_words;
2163         unsigned int remainder_words;
2164         const u32 *data_remainder;
2165         u32 chip_addx_remainder;
2166         unsigned int run_size_words;
2167         const struct dsp_image_seg *hci_write = NULL;
2168         unsigned long timeout;
2169         bool dma_active;
2170
2171         CTASSERT(fls != NULL);
2172         if (fls == NULL)
2173                 return -1;
2174         if (is_hci_prog_list_seg(fls)) {
2175                 hci_write = fls;
2176                 fls = get_next_seg_ptr(fls);
2177         }
2178
2179         if (hci_write && (!fls || is_last(fls))) {
2180                 CA0132_LOG("hci_write\n");
2181                 return dspxfr_hci_write(codec, hci_write);
2182         }
2183
2184         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2185                 CA0132_LOG("Invalid Params\n");
2186                 return -1;
2187         }
2188
2189         data = fls->data;
2190         chip_addx = fls->chip_addr,
2191         words_to_write = fls->count;
2192
2193         if (!words_to_write)
2194                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2195         if (reloc)
2196                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2197
2198         if (!UC_RANGE(chip_addx, words_to_write) &&
2199             !X_RANGE_ALL(chip_addx, words_to_write) &&
2200             !Y_RANGE_ALL(chip_addx, words_to_write)) {
2201                 CA0132_LOG("Invalid chip_addx Params\n");
2202                 return -1;
2203         }
2204
2205         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2206                                         sizeof(u32);
2207
2208         buffer_addx = dma_get_buffer_addr(dma_engine);
2209
2210         if (buffer_addx == NULL)
2211                 status = FAIL_MSG(-1, "dma_engine buffer NULL");
2212
2213         dma_get_converter_format(dma_engine, &hda_format);
2214         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2215         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2216         num_chans = get_hdafmt_chs(hda_format) + 1;
2217
2218         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2219                         (num_chans * sample_rate_mul / sample_rate_div));
2220
2221         buffer_size_words = min(buffer_size_words,
2222                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2223                                 65536 : 32768));
2224         buffer_size_words -= buffer_size_words % hda_frame_size_words;
2225         CA0132_LOG(
2226                    "chpadr=0x%08x frmsz=%u nchan=%u "
2227                    "rate_mul=%u div=%u bufsz=%u\n",
2228                    chip_addx, hda_frame_size_words, num_chans,
2229                    sample_rate_mul, sample_rate_div, buffer_size_words);
2230
2231         CTASSERT(SUCCEEDED(status));
2232         CTASSERT(buffer_addx != NULL);
2233         CTASSERT(buffer_size_words >= hda_frame_size_words);
2234         CTASSERT(hda_frame_size_words > 0);
2235
2236         if ((buffer_addx == NULL) || (hda_frame_size_words == 0) ||
2237             (buffer_size_words < hda_frame_size_words)) {
2238                 status = FAIL_MSG(-1, "dspxfr_one_seg:failed");
2239         }
2240
2241         if (FAILED(status))
2242                 return status;
2243
2244         remainder_words = words_to_write % hda_frame_size_words;
2245         data_remainder = data;
2246         chip_addx_remainder = chip_addx;
2247
2248         data += remainder_words;
2249         chip_addx += remainder_words*sizeof(u32);
2250         words_to_write -= remainder_words;
2251
2252         while ((words_to_write != 0) && SUCCEEDED(status)) {
2253                 run_size_words = min(buffer_size_words, words_to_write);
2254                 CA0132_LOG("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2255                            words_to_write, run_size_words, remainder_words);
2256                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2257                 if (!comm_dma_setup_done && SUCCEEDED(status)) {
2258                         status = dsp_dma_stop(codec, dma_chan, ovly);
2259                         if (SUCCEEDED(status))
2260                                 status = dsp_dma_setup_common(codec, chip_addx,
2261                                                 dma_chan, port_map_mask, ovly);
2262                         comm_dma_setup_done = true;
2263                 }
2264
2265                 if (SUCCEEDED(status))
2266                         status = dsp_dma_setup(codec, chip_addx,
2267                                                 run_size_words, dma_chan);
2268                 if (SUCCEEDED(status))
2269                         status = dsp_dma_start(codec, dma_chan, ovly);
2270                 if (SUCCEEDED(status) && !dsp_is_dma_active(codec, dma_chan))
2271                         status = FAIL_MSG(-1, "dspxfr:DMA did not start");
2272                 if (SUCCEEDED(status))
2273                         status = dma_set_state(dma_engine, DMA_STATE_RUN);
2274                 if (SUCCEEDED(status)) {
2275                         if (remainder_words != 0) {
2276                                 status = chipio_write_multiple(codec,
2277                                                         chip_addx_remainder,
2278                                                         data_remainder,
2279                                                         remainder_words);
2280                                 remainder_words = 0;
2281                         }
2282                         if (hci_write) {
2283                                 status = dspxfr_hci_write(codec, hci_write);
2284                                 hci_write = NULL;
2285                         }
2286
2287                         timeout = jiffies + msecs_to_jiffies(2000);
2288                         do {
2289                                 dma_active = dsp_is_dma_active(codec, dma_chan);
2290                                 if (!dma_active)
2291                                         break;
2292                                 msleep(1);
2293                         } while (time_before(jiffies, timeout));
2294                         if (dma_active)
2295                                 break;
2296                         CA0132_DSP_LOG("+++++ DMA complete");
2297                         dma_set_state(dma_engine, DMA_STATE_STOP);
2298                         status = dma_reset(dma_engine);
2299                         if (FAILED(status))
2300                                 break;
2301                 }
2302
2303                 CTASSERT(run_size_words <= words_to_write);
2304                 data += run_size_words;
2305                 chip_addx += run_size_words*sizeof(u32);
2306                 words_to_write -= run_size_words;
2307         }
2308
2309         if (SUCCEEDED(status) && (remainder_words != 0)) {
2310                 status = chipio_write_multiple(codec, chip_addx_remainder,
2311                                         data_remainder, remainder_words);
2312         }
2313
2314         return status;
2315 }
2316
2317 static int dspxfr_image(struct hda_codec *codec,
2318                         const struct dsp_image_seg *fls_data,
2319                         unsigned int reloc, struct hda_stream_format *format,
2320                         bool ovly)
2321 {
2322         struct ca0132_spec *spec = codec->spec;
2323         int status = 0;
2324         unsigned short hda_format = 0;
2325         unsigned int response;
2326         unsigned char stream_id = 0;
2327         struct dma_engine *dma_engine;
2328         unsigned int dma_chan;
2329         unsigned int port_map_mask;
2330
2331         CTASSERT(fls_data != NULL);
2332         if (fls_data == NULL)
2333                 return -1;
2334
2335         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2336         if (!dma_engine) {
2337                 status = -ENOMEM;
2338                 goto exit;
2339         }
2340
2341         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2342         if (!dma_engine->dmab) {
2343                 status = -ENOMEM;
2344                 goto free_dma_engine;
2345         }
2346
2347         dma_engine->codec = codec;
2348         dma_convert_to_hda_format(format, &hda_format);
2349         dma_engine->m_converter_format = hda_format;
2350         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2351                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2352
2353         dma_chan = 0;
2354         do {
2355                 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2356                                                 hda_format, &response);
2357
2358                 if (FAILED(status)) {
2359                         status = FAIL_MSG(status, "set converter format fail");
2360                         goto free_dma_engine_and_dmab;
2361                 }
2362
2363                 status = snd_hda_codec_load_dsp_prepare(codec,
2364                                         dma_engine->m_converter_format,
2365                                         dma_engine->buf_size,
2366                                         dma_engine->dmab);
2367                 if (FAILED(status))
2368                         break;
2369                 spec->dsp_stream_id = status;
2370
2371                 if (ovly) {
2372                         status = dspio_alloc_dma_chan(codec, &dma_chan);
2373                         if (FAILED(status)) {
2374                                 status = FAIL_MSG(status, "alloc dmachan fail");
2375                                 dma_chan = (unsigned int)INVALID_DMA_CHANNEL;
2376                                 break;
2377                         }
2378                 }
2379
2380                 port_map_mask = 0;
2381                 status = dsp_allocate_ports_format(codec, hda_format,
2382                                                 &port_map_mask);
2383                 if (FAILED(status)) {
2384                         status = FAIL_MSG(status, "alloc parts fail");
2385                         break;
2386                 }
2387
2388                 stream_id = dma_get_stream_id(dma_engine);
2389                 status = codec_set_converter_stream_channel(codec,
2390                                 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2391                 if (FAILED(status)) {
2392                         status = FAIL_MSG(status, "set stream chan fail");
2393                         break;
2394                 }
2395
2396                 while (SUCCEEDED(status) && (fls_data != NULL) &&
2397                                         !is_last(fls_data)) {
2398                         if (!is_valid(fls_data)) {
2399                                 status = FAIL_MSG(-1, "FLS check fail");
2400                                 break;
2401                         }
2402                         status = dspxfr_one_seg(codec, fls_data, reloc,
2403                                                 dma_engine, dma_chan,
2404                                                 port_map_mask, ovly);
2405                         if (is_hci_prog_list_seg(fls_data))
2406                                 fls_data = get_next_seg_ptr(fls_data);
2407
2408                         CTASSERT(fls_data != NULL);
2409                         if ((fls_data != NULL) && !is_last(fls_data))
2410                                 fls_data = get_next_seg_ptr(fls_data);
2411
2412                         CTASSERT(fls_data != NULL);
2413                 }
2414
2415                 if (port_map_mask != 0)
2416                         status = dsp_free_ports(codec);
2417
2418                 if (FAILED(status))
2419                         break;
2420
2421                 status = codec_set_converter_stream_channel(codec,
2422                                         WIDGET_CHIP_CTRL, 0, 0, &response);
2423         } while (0);
2424
2425         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2426                 status = dspio_free_dma_chan(codec, dma_chan);
2427
2428         snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2429 free_dma_engine_and_dmab:
2430         kfree(dma_engine->dmab);
2431 free_dma_engine:
2432         kfree(dma_engine);
2433 exit:
2434         return status;
2435 }
2436
2437 /*
2438  * CA0132 DSP download stuffs.
2439  */
2440 static void dspload_post_setup(struct hda_codec *codec)
2441 {
2442         CA0132_DSP_LOG("---- dspload_post_setup ------");
2443
2444         /*set DSP speaker to 2.0 configuration*/
2445         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2446         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2447
2448         /*update write pointer*/
2449         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2450 }
2451
2452 static int dspload_image(struct hda_codec *codec,
2453                         const struct dsp_image_seg *fls,
2454                         bool ovly,
2455                         unsigned int reloc,
2456                         bool autostart,
2457                         int router_chans)
2458 {
2459         int status = 0;
2460         struct hda_stream_format stream_format;
2461
2462         CA0132_DSP_LOG("---- dspload_image begin ------");
2463         if (router_chans == 0) {
2464                 if (!ovly)
2465                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2466                 else
2467                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2468         }
2469
2470         stream_format.sample_rate = 48000;
2471         stream_format.number_channels = (unsigned short)router_chans;
2472
2473         while (stream_format.number_channels > 16) {
2474                 stream_format.sample_rate *= 2;
2475                 stream_format.number_channels /= 2;
2476         }
2477
2478         stream_format.container_size = 32;
2479         stream_format.valid_bits_per_sample = 32;
2480
2481         do {
2482                 CA0132_DSP_LOG("Ready to program DMA");
2483                 if (!ovly)
2484                         status = dsp_reset(codec);
2485
2486                 if (FAILED(status))
2487                         break;
2488
2489                 CA0132_DSP_LOG("dsp_reset() complete");
2490                 status = dspxfr_image(codec, fls, reloc, &stream_format, ovly);
2491
2492                 if (FAILED(status))
2493                         break;
2494
2495                 CA0132_DSP_LOG("dspxfr_image() complete");
2496                 if (autostart && !ovly) {
2497                         dspload_post_setup(codec);
2498                         status = dsp_set_run_state(codec);
2499                 }
2500
2501                 CA0132_DSP_LOG("LOAD FINISHED");
2502         } while (0);
2503
2504         return status;
2505 }
2506
2507 static int dspload_get_speakereq_addx(struct hda_codec *codec,
2508                                 unsigned int *x,
2509                                 unsigned int *y)
2510 {
2511         int status = 0;
2512         struct { unsigned short y, x; } speakereq_info;
2513         unsigned int size = sizeof(speakereq_info);
2514
2515         CA0132_DSP_LOG("dspload_get_speakereq_addx() -- begin");
2516         status = dspio_scp(codec, MASTERCONTROL,
2517                         MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS,
2518                         SCP_GET, NULL, 0, &speakereq_info, &size);
2519
2520         if (FAILED(status)) {
2521                 CA0132_DSP_LOG("dspload_get_speakereq_addx: SCP Failed");
2522                 return -1;
2523         }
2524
2525         *x = speakereq_info.x;
2526         *y = speakereq_info.y;
2527         CA0132_LOG("dspload_get_speakereq_addx: X=0x%x Y=0x%x\n", *x, *y);
2528
2529         CA0132_DSP_LOG("dspload_get_speakereq_addx() -- complete");
2530
2531         return status;
2532 }
2533
2534 static const struct firmware *fw_speq;
2535 static const struct firmware *fw_efx;
2536
2537 static int request_firmware_cached(const struct firmware **firmware_p,
2538         const char *name, struct device *device)
2539 {
2540         if (*firmware_p)
2541                 return 0;  /* already loaded */
2542         return request_firmware(firmware_p, name, device);
2543 }
2544
2545 static void release_cached_firmware(void)
2546 {
2547         if (fw_speq) {
2548                 release_firmware(fw_speq);
2549                 fw_speq = NULL;
2550         }
2551         if (fw_efx) {
2552                 release_firmware(fw_efx);
2553                 fw_efx = NULL;
2554         }
2555 }
2556
2557 static int dspload_speakereq(struct hda_codec *codec)
2558 {
2559         int status = 0;
2560         const struct dsp_image_seg *image;
2561         unsigned int x, y;
2562
2563         CA0132_DSP_LOG("dspload_speakereq() -- begin");
2564
2565         if (request_firmware_cached(&fw_speq, SPEQ_FILE,
2566                                     codec->bus->card->dev) != 0)
2567                 return -1;
2568
2569         image = (struct dsp_image_seg *)(fw_speq->data);
2570
2571         status = dspload_get_speakereq_addx(codec, &x, &y);
2572         if (FAILED(status))
2573                 goto done;
2574
2575         status = dspload_image(codec, image, 1, y, 0, 8);
2576
2577 done:
2578         CA0132_DSP_LOG("dspload_speakereq() -- complete");
2579
2580         return status;
2581 }
2582
2583 static bool dspload_is_loaded(struct hda_codec *codec)
2584 {
2585         unsigned int data = 0;
2586         int status = 0;
2587
2588         status = chipio_read(codec, 0x40004, &data);
2589         if (FAILED(status) || (data != 1))
2590                 return false;
2591
2592         return true;
2593 }
2594
2595 static bool dspload_wait_loaded(struct hda_codec *codec)
2596 {
2597         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2598
2599         do {
2600                 if (dspload_is_loaded(codec)) {
2601                         pr_info("DOWNLOAD OK :-) DSP IS RUNNING.\n");
2602                         return true;
2603                 }
2604                 msleep(1);
2605         } while (time_before(jiffies, timeout));
2606
2607         pr_err("DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2608         return false;
2609 }
2610
2611 /*
2612  * PCM stuffs.
2613  */
2614 static void ca0132_setup_stream(struct hda_codec *codec, hda_nid_t nid,
2615                                 u32 stream_tag,
2616                                 int channel_id, int format)
2617 {
2618         unsigned int oldval, newval;
2619
2620         if (!nid)
2621                 return;
2622
2623         CA0132_LOG(
2624                    "ca0132_setup_stream: NID=0x%x, stream=0x%x, "
2625                    "channel=%d, format=0x%x\n",
2626                    nid, stream_tag, channel_id, format);
2627
2628         /* update the format-id if changed */
2629         oldval = snd_hda_codec_read(codec, nid, 0,
2630                                     AC_VERB_GET_STREAM_FORMAT, 0);
2631         if (oldval != format) {
2632                 msleep(20);
2633                 snd_hda_codec_write(codec, nid, 0,
2634                                     AC_VERB_SET_STREAM_FORMAT,
2635                                     format);
2636         }
2637
2638         oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2639         newval = (stream_tag << 4) | channel_id;
2640         if (oldval != newval) {
2641                 snd_hda_codec_write(codec, nid, 0,
2642                                     AC_VERB_SET_CHANNEL_STREAMID,
2643                                     newval);
2644         }
2645 }
2646
2647 static void ca0132_cleanup_stream(struct hda_codec *codec, hda_nid_t nid)
2648 {
2649         unsigned int val;
2650
2651         if (!nid)
2652                 return;
2653
2654         CA0132_LOG("ca0132_cleanup_stream: NID=0x%x\n", nid);
2655
2656         val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2657         if (!val)
2658                 return;
2659
2660         snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0);
2661         snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2662 }
2663
2664 /*
2665  * PCM playbacks
2666  */
2667 static unsigned int ca0132_get_playback_latency(struct hda_codec *codec)
2668 {
2669         struct ca0132_spec *spec = codec->spec;
2670         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2671
2672         if (!dspload_is_loaded(codec))
2673                 return 0;
2674
2675         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2676                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2677                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2678                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2679
2680                 if (spec->cur_out_type == SPEAKER_OUT)
2681                         latency += DSP_SPEAKER_OUT_LATENCY;
2682         }
2683         return latency;
2684 }
2685
2686 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2687                                        struct hda_codec *codec,
2688                                        unsigned int stream_tag,
2689                                        unsigned int format,
2690                                        struct snd_pcm_substream *substream)
2691 {
2692         struct ca0132_spec *spec = codec->spec;
2693         struct snd_pcm_runtime *runtime = substream->runtime;
2694         unsigned int latency = ca0132_get_playback_latency(codec);
2695
2696         if (spec->dsp_state == DSP_DOWNLOADING) {
2697                 spec->dsp_stream_id = stream_tag;
2698                 return 0;
2699         }
2700
2701         runtime->delay = bytes_to_frames(runtime, (latency * runtime->rate *
2702                                         runtime->byte_align) / 1000);
2703
2704         ca0132_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2705         return 0;
2706 }
2707
2708 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2709                                        struct hda_codec *codec,
2710                                        struct snd_pcm_substream *substream)
2711 {
2712         struct ca0132_spec *spec = codec->spec;
2713
2714         if (spec->dsp_state == DSP_DOWNLOADING)
2715                 return 0;
2716
2717         /*Allow stream some time to flush effects tail*/
2718         msleep(50);
2719
2720         ca0132_cleanup_stream(codec, spec->dacs[0]);
2721         return 0;
2722 }
2723
2724 /*
2725  * PCM capture
2726  */
2727
2728 static unsigned int ca0132_get_capture_latency(struct hda_codec *codec)
2729 {
2730         struct ca0132_spec *spec = codec->spec;
2731         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2732
2733         if (!dspload_is_loaded(codec))
2734                 return 0;
2735
2736         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2737                 latency += DSP_CRYSTAL_VOICE_LATENCY;
2738         return latency;
2739 }
2740
2741 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2742                                       struct hda_codec *codec,
2743                                       unsigned int stream_tag,
2744                                       unsigned int format,
2745                                       struct snd_pcm_substream *substream)
2746 {
2747         struct ca0132_spec *spec = codec->spec;
2748         struct snd_pcm_runtime *runtime = substream->runtime;
2749         unsigned int latency = ca0132_get_capture_latency(codec);
2750
2751         if (spec->dsp_state == DSP_DOWNLOADING)
2752                 return 0;
2753
2754         runtime->delay = bytes_to_frames(runtime, (latency * runtime->rate *
2755                                         runtime->byte_align) / 1000);
2756
2757         ca0132_setup_stream(codec, hinfo->nid, stream_tag, 0, format);
2758         return 0;
2759 }
2760
2761 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2762                                       struct hda_codec *codec,
2763                                       struct snd_pcm_substream *substream)
2764 {
2765         struct ca0132_spec *spec = codec->spec;
2766
2767         if (spec->dsp_state == DSP_DOWNLOADING)
2768                 return 0;
2769
2770         ca0132_cleanup_stream(codec, hinfo->nid);
2771         return 0;
2772 }
2773
2774
2775 /*
2776  * Controls stuffs.
2777  */
2778
2779 /*
2780  * Mixer controls helpers.
2781  */
2782 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2783         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2784           .name = xname, \
2785           .subdevice = HDA_SUBDEV_AMP_FLAG, \
2786           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2787                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2788                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2789           .info = ca0132_volume_info, \
2790           .get = ca0132_volume_get, \
2791           .put = ca0132_volume_put, \
2792           .tlv = { .c = ca0132_volume_tlv }, \
2793           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2794
2795 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2796         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2797           .name = xname, \
2798           .subdevice = HDA_SUBDEV_AMP_FLAG, \
2799           .info = snd_hda_mixer_amp_switch_info, \
2800           .get = ca0132_switch_get, \
2801           .put = ca0132_switch_put, \
2802           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2803
2804 /* stereo */
2805 #define CA0132_CODEC_VOL(xname, nid, dir) \
2806         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2807 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2808         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2809
2810
2811 /* The followings are for tuning of products */
2812 #ifdef ENABLE_TUNING_CONTROLS
2813
2814 static unsigned int voice_focus_vals_lookup[] = {
2815 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2816 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2817 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2818 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2819 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2820 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2821 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2822 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2823 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2824 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2825 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2826 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2827 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2828 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2829 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2830 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2831 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2832 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2833 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2834 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2835 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2836 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2837 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2838 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2839 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2840 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2841 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2842 };
2843
2844 static unsigned int mic_svm_vals_lookup[] = {
2845 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2846 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2847 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2848 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2849 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2850 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2851 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2852 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2853 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2854 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2855 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2856 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2857 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2858 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2859 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2860 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2861 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2862 };
2863
2864 static unsigned int equalizer_vals_lookup[] = {
2865 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2866 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2867 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2868 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2869 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2870 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2871 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2872 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2873 0x41C00000
2874 };
2875
2876 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2877                           unsigned int *lookup, int idx)
2878 {
2879         int i = 0;
2880
2881         for (i = 0; i < TUNING_CTLS_COUNT; i++)
2882                 if (nid == ca0132_tuning_ctls[i].nid)
2883                         break;
2884
2885         snd_hda_power_up(codec);
2886         dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2887                         ca0132_tuning_ctls[i].req,
2888                         &(lookup[idx]), sizeof(unsigned int));
2889         snd_hda_power_down(codec);
2890
2891         return 1;
2892 }
2893
2894 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2895                           struct snd_ctl_elem_value *ucontrol)
2896 {
2897         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2898         struct ca0132_spec *spec = codec->spec;
2899         hda_nid_t nid = get_amp_nid(kcontrol);
2900         long *valp = ucontrol->value.integer.value;
2901         int idx = nid - TUNING_CTL_START_NID;
2902
2903         *valp = spec->cur_ctl_vals[idx];
2904         return 0;
2905 }
2906
2907 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2908                               struct snd_ctl_elem_info *uinfo)
2909 {
2910         int chs = get_amp_channels(kcontrol);
2911         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2912         uinfo->count = chs == 3 ? 2 : 1;
2913         uinfo->value.integer.min = 20;
2914         uinfo->value.integer.max = 180;
2915         uinfo->value.integer.step = 1;
2916
2917         return 0;
2918 }
2919
2920 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2921                                 struct snd_ctl_elem_value *ucontrol)
2922 {
2923         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2924         struct ca0132_spec *spec = codec->spec;
2925         hda_nid_t nid = get_amp_nid(kcontrol);
2926         long *valp = ucontrol->value.integer.value;
2927         int idx;
2928
2929         idx = nid - TUNING_CTL_START_NID;
2930         /* any change? */
2931         if (spec->cur_ctl_vals[idx] == *valp)
2932                 return 0;
2933
2934         spec->cur_ctl_vals[idx] = *valp;
2935
2936         idx = *valp - 20;
2937         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2938
2939         return 1;
2940 }
2941
2942 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2943                               struct snd_ctl_elem_info *uinfo)
2944 {
2945         int chs = get_amp_channels(kcontrol);
2946         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2947         uinfo->count = chs == 3 ? 2 : 1;
2948         uinfo->value.integer.min = 0;
2949         uinfo->value.integer.max = 100;
2950         uinfo->value.integer.step = 1;
2951
2952         return 0;
2953 }
2954
2955 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
2956                                 struct snd_ctl_elem_value *ucontrol)
2957 {
2958         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2959         struct ca0132_spec *spec = codec->spec;
2960         hda_nid_t nid = get_amp_nid(kcontrol);
2961         long *valp = ucontrol->value.integer.value;
2962         int idx;
2963
2964         idx = nid - TUNING_CTL_START_NID;
2965         /* any change? */
2966         if (spec->cur_ctl_vals[idx] == *valp)
2967                 return 0;
2968
2969         spec->cur_ctl_vals[idx] = *valp;
2970
2971         idx = *valp;
2972         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
2973
2974         return 0;
2975 }
2976
2977 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
2978                               struct snd_ctl_elem_info *uinfo)
2979 {
2980         int chs = get_amp_channels(kcontrol);
2981         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2982         uinfo->count = chs == 3 ? 2 : 1;
2983         uinfo->value.integer.min = 0;
2984         uinfo->value.integer.max = 48;
2985         uinfo->value.integer.step = 1;
2986
2987         return 0;
2988 }
2989
2990 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
2991                                 struct snd_ctl_elem_value *ucontrol)
2992 {
2993         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2994         struct ca0132_spec *spec = codec->spec;
2995         hda_nid_t nid = get_amp_nid(kcontrol);
2996         long *valp = ucontrol->value.integer.value;
2997         int idx;
2998
2999         idx = nid - TUNING_CTL_START_NID;
3000         /* any change? */
3001         if (spec->cur_ctl_vals[idx] == *valp)
3002                 return 0;
3003
3004         spec->cur_ctl_vals[idx] = *valp;
3005
3006         idx = *valp;
3007         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3008
3009         return 1;
3010 }
3011
3012 DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3013 DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3014
3015 static int add_tuning_control(struct hda_codec *codec,
3016                                 hda_nid_t pnid, hda_nid_t nid,
3017                                 const char *name, int dir)
3018 {
3019         char namestr[44];
3020         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3021         struct snd_kcontrol_new knew =
3022                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3023
3024         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3025                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3026         knew.tlv.c = 0;
3027         knew.tlv.p = 0;
3028         switch (pnid) {
3029         case VOICE_FOCUS:
3030                 knew.info = voice_focus_ctl_info;
3031                 knew.get = tuning_ctl_get;
3032                 knew.put = voice_focus_ctl_put;
3033                 knew.tlv.p = voice_focus_db_scale;
3034                 break;
3035         case MIC_SVM:
3036                 knew.info = mic_svm_ctl_info;
3037                 knew.get = tuning_ctl_get;
3038                 knew.put = mic_svm_ctl_put;
3039                 break;
3040         case EQUALIZER:
3041                 knew.info = equalizer_ctl_info;
3042                 knew.get = tuning_ctl_get;
3043                 knew.put = equalizer_ctl_put;
3044                 knew.tlv.p = eq_db_scale;
3045                 break;
3046         default:
3047                 return 0;
3048         }
3049         knew.private_value =
3050                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3051         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3052         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3053 }
3054
3055 static int add_tuning_ctls(struct hda_codec *codec)
3056 {
3057         int i;
3058         int err;
3059
3060         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3061                 err = add_tuning_control(codec,
3062                                         ca0132_tuning_ctls[i].parent_nid,
3063                                         ca0132_tuning_ctls[i].nid,
3064                                         ca0132_tuning_ctls[i].name,
3065                                         ca0132_tuning_ctls[i].direct);
3066                 if (err < 0)
3067                         return err;
3068         }
3069
3070         return 0;
3071 }
3072
3073 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3074 {
3075         struct ca0132_spec *spec = codec->spec;
3076         int i;
3077
3078         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
3079         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3080         /* SVM level defaults to 0.74. */
3081         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3082
3083         /* EQ defaults to 0dB. */
3084         for (i = 2; i < TUNING_CTLS_COUNT; i++)
3085                 spec->cur_ctl_vals[i] = 24;
3086 }
3087 #endif
3088
3089 static int ca0132_select_out(struct hda_codec *codec)
3090 {
3091         struct ca0132_spec *spec = codec->spec;
3092         unsigned int pin_ctl;
3093         int jack_present;
3094         int auto_jack;
3095         unsigned int tmp;
3096         int err;
3097
3098         CA0132_LOG("ca0132_select_out\n");
3099
3100         snd_hda_power_up(codec);
3101
3102         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3103
3104         if (auto_jack)
3105                 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3106         else
3107                 jack_present =
3108                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3109
3110         if (jack_present)
3111                 spec->cur_out_type = HEADPHONE_OUT;
3112         else
3113                 spec->cur_out_type = SPEAKER_OUT;
3114
3115         if (spec->cur_out_type == SPEAKER_OUT) {
3116                 CA0132_LOG("ca0132_select_out speaker\n");
3117                 /*speaker out config*/
3118                 tmp = FLOAT_ONE;
3119                 err = dspio_set_param(codec, 0x80, 0x04,
3120                                         &tmp, sizeof(unsigned int));
3121                 if (err < 0)
3122                         goto exit;
3123                 /*enable speaker EQ*/
3124                 tmp = FLOAT_ONE;
3125                 err = dspio_set_param(codec, 0x8f, 0x00,
3126                                         &tmp, sizeof(unsigned int));
3127                 if (err < 0)
3128                         goto exit;
3129
3130                 /* disable headphone node */
3131                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3132                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3133                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3134                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
3135                                     pin_ctl & 0xBF);
3136                 /* disable headphone EAPD */
3137                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3138                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3139                 /* enable speaker node */
3140                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3141                                              AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3142                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3143                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
3144                                     pin_ctl | 0x40);
3145                 /* enable speaker EAPD */
3146                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3147                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3148                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3149                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3150         } else {
3151                 CA0132_LOG("ca0132_select_out hp\n");
3152                 /*headphone out config*/
3153                 tmp = FLOAT_ZERO;
3154                 err = dspio_set_param(codec, 0x80, 0x04,
3155                                         &tmp, sizeof(unsigned int));
3156                 if (err < 0)
3157                         goto exit;
3158                 /*disable speaker EQ*/
3159                 tmp = FLOAT_ZERO;
3160                 err = dspio_set_param(codec, 0x8f, 0x00,
3161                                         &tmp, sizeof(unsigned int));
3162                 if (err < 0)
3163                         goto exit;
3164
3165                 /* disable speaker*/
3166                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3167                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3168                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3169                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
3170                                     pin_ctl & 0xBF);
3171                 /* disable speaker EAPD */
3172                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3173                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3174                 /* enable headphone*/
3175                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3176                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3177                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3178                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
3179                                     pin_ctl | 0x40);
3180                 /* enable headphone EAPD */
3181                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3182                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3183                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3184                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3185         }
3186
3187 exit:
3188         snd_hda_power_down(codec);
3189
3190         return err < 0 ? err : 0;
3191 }
3192
3193 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3194 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3195 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3196
3197 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3198 {
3199         struct ca0132_spec *spec = codec->spec;
3200         unsigned int tmp;
3201
3202         if (!dspload_is_loaded(codec))
3203                 return 0;
3204
3205         /* if CrystalVoice if off, vipsource should be 0 */
3206         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]
3207                         || (val == 0)) {
3208                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3209                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3210                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3211                 if (spec->cur_mic_type == DIGITAL_MIC)
3212                         tmp = FLOAT_TWO;
3213                 else
3214                         tmp = FLOAT_ONE;
3215                 dspio_set_param(codec, 0x80, 0x00, &tmp, sizeof(unsigned int));
3216                 tmp = FLOAT_ZERO;
3217                 dspio_set_param(codec, 0x80, 0x05, &tmp, sizeof(unsigned int));
3218         } else {
3219                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3220                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3221                 if (spec->cur_mic_type == DIGITAL_MIC)
3222                         tmp = FLOAT_TWO;
3223                 else
3224                         tmp = FLOAT_ONE;
3225                 dspio_set_param(codec, 0x80, 0x00, &tmp, sizeof(unsigned int));
3226                 tmp = FLOAT_ONE;
3227                 dspio_set_param(codec, 0x80, 0x05, &tmp, sizeof(unsigned int));
3228                 msleep(20);
3229                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3230         }
3231
3232         return 1;
3233 }
3234
3235 static int ca0132_select_mic(struct hda_codec *codec)
3236 {
3237         struct ca0132_spec *spec = codec->spec;
3238         int jack_present;
3239         int auto_jack;
3240
3241         CA0132_LOG("ca0132_select_mic\n");
3242
3243         snd_hda_power_up(codec);
3244
3245         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3246
3247         if (auto_jack)
3248                 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3249         else
3250                 jack_present =
3251                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3252
3253         if (jack_present)
3254                 spec->cur_mic_type = LINE_MIC_IN;
3255         else
3256                 spec->cur_mic_type = DIGITAL_MIC;
3257
3258         if (spec->cur_mic_type == DIGITAL_MIC) {
3259                 /* enable digital Mic */
3260                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3261                 ca0132_set_dmic(codec, 1);
3262                 ca0132_mic_boost_set(codec, 0);
3263                 /* set voice focus */
3264                 ca0132_effects_set(codec, VOICE_FOCUS,
3265                                    spec->effects_switch
3266                                    [VOICE_FOCUS - EFFECT_START_NID]);
3267         } else {
3268                 /* disable digital Mic */
3269                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3270                 ca0132_set_dmic(codec, 0);
3271                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3272                 /* disable voice focus */
3273                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3274         }
3275
3276         snd_hda_power_down(codec);
3277
3278         return 0;
3279 }
3280
3281 /*
3282  * Check if VNODE settings take effect immediately.
3283  */
3284 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3285                                      hda_nid_t vnid,
3286                                      hda_nid_t *shared_nid)
3287 {
3288         struct ca0132_spec *spec = codec->spec;
3289         hda_nid_t nid;
3290         bool effective = false;
3291
3292         switch (vnid) {
3293         case VNID_SPK:
3294                 nid = spec->shared_out_nid;
3295                 effective = true;
3296                 break;
3297         case VNID_MIC:
3298                 nid = spec->shared_mic_nid;
3299                 effective = true;
3300                 break;
3301         default:
3302                 break;
3303         }
3304
3305         if (effective && shared_nid)
3306                 *shared_nid = nid;
3307
3308         return effective;
3309 }
3310
3311 /*
3312  * The following functions are control change helpers.
3313  * They return 0 if no changed.  Return 1 if changed.
3314  */
3315 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3316 {
3317         struct ca0132_spec *spec = codec->spec;
3318         unsigned int tmp;
3319
3320         /* based on CrystalVoice state to enable VoiceFX. */
3321         if (enable) {
3322                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3323                         FLOAT_ONE : FLOAT_ZERO;
3324         } else {
3325                 tmp = FLOAT_ZERO;
3326         }
3327
3328         dspio_set_param(codec, ca0132_voicefx.mid,
3329                         ca0132_voicefx.reqs[0], &tmp, sizeof(unsigned int));
3330
3331         return 1;
3332 }
3333
3334 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3335 {
3336         struct ca0132_spec *spec = codec->spec;
3337         unsigned int on;
3338         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3339         int err = 0;
3340         int idx = nid - EFFECT_START_NID;
3341
3342         if ((idx < 0) || (idx >= num_fx))
3343                 return 0; /* no changed */
3344
3345         /* for out effect, qualify with PE */
3346         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3347                 /* if PE if off, turn off out effects. */
3348                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3349                         val = 0;
3350         }
3351
3352         /* for in effect, qualify with CrystalVoice */
3353         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3354                 /* if CrystalVoice if off, turn off in effects. */
3355                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3356                         val = 0;
3357
3358                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3359                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3360                         val = 0;
3361         }
3362
3363         CA0132_LOG("ca0132_effect_set: nid=0x%x, val=%ld\n", nid, val);
3364
3365         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3366         err = dspio_set_param(codec, ca0132_effects[idx].mid,
3367                                 ca0132_effects[idx].reqs[0],
3368                                 &on, sizeof(unsigned int));
3369         if (err < 0)
3370                 return 0; /* no changed */
3371
3372         return 1;
3373 }
3374
3375 static int ca0132_pe_switch_set(struct hda_codec *codec)
3376 {
3377         struct ca0132_spec *spec = codec->spec;
3378         hda_nid_t nid;
3379         int i, ret = 0;
3380
3381         CA0132_LOG("ca0132_pe_switch_set: val=%ld\n",
3382                    spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3383
3384         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3385         nid = OUT_EFFECT_START_NID;
3386         /* PE affects all out effects */
3387         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3388                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3389
3390         return ret;
3391 }
3392
3393 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3394 {
3395         struct ca0132_spec *spec = codec->spec;
3396         hda_nid_t nid;
3397         int i, ret = 0;
3398
3399         CA0132_LOG("ca0132_cvoice_switch_set: val=%ld\n",
3400                    spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3401
3402         i = IN_EFFECT_START_NID - EFFECT_START_NID;
3403         nid = IN_EFFECT_START_NID;
3404         /* CrystalVoice affects all in effects */
3405         for (; nid < IN_EFFECT_END_NID; nid++, i++)
3406                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3407
3408         /* including VoiceFX */
3409         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3410
3411         /* set correct vipsource */
3412         ret |= ca0132_set_vipsource(codec, 1);
3413         return ret;
3414 }
3415
3416 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3417 {
3418         struct ca0132_spec *spec = codec->spec;
3419         int ret = 0;
3420
3421         if (val) /* on */
3422                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3423                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3424         else /* off */
3425                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3426                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3427
3428         return ret;
3429 }
3430
3431 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3432                                 struct snd_ctl_elem_value *ucontrol)
3433 {
3434         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3435         hda_nid_t nid = get_amp_nid(kcontrol);
3436         hda_nid_t shared_nid = 0;
3437         bool effective;
3438         int ret = 0;
3439         struct ca0132_spec *spec = codec->spec;
3440         int auto_jack;
3441
3442         if (nid == VNID_HP_SEL) {
3443                 auto_jack =
3444                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3445                 if (!auto_jack)
3446                         ca0132_select_out(codec);
3447                 return 1;
3448         }
3449
3450         if (nid == VNID_AMIC1_SEL) {
3451                 auto_jack =
3452                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3453                 if (!auto_jack)
3454                         ca0132_select_mic(codec);
3455                 return 1;
3456         }
3457
3458         if (nid == VNID_HP_ASEL) {
3459                 ca0132_select_out(codec);
3460                 return 1;
3461         }
3462
3463         if (nid == VNID_AMIC1_ASEL) {
3464                 ca0132_select_mic(codec);
3465                 return 1;
3466         }
3467
3468         /* if effective conditions, then update hw immediately. */
3469         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3470         if (effective) {
3471                 int dir = get_amp_direction(kcontrol);
3472                 int ch = get_amp_channels(kcontrol);
3473                 unsigned long pval;
3474
3475                 mutex_lock(&codec->control_mutex);
3476                 pval = kcontrol->private_value;
3477                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3478                                                                 0, dir);
3479                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3480                 kcontrol->private_value = pval;
3481                 mutex_unlock(&codec->control_mutex);
3482         }
3483
3484         return ret;
3485 }
3486 /* End of control change helpers. */
3487
3488 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3489                                  struct snd_ctl_elem_info *uinfo)
3490 {
3491         unsigned int items = sizeof(ca0132_voicefx_presets)
3492                                 / sizeof(struct ct_voicefx_preset);
3493
3494         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3495         uinfo->count = 1;
3496         uinfo->value.enumerated.items = items;
3497         if (uinfo->value.enumerated.item >= items)
3498                 uinfo->value.enumerated.item = items - 1;
3499         strcpy(uinfo->value.enumerated.name,
3500                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3501         return 0;
3502 }
3503
3504 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3505                                 struct snd_ctl_elem_value *ucontrol)
3506 {
3507         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3508         struct ca0132_spec *spec = codec->spec;
3509
3510         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3511         return 0;
3512 }
3513
3514 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3515                                 struct snd_ctl_elem_value *ucontrol)
3516 {
3517         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3518         struct ca0132_spec *spec = codec->spec;
3519         int i, err = 0;
3520         int sel = ucontrol->value.enumerated.item[0];
3521         unsigned int items = sizeof(ca0132_voicefx_presets)
3522                                 / sizeof(struct ct_voicefx_preset);
3523
3524         if (sel >= items)
3525                 return 0;
3526
3527         CA0132_LOG("ca0132_voicefx_put: sel=%d, preset=%s\n",
3528                    sel, ca0132_voicefx_presets[sel].name);
3529
3530         /*
3531          * Idx 0 is default.
3532          * Default needs to qualify with CrystalVoice state.
3533          */
3534         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3535                 err = dspio_set_param(codec, ca0132_voicefx.mid,
3536                                 ca0132_voicefx.reqs[i],
3537                                 &(ca0132_voicefx_presets[sel].vals[i]),
3538                                 sizeof(unsigned int));
3539                 if (err < 0)
3540                         break;
3541         }
3542
3543         if (err >= 0) {
3544                 spec->voicefx_val = sel;
3545                 /* enable voice fx */
3546                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3547         }
3548
3549         return 1;
3550 }
3551
3552 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3553                                 struct snd_ctl_elem_value *ucontrol)
3554 {
3555         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3556         struct ca0132_spec *spec = codec->spec;
3557         hda_nid_t nid = get_amp_nid(kcontrol);
3558         int ch = get_amp_channels(kcontrol);
3559         long *valp = ucontrol->value.integer.value;
3560
3561         /* vnode */
3562         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3563                 if (ch & 1) {
3564                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3565                         valp++;
3566                 }
3567                 if (ch & 2) {
3568                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3569                         valp++;
3570                 }
3571                 return 0;
3572         }
3573
3574         /* effects, include PE and CrystalVoice */
3575         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3576                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3577                 return 0;
3578         }
3579
3580         /* mic boost */
3581         if (nid == spec->input_pins[0]) {
3582                 *valp = spec->cur_mic_boost;
3583                 return 0;
3584         }
3585
3586         return 0;
3587 }
3588
3589 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3590                              struct snd_ctl_elem_value *ucontrol)
3591 {
3592         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3593         struct ca0132_spec *spec = codec->spec;
3594         hda_nid_t nid = get_amp_nid(kcontrol);
3595         int ch = get_amp_channels(kcontrol);
3596         long *valp = ucontrol->value.integer.value;
3597         int changed = 1;
3598
3599         CA0132_LOG("ca0132_switch_put: nid=0x%x, val=%ld\n", nid, *valp);
3600
3601         snd_hda_power_up(codec);
3602         /* vnode */
3603         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3604                 if (ch & 1) {
3605                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3606                         valp++;
3607                 }
3608                 if (ch & 2) {
3609                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3610                         valp++;
3611                 }
3612                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3613                 goto exit;
3614         }
3615
3616         /* PE */
3617         if (nid == PLAY_ENHANCEMENT) {
3618                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3619                 changed = ca0132_pe_switch_set(codec);
3620                 goto exit;
3621         }
3622
3623         /* CrystalVoice */
3624         if (nid == CRYSTAL_VOICE) {
3625                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3626                 changed = ca0132_cvoice_switch_set(codec);
3627                 goto exit;
3628         }
3629
3630         /* out and in effects */
3631         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3632             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3633                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3634                 changed = ca0132_effects_set(codec, nid, *valp);
3635                 goto exit;
3636         }
3637
3638         /* mic boost */
3639         if (nid == spec->input_pins[0]) {
3640                 spec->cur_mic_boost = *valp;
3641
3642                 /* Mic boost does not apply to Digital Mic */
3643                 if (spec->cur_mic_type != DIGITAL_MIC)
3644                         changed = ca0132_mic_boost_set(codec, *valp);
3645                 goto exit;
3646         }
3647
3648 exit:
3649         snd_hda_power_down(codec);
3650         return changed;
3651 }
3652
3653 /*
3654  * Volume related
3655  */
3656 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3657                               struct snd_ctl_elem_info *uinfo)
3658 {
3659         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3660         struct ca0132_spec *spec = codec->spec;
3661         hda_nid_t nid = get_amp_nid(kcontrol);
3662         int ch = get_amp_channels(kcontrol);
3663         int dir = get_amp_direction(kcontrol);
3664         unsigned long pval;
3665         int err;
3666
3667         switch (nid) {
3668         case VNID_SPK:
3669                 /* follow shared_out info */
3670                 nid = spec->shared_out_nid;
3671                 mutex_lock(&codec->control_mutex);
3672                 pval = kcontrol->private_value;
3673                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3674                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3675                 kcontrol->private_value = pval;
3676                 mutex_unlock(&codec->control_mutex);
3677                 break;
3678         case VNID_MIC:
3679                 /* follow shared_mic info */
3680                 nid = spec->shared_mic_nid;
3681                 mutex_lock(&codec->control_mutex);
3682                 pval = kcontrol->private_value;
3683                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3684                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3685                 kcontrol->private_value = pval;
3686                 mutex_unlock(&codec->control_mutex);
3687                 break;
3688         default:
3689                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3690         }
3691         return err;
3692 }
3693
3694 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3695                                 struct snd_ctl_elem_value *ucontrol)
3696 {
3697         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3698         struct ca0132_spec *spec = codec->spec;
3699         hda_nid_t nid = get_amp_nid(kcontrol);
3700         int ch = get_amp_channels(kcontrol);
3701         long *valp = ucontrol->value.integer.value;
3702
3703         /* store the left and right volume */
3704         if (ch & 1) {
3705                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3706                 valp++;
3707         }
3708         if (ch & 2) {
3709                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3710                 valp++;
3711         }
3712         return 0;
3713 }
3714
3715 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3716                                 struct snd_ctl_elem_value *ucontrol)
3717 {
3718         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3719         struct ca0132_spec *spec = codec->spec;
3720         hda_nid_t nid = get_amp_nid(kcontrol);
3721         int ch = get_amp_channels(kcontrol);
3722         long *valp = ucontrol->value.integer.value;
3723         hda_nid_t shared_nid = 0;
3724         bool effective;
3725         int changed = 1;
3726
3727         /* store the left and right volume */
3728         if (ch & 1) {
3729                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3730                 valp++;
3731         }
3732         if (ch & 2) {
3733                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3734                 valp++;
3735         }
3736
3737         /* if effective conditions, then update hw immediately. */
3738         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3739         if (effective) {
3740                 int dir = get_amp_direction(kcontrol);
3741                 unsigned long pval;
3742
3743                 snd_hda_power_up(codec);
3744                 mutex_lock(&codec->control_mutex);
3745                 pval = kcontrol->private_value;
3746                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3747                                                                 0, dir);
3748                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3749                 kcontrol->private_value = pval;
3750                 mutex_unlock(&codec->control_mutex);
3751                 snd_hda_power_down(codec);
3752         }
3753
3754         return changed;
3755 }
3756
3757 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3758                              unsigned int size, unsigned int __user *tlv)
3759 {
3760         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3761         struct ca0132_spec *spec = codec->spec;
3762         hda_nid_t nid = get_amp_nid(kcontrol);
3763         int ch = get_amp_channels(kcontrol);
3764         int dir = get_amp_direction(kcontrol);
3765         unsigned long pval;
3766         int err;
3767
3768         switch (nid) {
3769         case VNID_SPK:
3770                 /* follow shared_out tlv */
3771                 nid = spec->shared_out_nid;
3772                 mutex_lock(&codec->control_mutex);
3773                 pval = kcontrol->private_value;
3774                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3775                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3776                 kcontrol->private_value = pval;
3777                 mutex_unlock(&codec->control_mutex);
3778                 break;
3779         case VNID_MIC:
3780                 /* follow shared_mic tlv */
3781                 nid = spec->shared_mic_nid;
3782                 mutex_lock(&codec->control_mutex);
3783                 pval = kcontrol->private_value;
3784                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3785                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3786                 kcontrol->private_value = pval;
3787                 mutex_unlock(&codec->control_mutex);
3788                 break;
3789         default:
3790                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3791         }
3792         return err;
3793 }
3794
3795 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3796                          const char *pfx, int dir)
3797 {
3798         char namestr[44];
3799         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3800         struct snd_kcontrol_new knew =
3801                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3802         sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3803         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3804 }
3805
3806 static int add_voicefx(struct hda_codec *codec)
3807 {
3808         struct snd_kcontrol_new knew =
3809                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3810                                     VOICEFX, 1, 0, HDA_INPUT);
3811         knew.info = ca0132_voicefx_info;
3812         knew.get = ca0132_voicefx_get;
3813         knew.put = ca0132_voicefx_put;
3814         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3815 }
3816
3817 /*
3818  * When changing Node IDs for Mixer Controls below, make sure to update
3819  * Node IDs in ca0132_config() as well.
3820  */
3821 static struct snd_kcontrol_new ca0132_mixer[] = {
3822         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3823         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3824         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3825         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3826         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3827         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3828         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3829         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3830         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3831                                0x12, 1, HDA_INPUT),
3832         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3833                                VNID_HP_SEL, 1, HDA_OUTPUT),
3834         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3835                                VNID_AMIC1_SEL, 1, HDA_INPUT),
3836         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3837                                VNID_HP_ASEL, 1, HDA_OUTPUT),
3838         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3839                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
3840         { } /* end */
3841 };
3842
3843 static int ca0132_build_controls(struct hda_codec *codec)
3844 {
3845         struct ca0132_spec *spec = codec->spec;
3846         int i, num_fx;
3847         int err = 0;
3848
3849         /* Add Mixer controls */
3850         for (i = 0; i < spec->num_mixers; i++) {
3851                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3852                 if (err < 0)
3853                         return err;
3854         }
3855
3856         /* Add in and out effects controls.
3857          * VoiceFX, PE and CrystalVoice are added separately.
3858          */
3859         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3860         for (i = 0; i < num_fx; i++) {
3861                 err = add_fx_switch(codec, ca0132_effects[i].nid,
3862                                     ca0132_effects[i].name,
3863                                     ca0132_effects[i].direct);
3864                 if (err < 0)
3865                         return err;
3866         }
3867
3868         err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3869         if (err < 0)
3870                 return err;
3871
3872         err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3873         if (err < 0)
3874                 return err;
3875
3876         add_voicefx(codec);
3877
3878         #ifdef ENABLE_TUNING_CONTROLS
3879         add_tuning_ctls(codec);
3880         #endif
3881
3882         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3883         if (err < 0)
3884                 return err;
3885
3886         return 0;
3887 }
3888
3889 /*
3890  * PCM
3891  */
3892 static struct hda_pcm_stream ca0132_pcm_analog_playback = {
3893         .substreams = 1,
3894         .channels_min = 2,
3895         .channels_max = 6,
3896         .ops = {
3897                 .prepare = ca0132_playback_pcm_prepare,
3898                 .cleanup = ca0132_playback_pcm_cleanup
3899         },
3900 };
3901
3902 static struct hda_pcm_stream ca0132_pcm_analog_capture = {
3903         .substreams = 1,
3904         .channels_min = 2,
3905         .channels_max = 2,
3906         .ops = {
3907                 .prepare = ca0132_capture_pcm_prepare,
3908                 .cleanup = ca0132_capture_pcm_cleanup
3909         },
3910 };
3911
3912 static int ca0132_build_pcms(struct hda_codec *codec)
3913 {
3914         struct ca0132_spec *spec = codec->spec;
3915         struct hda_pcm *info = spec->pcm_rec;
3916
3917         codec->pcm_info = info;
3918         codec->num_pcms = 0;
3919
3920         info->name = "CA0132 Analog";
3921         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
3922         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
3923         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
3924                                                 spec->multiout.max_channels;
3925         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
3926         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
3927         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
3928         codec->num_pcms++;
3929
3930         info++;
3931         info->name = "CA0132 Analog Mic-In2";
3932         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
3933         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
3934         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
3935         codec->num_pcms++;
3936
3937         info++;
3938         info->name = "CA0132 What U Hear";
3939         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
3940         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
3941         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
3942         codec->num_pcms++;
3943
3944         return 0;
3945 }
3946
3947 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
3948 {
3949         if (pin) {
3950                 snd_hda_codec_write(codec, pin, 0,
3951                                     AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP);
3952                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3953                         snd_hda_codec_write(codec, pin, 0,
3954                                             AC_VERB_SET_AMP_GAIN_MUTE,
3955                                             AMP_OUT_UNMUTE);
3956         }
3957         if (dac)
3958                 snd_hda_codec_write(codec, dac, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3959                                     AMP_OUT_ZERO);
3960 }
3961
3962 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
3963 {
3964         if (pin) {
3965                 snd_hda_codec_write(codec, pin, 0,
3966                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
3967                                     PIN_VREF80);
3968                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
3969                         snd_hda_codec_write(codec, pin, 0,
3970                                             AC_VERB_SET_AMP_GAIN_MUTE,
3971                                             AMP_IN_UNMUTE(0));
3972         }
3973         if (adc) {
3974                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3975                                     AMP_IN_UNMUTE(0));
3976
3977                 /* init to 0 dB and unmute. */
3978                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
3979                                          HDA_AMP_VOLMASK, 0x5a);
3980                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
3981                                          HDA_AMP_MUTE, 0);
3982         }
3983 }
3984
3985 static void ca0132_init_unsol(struct hda_codec *codec)
3986 {
3987         snd_hda_jack_detect_enable(codec, UNSOL_TAG_HP, UNSOL_TAG_HP);
3988         snd_hda_jack_detect_enable(codec, UNSOL_TAG_AMIC1, UNSOL_TAG_AMIC1);
3989 }
3990
3991 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
3992 {
3993         unsigned int caps;
3994
3995         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
3996                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
3997         snd_hda_override_amp_caps(codec, nid, dir, caps);
3998 }
3999
4000 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4001 {
4002         struct ca0132_spec *spec = codec->spec;
4003         unsigned int tmp;
4004         u8 val;
4005
4006         CA0132_LOG("ca0132_set_dmic: enable=%d\n", enable);
4007
4008         ca0132_set_vipsource(codec, 0);
4009         if (enable) {
4010                 /* set DMic input as 2-ch */
4011                 tmp = FLOAT_TWO;
4012                 dspio_set_param(codec, 0x80, 0x00, &tmp, sizeof(unsigned int));
4013
4014                 val = spec->dmic_ctl;
4015                 val |= 0x80;
4016                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4017                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
4018
4019                 if (!(spec->dmic_ctl & 0x20))
4020                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4021         } else {
4022                 /* set AMic input as mono */
4023                 tmp = FLOAT_ONE;
4024                 dspio_set_param(codec, 0x80, 0x00, &tmp, sizeof(unsigned int));
4025
4026                 val = spec->dmic_ctl;
4027                 /* clear bit7 and bit5 to disable dmic */
4028                 val &= 0x5f;
4029                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4030                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
4031
4032                 if (!(spec->dmic_ctl & 0x20))
4033                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4034         }
4035         ca0132_set_vipsource(codec, 1);
4036 }
4037
4038 static void ca0132_init_dmic(struct hda_codec *codec)
4039 {
4040         struct ca0132_spec *spec = codec->spec;
4041         u8 val;
4042
4043         /* Setup Digital Mic here, but don't enable.
4044          * Enable based on jack detect.
4045          */
4046
4047         /* MCLK uses MPIO1, set to enable.
4048          * Bit 2-0: MPIO select
4049          * Bit   3: set to disable
4050          * Bit 7-4: reserved
4051          */
4052         val = 0x01;
4053         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4054                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4055
4056         /* Data1 uses MPIO3. Data2 not use
4057          * Bit 2-0: Data1 MPIO select
4058          * Bit   3: set disable Data1
4059          * Bit 6-4: Data2 MPIO select
4060          * Bit   7: set disable Data2
4061          */
4062         val = 0x83;
4063         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4064                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
4065
4066         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4067          * Bit 3-0: Channel mask
4068          * Bit   4: set for 48KHz, clear for 32KHz
4069          * Bit   5: mode
4070          * Bit   6: set to select Data2, clear for Data1
4071          * Bit   7: set to enable DMic, clear for AMic
4072          */
4073         val = 0x23;
4074         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4075         spec->dmic_ctl = val;
4076         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4077                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
4078 }
4079
4080 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4081 {
4082         struct ca0132_spec *spec = codec->spec;
4083
4084         mutex_lock(&spec->chipio_mutex);
4085         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4086                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4087         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4088                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4089         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4090                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4091         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4092                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4093         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4094                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4095         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4096                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4097         mutex_unlock(&spec->chipio_mutex);
4098 }
4099
4100 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4101 {
4102         struct ca0132_spec *spec = codec->spec;
4103         int i;
4104         hda_nid_t nid;
4105
4106         CA0132_LOG("ca0132_refresh_widget_caps.\n");
4107         nid = codec->start_nid;
4108         for (i = 0; i < codec->num_nodes; i++, nid++)
4109                 codec->wcaps[i] = snd_hda_param_read(codec, nid,
4110                                                      AC_PAR_AUDIO_WIDGET_CAP);
4111
4112         for (i = 0; i < spec->multiout.num_dacs; i++)
4113                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4114
4115         for (i = 0; i < spec->num_outputs; i++)
4116                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4117
4118         for (i = 0; i < spec->num_inputs; i++) {
4119                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4120                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4121         }
4122 }
4123
4124 static void ca0132_setup_defaults(struct hda_codec *codec)
4125 {
4126         unsigned int tmp;
4127         int num_fx;
4128         int idx, i;
4129
4130         if (!dspload_is_loaded(codec))
4131                 return;
4132
4133         /* out, in effects + voicefx */
4134         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4135         for (idx = 0; idx < num_fx; idx++) {
4136                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4137                         dspio_set_param(codec, ca0132_effects[idx].mid,
4138                                         ca0132_effects[idx].reqs[i],
4139                                         &(ca0132_effects[idx].def_vals[i]),
4140                                         sizeof(unsigned int));
4141                 }
4142         }
4143
4144         /*remove DSP headroom*/
4145         tmp = FLOAT_ZERO;
4146         dspio_set_param(codec, 0x96, 0x3C, &tmp, sizeof(unsigned int));
4147
4148         /*set speaker EQ bypass attenuation*/
4149         dspio_set_param(codec, 0x8f, 0x01, &tmp, sizeof(unsigned int));
4150
4151         /* set AMic1 and AMic2 as mono mic */
4152         tmp = FLOAT_ONE;
4153         dspio_set_param(codec, 0x80, 0x00, &tmp, sizeof(unsigned int));
4154         dspio_set_param(codec, 0x80, 0x01, &tmp, sizeof(unsigned int));
4155
4156         /* set AMic1 as CrystalVoice input */
4157         tmp = FLOAT_ONE;
4158         dspio_set_param(codec, 0x80, 0x05, &tmp, sizeof(unsigned int));
4159 }
4160
4161 static void ca0132_init_flags(struct hda_codec *codec)
4162 {
4163         chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4164         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4165         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4166         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4167         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4168         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4169 }
4170
4171 static void ca0132_init_params(struct hda_codec *codec)
4172 {
4173         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4174         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4175 }
4176
4177 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4178 {
4179         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4180         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4181         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4182         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4183         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4184         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4185
4186         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4187         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4188         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4189 }
4190
4191 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4192 {
4193         bool dsp_loaded = false;
4194         const struct dsp_image_seg *dsp_os_image;
4195
4196         if (request_firmware_cached(&fw_efx, EFX_FILE,
4197                                     codec->bus->card->dev) != 0)
4198                 return false;
4199
4200         dsp_os_image = (struct dsp_image_seg *)(fw_efx->data);
4201         dspload_image(codec, dsp_os_image, 0, 0, true, 0);
4202         dsp_loaded = dspload_wait_loaded(codec);
4203
4204         if (dsp_loaded)
4205                 dspload_speakereq(codec);
4206
4207         return dsp_loaded;
4208 }
4209
4210 static void ca0132_download_dsp(struct hda_codec *codec)
4211 {
4212         struct ca0132_spec *spec = codec->spec;
4213
4214         spec->dsp_state = DSP_DOWNLOAD_INIT;
4215
4216         if (spec->dsp_state == DSP_DOWNLOAD_INIT) {
4217                 chipio_enable_clocks(codec);
4218                 spec->dsp_state = DSP_DOWNLOADING;
4219                 if (!ca0132_download_dsp_images(codec))
4220                         spec->dsp_state = DSP_DOWNLOAD_FAILED;
4221                 else
4222                         spec->dsp_state = DSP_DOWNLOADED;
4223         }
4224
4225         if (spec->dsp_state == DSP_DOWNLOADED)
4226                 ca0132_set_dsp_msr(codec, true);
4227 }
4228
4229 static void ca0132_process_dsp_response(struct hda_codec *codec)
4230 {
4231         struct ca0132_spec *spec = codec->spec;
4232
4233         CA0132_LOG("ca0132_process_dsp_response\n");
4234         if (spec->wait_scp) {
4235                 if (dspio_get_response_data(codec) >= 0)
4236                         spec->wait_scp = 0;
4237         }
4238
4239         dspio_clear_response_queue(codec);
4240 }
4241
4242 static void ca0132_unsol_event(struct hda_codec *codec, unsigned int res)
4243 {
4244         CA0132_LOG("ca0132_unsol_event: 0x%x\n", res);
4245
4246
4247         if (((res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f) == UNSOL_TAG_DSP) {
4248                 ca0132_process_dsp_response(codec);
4249         } else {
4250                 res = snd_hda_jack_get_action(codec,
4251                                 (res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f);
4252
4253                 CA0132_LOG("snd_hda_jack_get_action: 0x%x\n", res);
4254
4255                 switch (res) {
4256                 case UNSOL_TAG_HP:
4257                         ca0132_select_out(codec);
4258                         break;
4259                 case UNSOL_TAG_AMIC1:
4260                         ca0132_select_mic(codec);
4261                         break;
4262                 default:
4263                         break;
4264                 }
4265                 snd_hda_jack_report_sync(codec);
4266         }
4267 }
4268
4269 /*
4270  * Verbs tables.
4271  */
4272
4273 /* Sends before DSP download. */
4274 static struct hda_verb ca0132_base_init_verbs[] = {
4275         /*enable ct extension*/
4276         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4277         /*enable DSP node unsol, needed for DSP download*/
4278         {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP},
4279         {}
4280 };
4281
4282 /* Send at exit. */
4283 static struct hda_verb ca0132_base_exit_verbs[] = {
4284         /*set afg to D3*/
4285         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4286         /*disable ct extension*/
4287         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4288         {}
4289 };
4290
4291 /* Other verbs tables.  Sends after DSP download. */
4292 static struct hda_verb ca0132_init_verbs0[] = {
4293         /* chip init verbs */
4294         {0x15, 0x70D, 0xF0},
4295         {0x15, 0x70E, 0xFE},
4296         {0x15, 0x707, 0x75},
4297         {0x15, 0x707, 0xD3},
4298         {0x15, 0x707, 0x09},
4299         {0x15, 0x707, 0x53},
4300         {0x15, 0x707, 0xD4},
4301         {0x15, 0x707, 0xEF},
4302         {0x15, 0x707, 0x75},
4303         {0x15, 0x707, 0xD3},
4304         {0x15, 0x707, 0x09},
4305         {0x15, 0x707, 0x02},
4306         {0x15, 0x707, 0x37},
4307         {0x15, 0x707, 0x78},
4308         {0x15, 0x53C, 0xCE},
4309         {0x15, 0x575, 0xC9},
4310         {0x15, 0x53D, 0xCE},
4311         {0x15, 0x5B7, 0xC9},
4312         {0x15, 0x70D, 0xE8},
4313         {0x15, 0x70E, 0xFE},
4314         {0x15, 0x707, 0x02},
4315         {0x15, 0x707, 0x68},
4316         {0x15, 0x707, 0x62},
4317         {0x15, 0x53A, 0xCE},
4318         {0x15, 0x546, 0xC9},
4319         {0x15, 0x53B, 0xCE},
4320         {0x15, 0x5E8, 0xC9},
4321         {0x15, 0x717, 0x0D},
4322         {0x15, 0x718, 0x20},
4323         {}
4324 };
4325
4326 static struct hda_verb ca0132_init_verbs1[] = {
4327         {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP},
4328         {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1},
4329         /* Set the default configuration for the mic pin because the
4330          * value set in BIOS will be reset after ct extension is enabled.
4331          */
4332         {0x12, AC_VERB_SET_CONFIG_DEFAULT_BYTES_0, 0xf0},
4333         {0x12, AC_VERB_SET_CONFIG_DEFAULT_BYTES_1, 0x10},
4334         {0x12, AC_VERB_SET_CONFIG_DEFAULT_BYTES_2, 0xa1},
4335         {0x12, AC_VERB_SET_CONFIG_DEFAULT_BYTES_3, 0x03},
4336         /* config EAPD */
4337         {0x0b, 0x78D, 0x00},
4338         /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4339         /*{0x10, 0x78D, 0x02},*/
4340         /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4341         {}
4342 };
4343
4344 static void ca0132_init_chip(struct hda_codec *codec)
4345 {
4346         struct ca0132_spec *spec = codec->spec;
4347         int num_fx;
4348         int i;
4349         unsigned int on;
4350
4351         mutex_init(&spec->chipio_mutex);
4352
4353         spec->cur_out_type = SPEAKER_OUT;
4354         spec->cur_mic_type = DIGITAL_MIC;
4355         spec->cur_mic_boost = 0;
4356
4357         for (i = 0; i < VNODES_COUNT; i++) {
4358                 spec->vnode_lvol[i] = 0x5a;
4359                 spec->vnode_rvol[i] = 0x5a;
4360                 spec->vnode_lswitch[i] = 0;
4361                 spec->vnode_rswitch[i] = 0;
4362         }
4363
4364         /*
4365          * Default states for effects are in ca0132_effects[].
4366          */
4367         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4368         for (i = 0; i < num_fx; i++) {
4369                 on = (unsigned int)ca0132_effects[i].reqs[0];
4370                 spec->effects_switch[i] = on ? 1 : 0;
4371         }
4372
4373         spec->voicefx_val = 0;
4374         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4375         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4376
4377         #ifdef ENABLE_TUNING_CONTROLS
4378         ca0132_init_tuning_defaults(codec);
4379         #endif
4380 }
4381
4382 static void ca0132_exit_chip(struct hda_codec *codec)
4383 {
4384         /* put any chip cleanup stuffs here. */
4385
4386         if (dspload_is_loaded(codec))
4387                 dsp_reset(codec);
4388 }
4389
4390 static int ca0132_init(struct hda_codec *codec)
4391 {
4392         struct ca0132_spec *spec = codec->spec;
4393         int i;
4394
4395         spec->dsp_state = DSP_DOWNLOAD_INIT;
4396         spec->curr_chip_addx = (unsigned int)INVALID_CHIP_ADDRESS;
4397
4398         snd_hda_power_up(codec);
4399
4400         ca0132_init_params(codec);
4401         ca0132_init_flags(codec);
4402         snd_hda_sequence_write(codec, spec->base_init_verbs);
4403         ca0132_download_dsp(codec);
4404         ca0132_refresh_widget_caps(codec);
4405         ca0132_setup_defaults(codec);
4406         ca0132_init_analog_mic2(codec);
4407         ca0132_init_dmic(codec);
4408
4409         for (i = 0; i < spec->num_outputs; i++)
4410                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4411
4412         for (i = 0; i < spec->num_inputs; i++)
4413                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4414
4415         for (i = 0; i < spec->num_init_verbs; i++)
4416                 snd_hda_sequence_write(codec, spec->init_verbs[i]);
4417
4418         ca0132_init_unsol(codec);
4419
4420         ca0132_select_out(codec);
4421         ca0132_select_mic(codec);
4422
4423         snd_hda_jack_report_sync(codec);
4424
4425         snd_hda_power_down(codec);
4426
4427         return 0;
4428 }
4429
4430 static void ca0132_free(struct hda_codec *codec)
4431 {
4432         struct ca0132_spec *spec = codec->spec;
4433
4434         snd_hda_power_up(codec);
4435         snd_hda_sequence_write(codec, spec->base_exit_verbs);
4436         ca0132_exit_chip(codec);
4437         snd_hda_power_down(codec);
4438         kfree(codec->spec);
4439 }
4440
4441
4442 static struct hda_codec_ops ca0132_patch_ops = {
4443         .build_controls = ca0132_build_controls,
4444         .build_pcms = ca0132_build_pcms,
4445         .init = ca0132_init,
4446         .free = ca0132_free,
4447         .unsol_event = ca0132_unsol_event,
4448 };
4449
4450 static void ca0132_config(struct hda_codec *codec)
4451 {
4452         struct ca0132_spec *spec = codec->spec;
4453
4454         spec->dacs[0] = 0x2;
4455         spec->dacs[1] = 0x3;
4456         spec->dacs[2] = 0x4;
4457
4458         spec->multiout.dac_nids = spec->dacs;
4459         spec->multiout.num_dacs = 3;
4460         spec->multiout.max_channels = 2;
4461
4462         spec->num_outputs = 2;
4463         spec->out_pins[0] = 0x0b; /* speaker out */
4464         spec->out_pins[1] = 0x10; /* headphone out */
4465         spec->shared_out_nid = 0x2;
4466
4467         spec->num_inputs = 3;
4468         spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4469         spec->adcs[1] = 0x8; /* analog mic2 */
4470         spec->adcs[2] = 0xa; /* what u hear */
4471         spec->shared_mic_nid = 0x7;
4472
4473         spec->input_pins[0] = 0x12;
4474         spec->input_pins[1] = 0x11;
4475         spec->input_pins[2] = 0x13;
4476 }
4477
4478 static int patch_ca0132(struct hda_codec *codec)
4479 {
4480         struct ca0132_spec *spec;
4481         int err;
4482
4483         snd_printdd("patch_ca0132\n");
4484
4485         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4486         if (!spec)
4487                 return -ENOMEM;
4488         codec->spec = spec;
4489
4490         spec->num_mixers = 1;
4491         spec->mixers[0] = ca0132_mixer;
4492
4493         spec->base_init_verbs = ca0132_base_init_verbs;
4494         spec->base_exit_verbs = ca0132_base_exit_verbs;
4495         spec->init_verbs[0] = ca0132_init_verbs0;
4496         spec->init_verbs[1] = ca0132_init_verbs1;
4497         spec->num_init_verbs = 2;
4498
4499         ca0132_init_chip(codec);
4500
4501         ca0132_config(codec);
4502
4503         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4504         if (err < 0)
4505                 return err;
4506
4507         codec->patch_ops = ca0132_patch_ops;
4508
4509         return 0;
4510 }
4511
4512
4513 /*
4514  * patch entries
4515  */
4516 static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4517         { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4518         {} /* terminator */
4519 };
4520
4521 MODULE_ALIAS("snd-hda-codec-id:11020011");
4522
4523 MODULE_LICENSE("GPL");
4524 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4525
4526 static struct hda_codec_preset_list ca0132_list = {
4527         .preset = snd_hda_preset_ca0132,
4528         .owner = THIS_MODULE,
4529 };
4530
4531 static int __init patch_ca0132_init(void)
4532 {
4533         return snd_hda_add_codec_preset(&ca0132_list);
4534 }
4535
4536 static void __exit patch_ca0132_exit(void)
4537 {
4538         release_cached_firmware();
4539         snd_hda_delete_codec_preset(&ca0132_list);
4540 }
4541
4542 module_init(patch_ca0132_init)
4543 module_exit(patch_ca0132_exit)