3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include <sound/hda_chmap.h>
43 #include "hda_codec.h"
44 #include "hda_local.h"
47 static bool static_hdmi_pcm;
48 module_param(static_hdmi_pcm, bool, 0644);
49 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
51 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
52 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
56 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
57 || is_skylake(codec) || is_broxton(codec) \
58 || is_kabylake(codec))
60 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
61 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
62 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
64 struct hdmi_spec_per_cvt {
67 unsigned int channels_min;
68 unsigned int channels_max;
74 /* max. connections to a widget */
75 #define HDA_MAX_CONNECTIONS 32
77 struct hdmi_spec_per_pin {
79 /* pin idx, different device entries on the same pin use the same idx */
82 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
86 struct hda_codec *codec;
87 struct hdmi_eld sink_eld;
89 struct delayed_work work;
90 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
91 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
93 bool setup; /* the stream has been set up by prepare callback */
94 int channels; /* current number of channels */
96 bool chmap_set; /* channel-map override by ALSA API? */
97 unsigned char chmap[8]; /* ALSA API channel-map */
98 #ifdef CONFIG_SND_PROC_FS
99 struct snd_info_entry *proc_entry;
103 /* operations used by generic code that can be overridden by patches */
105 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
106 unsigned char *buf, int *eld_size);
108 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
109 int ca, int active_channels, int conn_type);
111 /* enable/disable HBR (HD passthrough) */
112 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
114 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
115 hda_nid_t pin_nid, u32 stream_tag, int format);
121 struct snd_jack *jack;
122 struct snd_kcontrol *eld_ctl;
127 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
128 hda_nid_t cvt_nids[4]; /* only for haswell fix */
131 struct snd_array pins; /* struct hdmi_spec_per_pin */
132 struct hdmi_pcm pcm_rec[16];
133 struct mutex pcm_lock;
134 /* pcm_bitmap means which pcms have been assigned to pins*/
135 unsigned long pcm_bitmap;
136 int pcm_used; /* counter of pcm_rec[] */
137 /* bitmap shows whether the pcm is opened in user space
138 * bit 0 means the first playback PCM (PCM3);
139 * bit 1 means the second playback PCM, and so on.
141 unsigned long pcm_in_use;
143 struct hdmi_eld temp_eld;
149 * Non-generic VIA/NVIDIA specific
151 struct hda_multi_out multiout;
152 struct hda_pcm_stream pcm_playback;
154 /* i915/powerwell (Haswell+/Valleyview+) specific */
155 struct i915_audio_component_audio_ops i915_audio_ops;
156 bool i915_bound; /* was i915 bound in this driver? */
158 struct hdac_chmap chmap;
161 #ifdef CONFIG_SND_HDA_I915
162 #define codec_has_acomp(codec) \
163 ((codec)->bus->core.audio_component != NULL)
165 #define codec_has_acomp(codec) false
168 struct hdmi_audio_infoframe {
175 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
179 u8 LFEPBL01_LSV36_DM_INH7;
182 struct dp_audio_infoframe {
185 u8 ver; /* 0x11 << 2 */
187 u8 CC02_CT47; /* match with HDMI infoframe from this on */
191 u8 LFEPBL01_LSV36_DM_INH7;
194 union audio_infoframe {
195 struct hdmi_audio_infoframe hdmi;
196 struct dp_audio_infoframe dp;
204 #define get_pin(spec, idx) \
205 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
206 #define get_cvt(spec, idx) \
207 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
208 /* obtain hdmi_pcm object assigned to idx */
209 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
210 /* obtain hda_pcm object assigned to idx */
211 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
213 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
215 struct hdmi_spec *spec = codec->spec;
218 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
219 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
222 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
226 static int hinfo_to_pcm_index(struct hda_codec *codec,
227 struct hda_pcm_stream *hinfo)
229 struct hdmi_spec *spec = codec->spec;
232 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
233 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
236 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
240 static int hinfo_to_pin_index(struct hda_codec *codec,
241 struct hda_pcm_stream *hinfo)
243 struct hdmi_spec *spec = codec->spec;
244 struct hdmi_spec_per_pin *per_pin;
247 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
248 per_pin = get_pin(spec, pin_idx);
250 per_pin->pcm->pcm->stream == hinfo)
254 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
258 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
262 struct hdmi_spec_per_pin *per_pin;
264 for (i = 0; i < spec->num_pins; i++) {
265 per_pin = get_pin(spec, i);
266 if (per_pin->pcm_idx == pcm_idx)
272 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
274 struct hdmi_spec *spec = codec->spec;
277 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
278 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
281 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
285 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
286 struct snd_ctl_elem_info *uinfo)
288 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
289 struct hdmi_spec *spec = codec->spec;
290 struct hdmi_spec_per_pin *per_pin;
291 struct hdmi_eld *eld;
294 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
296 pcm_idx = kcontrol->private_value;
297 mutex_lock(&spec->pcm_lock);
298 per_pin = pcm_idx_to_pin(spec, pcm_idx);
300 /* no pin is bound to the pcm */
302 mutex_unlock(&spec->pcm_lock);
305 eld = &per_pin->sink_eld;
306 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
307 mutex_unlock(&spec->pcm_lock);
312 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
313 struct snd_ctl_elem_value *ucontrol)
315 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
316 struct hdmi_spec *spec = codec->spec;
317 struct hdmi_spec_per_pin *per_pin;
318 struct hdmi_eld *eld;
321 pcm_idx = kcontrol->private_value;
322 mutex_lock(&spec->pcm_lock);
323 per_pin = pcm_idx_to_pin(spec, pcm_idx);
325 /* no pin is bound to the pcm */
326 memset(ucontrol->value.bytes.data, 0,
327 ARRAY_SIZE(ucontrol->value.bytes.data));
328 mutex_unlock(&spec->pcm_lock);
331 eld = &per_pin->sink_eld;
333 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
334 eld->eld_size > ELD_MAX_SIZE) {
335 mutex_unlock(&spec->pcm_lock);
340 memset(ucontrol->value.bytes.data, 0,
341 ARRAY_SIZE(ucontrol->value.bytes.data));
343 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
345 mutex_unlock(&spec->pcm_lock);
350 static struct snd_kcontrol_new eld_bytes_ctl = {
351 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
352 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
354 .info = hdmi_eld_ctl_info,
355 .get = hdmi_eld_ctl_get,
358 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
361 struct snd_kcontrol *kctl;
362 struct hdmi_spec *spec = codec->spec;
365 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
368 kctl->private_value = pcm_idx;
369 kctl->id.device = device;
371 /* no pin nid is associated with the kctl now
372 * tbd: associate pin nid to eld ctl later
374 err = snd_hda_ctl_add(codec, 0, kctl);
378 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
383 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
384 int *packet_index, int *byte_index)
388 val = snd_hda_codec_read(codec, pin_nid, 0,
389 AC_VERB_GET_HDMI_DIP_INDEX, 0);
391 *packet_index = val >> 5;
392 *byte_index = val & 0x1f;
396 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
397 int packet_index, int byte_index)
401 val = (packet_index << 5) | (byte_index & 0x1f);
403 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
406 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
409 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
412 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
414 struct hdmi_spec *spec = codec->spec;
418 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
419 snd_hda_codec_write(codec, pin_nid, 0,
420 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
422 if (spec->dyn_pin_out)
423 /* Disable pin out until stream is active */
426 /* Enable pin out: some machines with GM965 gets broken output
427 * when the pin is disabled or changed while using with HDMI
431 snd_hda_codec_write(codec, pin_nid, 0,
432 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
439 #ifdef CONFIG_SND_PROC_FS
440 static void print_eld_info(struct snd_info_entry *entry,
441 struct snd_info_buffer *buffer)
443 struct hdmi_spec_per_pin *per_pin = entry->private_data;
445 mutex_lock(&per_pin->lock);
446 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
447 mutex_unlock(&per_pin->lock);
450 static void write_eld_info(struct snd_info_entry *entry,
451 struct snd_info_buffer *buffer)
453 struct hdmi_spec_per_pin *per_pin = entry->private_data;
455 mutex_lock(&per_pin->lock);
456 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
457 mutex_unlock(&per_pin->lock);
460 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
463 struct hda_codec *codec = per_pin->codec;
464 struct snd_info_entry *entry;
467 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
468 err = snd_card_proc_new(codec->card, name, &entry);
472 snd_info_set_text_ops(entry, per_pin, print_eld_info);
473 entry->c.text.write = write_eld_info;
474 entry->mode |= S_IWUSR;
475 per_pin->proc_entry = entry;
480 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
482 if (!per_pin->codec->bus->shutdown) {
483 snd_info_free_entry(per_pin->proc_entry);
484 per_pin->proc_entry = NULL;
488 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
493 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
499 * Audio InfoFrame routines
503 * Enable Audio InfoFrame Transmission
505 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
508 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
509 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
514 * Disable Audio InfoFrame Transmission
516 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
519 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
520 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
524 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
526 #ifdef CONFIG_SND_DEBUG_VERBOSE
530 size = snd_hdmi_get_eld_size(codec, pin_nid);
531 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
533 for (i = 0; i < 8; i++) {
534 size = snd_hda_codec_read(codec, pin_nid, 0,
535 AC_VERB_GET_HDMI_DIP_SIZE, i);
536 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
541 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
547 for (i = 0; i < 8; i++) {
548 size = snd_hda_codec_read(codec, pin_nid, 0,
549 AC_VERB_GET_HDMI_DIP_SIZE, i);
553 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
554 for (j = 1; j < 1000; j++) {
555 hdmi_write_dip_byte(codec, pin_nid, 0x0);
556 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
558 codec_dbg(codec, "dip index %d: %d != %d\n",
560 if (bi == 0) /* byte index wrapped around */
564 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
570 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
572 u8 *bytes = (u8 *)hdmi_ai;
576 hdmi_ai->checksum = 0;
578 for (i = 0; i < sizeof(*hdmi_ai); i++)
581 hdmi_ai->checksum = -sum;
584 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
590 hdmi_debug_dip_size(codec, pin_nid);
591 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
593 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
594 for (i = 0; i < size; i++)
595 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
598 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
604 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
608 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
609 for (i = 0; i < size; i++) {
610 val = snd_hda_codec_read(codec, pin_nid, 0,
611 AC_VERB_GET_HDMI_DIP_DATA, 0);
619 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
621 int ca, int active_channels,
624 union audio_infoframe ai;
626 memset(&ai, 0, sizeof(ai));
627 if (conn_type == 0) { /* HDMI */
628 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
630 hdmi_ai->type = 0x84;
633 hdmi_ai->CC02_CT47 = active_channels - 1;
635 hdmi_checksum_audio_infoframe(hdmi_ai);
636 } else if (conn_type == 1) { /* DisplayPort */
637 struct dp_audio_infoframe *dp_ai = &ai.dp;
641 dp_ai->ver = 0x11 << 2;
642 dp_ai->CC02_CT47 = active_channels - 1;
645 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
651 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
652 * sizeof(*dp_ai) to avoid partial match/update problems when
653 * the user switches between HDMI/DP monitors.
655 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
658 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
660 active_channels, ca);
661 hdmi_stop_infoframe_trans(codec, pin_nid);
662 hdmi_fill_audio_infoframe(codec, pin_nid,
663 ai.bytes, sizeof(ai));
664 hdmi_start_infoframe_trans(codec, pin_nid);
668 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
669 struct hdmi_spec_per_pin *per_pin,
672 struct hdmi_spec *spec = codec->spec;
673 struct hdac_chmap *chmap = &spec->chmap;
674 hda_nid_t pin_nid = per_pin->pin_nid;
675 int channels = per_pin->channels;
677 struct hdmi_eld *eld;
683 if (is_haswell_plus(codec))
684 snd_hda_codec_write(codec, pin_nid, 0,
685 AC_VERB_SET_AMP_GAIN_MUTE,
688 eld = &per_pin->sink_eld;
690 ca = snd_hdac_channel_allocation(&codec->core,
691 eld->info.spk_alloc, channels,
692 per_pin->chmap_set, non_pcm, per_pin->chmap);
694 active_channels = snd_hdac_get_active_channels(ca);
696 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
700 * always configure channel mapping, it may have been changed by the
701 * user in the meantime
703 snd_hdac_setup_channel_mapping(&spec->chmap,
704 pin_nid, non_pcm, ca, channels,
705 per_pin->chmap, per_pin->chmap_set);
707 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
708 eld->info.conn_type);
710 per_pin->non_pcm = non_pcm;
717 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
719 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
721 struct hdmi_spec *spec = codec->spec;
722 int pin_idx = pin_nid_to_pin_index(codec, nid);
726 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
727 snd_hda_jack_report_sync(codec);
730 static void jack_callback(struct hda_codec *codec,
731 struct hda_jack_callback *jack)
733 check_presence_and_report(codec, jack->nid);
736 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
738 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
739 struct hda_jack_tbl *jack;
740 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
742 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
745 jack->jack_dirty = 1;
748 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
749 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
750 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
752 check_presence_and_report(codec, jack->nid);
755 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
757 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
758 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
759 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
760 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
763 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
778 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
780 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
781 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
783 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
784 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
789 hdmi_intrinsic_event(codec, res);
791 hdmi_non_intrinsic_event(codec, res);
794 static void haswell_verify_D0(struct hda_codec *codec,
795 hda_nid_t cvt_nid, hda_nid_t nid)
799 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
800 * thus pins could only choose converter 0 for use. Make sure the
801 * converters are in correct power state */
802 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
803 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
805 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
806 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
809 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
810 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
811 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
819 /* HBR should be Non-PCM, 8 channels */
820 #define is_hbr_format(format) \
821 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
823 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
826 int pinctl, new_pinctl;
828 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
829 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
830 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
833 return hbr ? -EINVAL : 0;
835 new_pinctl = pinctl & ~AC_PINCTL_EPT;
837 new_pinctl |= AC_PINCTL_EPT_HBR;
839 new_pinctl |= AC_PINCTL_EPT_NATIVE;
842 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
844 pinctl == new_pinctl ? "" : "new-",
847 if (pinctl != new_pinctl)
848 snd_hda_codec_write(codec, pin_nid, 0,
849 AC_VERB_SET_PIN_WIDGET_CONTROL,
857 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
858 hda_nid_t pin_nid, u32 stream_tag, int format)
860 struct hdmi_spec *spec = codec->spec;
863 if (is_haswell_plus(codec))
864 haswell_verify_D0(codec, cvt_nid, pin_nid);
866 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
869 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
873 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
877 /* Try to find an available converter
878 * If pin_idx is less then zero, just try to find an available converter.
879 * Otherwise, try to find an available converter and get the cvt mux index
882 static int hdmi_choose_cvt(struct hda_codec *codec,
883 int pin_idx, int *cvt_id, int *mux_id)
885 struct hdmi_spec *spec = codec->spec;
886 struct hdmi_spec_per_pin *per_pin;
887 struct hdmi_spec_per_cvt *per_cvt = NULL;
888 int cvt_idx, mux_idx = 0;
890 /* pin_idx < 0 means no pin will be bound to the converter */
894 per_pin = get_pin(spec, pin_idx);
896 /* Dynamically assign converter to stream */
897 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
898 per_cvt = get_cvt(spec, cvt_idx);
900 /* Must not already be assigned */
901 if (per_cvt->assigned)
905 /* Must be in pin's mux's list of converters */
906 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
907 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
909 /* Not in mux list */
910 if (mux_idx == per_pin->num_mux_nids)
915 /* No free converters */
916 if (cvt_idx == spec->num_cvts)
920 per_pin->mux_idx = mux_idx;
930 /* Assure the pin select the right convetor */
931 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
932 struct hdmi_spec_per_pin *per_pin)
934 hda_nid_t pin_nid = per_pin->pin_nid;
937 mux_idx = per_pin->mux_idx;
938 curr = snd_hda_codec_read(codec, pin_nid, 0,
939 AC_VERB_GET_CONNECT_SEL, 0);
941 snd_hda_codec_write_cache(codec, pin_nid, 0,
942 AC_VERB_SET_CONNECT_SEL,
946 /* get the mux index for the converter of the pins
947 * converter's mux index is the same for all pins on Intel platform
949 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
954 for (i = 0; i < spec->num_cvts; i++)
955 if (spec->cvt_nids[i] == cvt_nid)
960 /* Intel HDMI workaround to fix audio routing issue:
961 * For some Intel display codecs, pins share the same connection list.
962 * So a conveter can be selected by multiple pins and playback on any of these
963 * pins will generate sound on the external display, because audio flows from
964 * the same converter to the display pipeline. Also muting one pin may make
965 * other pins have no sound output.
966 * So this function assures that an assigned converter for a pin is not selected
969 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
970 hda_nid_t pin_nid, int mux_idx)
972 struct hdmi_spec *spec = codec->spec;
975 struct hdmi_spec_per_cvt *per_cvt;
977 /* configure all pins, including "no physical connection" ones */
978 for_each_hda_codec_node(nid, codec) {
979 unsigned int wid_caps = get_wcaps(codec, nid);
980 unsigned int wid_type = get_wcaps_type(wid_caps);
982 if (wid_type != AC_WID_PIN)
988 curr = snd_hda_codec_read(codec, nid, 0,
989 AC_VERB_GET_CONNECT_SEL, 0);
993 /* choose an unassigned converter. The conveters in the
994 * connection list are in the same order as in the codec.
996 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
997 per_cvt = get_cvt(spec, cvt_idx);
998 if (!per_cvt->assigned) {
1000 "choose cvt %d for pin nid %d\n",
1002 snd_hda_codec_write_cache(codec, nid, 0,
1003 AC_VERB_SET_CONNECT_SEL,
1011 /* A wrapper of intel_not_share_asigned_cvt() */
1012 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1013 hda_nid_t pin_nid, hda_nid_t cvt_nid)
1016 struct hdmi_spec *spec = codec->spec;
1018 if (!is_haswell_plus(codec) && !is_valleyview_plus(codec))
1021 /* On Intel platform, the mapping of converter nid to
1022 * mux index of the pins are always the same.
1023 * The pin nid may be 0, this means all pins will not
1024 * share the converter.
1026 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1028 intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1031 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1032 * in dyn_pcm_assign mode.
1034 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1035 struct hda_codec *codec,
1036 struct snd_pcm_substream *substream)
1038 struct hdmi_spec *spec = codec->spec;
1039 struct snd_pcm_runtime *runtime = substream->runtime;
1040 int cvt_idx, pcm_idx;
1041 struct hdmi_spec_per_cvt *per_cvt = NULL;
1044 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1048 err = hdmi_choose_cvt(codec, -1, &cvt_idx, NULL);
1052 per_cvt = get_cvt(spec, cvt_idx);
1053 per_cvt->assigned = 1;
1054 hinfo->nid = per_cvt->cvt_nid;
1056 intel_not_share_assigned_cvt_nid(codec, 0, per_cvt->cvt_nid);
1058 set_bit(pcm_idx, &spec->pcm_in_use);
1059 /* todo: setup spdif ctls assign */
1061 /* Initially set the converter's capabilities */
1062 hinfo->channels_min = per_cvt->channels_min;
1063 hinfo->channels_max = per_cvt->channels_max;
1064 hinfo->rates = per_cvt->rates;
1065 hinfo->formats = per_cvt->formats;
1066 hinfo->maxbps = per_cvt->maxbps;
1068 /* Store the updated parameters */
1069 runtime->hw.channels_min = hinfo->channels_min;
1070 runtime->hw.channels_max = hinfo->channels_max;
1071 runtime->hw.formats = hinfo->formats;
1072 runtime->hw.rates = hinfo->rates;
1074 snd_pcm_hw_constraint_step(substream->runtime, 0,
1075 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1082 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1083 struct hda_codec *codec,
1084 struct snd_pcm_substream *substream)
1086 struct hdmi_spec *spec = codec->spec;
1087 struct snd_pcm_runtime *runtime = substream->runtime;
1088 int pin_idx, cvt_idx, pcm_idx, mux_idx = 0;
1089 struct hdmi_spec_per_pin *per_pin;
1090 struct hdmi_eld *eld;
1091 struct hdmi_spec_per_cvt *per_cvt = NULL;
1094 /* Validate hinfo */
1095 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1099 mutex_lock(&spec->pcm_lock);
1100 pin_idx = hinfo_to_pin_index(codec, hinfo);
1101 if (!spec->dyn_pcm_assign) {
1102 if (snd_BUG_ON(pin_idx < 0)) {
1103 mutex_unlock(&spec->pcm_lock);
1107 /* no pin is assigned to the PCM
1108 * PA need pcm open successfully when probe
1111 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1112 mutex_unlock(&spec->pcm_lock);
1117 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1119 mutex_unlock(&spec->pcm_lock);
1123 per_cvt = get_cvt(spec, cvt_idx);
1124 /* Claim converter */
1125 per_cvt->assigned = 1;
1127 set_bit(pcm_idx, &spec->pcm_in_use);
1128 per_pin = get_pin(spec, pin_idx);
1129 per_pin->cvt_nid = per_cvt->cvt_nid;
1130 hinfo->nid = per_cvt->cvt_nid;
1132 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1133 AC_VERB_SET_CONNECT_SEL,
1136 /* configure unused pins to choose other converters */
1137 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1138 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1140 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1142 /* Initially set the converter's capabilities */
1143 hinfo->channels_min = per_cvt->channels_min;
1144 hinfo->channels_max = per_cvt->channels_max;
1145 hinfo->rates = per_cvt->rates;
1146 hinfo->formats = per_cvt->formats;
1147 hinfo->maxbps = per_cvt->maxbps;
1149 eld = &per_pin->sink_eld;
1150 /* Restrict capabilities by ELD if this isn't disabled */
1151 if (!static_hdmi_pcm && eld->eld_valid) {
1152 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1153 if (hinfo->channels_min > hinfo->channels_max ||
1154 !hinfo->rates || !hinfo->formats) {
1155 per_cvt->assigned = 0;
1157 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1158 mutex_unlock(&spec->pcm_lock);
1163 mutex_unlock(&spec->pcm_lock);
1164 /* Store the updated parameters */
1165 runtime->hw.channels_min = hinfo->channels_min;
1166 runtime->hw.channels_max = hinfo->channels_max;
1167 runtime->hw.formats = hinfo->formats;
1168 runtime->hw.rates = hinfo->rates;
1170 snd_pcm_hw_constraint_step(substream->runtime, 0,
1171 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1176 * HDA/HDMI auto parsing
1178 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1180 struct hdmi_spec *spec = codec->spec;
1181 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1182 hda_nid_t pin_nid = per_pin->pin_nid;
1184 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1186 "HDMI: pin %d wcaps %#x does not support connection list\n",
1187 pin_nid, get_wcaps(codec, pin_nid));
1191 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1193 HDA_MAX_CONNECTIONS);
1198 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1199 struct hdmi_spec_per_pin *per_pin)
1203 /* try the prefer PCM */
1204 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1205 return per_pin->pin_nid_idx;
1207 /* have a second try; check the "reserved area" over num_pins */
1208 for (i = spec->num_pins; i < spec->pcm_used; i++) {
1209 if (!test_bit(i, &spec->pcm_bitmap))
1213 /* the last try; check the empty slots in pins */
1214 for (i = 0; i < spec->num_pins; i++) {
1215 if (!test_bit(i, &spec->pcm_bitmap))
1221 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1222 struct hdmi_spec_per_pin *per_pin)
1226 /* pcm already be attached to the pin */
1229 idx = hdmi_find_pcm_slot(spec, per_pin);
1232 per_pin->pcm_idx = idx;
1233 per_pin->pcm = get_hdmi_pcm(spec, idx);
1234 set_bit(idx, &spec->pcm_bitmap);
1237 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1238 struct hdmi_spec_per_pin *per_pin)
1242 /* pcm already be detached from the pin */
1245 idx = per_pin->pcm_idx;
1246 per_pin->pcm_idx = -1;
1247 per_pin->pcm = NULL;
1248 if (idx >= 0 && idx < spec->pcm_used)
1249 clear_bit(idx, &spec->pcm_bitmap);
1252 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1253 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1257 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1258 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1263 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1265 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1266 struct hdmi_spec_per_pin *per_pin)
1268 struct hda_codec *codec = per_pin->codec;
1269 struct hda_pcm *pcm;
1270 struct hda_pcm_stream *hinfo;
1271 struct snd_pcm_substream *substream;
1275 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1276 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1279 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1282 /* hdmi audio only uses playback and one substream */
1283 hinfo = pcm->stream;
1284 substream = pcm->pcm->streams[0].substream;
1286 per_pin->cvt_nid = hinfo->nid;
1288 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1289 if (mux_idx < per_pin->num_mux_nids)
1290 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1291 AC_VERB_SET_CONNECT_SEL,
1293 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1295 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1296 if (substream->runtime)
1297 per_pin->channels = substream->runtime->channels;
1298 per_pin->setup = true;
1299 per_pin->mux_idx = mux_idx;
1301 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1304 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1305 struct hdmi_spec_per_pin *per_pin)
1307 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1308 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1310 per_pin->chmap_set = false;
1311 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1313 per_pin->setup = false;
1314 per_pin->channels = 0;
1317 /* update per_pin ELD from the given new ELD;
1318 * setup info frame and notification accordingly
1320 static void update_eld(struct hda_codec *codec,
1321 struct hdmi_spec_per_pin *per_pin,
1322 struct hdmi_eld *eld)
1324 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1325 struct hdmi_spec *spec = codec->spec;
1326 bool old_eld_valid = pin_eld->eld_valid;
1330 /* for monitor disconnection, save pcm_idx firstly */
1331 pcm_idx = per_pin->pcm_idx;
1332 if (spec->dyn_pcm_assign) {
1333 if (eld->eld_valid) {
1334 hdmi_attach_hda_pcm(spec, per_pin);
1335 hdmi_pcm_setup_pin(spec, per_pin);
1337 hdmi_pcm_reset_pin(spec, per_pin);
1338 hdmi_detach_hda_pcm(spec, per_pin);
1341 /* if pcm_idx == -1, it means this is in monitor connection event
1342 * we can get the correct pcm_idx now.
1345 pcm_idx = per_pin->pcm_idx;
1348 snd_hdmi_show_eld(codec, &eld->info);
1350 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1351 if (eld->eld_valid && pin_eld->eld_valid)
1352 if (pin_eld->eld_size != eld->eld_size ||
1353 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1354 eld->eld_size) != 0)
1357 pin_eld->eld_valid = eld->eld_valid;
1358 pin_eld->eld_size = eld->eld_size;
1360 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1361 pin_eld->info = eld->info;
1364 * Re-setup pin and infoframe. This is needed e.g. when
1365 * - sink is first plugged-in
1366 * - transcoder can change during stream playback on Haswell
1367 * and this can make HW reset converter selection on a pin.
1369 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1370 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1371 intel_verify_pin_cvt_connect(codec, per_pin);
1372 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1376 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1379 if (eld_changed && pcm_idx >= 0)
1380 snd_ctl_notify(codec->card,
1381 SNDRV_CTL_EVENT_MASK_VALUE |
1382 SNDRV_CTL_EVENT_MASK_INFO,
1383 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1386 /* update ELD and jack state via HD-audio verbs */
1387 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1390 struct hda_jack_tbl *jack;
1391 struct hda_codec *codec = per_pin->codec;
1392 struct hdmi_spec *spec = codec->spec;
1393 struct hdmi_eld *eld = &spec->temp_eld;
1394 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1395 hda_nid_t pin_nid = per_pin->pin_nid;
1397 * Always execute a GetPinSense verb here, even when called from
1398 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1399 * response's PD bit is not the real PD value, but indicates that
1400 * the real PD value changed. An older version of the HD-audio
1401 * specification worked this way. Hence, we just ignore the data in
1402 * the unsolicited response to avoid custom WARs.
1406 bool do_repoll = false;
1408 snd_hda_power_up_pm(codec);
1409 present = snd_hda_pin_sense(codec, pin_nid);
1411 mutex_lock(&per_pin->lock);
1412 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1413 if (pin_eld->monitor_present)
1414 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1416 eld->eld_valid = false;
1419 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1420 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1422 if (eld->eld_valid) {
1423 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1424 &eld->eld_size) < 0)
1425 eld->eld_valid = false;
1427 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1429 eld->eld_valid = false;
1431 if (!eld->eld_valid && repoll)
1436 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1438 update_eld(codec, per_pin, eld);
1440 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1442 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1444 jack->block_report = !ret;
1446 mutex_unlock(&per_pin->lock);
1447 snd_hda_power_down_pm(codec);
1451 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1452 struct hdmi_spec_per_pin *per_pin)
1454 struct hdmi_spec *spec = codec->spec;
1455 struct snd_jack *jack = NULL;
1456 struct hda_jack_tbl *jack_tbl;
1458 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1459 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1460 * NULL even after snd_hda_jack_tbl_clear() is called to
1461 * free snd_jack. This may cause access invalid memory
1462 * when calling snd_jack_report
1464 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1465 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1466 else if (!spec->dyn_pcm_assign) {
1467 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1469 jack = jack_tbl->jack;
1474 /* update ELD and jack state via audio component */
1475 static void sync_eld_via_acomp(struct hda_codec *codec,
1476 struct hdmi_spec_per_pin *per_pin)
1478 struct hdmi_spec *spec = codec->spec;
1479 struct hdmi_eld *eld = &spec->temp_eld;
1480 struct snd_jack *jack = NULL;
1483 mutex_lock(&per_pin->lock);
1484 size = snd_hdac_acomp_get_eld(&codec->bus->core, per_pin->pin_nid,
1485 &eld->monitor_present, eld->eld_buffer,
1490 size = min(size, ELD_MAX_SIZE);
1491 if (snd_hdmi_parse_eld(codec, &eld->info,
1492 eld->eld_buffer, size) < 0)
1497 eld->eld_valid = true;
1498 eld->eld_size = size;
1500 eld->eld_valid = false;
1504 /* pcm_idx >=0 before update_eld() means it is in monitor
1505 * disconnected event. Jack must be fetched before update_eld()
1507 jack = pin_idx_to_jack(codec, per_pin);
1508 update_eld(codec, per_pin, eld);
1510 jack = pin_idx_to_jack(codec, per_pin);
1513 snd_jack_report(jack,
1514 eld->monitor_present ? SND_JACK_AVOUT : 0);
1516 mutex_unlock(&per_pin->lock);
1519 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1521 struct hda_codec *codec = per_pin->codec;
1522 struct hdmi_spec *spec = codec->spec;
1525 mutex_lock(&spec->pcm_lock);
1526 if (codec_has_acomp(codec)) {
1527 sync_eld_via_acomp(codec, per_pin);
1528 ret = false; /* don't call snd_hda_jack_report_sync() */
1530 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1532 mutex_unlock(&spec->pcm_lock);
1537 static void hdmi_repoll_eld(struct work_struct *work)
1539 struct hdmi_spec_per_pin *per_pin =
1540 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1542 if (per_pin->repoll_count++ > 6)
1543 per_pin->repoll_count = 0;
1545 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1546 snd_hda_jack_report_sync(per_pin->codec);
1549 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1552 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1554 struct hdmi_spec *spec = codec->spec;
1555 unsigned int caps, config;
1557 struct hdmi_spec_per_pin *per_pin;
1560 caps = snd_hda_query_pin_caps(codec, pin_nid);
1561 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1564 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1565 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1568 if (is_haswell_plus(codec))
1569 intel_haswell_fixup_connect_list(codec, pin_nid);
1571 pin_idx = spec->num_pins;
1572 per_pin = snd_array_new(&spec->pins);
1576 per_pin->pin_nid = pin_nid;
1577 per_pin->non_pcm = false;
1578 if (spec->dyn_pcm_assign)
1579 per_pin->pcm_idx = -1;
1581 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1582 per_pin->pcm_idx = pin_idx;
1584 per_pin->pin_nid_idx = pin_idx;
1586 err = hdmi_read_pin_conn(codec, pin_idx);
1595 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1597 struct hdmi_spec *spec = codec->spec;
1598 struct hdmi_spec_per_cvt *per_cvt;
1602 chans = get_wcaps(codec, cvt_nid);
1603 chans = get_wcaps_channels(chans);
1605 per_cvt = snd_array_new(&spec->cvts);
1609 per_cvt->cvt_nid = cvt_nid;
1610 per_cvt->channels_min = 2;
1612 per_cvt->channels_max = chans;
1613 if (chans > spec->chmap.channels_max)
1614 spec->chmap.channels_max = chans;
1617 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1624 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1625 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1631 static int hdmi_parse_codec(struct hda_codec *codec)
1636 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1637 if (!nid || nodes < 0) {
1638 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1642 for (i = 0; i < nodes; i++, nid++) {
1646 caps = get_wcaps(codec, nid);
1647 type = get_wcaps_type(caps);
1649 if (!(caps & AC_WCAP_DIGITAL))
1653 case AC_WID_AUD_OUT:
1654 hdmi_add_cvt(codec, nid);
1657 hdmi_add_pin(codec, nid);
1667 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1669 struct hda_spdif_out *spdif;
1672 mutex_lock(&codec->spdif_mutex);
1673 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1674 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1675 mutex_unlock(&codec->spdif_mutex);
1683 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1684 struct hda_codec *codec,
1685 unsigned int stream_tag,
1686 unsigned int format,
1687 struct snd_pcm_substream *substream)
1689 hda_nid_t cvt_nid = hinfo->nid;
1690 struct hdmi_spec *spec = codec->spec;
1692 struct hdmi_spec_per_pin *per_pin;
1694 struct snd_pcm_runtime *runtime = substream->runtime;
1699 mutex_lock(&spec->pcm_lock);
1700 pin_idx = hinfo_to_pin_index(codec, hinfo);
1701 if (spec->dyn_pcm_assign && pin_idx < 0) {
1702 /* when dyn_pcm_assign and pcm is not bound to a pin
1703 * skip pin setup and return 0 to make audio playback
1706 intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
1707 snd_hda_codec_setup_stream(codec, cvt_nid,
1708 stream_tag, 0, format);
1709 mutex_unlock(&spec->pcm_lock);
1713 if (snd_BUG_ON(pin_idx < 0)) {
1714 mutex_unlock(&spec->pcm_lock);
1717 per_pin = get_pin(spec, pin_idx);
1718 pin_nid = per_pin->pin_nid;
1719 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1720 /* Verify pin:cvt selections to avoid silent audio after S3.
1721 * After S3, the audio driver restores pin:cvt selections
1722 * but this can happen before gfx is ready and such selection
1723 * is overlooked by HW. Thus multiple pins can share a same
1724 * default convertor and mute control will affect each other,
1725 * which can cause a resumed audio playback become silent
1728 intel_verify_pin_cvt_connect(codec, per_pin);
1729 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1732 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1733 /* Todo: add DP1.2 MST audio support later */
1734 snd_hdac_sync_audio_rate(&codec->bus->core, pin_nid, runtime->rate);
1736 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1737 mutex_lock(&per_pin->lock);
1738 per_pin->channels = substream->runtime->channels;
1739 per_pin->setup = true;
1741 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1742 mutex_unlock(&per_pin->lock);
1743 if (spec->dyn_pin_out) {
1744 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1745 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1746 snd_hda_codec_write(codec, pin_nid, 0,
1747 AC_VERB_SET_PIN_WIDGET_CONTROL,
1751 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1752 stream_tag, format);
1753 mutex_unlock(&spec->pcm_lock);
1757 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1758 struct hda_codec *codec,
1759 struct snd_pcm_substream *substream)
1761 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1765 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1766 struct hda_codec *codec,
1767 struct snd_pcm_substream *substream)
1769 struct hdmi_spec *spec = codec->spec;
1770 int cvt_idx, pin_idx, pcm_idx;
1771 struct hdmi_spec_per_cvt *per_cvt;
1772 struct hdmi_spec_per_pin *per_pin;
1776 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1777 if (snd_BUG_ON(pcm_idx < 0))
1779 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1780 if (snd_BUG_ON(cvt_idx < 0))
1782 per_cvt = get_cvt(spec, cvt_idx);
1784 snd_BUG_ON(!per_cvt->assigned);
1785 per_cvt->assigned = 0;
1788 mutex_lock(&spec->pcm_lock);
1789 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1790 clear_bit(pcm_idx, &spec->pcm_in_use);
1791 pin_idx = hinfo_to_pin_index(codec, hinfo);
1792 if (spec->dyn_pcm_assign && pin_idx < 0) {
1793 mutex_unlock(&spec->pcm_lock);
1797 if (snd_BUG_ON(pin_idx < 0)) {
1798 mutex_unlock(&spec->pcm_lock);
1801 per_pin = get_pin(spec, pin_idx);
1803 if (spec->dyn_pin_out) {
1804 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1805 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1806 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1807 AC_VERB_SET_PIN_WIDGET_CONTROL,
1811 mutex_lock(&per_pin->lock);
1812 per_pin->chmap_set = false;
1813 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1815 per_pin->setup = false;
1816 per_pin->channels = 0;
1817 mutex_unlock(&per_pin->lock);
1818 mutex_unlock(&spec->pcm_lock);
1824 static const struct hda_pcm_ops generic_ops = {
1825 .open = hdmi_pcm_open,
1826 .close = hdmi_pcm_close,
1827 .prepare = generic_hdmi_playback_pcm_prepare,
1828 .cleanup = generic_hdmi_playback_pcm_cleanup,
1831 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
1832 unsigned char *chmap)
1834 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1835 struct hdmi_spec *spec = codec->spec;
1836 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1838 /* chmap is already set to 0 in caller */
1842 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
1845 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
1846 unsigned char *chmap, int prepared)
1848 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1849 struct hdmi_spec *spec = codec->spec;
1850 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1852 mutex_lock(&per_pin->lock);
1853 per_pin->chmap_set = true;
1854 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
1856 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1857 mutex_unlock(&per_pin->lock);
1860 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
1862 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1863 struct hdmi_spec *spec = codec->spec;
1864 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1866 return per_pin ? true:false;
1869 static int generic_hdmi_build_pcms(struct hda_codec *codec)
1871 struct hdmi_spec *spec = codec->spec;
1874 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1875 struct hda_pcm *info;
1876 struct hda_pcm_stream *pstr;
1878 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
1882 spec->pcm_rec[pin_idx].pcm = info;
1884 info->pcm_type = HDA_PCM_TYPE_HDMI;
1885 info->own_chmap = true;
1887 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1888 pstr->substreams = 1;
1889 pstr->ops = generic_ops;
1890 /* other pstr fields are set in open */
1896 static void free_hdmi_jack_priv(struct snd_jack *jack)
1898 struct hdmi_pcm *pcm = jack->private_data;
1903 static int add_hdmi_jack_kctl(struct hda_codec *codec,
1904 struct hdmi_spec *spec,
1908 struct snd_jack *jack;
1911 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
1916 spec->pcm_rec[pcm_idx].jack = jack;
1917 jack->private_data = &spec->pcm_rec[pcm_idx];
1918 jack->private_free = free_hdmi_jack_priv;
1922 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
1924 char hdmi_str[32] = "HDMI/DP";
1925 struct hdmi_spec *spec = codec->spec;
1926 struct hdmi_spec_per_pin *per_pin;
1927 struct hda_jack_tbl *jack;
1928 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
1933 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
1935 if (spec->dyn_pcm_assign)
1936 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
1938 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
1939 /* if !dyn_pcm_assign, it must be non-MST mode.
1940 * This means pcms and pins are statically mapped.
1941 * And pcm_idx is pin_idx.
1943 per_pin = get_pin(spec, pcm_idx);
1944 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
1946 strncat(hdmi_str, " Phantom",
1947 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
1948 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
1952 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1955 /* assign jack->jack to pcm_rec[].jack to
1956 * align with dyn_pcm_assign mode
1958 spec->pcm_rec[pcm_idx].jack = jack->jack;
1962 static int generic_hdmi_build_controls(struct hda_codec *codec)
1964 struct hdmi_spec *spec = codec->spec;
1966 int pin_idx, pcm_idx;
1969 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
1970 err = generic_hdmi_build_jack(codec, pcm_idx);
1974 /* create the spdif for each pcm
1975 * pin will be bound when monitor is connected
1977 if (spec->dyn_pcm_assign)
1978 err = snd_hda_create_dig_out_ctls(codec,
1979 0, spec->cvt_nids[0],
1982 struct hdmi_spec_per_pin *per_pin =
1983 get_pin(spec, pcm_idx);
1984 err = snd_hda_create_dig_out_ctls(codec,
1986 per_pin->mux_nids[0],
1991 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1993 /* add control for ELD Bytes */
1994 err = hdmi_create_eld_ctl(codec, pcm_idx,
1995 get_pcm_rec(spec, pcm_idx)->device);
2000 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2001 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2003 hdmi_present_sense(per_pin, 0);
2006 /* add channel maps */
2007 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2008 struct hda_pcm *pcm;
2010 pcm = get_pcm_rec(spec, pcm_idx);
2011 if (!pcm || !pcm->pcm)
2013 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2021 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2023 struct hdmi_spec *spec = codec->spec;
2026 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2027 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2029 per_pin->codec = codec;
2030 mutex_init(&per_pin->lock);
2031 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2032 eld_proc_new(per_pin, pin_idx);
2037 static int generic_hdmi_init(struct hda_codec *codec)
2039 struct hdmi_spec *spec = codec->spec;
2042 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2043 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2044 hda_nid_t pin_nid = per_pin->pin_nid;
2046 hdmi_init_pin(codec, pin_nid);
2047 if (!codec_has_acomp(codec))
2048 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2049 codec->jackpoll_interval > 0 ?
2050 jack_callback : NULL);
2055 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2057 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2058 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2061 static void hdmi_array_free(struct hdmi_spec *spec)
2063 snd_array_free(&spec->pins);
2064 snd_array_free(&spec->cvts);
2067 static void generic_hdmi_free(struct hda_codec *codec)
2069 struct hdmi_spec *spec = codec->spec;
2070 int pin_idx, pcm_idx;
2072 if (codec_has_acomp(codec))
2073 snd_hdac_i915_register_notifier(NULL);
2075 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2076 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2077 cancel_delayed_work_sync(&per_pin->work);
2078 eld_proc_free(per_pin);
2081 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2082 if (spec->pcm_rec[pcm_idx].jack == NULL)
2084 if (spec->dyn_pcm_assign)
2085 snd_device_free(codec->card,
2086 spec->pcm_rec[pcm_idx].jack);
2088 spec->pcm_rec[pcm_idx].jack = NULL;
2091 if (spec->i915_bound)
2092 snd_hdac_i915_exit(&codec->bus->core);
2093 hdmi_array_free(spec);
2098 static int generic_hdmi_resume(struct hda_codec *codec)
2100 struct hdmi_spec *spec = codec->spec;
2103 codec->patch_ops.init(codec);
2104 regcache_sync(codec->core.regmap);
2106 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2107 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2108 hdmi_present_sense(per_pin, 1);
2114 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2115 .init = generic_hdmi_init,
2116 .free = generic_hdmi_free,
2117 .build_pcms = generic_hdmi_build_pcms,
2118 .build_controls = generic_hdmi_build_controls,
2119 .unsol_event = hdmi_unsol_event,
2121 .resume = generic_hdmi_resume,
2125 static const struct hdmi_ops generic_standard_hdmi_ops = {
2126 .pin_get_eld = snd_hdmi_get_eld,
2127 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2128 .pin_hbr_setup = hdmi_pin_hbr_setup,
2129 .setup_stream = hdmi_setup_stream,
2132 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2135 struct hdmi_spec *spec = codec->spec;
2139 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2140 if (nconns == spec->num_cvts &&
2141 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2144 /* override pins connection list */
2145 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2146 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2149 #define INTEL_VENDOR_NID 0x08
2150 #define INTEL_GET_VENDOR_VERB 0xf81
2151 #define INTEL_SET_VENDOR_VERB 0x781
2152 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2153 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2155 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2158 unsigned int vendor_param;
2160 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2161 INTEL_GET_VENDOR_VERB, 0);
2162 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2165 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2166 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2167 INTEL_SET_VENDOR_VERB, vendor_param);
2168 if (vendor_param == -1)
2172 snd_hda_codec_update_widgets(codec);
2175 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2177 unsigned int vendor_param;
2179 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2180 INTEL_GET_VENDOR_VERB, 0);
2181 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2184 /* enable DP1.2 mode */
2185 vendor_param |= INTEL_EN_DP12;
2186 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2187 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2188 INTEL_SET_VENDOR_VERB, vendor_param);
2191 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2192 * Otherwise you may get severe h/w communication errors.
2194 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2195 unsigned int power_state)
2197 if (power_state == AC_PWRST_D0) {
2198 intel_haswell_enable_all_pins(codec, false);
2199 intel_haswell_fixup_enable_dp12(codec);
2202 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2203 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2206 static void intel_pin_eld_notify(void *audio_ptr, int port)
2208 struct hda_codec *codec = audio_ptr;
2209 int pin_nid = port + 0x04;
2211 /* we assume only from port-B to port-D */
2212 if (port < 1 || port > 3)
2215 /* skip notification during system suspend (but not in runtime PM);
2216 * the state will be updated at resume
2218 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2220 /* ditto during suspend/resume process itself */
2221 if (atomic_read(&(codec)->core.in_pm))
2224 check_presence_and_report(codec, pin_nid);
2227 static int patch_generic_hdmi(struct hda_codec *codec)
2229 struct hdmi_spec *spec;
2231 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2235 spec->ops = generic_standard_hdmi_ops;
2236 mutex_init(&spec->pcm_lock);
2237 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2239 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2240 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2241 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2244 hdmi_array_init(spec, 4);
2246 /* Try to bind with i915 for Intel HSW+ codecs (if not done yet) */
2247 if (!codec_has_acomp(codec) &&
2248 (codec->core.vendor_id >> 16) == 0x8086 &&
2249 is_haswell_plus(codec))
2250 if (!snd_hdac_i915_init(&codec->bus->core))
2251 spec->i915_bound = true;
2253 if (is_haswell_plus(codec)) {
2254 intel_haswell_enable_all_pins(codec, true);
2255 intel_haswell_fixup_enable_dp12(codec);
2258 /* For Valleyview/Cherryview, only the display codec is in the display
2259 * power well and can use link_power ops to request/release the power.
2260 * For Haswell/Broadwell, the controller is also in the power well and
2261 * can cover the codec power request, and so need not set this flag.
2262 * For previous platforms, there is no such power well feature.
2264 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2266 codec->core.link_power_control = 1;
2268 if (hdmi_parse_codec(codec) < 0) {
2269 if (spec->i915_bound)
2270 snd_hdac_i915_exit(&codec->bus->core);
2275 codec->patch_ops = generic_hdmi_patch_ops;
2276 if (is_haswell_plus(codec)) {
2277 codec->patch_ops.set_power_state = haswell_set_power_state;
2278 codec->dp_mst = true;
2281 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2282 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2283 codec->auto_runtime_pm = 1;
2285 generic_hdmi_init_per_pins(codec);
2288 if (codec_has_acomp(codec)) {
2289 codec->depop_delay = 0;
2290 spec->i915_audio_ops.audio_ptr = codec;
2291 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2292 * will call pin_eld_notify with using audio_ptr pointer
2293 * We need make sure audio_ptr is really setup
2296 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2297 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2300 WARN_ON(spec->dyn_pcm_assign && !codec_has_acomp(codec));
2305 * Shared non-generic implementations
2308 static int simple_playback_build_pcms(struct hda_codec *codec)
2310 struct hdmi_spec *spec = codec->spec;
2311 struct hda_pcm *info;
2313 struct hda_pcm_stream *pstr;
2314 struct hdmi_spec_per_cvt *per_cvt;
2316 per_cvt = get_cvt(spec, 0);
2317 chans = get_wcaps(codec, per_cvt->cvt_nid);
2318 chans = get_wcaps_channels(chans);
2320 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2323 spec->pcm_rec[0].pcm = info;
2324 info->pcm_type = HDA_PCM_TYPE_HDMI;
2325 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2326 *pstr = spec->pcm_playback;
2327 pstr->nid = per_cvt->cvt_nid;
2328 if (pstr->channels_max <= 2 && chans && chans <= 16)
2329 pstr->channels_max = chans;
2334 /* unsolicited event for jack sensing */
2335 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2338 snd_hda_jack_set_dirty_all(codec);
2339 snd_hda_jack_report_sync(codec);
2342 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2343 * as long as spec->pins[] is set correctly
2345 #define simple_hdmi_build_jack generic_hdmi_build_jack
2347 static int simple_playback_build_controls(struct hda_codec *codec)
2349 struct hdmi_spec *spec = codec->spec;
2350 struct hdmi_spec_per_cvt *per_cvt;
2353 per_cvt = get_cvt(spec, 0);
2354 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2359 return simple_hdmi_build_jack(codec, 0);
2362 static int simple_playback_init(struct hda_codec *codec)
2364 struct hdmi_spec *spec = codec->spec;
2365 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2366 hda_nid_t pin = per_pin->pin_nid;
2368 snd_hda_codec_write(codec, pin, 0,
2369 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2370 /* some codecs require to unmute the pin */
2371 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2372 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2374 snd_hda_jack_detect_enable(codec, pin);
2378 static void simple_playback_free(struct hda_codec *codec)
2380 struct hdmi_spec *spec = codec->spec;
2382 hdmi_array_free(spec);
2387 * Nvidia specific implementations
2390 #define Nv_VERB_SET_Channel_Allocation 0xF79
2391 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2392 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2393 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2395 #define nvhdmi_master_con_nid_7x 0x04
2396 #define nvhdmi_master_pin_nid_7x 0x05
2398 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2399 /*front, rear, clfe, rear_surr */
2403 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2404 /* set audio protect on */
2405 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2406 /* enable digital output on pin widget */
2407 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2411 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2412 /* set audio protect on */
2413 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2414 /* enable digital output on pin widget */
2415 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2416 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2417 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2418 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2419 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2423 #ifdef LIMITED_RATE_FMT_SUPPORT
2424 /* support only the safe format and rate */
2425 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2426 #define SUPPORTED_MAXBPS 16
2427 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2429 /* support all rates and formats */
2430 #define SUPPORTED_RATES \
2431 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2432 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2433 SNDRV_PCM_RATE_192000)
2434 #define SUPPORTED_MAXBPS 24
2435 #define SUPPORTED_FORMATS \
2436 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2439 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2441 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2445 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2447 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2451 static unsigned int channels_2_6_8[] = {
2455 static unsigned int channels_2_8[] = {
2459 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2460 .count = ARRAY_SIZE(channels_2_6_8),
2461 .list = channels_2_6_8,
2465 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2466 .count = ARRAY_SIZE(channels_2_8),
2467 .list = channels_2_8,
2471 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2472 struct hda_codec *codec,
2473 struct snd_pcm_substream *substream)
2475 struct hdmi_spec *spec = codec->spec;
2476 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2478 switch (codec->preset->vendor_id) {
2483 hw_constraints_channels = &hw_constraints_2_8_channels;
2486 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2492 if (hw_constraints_channels != NULL) {
2493 snd_pcm_hw_constraint_list(substream->runtime, 0,
2494 SNDRV_PCM_HW_PARAM_CHANNELS,
2495 hw_constraints_channels);
2497 snd_pcm_hw_constraint_step(substream->runtime, 0,
2498 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2501 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2504 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2505 struct hda_codec *codec,
2506 struct snd_pcm_substream *substream)
2508 struct hdmi_spec *spec = codec->spec;
2509 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2512 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2513 struct hda_codec *codec,
2514 unsigned int stream_tag,
2515 unsigned int format,
2516 struct snd_pcm_substream *substream)
2518 struct hdmi_spec *spec = codec->spec;
2519 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2520 stream_tag, format, substream);
2523 static const struct hda_pcm_stream simple_pcm_playback = {
2528 .open = simple_playback_pcm_open,
2529 .close = simple_playback_pcm_close,
2530 .prepare = simple_playback_pcm_prepare
2534 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2535 .build_controls = simple_playback_build_controls,
2536 .build_pcms = simple_playback_build_pcms,
2537 .init = simple_playback_init,
2538 .free = simple_playback_free,
2539 .unsol_event = simple_hdmi_unsol_event,
2542 static int patch_simple_hdmi(struct hda_codec *codec,
2543 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2545 struct hdmi_spec *spec;
2546 struct hdmi_spec_per_cvt *per_cvt;
2547 struct hdmi_spec_per_pin *per_pin;
2549 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2554 hdmi_array_init(spec, 1);
2556 spec->multiout.num_dacs = 0; /* no analog */
2557 spec->multiout.max_channels = 2;
2558 spec->multiout.dig_out_nid = cvt_nid;
2561 per_pin = snd_array_new(&spec->pins);
2562 per_cvt = snd_array_new(&spec->cvts);
2563 if (!per_pin || !per_cvt) {
2564 simple_playback_free(codec);
2567 per_cvt->cvt_nid = cvt_nid;
2568 per_pin->pin_nid = pin_nid;
2569 spec->pcm_playback = simple_pcm_playback;
2571 codec->patch_ops = simple_hdmi_patch_ops;
2576 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2579 unsigned int chanmask;
2580 int chan = channels ? (channels - 1) : 1;
2599 /* Set the audio infoframe channel allocation and checksum fields. The
2600 * channel count is computed implicitly by the hardware. */
2601 snd_hda_codec_write(codec, 0x1, 0,
2602 Nv_VERB_SET_Channel_Allocation, chanmask);
2604 snd_hda_codec_write(codec, 0x1, 0,
2605 Nv_VERB_SET_Info_Frame_Checksum,
2606 (0x71 - chan - chanmask));
2609 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2610 struct hda_codec *codec,
2611 struct snd_pcm_substream *substream)
2613 struct hdmi_spec *spec = codec->spec;
2616 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2617 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2618 for (i = 0; i < 4; i++) {
2619 /* set the stream id */
2620 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2621 AC_VERB_SET_CHANNEL_STREAMID, 0);
2622 /* set the stream format */
2623 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2624 AC_VERB_SET_STREAM_FORMAT, 0);
2627 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2628 * streams are disabled. */
2629 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2631 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2634 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2635 struct hda_codec *codec,
2636 unsigned int stream_tag,
2637 unsigned int format,
2638 struct snd_pcm_substream *substream)
2641 unsigned int dataDCC2, channel_id;
2643 struct hdmi_spec *spec = codec->spec;
2644 struct hda_spdif_out *spdif;
2645 struct hdmi_spec_per_cvt *per_cvt;
2647 mutex_lock(&codec->spdif_mutex);
2648 per_cvt = get_cvt(spec, 0);
2649 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2651 chs = substream->runtime->channels;
2655 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2656 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2657 snd_hda_codec_write(codec,
2658 nvhdmi_master_con_nid_7x,
2660 AC_VERB_SET_DIGI_CONVERT_1,
2661 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2663 /* set the stream id */
2664 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2665 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2667 /* set the stream format */
2668 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2669 AC_VERB_SET_STREAM_FORMAT, format);
2671 /* turn on again (if needed) */
2672 /* enable and set the channel status audio/data flag */
2673 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2674 snd_hda_codec_write(codec,
2675 nvhdmi_master_con_nid_7x,
2677 AC_VERB_SET_DIGI_CONVERT_1,
2678 spdif->ctls & 0xff);
2679 snd_hda_codec_write(codec,
2680 nvhdmi_master_con_nid_7x,
2682 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2685 for (i = 0; i < 4; i++) {
2691 /* turn off SPDIF once;
2692 *otherwise the IEC958 bits won't be updated
2694 if (codec->spdif_status_reset &&
2695 (spdif->ctls & AC_DIG1_ENABLE))
2696 snd_hda_codec_write(codec,
2697 nvhdmi_con_nids_7x[i],
2699 AC_VERB_SET_DIGI_CONVERT_1,
2700 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2701 /* set the stream id */
2702 snd_hda_codec_write(codec,
2703 nvhdmi_con_nids_7x[i],
2705 AC_VERB_SET_CHANNEL_STREAMID,
2706 (stream_tag << 4) | channel_id);
2707 /* set the stream format */
2708 snd_hda_codec_write(codec,
2709 nvhdmi_con_nids_7x[i],
2711 AC_VERB_SET_STREAM_FORMAT,
2713 /* turn on again (if needed) */
2714 /* enable and set the channel status audio/data flag */
2715 if (codec->spdif_status_reset &&
2716 (spdif->ctls & AC_DIG1_ENABLE)) {
2717 snd_hda_codec_write(codec,
2718 nvhdmi_con_nids_7x[i],
2720 AC_VERB_SET_DIGI_CONVERT_1,
2721 spdif->ctls & 0xff);
2722 snd_hda_codec_write(codec,
2723 nvhdmi_con_nids_7x[i],
2725 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2729 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2731 mutex_unlock(&codec->spdif_mutex);
2735 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2739 .nid = nvhdmi_master_con_nid_7x,
2740 .rates = SUPPORTED_RATES,
2741 .maxbps = SUPPORTED_MAXBPS,
2742 .formats = SUPPORTED_FORMATS,
2744 .open = simple_playback_pcm_open,
2745 .close = nvhdmi_8ch_7x_pcm_close,
2746 .prepare = nvhdmi_8ch_7x_pcm_prepare
2750 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2752 struct hdmi_spec *spec;
2753 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2754 nvhdmi_master_pin_nid_7x);
2758 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2759 /* override the PCM rates, etc, as the codec doesn't give full list */
2761 spec->pcm_playback.rates = SUPPORTED_RATES;
2762 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2763 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2767 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2769 struct hdmi_spec *spec = codec->spec;
2770 int err = simple_playback_build_pcms(codec);
2772 struct hda_pcm *info = get_pcm_rec(spec, 0);
2773 info->own_chmap = true;
2778 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2780 struct hdmi_spec *spec = codec->spec;
2781 struct hda_pcm *info;
2782 struct snd_pcm_chmap *chmap;
2785 err = simple_playback_build_controls(codec);
2789 /* add channel maps */
2790 info = get_pcm_rec(spec, 0);
2791 err = snd_pcm_add_chmap_ctls(info->pcm,
2792 SNDRV_PCM_STREAM_PLAYBACK,
2793 snd_pcm_alt_chmaps, 8, 0, &chmap);
2796 switch (codec->preset->vendor_id) {
2801 chmap->channel_mask = (1U << 2) | (1U << 8);
2804 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2809 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2811 struct hdmi_spec *spec;
2812 int err = patch_nvhdmi_2ch(codec);
2816 spec->multiout.max_channels = 8;
2817 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2818 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2819 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2820 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2822 /* Initialize the audio infoframe channel mask and checksum to something
2824 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2830 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2834 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
2835 struct hdac_cea_channel_speaker_allocation *cap, int channels)
2837 if (cap->ca_index == 0x00 && channels == 2)
2838 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2840 /* If the speaker allocation matches the channel count, it is OK. */
2841 if (cap->channels != channels)
2844 /* all channels are remappable freely */
2845 return SNDRV_CTL_TLVT_CHMAP_VAR;
2848 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
2849 int ca, int chs, unsigned char *map)
2851 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2857 static int patch_nvhdmi(struct hda_codec *codec)
2859 struct hdmi_spec *spec;
2862 err = patch_generic_hdmi(codec);
2867 spec->dyn_pin_out = true;
2869 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
2870 nvhdmi_chmap_cea_alloc_validate_get_type;
2871 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
2877 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2878 * accessed using vendor-defined verbs. These registers can be used for
2879 * interoperability between the HDA and HDMI drivers.
2882 /* Audio Function Group node */
2883 #define NVIDIA_AFG_NID 0x01
2886 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2887 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
2888 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
2889 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
2890 * additional bit (at position 30) to signal the validity of the format.
2892 * | 31 | 30 | 29 16 | 15 0 |
2893 * +---------+-------+--------+--------+
2894 * | TRIGGER | VALID | UNUSED | FORMAT |
2895 * +-----------------------------------|
2897 * Note that for the trigger bit to take effect it needs to change value
2898 * (i.e. it needs to be toggled).
2900 #define NVIDIA_GET_SCRATCH0 0xfa6
2901 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
2902 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
2903 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
2904 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
2905 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
2906 #define NVIDIA_SCRATCH_VALID (1 << 6)
2908 #define NVIDIA_GET_SCRATCH1 0xfab
2909 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
2910 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
2911 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
2912 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
2915 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
2916 * the format is invalidated so that the HDMI codec can be disabled.
2918 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
2922 /* bits [31:30] contain the trigger and valid bits */
2923 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
2924 NVIDIA_GET_SCRATCH0, 0);
2925 value = (value >> 24) & 0xff;
2927 /* bits [15:0] are used to store the HDA format */
2928 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2929 NVIDIA_SET_SCRATCH0_BYTE0,
2930 (format >> 0) & 0xff);
2931 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2932 NVIDIA_SET_SCRATCH0_BYTE1,
2933 (format >> 8) & 0xff);
2935 /* bits [16:24] are unused */
2936 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2937 NVIDIA_SET_SCRATCH0_BYTE2, 0);
2940 * Bit 30 signals that the data is valid and hence that HDMI audio can
2944 value &= ~NVIDIA_SCRATCH_VALID;
2946 value |= NVIDIA_SCRATCH_VALID;
2949 * Whenever the trigger bit is toggled, an interrupt is raised in the
2950 * HDMI codec. The HDMI driver will use that as trigger to update its
2953 value ^= NVIDIA_SCRATCH_TRIGGER;
2955 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2956 NVIDIA_SET_SCRATCH0_BYTE3, value);
2959 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
2960 struct hda_codec *codec,
2961 unsigned int stream_tag,
2962 unsigned int format,
2963 struct snd_pcm_substream *substream)
2967 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
2972 /* notify the HDMI codec of the format change */
2973 tegra_hdmi_set_format(codec, format);
2978 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
2979 struct hda_codec *codec,
2980 struct snd_pcm_substream *substream)
2982 /* invalidate the format in the HDMI codec */
2983 tegra_hdmi_set_format(codec, 0);
2985 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
2988 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
2990 struct hdmi_spec *spec = codec->spec;
2993 for (i = 0; i < spec->num_pins; i++) {
2994 struct hda_pcm *pcm = get_pcm_rec(spec, i);
2996 if (pcm->pcm_type == type)
3003 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3005 struct hda_pcm_stream *stream;
3006 struct hda_pcm *pcm;
3009 err = generic_hdmi_build_pcms(codec);
3013 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3018 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3019 * codec about format changes.
3021 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3022 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3023 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3028 static int patch_tegra_hdmi(struct hda_codec *codec)
3032 err = patch_generic_hdmi(codec);
3036 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3042 * ATI/AMD-specific implementations
3045 #define is_amdhdmi_rev3_or_later(codec) \
3046 ((codec)->core.vendor_id == 0x1002aa01 && \
3047 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3048 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3050 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3051 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3052 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3053 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3054 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3055 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3056 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3057 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3058 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3059 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3060 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3061 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3062 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3063 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3064 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3065 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3066 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3067 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3068 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3069 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3070 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3071 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3072 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3073 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3074 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3076 /* AMD specific HDA cvt verbs */
3077 #define ATI_VERB_SET_RAMP_RATE 0x770
3078 #define ATI_VERB_GET_RAMP_RATE 0xf70
3080 #define ATI_OUT_ENABLE 0x1
3082 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3083 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3085 #define ATI_HBR_CAPABLE 0x01
3086 #define ATI_HBR_ENABLE 0x10
3088 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3089 unsigned char *buf, int *eld_size)
3091 /* call hda_eld.c ATI/AMD-specific function */
3092 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3093 is_amdhdmi_rev3_or_later(codec));
3096 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3097 int active_channels, int conn_type)
3099 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3102 static int atihdmi_paired_swap_fc_lfe(int pos)
3105 * ATI/AMD have automatic FC/LFE swap built-in
3106 * when in pairwise mapping mode.
3110 /* see channel_allocations[].speakers[] */
3119 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3120 int ca, int chs, unsigned char *map)
3122 struct hdac_cea_channel_speaker_allocation *cap;
3125 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3127 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3128 for (i = 0; i < chs; ++i) {
3129 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3131 bool companion_ok = false;
3136 for (j = 0 + i % 2; j < 8; j += 2) {
3137 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3138 if (cap->speakers[chan_idx] == mask) {
3139 /* channel is in a supported position */
3142 if (i % 2 == 0 && i + 1 < chs) {
3143 /* even channel, check the odd companion */
3144 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3145 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3146 int comp_mask_act = cap->speakers[comp_chan_idx];
3148 if (comp_mask_req == comp_mask_act)
3149 companion_ok = true;
3161 i++; /* companion channel already checked */
3167 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3168 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3170 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3172 int ati_channel_setup = 0;
3177 if (!has_amd_full_remap_support(codec)) {
3178 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3180 /* In case this is an odd slot but without stream channel, do not
3181 * disable the slot since the corresponding even slot could have a
3182 * channel. In case neither have a channel, the slot pair will be
3183 * disabled when this function is called for the even slot. */
3184 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3187 hdmi_slot -= hdmi_slot % 2;
3189 if (stream_channel != 0xf)
3190 stream_channel -= stream_channel % 2;
3193 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3195 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3197 if (stream_channel != 0xf)
3198 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3200 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3203 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3204 hda_nid_t pin_nid, int asp_slot)
3206 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3207 bool was_odd = false;
3208 int ati_asp_slot = asp_slot;
3210 int ati_channel_setup;
3215 if (!has_amd_full_remap_support(codec)) {
3216 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3217 if (ati_asp_slot % 2 != 0) {
3223 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3225 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3227 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3230 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3233 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3234 struct hdac_chmap *chmap,
3235 struct hdac_cea_channel_speaker_allocation *cap,
3241 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3242 * we need to take that into account (a single channel may take 2
3243 * channel slots if we need to carry a silent channel next to it).
3244 * On Rev3+ AMD codecs this function is not used.
3248 /* We only produce even-numbered channel count TLVs */
3249 if ((channels % 2) != 0)
3252 for (c = 0; c < 7; c += 2) {
3253 if (cap->speakers[c] || cap->speakers[c+1])
3257 if (chanpairs * 2 != channels)
3260 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3263 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3264 struct hdac_cea_channel_speaker_allocation *cap,
3265 unsigned int *chmap, int channels)
3267 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3271 for (c = 7; c >= 0; c--) {
3272 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3273 int spk = cap->speakers[chan];
3275 /* add N/A channel if the companion channel is occupied */
3276 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3277 chmap[count++] = SNDRV_CHMAP_NA;
3282 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3285 WARN_ON(count != channels);
3288 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3291 int hbr_ctl, hbr_ctl_new;
3293 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3294 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3296 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3298 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3301 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3303 hbr_ctl == hbr_ctl_new ? "" : "new-",
3306 if (hbr_ctl != hbr_ctl_new)
3307 snd_hda_codec_write(codec, pin_nid, 0,
3308 ATI_VERB_SET_HBR_CONTROL,
3317 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3318 hda_nid_t pin_nid, u32 stream_tag, int format)
3321 if (is_amdhdmi_rev3_or_later(codec)) {
3322 int ramp_rate = 180; /* default as per AMD spec */
3323 /* disable ramp-up/down for non-pcm as per AMD spec */
3324 if (format & AC_FMT_TYPE_NON_PCM)
3327 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3330 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3334 static int atihdmi_init(struct hda_codec *codec)
3336 struct hdmi_spec *spec = codec->spec;
3339 err = generic_hdmi_init(codec);
3344 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3345 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3347 /* make sure downmix information in infoframe is zero */
3348 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3350 /* enable channel-wise remap mode if supported */
3351 if (has_amd_full_remap_support(codec))
3352 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3353 ATI_VERB_SET_MULTICHANNEL_MODE,
3354 ATI_MULTICHANNEL_MODE_SINGLE);
3360 static int patch_atihdmi(struct hda_codec *codec)
3362 struct hdmi_spec *spec;
3363 struct hdmi_spec_per_cvt *per_cvt;
3366 err = patch_generic_hdmi(codec);
3371 codec->patch_ops.init = atihdmi_init;
3375 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3376 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3377 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3378 spec->ops.setup_stream = atihdmi_setup_stream;
3380 if (!has_amd_full_remap_support(codec)) {
3381 /* override to ATI/AMD-specific versions with pairwise mapping */
3382 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3383 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3384 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3385 atihdmi_paired_cea_alloc_to_tlv_chmap;
3386 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3387 spec->chmap.ops.pin_get_slot_channel =
3388 atihdmi_pin_get_slot_channel;
3389 spec->chmap.ops.pin_set_slot_channel =
3390 atihdmi_pin_set_slot_channel;
3393 /* ATI/AMD converters do not advertise all of their capabilities */
3394 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3395 per_cvt = get_cvt(spec, cvt_idx);
3396 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3397 per_cvt->rates |= SUPPORTED_RATES;
3398 per_cvt->formats |= SUPPORTED_FORMATS;
3399 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3402 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3407 /* VIA HDMI Implementation */
3408 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3409 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3411 static int patch_via_hdmi(struct hda_codec *codec)
3413 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3419 static const struct hda_device_id snd_hda_id_hdmi[] = {
3420 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3421 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3422 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3423 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3424 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3425 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3426 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3427 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3428 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3429 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3430 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3431 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3432 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3433 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3434 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3435 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3436 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3437 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3438 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3439 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3440 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3441 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3442 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3443 /* 17 is known to be absent */
3444 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3445 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3446 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3447 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3448 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3449 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3450 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3451 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3452 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3453 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3454 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3455 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3456 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3457 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3458 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3459 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3460 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3461 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3462 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3463 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3464 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3465 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3466 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3467 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3468 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3469 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3470 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3471 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3472 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
3473 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3474 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3475 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3476 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
3477 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3478 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3479 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
3480 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
3481 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
3482 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
3483 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_generic_hdmi),
3484 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3485 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3486 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
3487 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3488 /* special ID for generic HDMI */
3489 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3492 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3494 MODULE_LICENSE("GPL");
3495 MODULE_DESCRIPTION("HDMI HD-audio codec");
3496 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3497 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3498 MODULE_ALIAS("snd-hda-codec-atihdmi");
3500 static struct hda_codec_driver hdmi_driver = {
3501 .id = snd_hda_id_hdmi,
3504 module_hda_codec_driver(hdmi_driver);