sound/soc/codecs/pcm512x.c

   1 /*
   2  * Driver for the PCM512x CODECs
   3  *
   4  * Author:      Mark Brown <broonie@linaro.org>
   5  *              Copyright 2014 Linaro Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  */
  16
  17
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/clk.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regmap.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/gcd.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/tlv.h>
  29
  30 #include "pcm512x.h"
  31
  32 #define DIV_ROUND_DOWN_ULL(ll, d) \
  33         ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
  34 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
  35         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  36
  37 #define PCM512x_NUM_SUPPLIES 3
  38 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = {
  39         "AVDD",
  40         "DVDD",
  41         "CPVDD",
  42 };
  43
  44 struct pcm512x_priv {
  45         struct regmap *regmap;
  46         struct clk *sclk;
  47         struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
  48         struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
  49         int fmt;
  50         int pll_in;
  51         int pll_out;
  52         int pll_r;
  53         int pll_j;
  54         int pll_d;
  55         int pll_p;
  56         unsigned long real_pll;
  57 };
  58
  59 /*
  60  * We can't use the same notifier block for more than one supply and
  61  * there's no way I can see to get from a callback to the caller
  62  * except container_of().
  63  */
  64 #define PCM512x_REGULATOR_EVENT(n) \
  65 static int pcm512x_regulator_event_##n(struct notifier_block *nb, \
  66                                       unsigned long event, void *data)    \
  67 { \
  68         struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \
  69                                                     supply_nb[n]); \
  70         if (event & REGULATOR_EVENT_DISABLE) { \
  71                 regcache_mark_dirty(pcm512x->regmap);   \
  72                 regcache_cache_only(pcm512x->regmap, true);     \
  73         } \
  74         return 0; \
  75 }
  76
  77 PCM512x_REGULATOR_EVENT(0)
  78 PCM512x_REGULATOR_EVENT(1)
  79 PCM512x_REGULATOR_EVENT(2)
  80
  81 static const struct reg_default pcm512x_reg_defaults[] = {
  82         { PCM512x_RESET,             0x00 },
  83         { PCM512x_POWER,             0x00 },
  84         { PCM512x_MUTE,              0x00 },
  85         { PCM512x_DSP,               0x00 },
  86         { PCM512x_PLL_REF,           0x00 },
  87         { PCM512x_DAC_REF,           0x00 },
  88         { PCM512x_DAC_ROUTING,       0x11 },
  89         { PCM512x_DSP_PROGRAM,       0x01 },
  90         { PCM512x_CLKDET,            0x00 },
  91         { PCM512x_AUTO_MUTE,         0x00 },
  92         { PCM512x_ERROR_DETECT,      0x00 },
  93         { PCM512x_DIGITAL_VOLUME_1,  0x00 },
  94         { PCM512x_DIGITAL_VOLUME_2,  0x30 },
  95         { PCM512x_DIGITAL_VOLUME_3,  0x30 },
  96         { PCM512x_DIGITAL_MUTE_1,    0x22 },
  97         { PCM512x_DIGITAL_MUTE_2,    0x00 },
  98         { PCM512x_DIGITAL_MUTE_3,    0x07 },
  99         { PCM512x_OUTPUT_AMPLITUDE,  0x00 },
 100         { PCM512x_ANALOG_GAIN_CTRL,  0x00 },
 101         { PCM512x_UNDERVOLTAGE_PROT, 0x00 },
 102         { PCM512x_ANALOG_MUTE_CTRL,  0x00 },
 103         { PCM512x_ANALOG_GAIN_BOOST, 0x00 },
 104         { PCM512x_VCOM_CTRL_1,       0x00 },
 105         { PCM512x_VCOM_CTRL_2,       0x01 },
 106         { PCM512x_BCLK_LRCLK_CFG,    0x00 },
 107         { PCM512x_MASTER_MODE,       0x7c },
 108         { PCM512x_GPIO_DACIN,        0x00 },
 109         { PCM512x_GPIO_PLLIN,        0x00 },
 110         { PCM512x_SYNCHRONIZE,       0x10 },
 111         { PCM512x_PLL_COEFF_0,       0x00 },
 112         { PCM512x_PLL_COEFF_1,       0x00 },
 113         { PCM512x_PLL_COEFF_2,       0x00 },
 114         { PCM512x_PLL_COEFF_3,       0x00 },
 115         { PCM512x_PLL_COEFF_4,       0x00 },
 116         { PCM512x_DSP_CLKDIV,        0x00 },
 117         { PCM512x_DAC_CLKDIV,        0x00 },
 118         { PCM512x_NCP_CLKDIV,        0x00 },
 119         { PCM512x_OSR_CLKDIV,        0x00 },
 120         { PCM512x_MASTER_CLKDIV_1,   0x00 },
 121         { PCM512x_MASTER_CLKDIV_2,   0x00 },
 122         { PCM512x_FS_SPEED_MODE,     0x00 },
 123         { PCM512x_IDAC_1,            0x01 },
 124         { PCM512x_IDAC_2,            0x00 },
 125 };
 126
 127 static bool pcm512x_readable(struct device *dev, unsigned int reg)
 128 {
 129         switch (reg) {
 130         case PCM512x_RESET:
 131         case PCM512x_POWER:
 132         case PCM512x_MUTE:
 133         case PCM512x_PLL_EN:
 134         case PCM512x_SPI_MISO_FUNCTION:
 135         case PCM512x_DSP:
 136         case PCM512x_GPIO_EN:
 137         case PCM512x_BCLK_LRCLK_CFG:
 138         case PCM512x_DSP_GPIO_INPUT:
 139         case PCM512x_MASTER_MODE:
 140         case PCM512x_PLL_REF:
 141         case PCM512x_DAC_REF:
 142         case PCM512x_GPIO_DACIN:
 143         case PCM512x_GPIO_PLLIN:
 144         case PCM512x_SYNCHRONIZE:
 145         case PCM512x_PLL_COEFF_0:
 146         case PCM512x_PLL_COEFF_1:
 147         case PCM512x_PLL_COEFF_2:
 148         case PCM512x_PLL_COEFF_3:
 149         case PCM512x_PLL_COEFF_4:
 150         case PCM512x_DSP_CLKDIV:
 151         case PCM512x_DAC_CLKDIV:
 152         case PCM512x_NCP_CLKDIV:
 153         case PCM512x_OSR_CLKDIV:
 154         case PCM512x_MASTER_CLKDIV_1:
 155         case PCM512x_MASTER_CLKDIV_2:
 156         case PCM512x_FS_SPEED_MODE:
 157         case PCM512x_IDAC_1:
 158         case PCM512x_IDAC_2:
 159         case PCM512x_ERROR_DETECT:
 160         case PCM512x_I2S_1:
 161         case PCM512x_I2S_2:
 162         case PCM512x_DAC_ROUTING:
 163         case PCM512x_DSP_PROGRAM:
 164         case PCM512x_CLKDET:
 165         case PCM512x_AUTO_MUTE:
 166         case PCM512x_DIGITAL_VOLUME_1:
 167         case PCM512x_DIGITAL_VOLUME_2:
 168         case PCM512x_DIGITAL_VOLUME_3:
 169         case PCM512x_DIGITAL_MUTE_1:
 170         case PCM512x_DIGITAL_MUTE_2:
 171         case PCM512x_DIGITAL_MUTE_3:
 172         case PCM512x_GPIO_OUTPUT_1:
 173         case PCM512x_GPIO_OUTPUT_2:
 174         case PCM512x_GPIO_OUTPUT_3:
 175         case PCM512x_GPIO_OUTPUT_4:
 176         case PCM512x_GPIO_OUTPUT_5:
 177         case PCM512x_GPIO_OUTPUT_6:
 178         case PCM512x_GPIO_CONTROL_1:
 179         case PCM512x_GPIO_CONTROL_2:
 180         case PCM512x_OVERFLOW:
 181         case PCM512x_RATE_DET_1:
 182         case PCM512x_RATE_DET_2:
 183         case PCM512x_RATE_DET_3:
 184         case PCM512x_RATE_DET_4:
 185         case PCM512x_CLOCK_STATUS:
 186         case PCM512x_ANALOG_MUTE_DET:
 187         case PCM512x_GPIN:
 188         case PCM512x_DIGITAL_MUTE_DET:
 189         case PCM512x_OUTPUT_AMPLITUDE:
 190         case PCM512x_ANALOG_GAIN_CTRL:
 191         case PCM512x_UNDERVOLTAGE_PROT:
 192         case PCM512x_ANALOG_MUTE_CTRL:
 193         case PCM512x_ANALOG_GAIN_BOOST:
 194         case PCM512x_VCOM_CTRL_1:
 195         case PCM512x_VCOM_CTRL_2:
 196         case PCM512x_CRAM_CTRL:
 197         case PCM512x_FLEX_A:
 198         case PCM512x_FLEX_B:
 199                 return true;
 200         default:
 201                 /* There are 256 raw register addresses */
 202                 return reg < 0xff;
 203         }
 204 }
 205
 206 static bool pcm512x_volatile(struct device *dev, unsigned int reg)
 207 {
 208         switch (reg) {
 209         case PCM512x_PLL_EN:
 210         case PCM512x_OVERFLOW:
 211         case PCM512x_RATE_DET_1:
 212         case PCM512x_RATE_DET_2:
 213         case PCM512x_RATE_DET_3:
 214         case PCM512x_RATE_DET_4:
 215         case PCM512x_CLOCK_STATUS:
 216         case PCM512x_ANALOG_MUTE_DET:
 217         case PCM512x_GPIN:
 218         case PCM512x_DIGITAL_MUTE_DET:
 219         case PCM512x_CRAM_CTRL:
 220                 return true;
 221         default:
 222                 /* There are 256 raw register addresses */
 223                 return reg < 0xff;
 224         }
 225 }
 226
 227 static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1);
 228 static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0);
 229 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0);
 230
 231 static const char * const pcm512x_dsp_program_texts[] = {
 232         "FIR interpolation with de-emphasis",
 233         "Low latency IIR with de-emphasis",
 234         "Fixed process flow",
 235         "High attenuation with de-emphasis",
 236         "Ringing-less low latency FIR",
 237 };
 238
 239 static const unsigned int pcm512x_dsp_program_values[] = {
 240         1,
 241         2,
 242         3,
 243         5,
 244         7,
 245 };
 246
 247 static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program,
 248                                   PCM512x_DSP_PROGRAM, 0, 0x1f,
 249                                   pcm512x_dsp_program_texts,
 250                                   pcm512x_dsp_program_values);
 251
 252 static const char * const pcm512x_clk_missing_text[] = {
 253         "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s"
 254 };
 255
 256 static const struct soc_enum pcm512x_clk_missing =
 257         SOC_ENUM_SINGLE(PCM512x_CLKDET, 0,  8, pcm512x_clk_missing_text);
 258
 259 static const char * const pcm512x_autom_text[] = {
 260         "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s"
 261 };
 262
 263 static const struct soc_enum pcm512x_autom_l =
 264         SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8,
 265                         pcm512x_autom_text);
 266
 267 static const struct soc_enum pcm512x_autom_r =
 268         SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8,
 269                         pcm512x_autom_text);
 270
 271 static const char * const pcm512x_ramp_rate_text[] = {
 272         "1 sample/update", "2 samples/update", "4 samples/update",
 273         "Immediate"
 274 };
 275
 276 static const struct soc_enum pcm512x_vndf =
 277         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4,
 278                         pcm512x_ramp_rate_text);
 279
 280 static const struct soc_enum pcm512x_vnuf =
 281         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4,
 282                         pcm512x_ramp_rate_text);
 283
 284 static const struct soc_enum pcm512x_vedf =
 285         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4,
 286                         pcm512x_ramp_rate_text);
 287
 288 static const char * const pcm512x_ramp_step_text[] = {
 289         "4dB/step", "2dB/step", "1dB/step", "0.5dB/step"
 290 };
 291
 292 static const struct soc_enum pcm512x_vnds =
 293         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4,
 294                         pcm512x_ramp_step_text);
 295
 296 static const struct soc_enum pcm512x_vnus =
 297         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4,
 298                         pcm512x_ramp_step_text);
 299
 300 static const struct soc_enum pcm512x_veds =
 301         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4,
 302                         pcm512x_ramp_step_text);
 303
 304 static const struct snd_kcontrol_new pcm512x_controls[] = {
 305 SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2,
 306                  PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv),
 307 SOC_DOUBLE_TLV("Playback Volume", PCM512x_ANALOG_GAIN_CTRL,
 308                PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv),
 309 SOC_DOUBLE_TLV("Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST,
 310                PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv),
 311 SOC_DOUBLE("Digital Playback Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT,
 312            PCM512x_RQMR_SHIFT, 1, 1),
 313
 314 SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
 315 SOC_ENUM("DSP Program", pcm512x_dsp_program),
 316
 317 SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
 318 SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
 319 SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r),
 320 SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3,
 321            PCM512x_ACTL_SHIFT, 1, 0),
 322 SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT,
 323            PCM512x_AMRE_SHIFT, 1, 0),
 324
 325 SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf),
 326 SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds),
 327 SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf),
 328 SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus),
 329 SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf),
 330 SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds),
 331 };
 332
 333 static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = {
 334 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
 335 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
 336
 337 SND_SOC_DAPM_OUTPUT("OUTL"),
 338 SND_SOC_DAPM_OUTPUT("OUTR"),
 339 };
 340
 341 static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
 342         { "DACL", NULL, "Playback" },
 343         { "DACR", NULL, "Playback" },
 344
 345         { "OUTL", NULL, "DACL" },
 346         { "OUTR", NULL, "DACR" },
 347 };
 348
 349 static const u32 pcm512x_dai_rates[] = {
 350         8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
 351         88200, 96000, 176400, 192000, 384000,
 352 };
 353
 354 static const struct snd_pcm_hw_constraint_list constraints_slave = {
 355         .count = ARRAY_SIZE(pcm512x_dai_rates),
 356         .list  = pcm512x_dai_rates,
 357 };
 358
 359 static const struct snd_interval pcm512x_dai_ranges_64bpf[] = {
 360         {
 361                 .min = 8000,
 362                 .max = 195312,
 363         }, {
 364                 .min = 250000,
 365                 .max = 390625,
 366         },
 367 };
 368
 369 static struct snd_pcm_hw_constraint_ranges constraints_64bpf = {
 370         .count  = ARRAY_SIZE(pcm512x_dai_ranges_64bpf),
 371         .ranges = pcm512x_dai_ranges_64bpf,
 372 };
 373
 374 static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params,
 375                                 struct snd_pcm_hw_rule *rule)
 376 {
 377         struct snd_pcm_hw_constraint_ranges *r = rule->private;
 378         int frame_size;
 379
 380         frame_size = snd_soc_params_to_frame_size(params);
 381         if (frame_size < 0)
 382                 return frame_size;
 383
 384         if (frame_size != 64)
 385                 return 0;
 386
 387         return snd_interval_ranges(hw_param_interval(params, rule->var),
 388                                    r->count, r->ranges, r->mask);
 389 }
 390
 391 static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
 392                                       struct snd_soc_dai *dai)
 393 {
 394         struct snd_soc_codec *codec = dai->codec;
 395         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 396         struct device *dev = dai->dev;
 397         struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
 398         struct snd_ratnum *rats_no_pll;
 399
 400         if (IS_ERR(pcm512x->sclk)) {
 401                 dev_err(dev, "Need SCLK for master mode: %ld\n",
 402                         PTR_ERR(pcm512x->sclk));
 403                 return PTR_ERR(pcm512x->sclk);
 404         }
 405
 406         if (pcm512x->pll_out)
 407                 return snd_pcm_hw_rule_add(substream->runtime, 0,
 408                                            SNDRV_PCM_HW_PARAM_RATE,
 409                                            pcm512x_hw_rule_rate,
 410                                            (void *)&constraints_64bpf,
 411                                            SNDRV_PCM_HW_PARAM_FRAME_BITS,
 412                                            SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 413
 414         constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
 415                                           GFP_KERNEL);
 416         if (!constraints_no_pll)
 417                 return -ENOMEM;
 418         constraints_no_pll->nrats = 1;
 419         rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
 420         if (!rats_no_pll)
 421                 return -ENOMEM;
 422         constraints_no_pll->rats = rats_no_pll;
 423         rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
 424         rats_no_pll->den_min = 1;
 425         rats_no_pll->den_max = 128;
 426         rats_no_pll->den_step = 1;
 427
 428         return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
 429                                              SNDRV_PCM_HW_PARAM_RATE,
 430                                              constraints_no_pll);
 431 }
 432
 433 static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
 434                                      struct snd_soc_dai *dai)
 435 {
 436         struct snd_soc_codec *codec = dai->codec;
 437         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 438         struct device *dev = dai->dev;
 439         struct regmap *regmap = pcm512x->regmap;
 440
 441         if (IS_ERR(pcm512x->sclk)) {
 442                 dev_info(dev, "No SCLK, using BCLK: %ld\n",
 443                          PTR_ERR(pcm512x->sclk));
 444
 445                 /* Disable reporting of missing SCLK as an error */
 446                 regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
 447                                    PCM512x_IDCH, PCM512x_IDCH);
 448
 449                 /* Switch PLL input to BCLK */
 450                 regmap_update_bits(regmap, PCM512x_PLL_REF,
 451                                    PCM512x_SREF, PCM512x_SREF_BCK);
 452         }
 453
 454         return snd_pcm_hw_constraint_list(substream->runtime, 0,
 455                                           SNDRV_PCM_HW_PARAM_RATE,
 456                                           &constraints_slave);
 457 }
 458
 459 static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
 460                                struct snd_soc_dai *dai)
 461 {
 462         struct snd_soc_codec *codec = dai->codec;
 463         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 464
 465         switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 466         case SND_SOC_DAIFMT_CBM_CFM:
 467         case SND_SOC_DAIFMT_CBM_CFS:
 468                 return pcm512x_dai_startup_master(substream, dai);
 469
 470         case SND_SOC_DAIFMT_CBS_CFS:
 471                 return pcm512x_dai_startup_slave(substream, dai);
 472
 473         default:
 474                 return -EINVAL;
 475         }
 476 }
 477
 478 static int pcm512x_set_bias_level(struct snd_soc_codec *codec,
 479                                   enum snd_soc_bias_level level)
 480 {
 481         struct pcm512x_priv *pcm512x = dev_get_drvdata(codec->dev);
 482         int ret;
 483
 484         switch (level) {
 485         case SND_SOC_BIAS_ON:
 486         case SND_SOC_BIAS_PREPARE:
 487                 break;
 488
 489         case SND_SOC_BIAS_STANDBY:
 490                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
 491                                          PCM512x_RQST, 0);
 492                 if (ret != 0) {
 493                         dev_err(codec->dev, "Failed to remove standby: %d\n",
 494                                 ret);
 495                         return ret;
 496                 }
 497                 break;
 498
 499         case SND_SOC_BIAS_OFF:
 500                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
 501                                          PCM512x_RQST, PCM512x_RQST);
 502                 if (ret != 0) {
 503                         dev_err(codec->dev, "Failed to request standby: %d\n",
 504                                 ret);
 505                         return ret;
 506                 }
 507                 break;
 508         }
 509
 510         codec->dapm.bias_level = level;
 511
 512         return 0;
 513 }
 514
 515 static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai,
 516                                       unsigned long bclk_rate)
 517 {
 518         struct device *dev = dai->dev;
 519         unsigned long sck_rate;
 520         int pow2;
 521
 522         /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */
 523         /* 16 MHz <= sck_rate <=  25 MHz, VREF mode */
 524
 525         /* select sck_rate as a multiple of bclk_rate but still with
 526          * as many factors of 2 as possible, as that makes it easier
 527          * to find a fast DAC rate
 528          */
 529         pow2 = 1 << fls((25000000 - 16000000) / bclk_rate);
 530         for (; pow2; pow2 >>= 1) {
 531                 sck_rate = rounddown(25000000, bclk_rate * pow2);
 532                 if (sck_rate >= 16000000)
 533                         break;
 534         }
 535         if (!pow2) {
 536                 dev_err(dev, "Impossible to generate a suitable SCK\n");
 537                 return 0;
 538         }
 539
 540         dev_dbg(dev, "sck_rate %lu\n", sck_rate);
 541         return sck_rate;
 542 }
 543
 544 /* pll_rate = pllin_rate * R * J.D / P
 545  * 1 <= R <= 16
 546  * 1 <= J <= 63
 547  * 0 <= D <= 9999
 548  * 1 <= P <= 15
 549  * 64 MHz <= pll_rate <= 100 MHz
 550  * if D == 0
 551  *     1 MHz <= pllin_rate / P <= 20 MHz
 552  * else if D > 0
 553  *     6.667 MHz <= pllin_rate / P <= 20 MHz
 554  *     4 <= J <= 11
 555  *     R = 1
 556  */
 557 static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai,
 558                                   unsigned long pllin_rate,
 559                                   unsigned long pll_rate)
 560 {
 561         struct device *dev = dai->dev;
 562         struct snd_soc_codec *codec = dai->codec;
 563         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 564         unsigned long common;
 565         int R, J, D, P;
 566         unsigned long K; /* 10000 * J.D */
 567         unsigned long num;
 568         unsigned long den;
 569
 570         common = gcd(pll_rate, pllin_rate);
 571         dev_dbg(dev, "pll %lu pllin %lu common %lu\n",
 572                 pll_rate, pllin_rate, common);
 573         num = pll_rate / common;
 574         den = pllin_rate / common;
 575
 576         /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */
 577         if (pllin_rate / den > 20000000 && num < 8) {
 578                 num *= 20000000 / (pllin_rate / den);
 579                 den *= 20000000 / (pllin_rate / den);
 580         }
 581         dev_dbg(dev, "num / den = %lu / %lu\n", num, den);
 582
 583         P = den;
 584         if (den <= 15 && num <= 16 * 63
 585             && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) {
 586                 /* Try the case with D = 0 */
 587                 D = 0;
 588                 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */
 589                 for (R = 16; R; R--) {
 590                         if (num % R)
 591                                 continue;
 592                         J = num / R;
 593                         if (J == 0 || J > 63)
 594                                 continue;
 595
 596                         dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P);
 597                         pcm512x->real_pll = pll_rate;
 598                         goto done;
 599                 }
 600                 /* no luck */
 601         }
 602
 603         R = 1;
 604
 605         if (num > 0xffffffffUL / 10000)
 606                 goto fallback;
 607
 608         /* Try to find an exact pll_rate using the D > 0 case */
 609         common = gcd(10000 * num, den);
 610         num = 10000 * num / common;
 611         den /= common;
 612         dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common);
 613
 614         for (P = den; P <= 15; P++) {
 615                 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P)
 616                         continue;
 617                 if (num * P % den)
 618                         continue;
 619                 K = num * P / den;
 620                 /* J == 12 is ok if D == 0 */
 621                 if (K < 40000 || K > 120000)
 622                         continue;
 623
 624                 J = K / 10000;
 625                 D = K % 10000;
 626                 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P);
 627                 pcm512x->real_pll = pll_rate;
 628                 goto done;
 629         }
 630
 631         /* Fall back to an approximate pll_rate */
 632
 633 fallback:
 634         /* find smallest possible P */
 635         P = DIV_ROUND_UP(pllin_rate, 20000000);
 636         if (!P)
 637                 P = 1;
 638         else if (P > 15) {
 639                 dev_err(dev, "Need a slower clock as pll-input\n");
 640                 return -EINVAL;
 641         }
 642         if (pllin_rate / P < 6667000) {
 643                 dev_err(dev, "Need a faster clock as pll-input\n");
 644                 return -EINVAL;
 645         }
 646         K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate);
 647         if (K < 40000)
 648                 K = 40000;
 649         /* J == 12 is ok if D == 0 */
 650         if (K > 120000)
 651                 K = 120000;
 652         J = K / 10000;
 653         D = K % 10000;
 654         dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P);
 655         pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P);
 656
 657 done:
 658         pcm512x->pll_r = R;
 659         pcm512x->pll_j = J;
 660         pcm512x->pll_d = D;
 661         pcm512x->pll_p = P;
 662         return 0;
 663 }
 664
 665 static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai,
 666                                             unsigned long osr_rate,
 667                                             unsigned long pllin_rate)
 668 {
 669         struct snd_soc_codec *codec = dai->codec;
 670         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 671         unsigned long dac_rate;
 672
 673         if (!pcm512x->pll_out)
 674                 return 0; /* no PLL to bypass, force SCK as DAC input */
 675
 676         if (pllin_rate % osr_rate)
 677                 return 0; /* futile, quit early */
 678
 679         /* run DAC no faster than 6144000 Hz */
 680         for (dac_rate = rounddown(6144000, osr_rate);
 681              dac_rate;
 682              dac_rate -= osr_rate) {
 683
 684                 if (pllin_rate / dac_rate > 128)
 685                         return 0; /* DAC divider would be too big */
 686
 687                 if (!(pllin_rate % dac_rate))
 688                         return dac_rate;
 689
 690                 dac_rate -= osr_rate;
 691         }
 692
 693         return 0;
 694 }
 695
 696 static int pcm512x_set_dividers(struct snd_soc_dai *dai,
 697                                 struct snd_pcm_hw_params *params)
 698 {
 699         struct device *dev = dai->dev;
 700         struct snd_soc_codec *codec = dai->codec;
 701         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 702         unsigned long pllin_rate = 0;
 703         unsigned long pll_rate;
 704         unsigned long sck_rate;
 705         unsigned long mck_rate;
 706         unsigned long bclk_rate;
 707         unsigned long sample_rate;
 708         unsigned long osr_rate;
 709         unsigned long dacsrc_rate;
 710         int bclk_div;
 711         int lrclk_div;
 712         int dsp_div;
 713         int dac_div;
 714         unsigned long dac_rate;
 715         int ncp_div;
 716         int osr_div;
 717         int ret;
 718         int idac;
 719         int fssp;
 720         int gpio;
 721
 722         lrclk_div = snd_soc_params_to_frame_size(params);
 723         if (lrclk_div == 0) {
 724                 dev_err(dev, "No LRCLK?\n");
 725                 return -EINVAL;
 726         }
 727
 728         if (!pcm512x->pll_out) {
 729                 sck_rate = clk_get_rate(pcm512x->sclk);
 730                 bclk_div = params->rate_den * 64 / lrclk_div;
 731                 bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div);
 732
 733                 mck_rate = sck_rate;
 734         } else {
 735                 ret = snd_soc_params_to_bclk(params);
 736                 if (ret < 0) {
 737                         dev_err(dev, "Failed to find suitable BCLK: %d\n", ret);
 738                         return ret;
 739                 }
 740                 if (ret == 0) {
 741                         dev_err(dev, "No BCLK?\n");
 742                         return -EINVAL;
 743                 }
 744                 bclk_rate = ret;
 745
 746                 pllin_rate = clk_get_rate(pcm512x->sclk);
 747
 748                 sck_rate = pcm512x_find_sck(dai, bclk_rate);
 749                 if (!sck_rate)
 750                         return -EINVAL;
 751                 pll_rate = 4 * sck_rate;
 752
 753                 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate);
 754                 if (ret != 0)
 755                         return ret;
 756
 757                 ret = regmap_write(pcm512x->regmap,
 758                                    PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1);
 759                 if (ret != 0) {
 760                         dev_err(dev, "Failed to write PLL P: %d\n", ret);
 761                         return ret;
 762                 }
 763
 764                 ret = regmap_write(pcm512x->regmap,
 765                                    PCM512x_PLL_COEFF_1, pcm512x->pll_j);
 766                 if (ret != 0) {
 767                         dev_err(dev, "Failed to write PLL J: %d\n", ret);
 768                         return ret;
 769                 }
 770
 771                 ret = regmap_write(pcm512x->regmap,
 772                                    PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8);
 773                 if (ret != 0) {
 774                         dev_err(dev, "Failed to write PLL D msb: %d\n", ret);
 775                         return ret;
 776                 }
 777
 778                 ret = regmap_write(pcm512x->regmap,
 779                                    PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff);
 780                 if (ret != 0) {
 781                         dev_err(dev, "Failed to write PLL D lsb: %d\n", ret);
 782                         return ret;
 783                 }
 784
 785                 ret = regmap_write(pcm512x->regmap,
 786                                    PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1);
 787                 if (ret != 0) {
 788                         dev_err(dev, "Failed to write PLL R: %d\n", ret);
 789                         return ret;
 790                 }
 791
 792                 mck_rate = pcm512x->real_pll;
 793
 794                 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
 795         }
 796
 797         if (bclk_div > 128) {
 798                 dev_err(dev, "Failed to find BCLK divider\n");
 799                 return -EINVAL;
 800         }
 801
 802         /* the actual rate */
 803         sample_rate = sck_rate / bclk_div / lrclk_div;
 804         osr_rate = 16 * sample_rate;
 805
 806         /* run DSP no faster than 50 MHz */
 807         dsp_div = mck_rate > 50000000 ? 2 : 1;
 808
 809         dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate);
 810         if (dac_rate) {
 811                 /* the desired clock rate is "compatible" with the pll input
 812                  * clock, so use that clock as dac input instead of the pll
 813                  * output clock since the pll will introduce jitter and thus
 814                  * noise.
 815                  */
 816                 dev_dbg(dev, "using pll input as dac input\n");
 817                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
 818                                          PCM512x_SDAC, PCM512x_SDAC_GPIO);
 819                 if (ret != 0) {
 820                         dev_err(codec->dev,
 821                                 "Failed to set gpio as dacref: %d\n", ret);
 822                         return ret;
 823                 }
 824
 825                 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
 826                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN,
 827                                          PCM512x_GREF, gpio);
 828                 if (ret != 0) {
 829                         dev_err(codec->dev,
 830                                 "Failed to set gpio %d as dacin: %d\n",
 831                                 pcm512x->pll_in, ret);
 832                         return ret;
 833                 }
 834
 835                 dacsrc_rate = pllin_rate;
 836         } else {
 837                 /* run DAC no faster than 6144000 Hz */
 838                 unsigned long dac_mul = 6144000 / osr_rate;
 839                 unsigned long sck_mul = sck_rate / osr_rate;
 840
 841                 for (; dac_mul; dac_mul--) {
 842                         if (!(sck_mul % dac_mul))
 843                                 break;
 844                 }
 845                 if (!dac_mul) {
 846                         dev_err(dev, "Failed to find DAC rate\n");
 847                         return -EINVAL;
 848                 }
 849
 850                 dac_rate = dac_mul * osr_rate;
 851                 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n",
 852                         dac_rate, sample_rate);
 853
 854                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
 855                                          PCM512x_SDAC, PCM512x_SDAC_SCK);
 856                 if (ret != 0) {
 857                         dev_err(codec->dev,
 858                                 "Failed to set sck as dacref: %d\n", ret);
 859                         return ret;
 860                 }
 861
 862                 dacsrc_rate = sck_rate;
 863         }
 864
 865         dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate);
 866         if (dac_div > 128) {
 867                 dev_err(dev, "Failed to find DAC divider\n");
 868                 return -EINVAL;
 869         }
 870
 871         ncp_div = DIV_ROUND_CLOSEST(dacsrc_rate / dac_div, 1536000);
 872         if (ncp_div > 128 || dacsrc_rate / dac_div / ncp_div > 2048000) {
 873                 /* run NCP no faster than 2048000 Hz, but why? */
 874                 ncp_div = DIV_ROUND_UP(dacsrc_rate / dac_div, 2048000);
 875                 if (ncp_div > 128) {
 876                         dev_err(dev, "Failed to find NCP divider\n");
 877                         return -EINVAL;
 878                 }
 879         }
 880
 881         osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
 882         if (osr_div > 128) {
 883                 dev_err(dev, "Failed to find OSR divider\n");
 884                 return -EINVAL;
 885         }
 886
 887         idac = mck_rate / (dsp_div * sample_rate);
 888
 889         ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
 890         if (ret != 0) {
 891                 dev_err(dev, "Failed to write DSP divider: %d\n", ret);
 892                 return ret;
 893         }
 894
 895         ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
 896         if (ret != 0) {
 897                 dev_err(dev, "Failed to write DAC divider: %d\n", ret);
 898                 return ret;
 899         }
 900
 901         ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
 902         if (ret != 0) {
 903                 dev_err(dev, "Failed to write NCP divider: %d\n", ret);
 904                 return ret;
 905         }
 906
 907         ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
 908         if (ret != 0) {
 909                 dev_err(dev, "Failed to write OSR divider: %d\n", ret);
 910                 return ret;
 911         }
 912
 913         ret = regmap_write(pcm512x->regmap,
 914                            PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
 915         if (ret != 0) {
 916                 dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
 917                 return ret;
 918         }
 919
 920         ret = regmap_write(pcm512x->regmap,
 921                            PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
 922         if (ret != 0) {
 923                 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
 924                 return ret;
 925         }
 926
 927         ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
 928         if (ret != 0) {
 929                 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
 930                 return ret;
 931         }
 932
 933         ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
 934         if (ret != 0) {
 935                 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
 936                 return ret;
 937         }
 938
 939         if (sample_rate <= 48000)
 940                 fssp = PCM512x_FSSP_48KHZ;
 941         else if (sample_rate <= 96000)
 942                 fssp = PCM512x_FSSP_96KHZ;
 943         else if (sample_rate <= 192000)
 944                 fssp = PCM512x_FSSP_192KHZ;
 945         else
 946                 fssp = PCM512x_FSSP_384KHZ;
 947         ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
 948                                  PCM512x_FSSP, fssp);
 949         if (ret != 0) {
 950                 dev_err(codec->dev, "Failed to set fs speed: %d\n", ret);
 951                 return ret;
 952         }
 953
 954         dev_dbg(codec->dev, "DSP divider %d\n", dsp_div);
 955         dev_dbg(codec->dev, "DAC divider %d\n", dac_div);
 956         dev_dbg(codec->dev, "NCP divider %d\n", ncp_div);
 957         dev_dbg(codec->dev, "OSR divider %d\n", osr_div);
 958         dev_dbg(codec->dev, "BCK divider %d\n", bclk_div);
 959         dev_dbg(codec->dev, "LRCK divider %d\n", lrclk_div);
 960         dev_dbg(codec->dev, "IDAC %d\n", idac);
 961         dev_dbg(codec->dev, "1<<FSSP %d\n", 1 << fssp);
 962
 963         return 0;
 964 }
 965
 966 static int pcm512x_hw_params(struct snd_pcm_substream *substream,
 967                              struct snd_pcm_hw_params *params,
 968                              struct snd_soc_dai *dai)
 969 {
 970         struct snd_soc_codec *codec = dai->codec;
 971         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 972         int alen;
 973         int gpio;
 974         int clock_output;
 975         int master_mode;
 976         int ret;
 977
 978         dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n",
 979                 params_rate(params),
 980                 params_channels(params));
 981
 982         switch (snd_pcm_format_width(params_format(params))) {
 983         case 16:
 984                 alen = PCM512x_ALEN_16;
 985                 break;
 986         case 20:
 987                 alen = PCM512x_ALEN_20;
 988                 break;
 989         case 24:
 990                 alen = PCM512x_ALEN_24;
 991                 break;
 992         case 32:
 993                 alen = PCM512x_ALEN_32;
 994                 break;
 995         default:
 996                 dev_err(codec->dev, "Bad frame size: %d\n",
 997                         snd_pcm_format_width(params_format(params)));
 998                 return -EINVAL;
 999         }
1000
1001         switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1002         case SND_SOC_DAIFMT_CBS_CFS:
1003                 ret = regmap_update_bits(pcm512x->regmap,
1004                                          PCM512x_BCLK_LRCLK_CFG,
1005                                          PCM512x_BCKP
1006                                          | PCM512x_BCKO | PCM512x_LRKO,
1007                                          0);
1008                 if (ret != 0) {
1009                         dev_err(codec->dev,
1010                                 "Failed to enable slave mode: %d\n", ret);
1011                         return ret;
1012                 }
1013
1014                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1015                                          PCM512x_DCAS, 0);
1016                 if (ret != 0) {
1017                         dev_err(codec->dev,
1018                                 "Failed to enable clock divider autoset: %d\n",
1019                                 ret);
1020                         return ret;
1021                 }
1022                 return 0;
1023         case SND_SOC_DAIFMT_CBM_CFM:
1024                 clock_output = PCM512x_BCKO | PCM512x_LRKO;
1025                 master_mode = PCM512x_RLRK | PCM512x_RBCK;
1026                 break;
1027         case SND_SOC_DAIFMT_CBM_CFS:
1028                 clock_output = PCM512x_BCKO;
1029                 master_mode = PCM512x_RBCK;
1030                 break;
1031         default:
1032                 return -EINVAL;
1033         }
1034
1035         ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
1036                                  PCM512x_ALEN, alen);
1037         if (ret != 0) {
1038                 dev_err(codec->dev, "Failed to set frame size: %d\n", ret);
1039                 return ret;
1040         }
1041
1042         if (pcm512x->pll_out) {
1043                 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11);
1044                 if (ret != 0) {
1045                         dev_err(codec->dev, "Failed to set FLEX_A: %d\n", ret);
1046                         return ret;
1047                 }
1048
1049                 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff);
1050                 if (ret != 0) {
1051                         dev_err(codec->dev, "Failed to set FLEX_B: %d\n", ret);
1052                         return ret;
1053                 }
1054
1055                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1056                                          PCM512x_IDFS | PCM512x_IDBK
1057                                          | PCM512x_IDSK | PCM512x_IDCH
1058                                          | PCM512x_IDCM | PCM512x_DCAS
1059                                          | PCM512x_IPLK,
1060                                          PCM512x_IDFS | PCM512x_IDBK
1061                                          | PCM512x_IDSK | PCM512x_IDCH
1062                                          | PCM512x_DCAS);
1063                 if (ret != 0) {
1064                         dev_err(codec->dev,
1065                                 "Failed to ignore auto-clock failures: %d\n",
1066                                 ret);
1067                         return ret;
1068                 }
1069         } else {
1070                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1071                                          PCM512x_IDFS | PCM512x_IDBK
1072                                          | PCM512x_IDSK | PCM512x_IDCH
1073                                          | PCM512x_IDCM | PCM512x_DCAS
1074                                          | PCM512x_IPLK,
1075                                          PCM512x_IDFS | PCM512x_IDBK
1076                                          | PCM512x_IDSK | PCM512x_IDCH
1077                                          | PCM512x_DCAS | PCM512x_IPLK);
1078                 if (ret != 0) {
1079                         dev_err(codec->dev,
1080                                 "Failed to ignore auto-clock failures: %d\n",
1081                                 ret);
1082                         return ret;
1083                 }
1084
1085                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1086                                          PCM512x_PLLE, 0);
1087                 if (ret != 0) {
1088                         dev_err(codec->dev, "Failed to disable pll: %d\n", ret);
1089                         return ret;
1090                 }
1091         }
1092
1093         ret = pcm512x_set_dividers(dai, params);
1094         if (ret != 0)
1095                 return ret;
1096
1097         if (pcm512x->pll_out) {
1098                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF,
1099                                          PCM512x_SREF, PCM512x_SREF_GPIO);
1100                 if (ret != 0) {
1101                         dev_err(codec->dev,
1102                                 "Failed to set gpio as pllref: %d\n", ret);
1103                         return ret;
1104                 }
1105
1106                 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
1107                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN,
1108                                          PCM512x_GREF, gpio);
1109                 if (ret != 0) {
1110                         dev_err(codec->dev,
1111                                 "Failed to set gpio %d as pllin: %d\n",
1112                                 pcm512x->pll_in, ret);
1113                         return ret;
1114                 }
1115
1116                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1117                                          PCM512x_PLLE, PCM512x_PLLE);
1118                 if (ret != 0) {
1119                         dev_err(codec->dev, "Failed to enable pll: %d\n", ret);
1120                         return ret;
1121                 }
1122         }
1123
1124         ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
1125                                  PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
1126                                  clock_output);
1127         if (ret != 0) {
1128                 dev_err(codec->dev, "Failed to enable clock output: %d\n", ret);
1129                 return ret;
1130         }
1131
1132         ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
1133                                  PCM512x_RLRK | PCM512x_RBCK,
1134                                  master_mode);
1135         if (ret != 0) {
1136                 dev_err(codec->dev, "Failed to enable master mode: %d\n", ret);
1137                 return ret;
1138         }
1139
1140         if (pcm512x->pll_out) {
1141                 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1);
1142                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
1143                                          gpio, gpio);
1144                 if (ret != 0) {
1145                         dev_err(codec->dev, "Failed to enable gpio %d: %d\n",
1146                                 pcm512x->pll_out, ret);
1147                         return ret;
1148                 }
1149
1150                 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1;
1151                 ret = regmap_update_bits(pcm512x->regmap, gpio,
1152                                          PCM512x_GxSL, PCM512x_GxSL_PLLCK);
1153                 if (ret != 0) {
1154                         dev_err(codec->dev, "Failed to output pll on %d: %d\n",
1155                                 ret, pcm512x->pll_out);
1156                         return ret;
1157                 }
1158
1159                 gpio = PCM512x_G1OE << (4 - 1);
1160                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
1161                                          gpio, gpio);
1162                 if (ret != 0) {
1163                         dev_err(codec->dev, "Failed to enable gpio %d: %d\n",
1164                                 4, ret);
1165                         return ret;
1166                 }
1167
1168                 gpio = PCM512x_GPIO_OUTPUT_1 + 4 - 1;
1169                 ret = regmap_update_bits(pcm512x->regmap, gpio,
1170                                          PCM512x_GxSL, PCM512x_GxSL_PLLLK);
1171                 if (ret != 0) {
1172                         dev_err(codec->dev,
1173                                 "Failed to output pll lock on %d: %d\n",
1174                                 ret, 4);
1175                         return ret;
1176                 }
1177         }
1178
1179         ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1180                                  PCM512x_RQSY, PCM512x_RQSY_HALT);
1181         if (ret != 0) {
1182                 dev_err(codec->dev, "Failed to halt clocks: %d\n", ret);
1183                 return ret;
1184         }
1185
1186         ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1187                                  PCM512x_RQSY, PCM512x_RQSY_RESUME);
1188         if (ret != 0) {
1189                 dev_err(codec->dev, "Failed to resume clocks: %d\n", ret);
1190                 return ret;
1191         }
1192
1193         return 0;
1194 }
1195
1196 static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1197 {
1198         struct snd_soc_codec *codec = dai->codec;
1199         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
1200
1201         pcm512x->fmt = fmt;
1202
1203         return 0;
1204 }
1205
1206 static const struct snd_soc_dai_ops pcm512x_dai_ops = {
1207         .startup = pcm512x_dai_startup,
1208         .hw_params = pcm512x_hw_params,
1209         .set_fmt = pcm512x_set_fmt,
1210 };
1211
1212 static struct snd_soc_dai_driver pcm512x_dai = {
1213         .name = "pcm512x-hifi",
1214         .playback = {
1215                 .stream_name = "Playback",
1216                 .channels_min = 2,
1217                 .channels_max = 2,
1218                 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1219                 .rate_min = 8000,
1220                 .rate_max = 384000,
1221                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1222                            SNDRV_PCM_FMTBIT_S24_LE |
1223                            SNDRV_PCM_FMTBIT_S32_LE
1224         },
1225         .ops = &pcm512x_dai_ops,
1226 };
1227
1228 static struct snd_soc_codec_driver pcm512x_codec_driver = {
1229         .set_bias_level = pcm512x_set_bias_level,
1230         .idle_bias_off = true,
1231
1232         .controls = pcm512x_controls,
1233         .num_controls = ARRAY_SIZE(pcm512x_controls),
1234         .dapm_widgets = pcm512x_dapm_widgets,
1235         .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets),
1236         .dapm_routes = pcm512x_dapm_routes,
1237         .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes),
1238 };
1239
1240 static const struct regmap_range_cfg pcm512x_range = {
1241         .name = "Pages", .range_min = PCM512x_VIRT_BASE,
1242         .range_max = PCM512x_MAX_REGISTER,
1243         .selector_reg = PCM512x_PAGE,
1244         .selector_mask = 0xff,
1245         .window_start = 0, .window_len = 0x100,
1246 };
1247
1248 const struct regmap_config pcm512x_regmap = {
1249         .reg_bits = 8,
1250         .val_bits = 8,
1251
1252         .readable_reg = pcm512x_readable,
1253         .volatile_reg = pcm512x_volatile,
1254
1255         .ranges = &pcm512x_range,
1256         .num_ranges = 1,
1257
1258         .max_register = PCM512x_MAX_REGISTER,
1259         .reg_defaults = pcm512x_reg_defaults,
1260         .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults),
1261         .cache_type = REGCACHE_RBTREE,
1262 };
1263 EXPORT_SYMBOL_GPL(pcm512x_regmap);
1264
1265 int pcm512x_probe(struct device *dev, struct regmap *regmap)
1266 {
1267         struct pcm512x_priv *pcm512x;
1268         int i, ret;
1269
1270         pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL);
1271         if (!pcm512x)
1272                 return -ENOMEM;
1273
1274         dev_set_drvdata(dev, pcm512x);
1275         pcm512x->regmap = regmap;
1276
1277         for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++)
1278                 pcm512x->supplies[i].supply = pcm512x_supply_names[i];
1279
1280         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies),
1281                                       pcm512x->supplies);
1282         if (ret != 0) {
1283                 dev_err(dev, "Failed to get supplies: %d\n", ret);
1284                 return ret;
1285         }
1286
1287         pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0;
1288         pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1;
1289         pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2;
1290
1291         for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) {
1292                 ret = regulator_register_notifier(pcm512x->supplies[i].consumer,
1293                                                   &pcm512x->supply_nb[i]);
1294                 if (ret != 0) {
1295                         dev_err(dev,
1296                                 "Failed to register regulator notifier: %d\n",
1297                                 ret);
1298                 }
1299         }
1300
1301         ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1302                                     pcm512x->supplies);
1303         if (ret != 0) {
1304                 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1305                 return ret;
1306         }
1307
1308         /* Reset the device, verifying I/O in the process for I2C */
1309         ret = regmap_write(regmap, PCM512x_RESET,
1310                            PCM512x_RSTM | PCM512x_RSTR);
1311         if (ret != 0) {
1312                 dev_err(dev, "Failed to reset device: %d\n", ret);
1313                 goto err;
1314         }
1315
1316         ret = regmap_write(regmap, PCM512x_RESET, 0);
1317         if (ret != 0) {
1318                 dev_err(dev, "Failed to reset device: %d\n", ret);
1319                 goto err;
1320         }
1321
1322         pcm512x->sclk = devm_clk_get(dev, NULL);
1323         if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER)
1324                 return -EPROBE_DEFER;
1325         if (!IS_ERR(pcm512x->sclk)) {
1326                 ret = clk_prepare_enable(pcm512x->sclk);
1327                 if (ret != 0) {
1328                         dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1329                         return ret;
1330                 }
1331         }
1332
1333         /* Default to standby mode */
1334         ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1335                                  PCM512x_RQST, PCM512x_RQST);
1336         if (ret != 0) {
1337                 dev_err(dev, "Failed to request standby: %d\n",
1338                         ret);
1339                 goto err_clk;
1340         }
1341
1342         pm_runtime_set_active(dev);
1343         pm_runtime_enable(dev);
1344         pm_runtime_idle(dev);
1345
1346 #ifdef CONFIG_OF
1347         if (dev->of_node) {
1348                 const struct device_node *np = dev->of_node;
1349                 u32 val;
1350
1351                 if (of_property_read_u32(np, "pll-in", &val) >= 0) {
1352                         if (val > 6) {
1353                                 dev_err(dev, "Invalid pll-in\n");
1354                                 ret = -EINVAL;
1355                                 goto err_clk;
1356                         }
1357                         pcm512x->pll_in = val;
1358                 }
1359
1360                 if (of_property_read_u32(np, "pll-out", &val) >= 0) {
1361                         if (val > 6) {
1362                                 dev_err(dev, "Invalid pll-out\n");
1363                                 ret = -EINVAL;
1364                                 goto err_clk;
1365                         }
1366                         pcm512x->pll_out = val;
1367                 }
1368
1369                 if (!pcm512x->pll_in != !pcm512x->pll_out) {
1370                         dev_err(dev,
1371                                 "Error: both pll-in and pll-out, or none\n");
1372                         ret = -EINVAL;
1373                         goto err_clk;
1374                 }
1375                 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) {
1376                         dev_err(dev, "Error: pll-in == pll-out\n");
1377                         ret = -EINVAL;
1378                         goto err_clk;
1379                 }
1380         }
1381 #endif
1382
1383         ret = snd_soc_register_codec(dev, &pcm512x_codec_driver,
1384                                     &pcm512x_dai, 1);
1385         if (ret != 0) {
1386                 dev_err(dev, "Failed to register CODEC: %d\n", ret);
1387                 goto err_pm;
1388         }
1389
1390         return 0;
1391
1392 err_pm:
1393         pm_runtime_disable(dev);
1394 err_clk:
1395         if (!IS_ERR(pcm512x->sclk))
1396                 clk_disable_unprepare(pcm512x->sclk);
1397 err:
1398         regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1399                                      pcm512x->supplies);
1400         return ret;
1401 }
1402 EXPORT_SYMBOL_GPL(pcm512x_probe);
1403
1404 void pcm512x_remove(struct device *dev)
1405 {
1406         struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1407
1408         snd_soc_unregister_codec(dev);
1409         pm_runtime_disable(dev);
1410         if (!IS_ERR(pcm512x->sclk))
1411                 clk_disable_unprepare(pcm512x->sclk);
1412         regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1413                                pcm512x->supplies);
1414 }
1415 EXPORT_SYMBOL_GPL(pcm512x_remove);
1416
1417 #ifdef CONFIG_PM
1418 static int pcm512x_suspend(struct device *dev)
1419 {
1420         struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1421         int ret;
1422
1423         ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1424                                  PCM512x_RQPD, PCM512x_RQPD);
1425         if (ret != 0) {
1426                 dev_err(dev, "Failed to request power down: %d\n", ret);
1427                 return ret;
1428         }
1429
1430         ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1431                                      pcm512x->supplies);
1432         if (ret != 0) {
1433                 dev_err(dev, "Failed to disable supplies: %d\n", ret);
1434                 return ret;
1435         }
1436
1437         if (!IS_ERR(pcm512x->sclk))
1438                 clk_disable_unprepare(pcm512x->sclk);
1439
1440         return 0;
1441 }
1442
1443 static int pcm512x_resume(struct device *dev)
1444 {
1445         struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1446         int ret;
1447
1448         if (!IS_ERR(pcm512x->sclk)) {
1449                 ret = clk_prepare_enable(pcm512x->sclk);
1450                 if (ret != 0) {
1451                         dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1452                         return ret;
1453                 }
1454         }
1455
1456         ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1457                                     pcm512x->supplies);
1458         if (ret != 0) {
1459                 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1460                 return ret;
1461         }
1462
1463         regcache_cache_only(pcm512x->regmap, false);
1464         ret = regcache_sync(pcm512x->regmap);
1465         if (ret != 0) {
1466                 dev_err(dev, "Failed to sync cache: %d\n", ret);
1467                 return ret;
1468         }
1469
1470         ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1471                                  PCM512x_RQPD, 0);
1472         if (ret != 0) {
1473                 dev_err(dev, "Failed to remove power down: %d\n", ret);
1474                 return ret;
1475         }
1476
1477         return 0;
1478 }
1479 #endif
1480
1481 const struct dev_pm_ops pcm512x_pm_ops = {
1482         SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
1483 };
1484 EXPORT_SYMBOL_GPL(pcm512x_pm_ops);
1485
1486 MODULE_DESCRIPTION("ASoC PCM512x codec driver");
1487 MODULE_AUTHOR("Mark Brown <broonie@linaro.org>");
1488 MODULE_LICENSE("GPL v2");