2 * bxt-sst.c - DSP library functions for BXT platform
4 * Copyright (C) 2015-16 Intel Corp
5 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
6 * Jeeja KP <jeeja.kp@intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/firmware.h>
21 #include <linux/device.h>
23 #include "../common/sst-dsp.h"
24 #include "../common/sst-dsp-priv.h"
25 #include "skl-sst-ipc.h"
26 #include "skl-tplg-interface.h"
28 #define BXT_BASEFW_TIMEOUT 3000
29 #define BXT_INIT_TIMEOUT 500
30 #define BXT_IPC_PURGE_FW 0x01004000
32 #define BXT_ROM_INIT 0x5
33 #define BXT_ADSP_SRAM0_BASE 0x80000
35 /* Firmware status window */
36 #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE
37 #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4)
39 #define BXT_ADSP_SRAM1_BASE 0xA0000
41 #define BXT_INSTANCE_ID 0
42 #define BXT_BASE_FW_MODULE_ID 0
44 #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000
46 static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
48 return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
52 bxt_load_library(struct sst_dsp *ctx, struct skl_dfw_manifest *minfo)
54 struct snd_dma_buffer dmab;
55 struct skl_sst *skl = ctx->thread_context;
56 const struct firmware *fw = NULL;
57 struct firmware stripped_fw;
58 int ret = 0, i, dma_id, stream_tag;
60 /* library indices start from 1 to N. 0 represents base FW */
61 for (i = 1; i < minfo->lib_count; i++) {
62 ret = request_firmware(&fw, minfo->lib[i].name, ctx->dev);
64 dev_err(ctx->dev, "Request lib %s failed:%d\n",
65 minfo->lib[i].name, ret);
69 if (skl->is_first_boot) {
70 ret = snd_skl_parse_uuids(ctx, fw,
71 BXT_ADSP_FW_BIN_HDR_OFFSET, i);
73 goto load_library_failed;
76 stripped_fw.data = fw->data;
77 stripped_fw.size = fw->size;
78 skl_dsp_strip_extended_manifest(&stripped_fw);
80 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40,
81 stripped_fw.size, &dmab);
82 if (stream_tag <= 0) {
83 dev_err(ctx->dev, "Lib prepare DMA err: %x\n",
86 goto load_library_failed;
89 dma_id = stream_tag - 1;
90 memcpy(dmab.area, stripped_fw.data, stripped_fw.size);
92 ctx->dsp_ops.trigger(ctx->dev, true, stream_tag);
93 ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i);
95 dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n",
96 minfo->lib[i].name, ret);
98 ctx->dsp_ops.trigger(ctx->dev, false, stream_tag);
99 ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag);
100 release_firmware(fw);
107 release_firmware(fw);
112 * First boot sequence has some extra steps. Core 0 waits for power
113 * status on core 1, so power up core 1 also momentarily, keep it in
114 * reset/stall and then turn it off
116 static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
117 const void *fwdata, u32 fwsize)
119 int stream_tag, ret, i;
122 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
123 if (stream_tag <= 0) {
124 dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
129 ctx->dsp_ops.stream_tag = stream_tag;
130 memcpy(ctx->dmab.area, fwdata, fwsize);
132 /* Step 1: Power up core 0 and core1 */
133 ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK |
134 SKL_DSP_CORE_MASK(1));
136 dev_err(ctx->dev, "dsp core0/1 power up failed\n");
137 goto base_fw_load_failed;
140 /* Step 2: Purge FW request */
141 sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
142 (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));
144 /* Step 3: Unset core0 reset state & unstall/run core0 */
145 ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
147 dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
149 goto base_fw_load_failed;
152 /* Step 4: Wait for DONE Bit */
153 for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
154 reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE);
156 if (reg & SKL_ADSP_REG_HIPCIE_DONE) {
157 sst_dsp_shim_update_bits_forced(ctx,
159 SKL_ADSP_REG_HIPCIE_DONE,
160 SKL_ADSP_REG_HIPCIE_DONE);
166 dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg);
167 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE,
168 SKL_ADSP_REG_HIPCIE_DONE,
169 SKL_ADSP_REG_HIPCIE_DONE);
172 /* Step 5: power down core1 */
173 ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
175 dev_err(ctx->dev, "dsp core1 power down failed\n");
176 goto base_fw_load_failed;
179 /* Step 6: Enable Interrupt */
180 skl_ipc_int_enable(ctx);
181 skl_ipc_op_int_enable(ctx);
183 /* Step 7: Wait for ROM init */
184 for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
186 (sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) &
189 dev_info(ctx->dev, "ROM loaded, continue FW loading\n");
195 dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg);
197 goto base_fw_load_failed;
203 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
204 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
205 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
209 static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
213 ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
214 ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
215 BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
217 ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
218 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
223 static int bxt_load_base_firmware(struct sst_dsp *ctx)
225 struct firmware stripped_fw;
226 struct skl_sst *skl = ctx->thread_context;
229 ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
231 dev_err(ctx->dev, "Request firmware failed %d\n", ret);
232 goto sst_load_base_firmware_failed;
235 /* check for extended manifest */
237 goto sst_load_base_firmware_failed;
239 /* prase uuids on first boot */
240 if (skl->is_first_boot) {
241 ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0);
243 goto sst_load_base_firmware_failed;
246 stripped_fw.data = ctx->fw->data;
247 stripped_fw.size = ctx->fw->size;
248 skl_dsp_strip_extended_manifest(&stripped_fw);
250 ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
251 /* Retry Enabling core and ROM load. Retry seemed to help */
253 ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
255 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
256 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
257 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
259 dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
260 goto sst_load_base_firmware_failed;
264 ret = sst_transfer_fw_host_dma(ctx);
266 dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
267 dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
268 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
269 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
271 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
273 dev_dbg(ctx->dev, "Firmware download successful\n");
274 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
275 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
277 dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
278 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
282 skl->fw_loaded = true;
286 sst_load_base_firmware_failed:
287 release_firmware(ctx->fw);
291 static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
293 struct skl_sst *skl = ctx->thread_context;
295 struct skl_ipc_dxstate_info dx;
296 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
297 struct skl_dfw_manifest *minfo = &skl->manifest;
299 if (skl->fw_loaded == false) {
300 skl->boot_complete = false;
301 ret = bxt_load_base_firmware(ctx);
303 dev_err(ctx->dev, "reload fw failed: %d\n", ret);
307 if (minfo->lib_count > 1) {
308 ret = bxt_load_library(ctx, minfo);
310 dev_err(ctx->dev, "reload libs failed: %d\n", ret);
317 /* If core 0 is being turned on, turn on core 1 as well */
318 if (core_id == SKL_DSP_CORE0_ID)
319 ret = skl_dsp_core_power_up(ctx, core_mask |
320 SKL_DSP_CORE_MASK(1));
322 ret = skl_dsp_core_power_up(ctx, core_mask);
327 if (core_id == SKL_DSP_CORE0_ID) {
330 * Enable interrupt after SPA is set and before
333 skl_ipc_int_enable(ctx);
334 skl_ipc_op_int_enable(ctx);
335 skl->boot_complete = false;
338 ret = skl_dsp_start_core(ctx, core_mask);
342 if (core_id == SKL_DSP_CORE0_ID) {
343 ret = wait_event_timeout(skl->boot_wait,
345 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
347 /* If core 1 was turned on for booting core 0, turn it off */
348 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
350 dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
351 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
352 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
353 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
354 dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
360 /* Tell FW if additional core in now On */
362 if (core_id != SKL_DSP_CORE0_ID) {
363 dx.core_mask = core_mask;
364 dx.dx_mask = core_mask;
366 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
367 BXT_BASE_FW_MODULE_ID, &dx);
369 dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
375 skl->cores.state[core_id] = SKL_DSP_RUNNING;
378 if (core_id == SKL_DSP_CORE0_ID)
379 core_mask |= SKL_DSP_CORE_MASK(1);
380 skl_dsp_disable_core(ctx, core_mask);
385 static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
388 struct skl_ipc_dxstate_info dx;
389 struct skl_sst *skl = ctx->thread_context;
390 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
392 dx.core_mask = core_mask;
393 dx.dx_mask = SKL_IPC_D3_MASK;
395 dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
396 dx.core_mask, dx.dx_mask);
398 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
399 BXT_BASE_FW_MODULE_ID, &dx);
402 "Failed to set DSP to D3:core id = %d;Continue reset\n",
405 ret = skl_dsp_disable_core(ctx, core_mask);
407 dev_err(ctx->dev, "Failed to disable core %d\n", ret);
410 skl->cores.state[core_id] = SKL_DSP_RESET;
414 static struct skl_dsp_fw_ops bxt_fw_ops = {
415 .set_state_D0 = bxt_set_dsp_D0,
416 .set_state_D3 = bxt_set_dsp_D3,
417 .load_fw = bxt_load_base_firmware,
418 .get_fw_errcode = bxt_get_errorcode,
419 .load_library = bxt_load_library,
422 static struct sst_ops skl_ops = {
423 .irq_handler = skl_dsp_sst_interrupt,
424 .write = sst_shim32_write,
425 .read = sst_shim32_read,
426 .ram_read = sst_memcpy_fromio_32,
427 .ram_write = sst_memcpy_toio_32,
428 .free = skl_dsp_free,
431 static struct sst_dsp_device skl_dev = {
432 .thread = skl_dsp_irq_thread_handler,
436 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
437 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
438 struct skl_sst **dsp)
444 skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL);
449 skl_dev.thread_context = skl;
450 INIT_LIST_HEAD(&skl->uuid_list);
452 skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq);
454 dev_err(skl->dev, "skl_dsp_ctx_init failed\n");
459 sst->fw_name = fw_name;
460 sst->dsp_ops = dsp_ops;
461 sst->fw_ops = bxt_fw_ops;
462 sst->addr.lpe = mmio_base;
463 sst->addr.shim = mmio_base;
465 sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
466 SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
468 INIT_LIST_HEAD(&sst->module_list);
469 ret = skl_ipc_init(dev, skl);
473 skl->cores.count = 2;
474 skl->boot_complete = false;
475 init_waitqueue_head(&skl->boot_wait);
476 skl->is_first_boot = true;
483 EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
485 int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx)
488 struct sst_dsp *sst = ctx->dsp;
490 ret = sst->fw_ops.load_fw(sst);
492 dev_err(dev, "Load base fw failed: %x\n", ret);
496 skl_dsp_init_core_state(sst);
498 if (ctx->manifest.lib_count > 1) {
499 ret = sst->fw_ops.load_library(sst, &ctx->manifest);
501 dev_err(dev, "Load Library failed : %x\n", ret);
505 ctx->is_first_boot = false;
509 EXPORT_SYMBOL_GPL(bxt_sst_init_fw);
511 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
513 skl_freeup_uuid_list(ctx);
514 skl_ipc_free(&ctx->ipc);
515 ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);
517 if (ctx->dsp->addr.lpe)
518 iounmap(ctx->dsp->addr.lpe);
520 ctx->dsp->ops->free(ctx->dsp);
522 EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
524 MODULE_LICENSE("GPL v2");
525 MODULE_DESCRIPTION("Intel Broxton IPC driver");