sound/soc/mediatek/mtk-afe-pcm.c

   1 /*
   2  * Mediatek ALSA SoC AFE platform driver
   3  *
   4  * Copyright (c) 2015 MediaTek Inc.
   5  * Author: Koro Chen <koro.chen@mediatek.com>
   6  *             Sascha Hauer <s.hauer@pengutronix.de>
   7  *             Hidalgo Huang <hidalgo.huang@mediatek.com>
   8  *             Ir Lian <ir.lian@mediatek.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 and
  12  * only version 2 as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/pm_runtime.h>
  26 #include <sound/soc.h>
  27 #include "mtk-afe-common.h"
  28
  29 /*****************************************************************************
  30  *                  R E G I S T E R       D E F I N I T I O N
  31  *****************************************************************************/
  32 #define AUDIO_TOP_CON0          0x0000
  33 #define AUDIO_TOP_CON1          0x0004
  34 #define AFE_DAC_CON0            0x0010
  35 #define AFE_DAC_CON1            0x0014
  36 #define AFE_I2S_CON1            0x0034
  37 #define AFE_I2S_CON2            0x0038
  38 #define AFE_CONN_24BIT          0x006c
  39 #define AFE_MEMIF_MSB           0x00cc
  40
  41 #define AFE_CONN1               0x0024
  42 #define AFE_CONN2               0x0028
  43 #define AFE_CONN3               0x002c
  44 #define AFE_CONN7               0x0460
  45 #define AFE_CONN8               0x0464
  46 #define AFE_HDMI_CONN0          0x0390
  47
  48 /* Memory interface */
  49 #define AFE_DL1_BASE            0x0040
  50 #define AFE_DL1_CUR             0x0044
  51 #define AFE_DL1_END             0x0048
  52 #define AFE_DL2_BASE            0x0050
  53 #define AFE_DL2_CUR             0x0054
  54 #define AFE_AWB_BASE            0x0070
  55 #define AFE_AWB_CUR             0x007c
  56 #define AFE_VUL_BASE            0x0080
  57 #define AFE_VUL_CUR             0x008c
  58 #define AFE_VUL_END             0x0088
  59 #define AFE_DAI_BASE            0x0090
  60 #define AFE_DAI_CUR             0x009c
  61 #define AFE_MOD_PCM_BASE        0x0330
  62 #define AFE_MOD_PCM_CUR         0x033c
  63 #define AFE_HDMI_OUT_BASE       0x0374
  64 #define AFE_HDMI_OUT_CUR        0x0378
  65 #define AFE_HDMI_OUT_END        0x037c
  66
  67 #define AFE_ADDA_TOP_CON0       0x0120
  68 #define AFE_ADDA2_TOP_CON0      0x0600
  69
  70 #define AFE_HDMI_OUT_CON0       0x0370
  71
  72 #define AFE_IRQ_MCU_CON         0x03a0
  73 #define AFE_IRQ_STATUS          0x03a4
  74 #define AFE_IRQ_CLR             0x03a8
  75 #define AFE_IRQ_CNT1            0x03ac
  76 #define AFE_IRQ_CNT2            0x03b0
  77 #define AFE_IRQ_MCU_EN          0x03b4
  78 #define AFE_IRQ_CNT5            0x03bc
  79 #define AFE_IRQ_CNT7            0x03dc
  80
  81 #define AFE_TDM_CON1            0x0548
  82 #define AFE_TDM_CON2            0x054c
  83
  84 #define AFE_BASE_END_OFFSET     8
  85 #define AFE_IRQ_STATUS_BITS     0xff
  86
  87 /* AUDIO_TOP_CON0 (0x0000) */
  88 #define AUD_TCON0_PDN_SPDF              (0x1 << 21)
  89 #define AUD_TCON0_PDN_HDMI              (0x1 << 20)
  90 #define AUD_TCON0_PDN_24M               (0x1 << 9)
  91 #define AUD_TCON0_PDN_22M               (0x1 << 8)
  92 #define AUD_TCON0_PDN_AFE               (0x1 << 2)
  93
  94 /* AFE_I2S_CON1 (0x0034) */
  95 #define AFE_I2S_CON1_LOW_JITTER_CLK     (0x1 << 12)
  96 #define AFE_I2S_CON1_RATE(x)            (((x) & 0xf) << 8)
  97 #define AFE_I2S_CON1_FORMAT_I2S         (0x1 << 3)
  98 #define AFE_I2S_CON1_EN                 (0x1 << 0)
  99
 100 /* AFE_I2S_CON2 (0x0038) */
 101 #define AFE_I2S_CON2_LOW_JITTER_CLK     (0x1 << 12)
 102 #define AFE_I2S_CON2_RATE(x)            (((x) & 0xf) << 8)
 103 #define AFE_I2S_CON2_FORMAT_I2S         (0x1 << 3)
 104 #define AFE_I2S_CON2_EN                 (0x1 << 0)
 105
 106 /* AFE_CONN_24BIT (0x006c) */
 107 #define AFE_CONN_24BIT_O04              (0x1 << 4)
 108 #define AFE_CONN_24BIT_O03              (0x1 << 3)
 109
 110 /* AFE_HDMI_CONN0 (0x0390) */
 111 #define AFE_HDMI_CONN0_O37_I37          (0x7 << 21)
 112 #define AFE_HDMI_CONN0_O36_I36          (0x6 << 18)
 113 #define AFE_HDMI_CONN0_O35_I33          (0x3 << 15)
 114 #define AFE_HDMI_CONN0_O34_I32          (0x2 << 12)
 115 #define AFE_HDMI_CONN0_O33_I35          (0x5 << 9)
 116 #define AFE_HDMI_CONN0_O32_I34          (0x4 << 6)
 117 #define AFE_HDMI_CONN0_O31_I31          (0x1 << 3)
 118 #define AFE_HDMI_CONN0_O30_I30          (0x0 << 0)
 119
 120 /* AFE_TDM_CON1 (0x0548) */
 121 #define AFE_TDM_CON1_LRCK_WIDTH(x)      (((x) - 1) << 24)
 122 #define AFE_TDM_CON1_32_BCK_CYCLES      (0x2 << 12)
 123 #define AFE_TDM_CON1_WLEN_32BIT         (0x2 << 8)
 124 #define AFE_TDM_CON1_MSB_ALIGNED        (0x1 << 4)
 125 #define AFE_TDM_CON1_1_BCK_DELAY        (0x1 << 3)
 126 #define AFE_TDM_CON1_BCK_INV            (0x1 << 1)
 127 #define AFE_TDM_CON1_EN                 (0x1 << 0)
 128
 129 enum afe_tdm_ch_start {
 130         AFE_TDM_CH_START_O30_O31 = 0,
 131         AFE_TDM_CH_START_O32_O33,
 132         AFE_TDM_CH_START_O34_O35,
 133         AFE_TDM_CH_START_O36_O37,
 134         AFE_TDM_CH_ZERO,
 135 };
 136
 137 static const unsigned int mtk_afe_backup_list[] = {
 138         AUDIO_TOP_CON0,
 139         AFE_CONN1,
 140         AFE_CONN2,
 141         AFE_CONN7,
 142         AFE_CONN8,
 143         AFE_DAC_CON1,
 144         AFE_DL1_BASE,
 145         AFE_DL1_END,
 146         AFE_VUL_BASE,
 147         AFE_VUL_END,
 148         AFE_HDMI_OUT_BASE,
 149         AFE_HDMI_OUT_END,
 150         AFE_HDMI_CONN0,
 151         AFE_DAC_CON0,
 152 };
 153
 154 struct mtk_afe {
 155         /* address for ioremap audio hardware register */
 156         void __iomem *base_addr;
 157         struct device *dev;
 158         struct regmap *regmap;
 159         struct mtk_afe_memif memif[MTK_AFE_MEMIF_NUM];
 160         struct clk *clocks[MTK_CLK_NUM];
 161         unsigned int backup_regs[ARRAY_SIZE(mtk_afe_backup_list)];
 162         bool suspended;
 163 };
 164
 165 static const struct snd_pcm_hardware mtk_afe_hardware = {
 166         .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 167                  SNDRV_PCM_INFO_MMAP_VALID),
 168         .buffer_bytes_max = 256 * 1024,
 169         .period_bytes_min = 512,
 170         .period_bytes_max = 128 * 1024,
 171         .periods_min = 2,
 172         .periods_max = 256,
 173         .fifo_size = 0,
 174 };
 175
 176 static snd_pcm_uframes_t mtk_afe_pcm_pointer
 177                          (struct snd_pcm_substream *substream)
 178 {
 179         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 180         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 181         struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
 182         unsigned int hw_ptr;
 183         int ret;
 184
 185         ret = regmap_read(afe->regmap, memif->data->reg_ofs_cur, &hw_ptr);
 186         if (ret || hw_ptr == 0) {
 187                 dev_err(afe->dev, "%s hw_ptr err\n", __func__);
 188                 hw_ptr = memif->phys_buf_addr;
 189         }
 190
 191         return bytes_to_frames(substream->runtime,
 192                                hw_ptr - memif->phys_buf_addr);
 193 }
 194
 195 static const struct snd_pcm_ops mtk_afe_pcm_ops = {
 196         .ioctl = snd_pcm_lib_ioctl,
 197         .pointer = mtk_afe_pcm_pointer,
 198 };
 199
 200 static int mtk_afe_pcm_new(struct snd_soc_pcm_runtime *rtd)
 201 {
 202         size_t size;
 203         struct snd_card *card = rtd->card->snd_card;
 204         struct snd_pcm *pcm = rtd->pcm;
 205
 206         size = mtk_afe_hardware.buffer_bytes_max;
 207
 208         return snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
 209                                                      card->dev, size, size);
 210 }
 211
 212 static void mtk_afe_pcm_free(struct snd_pcm *pcm)
 213 {
 214         snd_pcm_lib_preallocate_free_for_all(pcm);
 215 }
 216
 217 static const struct snd_soc_platform_driver mtk_afe_pcm_platform = {
 218         .ops = &mtk_afe_pcm_ops,
 219         .pcm_new = mtk_afe_pcm_new,
 220         .pcm_free = mtk_afe_pcm_free,
 221 };
 222
 223 struct mtk_afe_rate {
 224         unsigned int rate;
 225         unsigned int regvalue;
 226 };
 227
 228 static const struct mtk_afe_rate mtk_afe_i2s_rates[] = {
 229         { .rate = 8000, .regvalue = 0 },
 230         { .rate = 11025, .regvalue = 1 },
 231         { .rate = 12000, .regvalue = 2 },
 232         { .rate = 16000, .regvalue = 4 },
 233         { .rate = 22050, .regvalue = 5 },
 234         { .rate = 24000, .regvalue = 6 },
 235         { .rate = 32000, .regvalue = 8 },
 236         { .rate = 44100, .regvalue = 9 },
 237         { .rate = 48000, .regvalue = 10 },
 238         { .rate = 88000, .regvalue = 11 },
 239         { .rate = 96000, .regvalue = 12 },
 240         { .rate = 174000, .regvalue = 13 },
 241         { .rate = 192000, .regvalue = 14 },
 242 };
 243
 244 static int mtk_afe_i2s_fs(unsigned int sample_rate)
 245 {
 246         int i;
 247
 248         for (i = 0; i < ARRAY_SIZE(mtk_afe_i2s_rates); i++)
 249                 if (mtk_afe_i2s_rates[i].rate == sample_rate)
 250                         return mtk_afe_i2s_rates[i].regvalue;
 251
 252         return -EINVAL;
 253 }
 254
 255 static int mtk_afe_set_i2s(struct mtk_afe *afe, unsigned int rate)
 256 {
 257         unsigned int val;
 258         int fs = mtk_afe_i2s_fs(rate);
 259
 260         if (fs < 0)
 261                 return -EINVAL;
 262
 263         /* from external ADC */
 264         regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1);
 265         regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
 266
 267         /* set input */
 268         val = AFE_I2S_CON2_LOW_JITTER_CLK |
 269               AFE_I2S_CON2_RATE(fs) |
 270               AFE_I2S_CON2_FORMAT_I2S;
 271
 272         regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
 273
 274         /* set output */
 275         val = AFE_I2S_CON1_LOW_JITTER_CLK |
 276               AFE_I2S_CON1_RATE(fs) |
 277               AFE_I2S_CON1_FORMAT_I2S;
 278
 279         regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
 280         return 0;
 281 }
 282
 283 static void mtk_afe_set_i2s_enable(struct mtk_afe *afe, bool enable)
 284 {
 285         unsigned int val;
 286
 287         regmap_read(afe->regmap, AFE_I2S_CON2, &val);
 288         if (!!(val & AFE_I2S_CON2_EN) == enable)
 289                 return;
 290
 291         /* input */
 292         regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
 293
 294         /* output */
 295         regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
 296 }
 297
 298 static int mtk_afe_dais_enable_clks(struct mtk_afe *afe,
 299                                     struct clk *m_ck, struct clk *b_ck)
 300 {
 301         int ret;
 302
 303         if (m_ck) {
 304                 ret = clk_prepare_enable(m_ck);
 305                 if (ret) {
 306                         dev_err(afe->dev, "Failed to enable m_ck\n");
 307                         return ret;
 308                 }
 309         }
 310
 311         if (b_ck) {
 312                 ret = clk_prepare_enable(b_ck);
 313                 if (ret) {
 314                         dev_err(afe->dev, "Failed to enable b_ck\n");
 315                         return ret;
 316                 }
 317         }
 318         return 0;
 319 }
 320
 321 static int mtk_afe_dais_set_clks(struct mtk_afe *afe,
 322                                  struct clk *m_ck, unsigned int mck_rate,
 323                                  struct clk *b_ck, unsigned int bck_rate)
 324 {
 325         int ret;
 326
 327         if (m_ck) {
 328                 ret = clk_set_rate(m_ck, mck_rate);
 329                 if (ret) {
 330                         dev_err(afe->dev, "Failed to set m_ck rate\n");
 331                         return ret;
 332                 }
 333         }
 334
 335         if (b_ck) {
 336                 ret = clk_set_rate(b_ck, bck_rate);
 337                 if (ret) {
 338                         dev_err(afe->dev, "Failed to set b_ck rate\n");
 339                         return ret;
 340                 }
 341         }
 342         return 0;
 343 }
 344
 345 static void mtk_afe_dais_disable_clks(struct mtk_afe *afe,
 346                                       struct clk *m_ck, struct clk *b_ck)
 347 {
 348         if (m_ck)
 349                 clk_disable_unprepare(m_ck);
 350         if (b_ck)
 351                 clk_disable_unprepare(b_ck);
 352 }
 353
 354 static int mtk_afe_i2s_startup(struct snd_pcm_substream *substream,
 355                                struct snd_soc_dai *dai)
 356 {
 357         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 358         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 359
 360         if (dai->active)
 361                 return 0;
 362
 363         mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
 364         mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S2_M], NULL);
 365         regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 366                            AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
 367         return 0;
 368 }
 369
 370 static void mtk_afe_i2s_shutdown(struct snd_pcm_substream *substream,
 371                                  struct snd_soc_dai *dai)
 372 {
 373         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 374         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 375
 376         if (dai->active)
 377                 return;
 378
 379         mtk_afe_set_i2s_enable(afe, false);
 380         regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 381                            AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
 382                            AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
 383         mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
 384         mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S2_M], NULL);
 385 }
 386
 387 static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream,
 388                                struct snd_soc_dai *dai)
 389 {
 390         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 391         struct snd_pcm_runtime * const runtime = substream->runtime;
 392         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 393         int ret;
 394
 395         mtk_afe_dais_set_clks(afe,
 396                               afe->clocks[MTK_CLK_I2S1_M], runtime->rate * 256,
 397                               NULL, 0);
 398         mtk_afe_dais_set_clks(afe,
 399                               afe->clocks[MTK_CLK_I2S2_M], runtime->rate * 256,
 400                               NULL, 0);
 401         /* config I2S */
 402         ret = mtk_afe_set_i2s(afe, substream->runtime->rate);
 403         if (ret)
 404                 return ret;
 405
 406         mtk_afe_set_i2s_enable(afe, true);
 407
 408         return 0;
 409 }
 410
 411 static int mtk_afe_hdmi_startup(struct snd_pcm_substream *substream,
 412                                 struct snd_soc_dai *dai)
 413 {
 414         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 415         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 416
 417         if (dai->active)
 418                 return 0;
 419
 420         mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
 421                                  afe->clocks[MTK_CLK_I2S3_B]);
 422         return 0;
 423 }
 424
 425 static void mtk_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
 426                                   struct snd_soc_dai *dai)
 427 {
 428         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 429         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 430
 431         if (dai->active)
 432                 return;
 433
 434         mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
 435                                   afe->clocks[MTK_CLK_I2S3_B]);
 436 }
 437
 438 static int mtk_afe_hdmi_prepare(struct snd_pcm_substream *substream,
 439                                 struct snd_soc_dai *dai)
 440 {
 441         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 442         struct snd_pcm_runtime * const runtime = substream->runtime;
 443         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 444         unsigned int val;
 445
 446         mtk_afe_dais_set_clks(afe,
 447                               afe->clocks[MTK_CLK_I2S3_M], runtime->rate * 128,
 448                               afe->clocks[MTK_CLK_I2S3_B],
 449                               runtime->rate * runtime->channels * 32);
 450
 451         val = AFE_TDM_CON1_BCK_INV |
 452               AFE_TDM_CON1_1_BCK_DELAY |
 453               AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
 454               AFE_TDM_CON1_WLEN_32BIT |
 455               AFE_TDM_CON1_32_BCK_CYCLES |
 456               AFE_TDM_CON1_LRCK_WIDTH(32);
 457         regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
 458
 459         /* set tdm2 config */
 460         switch (runtime->channels) {
 461         case 1:
 462         case 2:
 463                 val = AFE_TDM_CH_START_O30_O31;
 464                 val |= (AFE_TDM_CH_ZERO << 4);
 465                 val |= (AFE_TDM_CH_ZERO << 8);
 466                 val |= (AFE_TDM_CH_ZERO << 12);
 467                 break;
 468         case 3:
 469         case 4:
 470                 val = AFE_TDM_CH_START_O30_O31;
 471                 val |= (AFE_TDM_CH_START_O32_O33 << 4);
 472                 val |= (AFE_TDM_CH_ZERO << 8);
 473                 val |= (AFE_TDM_CH_ZERO << 12);
 474                 break;
 475         case 5:
 476         case 6:
 477                 val = AFE_TDM_CH_START_O30_O31;
 478                 val |= (AFE_TDM_CH_START_O32_O33 << 4);
 479                 val |= (AFE_TDM_CH_START_O34_O35 << 8);
 480                 val |= (AFE_TDM_CH_ZERO << 12);
 481                 break;
 482         case 7:
 483         case 8:
 484                 val = AFE_TDM_CH_START_O30_O31;
 485                 val |= (AFE_TDM_CH_START_O32_O33 << 4);
 486                 val |= (AFE_TDM_CH_START_O34_O35 << 8);
 487                 val |= (AFE_TDM_CH_START_O36_O37 << 12);
 488                 break;
 489         default:
 490                 val = 0;
 491         }
 492         regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
 493
 494         regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
 495                            0x000000f0, runtime->channels << 4);
 496         return 0;
 497 }
 498
 499 static int mtk_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
 500                                 struct snd_soc_dai *dai)
 501 {
 502         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 503         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 504
 505         dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
 506
 507         switch (cmd) {
 508         case SNDRV_PCM_TRIGGER_START:
 509         case SNDRV_PCM_TRIGGER_RESUME:
 510                 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 511                                    AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
 512
 513                 /* set connections:  O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
 514                 regmap_write(afe->regmap, AFE_HDMI_CONN0,
 515                              AFE_HDMI_CONN0_O30_I30 | AFE_HDMI_CONN0_O31_I31 |
 516                              AFE_HDMI_CONN0_O32_I34 | AFE_HDMI_CONN0_O33_I35 |
 517                              AFE_HDMI_CONN0_O34_I32 | AFE_HDMI_CONN0_O35_I33 |
 518                              AFE_HDMI_CONN0_O36_I36 | AFE_HDMI_CONN0_O37_I37);
 519
 520                 /* enable Out control */
 521                 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
 522
 523                 /* enable tdm */
 524                 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
 525
 526                 return 0;
 527         case SNDRV_PCM_TRIGGER_STOP:
 528         case SNDRV_PCM_TRIGGER_SUSPEND:
 529                 /* disable tdm */
 530                 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
 531
 532                 /* disable Out control */
 533                 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
 534
 535                 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 536                                    AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
 537                                    AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
 538
 539                 return 0;
 540         default:
 541                 return -EINVAL;
 542         }
 543 }
 544
 545 static int mtk_afe_dais_startup(struct snd_pcm_substream *substream,
 546                                 struct snd_soc_dai *dai)
 547 {
 548         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 549         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 550         struct snd_pcm_runtime *runtime = substream->runtime;
 551         struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
 552         int ret;
 553
 554         memif->substream = substream;
 555
 556         snd_soc_set_runtime_hwparams(substream, &mtk_afe_hardware);
 557
 558         /*
 559          * Capture cannot use ping-pong buffer since hw_ptr at IRQ may be
 560          * smaller than period_size due to AFE's internal buffer.
 561          * This easily leads to overrun when avail_min is period_size.
 562          * One more period can hold the possible unread buffer.
 563          */
 564         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 565                 ret = snd_pcm_hw_constraint_minmax(runtime,
 566                                                    SNDRV_PCM_HW_PARAM_PERIODS,
 567                                                    3,
 568                                                    mtk_afe_hardware.periods_max);
 569                 if (ret < 0) {
 570                         dev_err(afe->dev, "hw_constraint_minmax failed\n");
 571                         return ret;
 572                 }
 573         }
 574         ret = snd_pcm_hw_constraint_integer(runtime,
 575                                             SNDRV_PCM_HW_PARAM_PERIODS);
 576         if (ret < 0)
 577                 dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
 578         return ret;
 579 }
 580
 581 static void mtk_afe_dais_shutdown(struct snd_pcm_substream *substream,
 582                                   struct snd_soc_dai *dai)
 583 {
 584         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 585         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 586         struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
 587
 588         memif->substream = NULL;
 589 }
 590
 591 static int mtk_afe_dais_hw_params(struct snd_pcm_substream *substream,
 592                                   struct snd_pcm_hw_params *params,
 593                                   struct snd_soc_dai *dai)
 594 {
 595         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 596         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 597         struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
 598         int msb_at_bit33 = 0;
 599         int ret;
 600
 601         dev_dbg(afe->dev,
 602                 "%s period = %u, rate= %u, channels=%u\n",
 603                 __func__, params_period_size(params), params_rate(params),
 604                 params_channels(params));
 605
 606         ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
 607         if (ret < 0)
 608                 return ret;
 609
 610         msb_at_bit33 = upper_32_bits(substream->runtime->dma_addr) ? 1 : 0;
 611         memif->phys_buf_addr = lower_32_bits(substream->runtime->dma_addr);
 612         memif->buffer_size = substream->runtime->dma_bytes;
 613
 614         /* start */
 615         regmap_write(afe->regmap,
 616                      memif->data->reg_ofs_base, memif->phys_buf_addr);
 617         /* end */
 618         regmap_write(afe->regmap,
 619                      memif->data->reg_ofs_base + AFE_BASE_END_OFFSET,
 620                      memif->phys_buf_addr + memif->buffer_size - 1);
 621
 622         /* set MSB to 33-bit */
 623         regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
 624                            1 << memif->data->msb_shift,
 625                            msb_at_bit33 << memif->data->msb_shift);
 626
 627         /* set channel */
 628         if (memif->data->mono_shift >= 0) {
 629                 unsigned int mono = (params_channels(params) == 1) ? 1 : 0;
 630
 631                 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
 632                                    1 << memif->data->mono_shift,
 633                                    mono << memif->data->mono_shift);
 634         }
 635
 636         /* set rate */
 637         if (memif->data->fs_shift < 0)
 638                 return 0;
 639         if (memif->data->id == MTK_AFE_MEMIF_DAI ||
 640             memif->data->id == MTK_AFE_MEMIF_MOD_DAI) {
 641                 unsigned int val;
 642
 643                 switch (params_rate(params)) {
 644                 case 8000:
 645                         val = 0;
 646                         break;
 647                 case 16000:
 648                         val = 1;
 649                         break;
 650                 case 32000:
 651                         val = 2;
 652                         break;
 653                 default:
 654                         return -EINVAL;
 655                 }
 656
 657                 if (memif->data->id == MTK_AFE_MEMIF_DAI)
 658                         regmap_update_bits(afe->regmap, AFE_DAC_CON0,
 659                                            0x3 << memif->data->fs_shift,
 660                                            val << memif->data->fs_shift);
 661                 else
 662                         regmap_update_bits(afe->regmap, AFE_DAC_CON1,
 663                                            0x3 << memif->data->fs_shift,
 664                                            val << memif->data->fs_shift);
 665
 666         } else {
 667                 int fs = mtk_afe_i2s_fs(params_rate(params));
 668
 669                 if (fs < 0)
 670                         return -EINVAL;
 671
 672                 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
 673                                    0xf << memif->data->fs_shift,
 674                                    fs << memif->data->fs_shift);
 675         }
 676
 677         return 0;
 678 }
 679
 680 static int mtk_afe_dais_hw_free(struct snd_pcm_substream *substream,
 681                                 struct snd_soc_dai *dai)
 682 {
 683         return snd_pcm_lib_free_pages(substream);
 684 }
 685
 686 static int mtk_afe_dais_trigger(struct snd_pcm_substream *substream, int cmd,
 687                                 struct snd_soc_dai *dai)
 688 {
 689         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 690         struct snd_pcm_runtime * const runtime = substream->runtime;
 691         struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 692         struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
 693         unsigned int counter = runtime->period_size;
 694
 695         dev_info(afe->dev, "%s %s cmd=%d\n", __func__, memif->data->name, cmd);
 696
 697         switch (cmd) {
 698         case SNDRV_PCM_TRIGGER_START:
 699         case SNDRV_PCM_TRIGGER_RESUME:
 700                 if (memif->data->enable_shift >= 0)
 701                         regmap_update_bits(afe->regmap, AFE_DAC_CON0,
 702                                            1 << memif->data->enable_shift,
 703                                            1 << memif->data->enable_shift);
 704
 705                 /* set irq counter */
 706                 regmap_update_bits(afe->regmap,
 707                                    memif->data->irq_reg_cnt,
 708                                    0x3ffff << memif->data->irq_cnt_shift,
 709                                    counter << memif->data->irq_cnt_shift);
 710
 711                 /* set irq fs */
 712                 if (memif->data->irq_fs_shift >= 0) {
 713                         int fs = mtk_afe_i2s_fs(runtime->rate);
 714
 715                         if (fs < 0)
 716                                 return -EINVAL;
 717
 718                         regmap_update_bits(afe->regmap,
 719                                            AFE_IRQ_MCU_CON,
 720                                            0xf << memif->data->irq_fs_shift,
 721                                            fs << memif->data->irq_fs_shift);
 722                 }
 723                 /* enable interrupt */
 724                 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
 725                                    1 << memif->data->irq_en_shift,
 726                                    1 << memif->data->irq_en_shift);
 727
 728                 return 0;
 729         case SNDRV_PCM_TRIGGER_STOP:
 730         case SNDRV_PCM_TRIGGER_SUSPEND:
 731                 if (memif->data->enable_shift >= 0)
 732                         regmap_update_bits(afe->regmap, AFE_DAC_CON0,
 733                                            1 << memif->data->enable_shift, 0);
 734                 /* disable interrupt */
 735                 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
 736                                    1 << memif->data->irq_en_shift,
 737                                    0 << memif->data->irq_en_shift);
 738                 /* and clear pending IRQ */
 739                 regmap_write(afe->regmap, AFE_IRQ_CLR,
 740                              1 << memif->data->irq_clr_shift);
 741                 return 0;
 742         default:
 743                 return -EINVAL;
 744         }
 745 }
 746
 747 /* FE DAIs */
 748 static const struct snd_soc_dai_ops mtk_afe_dai_ops = {
 749         .startup        = mtk_afe_dais_startup,
 750         .shutdown       = mtk_afe_dais_shutdown,
 751         .hw_params      = mtk_afe_dais_hw_params,
 752         .hw_free        = mtk_afe_dais_hw_free,
 753         .trigger        = mtk_afe_dais_trigger,
 754 };
 755
 756 /* BE DAIs */
 757 static const struct snd_soc_dai_ops mtk_afe_i2s_ops = {
 758         .startup        = mtk_afe_i2s_startup,
 759         .shutdown       = mtk_afe_i2s_shutdown,
 760         .prepare        = mtk_afe_i2s_prepare,
 761 };
 762
 763 static const struct snd_soc_dai_ops mtk_afe_hdmi_ops = {
 764         .startup        = mtk_afe_hdmi_startup,
 765         .shutdown       = mtk_afe_hdmi_shutdown,
 766         .prepare        = mtk_afe_hdmi_prepare,
 767         .trigger        = mtk_afe_hdmi_trigger,
 768
 769 };
 770
 771 static int mtk_afe_runtime_suspend(struct device *dev);
 772 static int mtk_afe_runtime_resume(struct device *dev);
 773
 774 static int mtk_afe_dai_suspend(struct snd_soc_dai *dai)
 775 {
 776         struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
 777         int i;
 778
 779         dev_dbg(afe->dev, "%s\n", __func__);
 780         if (pm_runtime_status_suspended(afe->dev) || afe->suspended)
 781                 return 0;
 782
 783         for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
 784                 regmap_read(afe->regmap, mtk_afe_backup_list[i],
 785                             &afe->backup_regs[i]);
 786
 787         afe->suspended = true;
 788         mtk_afe_runtime_suspend(afe->dev);
 789         return 0;
 790 }
 791
 792 static int mtk_afe_dai_resume(struct snd_soc_dai *dai)
 793 {
 794         struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
 795         int i = 0;
 796
 797         dev_dbg(afe->dev, "%s\n", __func__);
 798         if (pm_runtime_status_suspended(afe->dev) || !afe->suspended)
 799                 return 0;
 800
 801         mtk_afe_runtime_resume(afe->dev);
 802
 803         for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
 804                 regmap_write(afe->regmap, mtk_afe_backup_list[i],
 805                              afe->backup_regs[i]);
 806
 807         afe->suspended = false;
 808         return 0;
 809 }
 810
 811 static struct snd_soc_dai_driver mtk_afe_pcm_dais[] = {
 812         /* FE DAIs: memory intefaces to CPU */
 813         {
 814                 .name = "DL1", /* downlink 1 */
 815                 .id = MTK_AFE_MEMIF_DL1,
 816                 .suspend = mtk_afe_dai_suspend,
 817                 .resume = mtk_afe_dai_resume,
 818                 .playback = {
 819                         .stream_name = "DL1",
 820                         .channels_min = 1,
 821                         .channels_max = 2,
 822                         .rates = SNDRV_PCM_RATE_8000_48000,
 823                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 824                 },
 825                 .ops = &mtk_afe_dai_ops,
 826         }, {
 827                 .name = "VUL", /* voice uplink */
 828                 .id = MTK_AFE_MEMIF_VUL,
 829                 .suspend = mtk_afe_dai_suspend,
 830                 .resume = mtk_afe_dai_resume,
 831                 .capture = {
 832                         .stream_name = "VUL",
 833                         .channels_min = 1,
 834                         .channels_max = 2,
 835                         .rates = SNDRV_PCM_RATE_8000_48000,
 836                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 837                 },
 838                 .ops = &mtk_afe_dai_ops,
 839         }, {
 840         /* BE DAIs */
 841                 .name = "I2S",
 842                 .id = MTK_AFE_IO_I2S,
 843                 .playback = {
 844                         .stream_name = "I2S Playback",
 845                         .channels_min = 1,
 846                         .channels_max = 2,
 847                         .rates = SNDRV_PCM_RATE_8000_48000,
 848                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 849                 },
 850                 .capture = {
 851                         .stream_name = "I2S Capture",
 852                         .channels_min = 1,
 853                         .channels_max = 2,
 854                         .rates = SNDRV_PCM_RATE_8000_48000,
 855                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 856                 },
 857                 .ops = &mtk_afe_i2s_ops,
 858                 .symmetric_rates = 1,
 859         },
 860 };
 861
 862 static struct snd_soc_dai_driver mtk_afe_hdmi_dais[] = {
 863         /* FE DAIs */
 864         {
 865                 .name = "HDMI",
 866                 .id = MTK_AFE_MEMIF_HDMI,
 867                 .suspend = mtk_afe_dai_suspend,
 868                 .resume = mtk_afe_dai_resume,
 869                 .playback = {
 870                         .stream_name = "HDMI",
 871                         .channels_min = 2,
 872                         .channels_max = 8,
 873                         .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 874                                 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 875                                 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 876                                 SNDRV_PCM_RATE_192000,
 877                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 878                 },
 879                 .ops = &mtk_afe_dai_ops,
 880         }, {
 881         /* BE DAIs */
 882                 .name = "HDMIO",
 883                 .id = MTK_AFE_IO_HDMI,
 884                 .playback = {
 885                         .stream_name = "HDMIO Playback",
 886                         .channels_min = 2,
 887                         .channels_max = 8,
 888                         .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 889                                 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 890                                 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 891                                 SNDRV_PCM_RATE_192000,
 892                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 893                 },
 894                 .ops = &mtk_afe_hdmi_ops,
 895         },
 896 };
 897
 898 static const struct snd_kcontrol_new mtk_afe_o03_mix[] = {
 899         SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
 900 };
 901
 902 static const struct snd_kcontrol_new mtk_afe_o04_mix[] = {
 903         SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
 904 };
 905
 906 static const struct snd_kcontrol_new mtk_afe_o09_mix[] = {
 907         SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0),
 908         SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
 909 };
 910
 911 static const struct snd_kcontrol_new mtk_afe_o10_mix[] = {
 912         SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0),
 913         SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
 914 };
 915
 916 static const struct snd_soc_dapm_widget mtk_afe_pcm_widgets[] = {
 917         /* inter-connections */
 918         SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
 919         SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
 920         SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
 921         SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
 922         SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
 923         SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
 924
 925         SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
 926                            mtk_afe_o03_mix, ARRAY_SIZE(mtk_afe_o03_mix)),
 927         SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
 928                            mtk_afe_o04_mix, ARRAY_SIZE(mtk_afe_o04_mix)),
 929         SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
 930                            mtk_afe_o09_mix, ARRAY_SIZE(mtk_afe_o09_mix)),
 931         SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
 932                            mtk_afe_o10_mix, ARRAY_SIZE(mtk_afe_o10_mix)),
 933 };
 934
 935 static const struct snd_soc_dapm_route mtk_afe_pcm_routes[] = {
 936         {"I05", NULL, "DL1"},
 937         {"I06", NULL, "DL1"},
 938         {"I2S Playback", NULL, "O03"},
 939         {"I2S Playback", NULL, "O04"},
 940         {"VUL", NULL, "O09"},
 941         {"VUL", NULL, "O10"},
 942         {"I03", NULL, "I2S Capture"},
 943         {"I04", NULL, "I2S Capture"},
 944         {"I17", NULL, "I2S Capture"},
 945         {"I18", NULL, "I2S Capture"},
 946         { "O03", "I05 Switch", "I05" },
 947         { "O04", "I06 Switch", "I06" },
 948         { "O09", "I17 Switch", "I17" },
 949         { "O09", "I03 Switch", "I03" },
 950         { "O10", "I18 Switch", "I18" },
 951         { "O10", "I04 Switch", "I04" },
 952 };
 953
 954 static const struct snd_soc_dapm_route mtk_afe_hdmi_routes[] = {
 955         {"HDMIO Playback", NULL, "HDMI"},
 956 };
 957
 958 static const struct snd_soc_component_driver mtk_afe_pcm_dai_component = {
 959         .name = "mtk-afe-pcm-dai",
 960         .dapm_widgets = mtk_afe_pcm_widgets,
 961         .num_dapm_widgets = ARRAY_SIZE(mtk_afe_pcm_widgets),
 962         .dapm_routes = mtk_afe_pcm_routes,
 963         .num_dapm_routes = ARRAY_SIZE(mtk_afe_pcm_routes),
 964 };
 965
 966 static const struct snd_soc_component_driver mtk_afe_hdmi_dai_component = {
 967         .name = "mtk-afe-hdmi-dai",
 968         .dapm_routes = mtk_afe_hdmi_routes,
 969         .num_dapm_routes = ARRAY_SIZE(mtk_afe_hdmi_routes),
 970 };
 971
 972 static const char *aud_clks[MTK_CLK_NUM] = {
 973         [MTK_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
 974         [MTK_CLK_TOP_PDN_AUD] = "top_pdn_audio",
 975         [MTK_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
 976         [MTK_CLK_I2S0_M] =  "i2s0_m",
 977         [MTK_CLK_I2S1_M] =  "i2s1_m",
 978         [MTK_CLK_I2S2_M] =  "i2s2_m",
 979         [MTK_CLK_I2S3_M] =  "i2s3_m",
 980         [MTK_CLK_I2S3_B] =  "i2s3_b",
 981         [MTK_CLK_BCK0] =  "bck0",
 982         [MTK_CLK_BCK1] =  "bck1",
 983 };
 984
 985 static const struct mtk_afe_memif_data memif_data[MTK_AFE_MEMIF_NUM] = {
 986         {
 987                 .name = "DL1",
 988                 .id = MTK_AFE_MEMIF_DL1,
 989                 .reg_ofs_base = AFE_DL1_BASE,
 990                 .reg_ofs_cur = AFE_DL1_CUR,
 991                 .fs_shift = 0,
 992                 .mono_shift = 21,
 993                 .enable_shift = 1,
 994                 .irq_reg_cnt = AFE_IRQ_CNT1,
 995                 .irq_cnt_shift = 0,
 996                 .irq_en_shift = 0,
 997                 .irq_fs_shift = 4,
 998                 .irq_clr_shift = 0,
 999                 .msb_shift = 0,
1000         }, {
1001                 .name = "DL2",
1002                 .id = MTK_AFE_MEMIF_DL2,
1003                 .reg_ofs_base = AFE_DL2_BASE,
1004                 .reg_ofs_cur = AFE_DL2_CUR,
1005                 .fs_shift = 4,
1006                 .mono_shift = 22,
1007                 .enable_shift = 2,
1008                 .irq_reg_cnt = AFE_IRQ_CNT1,
1009                 .irq_cnt_shift = 20,
1010                 .irq_en_shift = 2,
1011                 .irq_fs_shift = 16,
1012                 .irq_clr_shift = 2,
1013                 .msb_shift = 1,
1014         }, {
1015                 .name = "VUL",
1016                 .id = MTK_AFE_MEMIF_VUL,
1017                 .reg_ofs_base = AFE_VUL_BASE,
1018                 .reg_ofs_cur = AFE_VUL_CUR,
1019                 .fs_shift = 16,
1020                 .mono_shift = 27,
1021                 .enable_shift = 3,
1022                 .irq_reg_cnt = AFE_IRQ_CNT2,
1023                 .irq_cnt_shift = 0,
1024                 .irq_en_shift = 1,
1025                 .irq_fs_shift = 8,
1026                 .irq_clr_shift = 1,
1027                 .msb_shift = 6,
1028         }, {
1029                 .name = "DAI",
1030                 .id = MTK_AFE_MEMIF_DAI,
1031                 .reg_ofs_base = AFE_DAI_BASE,
1032                 .reg_ofs_cur = AFE_DAI_CUR,
1033                 .fs_shift = 24,
1034                 .mono_shift = -1,
1035                 .enable_shift = 4,
1036                 .irq_reg_cnt = AFE_IRQ_CNT2,
1037                 .irq_cnt_shift = 20,
1038                 .irq_en_shift = 3,
1039                 .irq_fs_shift = 20,
1040                 .irq_clr_shift = 3,
1041                 .msb_shift = 5,
1042         }, {
1043                 .name = "AWB",
1044                 .id = MTK_AFE_MEMIF_AWB,
1045                 .reg_ofs_base = AFE_AWB_BASE,
1046                 .reg_ofs_cur = AFE_AWB_CUR,
1047                 .fs_shift = 12,
1048                 .mono_shift = 24,
1049                 .enable_shift = 6,
1050                 .irq_reg_cnt = AFE_IRQ_CNT7,
1051                 .irq_cnt_shift = 0,
1052                 .irq_en_shift = 14,
1053                 .irq_fs_shift = 24,
1054                 .irq_clr_shift = 6,
1055                 .msb_shift = 3,
1056         }, {
1057                 .name = "MOD_DAI",
1058                 .id = MTK_AFE_MEMIF_MOD_DAI,
1059                 .reg_ofs_base = AFE_MOD_PCM_BASE,
1060                 .reg_ofs_cur = AFE_MOD_PCM_CUR,
1061                 .fs_shift = 30,
1062                 .mono_shift = 30,
1063                 .enable_shift = 7,
1064                 .irq_reg_cnt = AFE_IRQ_CNT2,
1065                 .irq_cnt_shift = 20,
1066                 .irq_en_shift = 3,
1067                 .irq_fs_shift = 20,
1068                 .irq_clr_shift = 3,
1069                 .msb_shift = 4,
1070         }, {
1071                 .name = "HDMI",
1072                 .id = MTK_AFE_MEMIF_HDMI,
1073                 .reg_ofs_base = AFE_HDMI_OUT_BASE,
1074                 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
1075                 .fs_shift = -1,
1076                 .mono_shift = -1,
1077                 .enable_shift = -1,
1078                 .irq_reg_cnt = AFE_IRQ_CNT5,
1079                 .irq_cnt_shift = 0,
1080                 .irq_en_shift = 12,
1081                 .irq_fs_shift = -1,
1082                 .irq_clr_shift = 4,
1083                 .msb_shift = 8,
1084         },
1085 };
1086
1087 static const struct regmap_config mtk_afe_regmap_config = {
1088         .reg_bits = 32,
1089         .reg_stride = 4,
1090         .val_bits = 32,
1091         .max_register = AFE_ADDA2_TOP_CON0,
1092         .cache_type = REGCACHE_NONE,
1093 };
1094
1095 static irqreturn_t mtk_afe_irq_handler(int irq, void *dev_id)
1096 {
1097         struct mtk_afe *afe = dev_id;
1098         unsigned int reg_value;
1099         int i, ret;
1100
1101         ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &reg_value);
1102         if (ret) {
1103                 dev_err(afe->dev, "%s irq status err\n", __func__);
1104                 reg_value = AFE_IRQ_STATUS_BITS;
1105                 goto err_irq;
1106         }
1107
1108         for (i = 0; i < MTK_AFE_MEMIF_NUM; i++) {
1109                 struct mtk_afe_memif *memif = &afe->memif[i];
1110
1111                 if (!(reg_value & (1 << memif->data->irq_clr_shift)))
1112                         continue;
1113
1114                 snd_pcm_period_elapsed(memif->substream);
1115         }
1116
1117 err_irq:
1118         /* clear irq */
1119         regmap_write(afe->regmap, AFE_IRQ_CLR, reg_value & AFE_IRQ_STATUS_BITS);
1120
1121         return IRQ_HANDLED;
1122 }
1123
1124 static int mtk_afe_runtime_suspend(struct device *dev)
1125 {
1126         struct mtk_afe *afe = dev_get_drvdata(dev);
1127
1128         /* disable AFE */
1129         regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
1130
1131         /* disable AFE clk */
1132         regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
1133                            AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
1134
1135         clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1136         clk_disable_unprepare(afe->clocks[MTK_CLK_BCK1]);
1137         clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1138         clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1139         clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1140         return 0;
1141 }
1142
1143 static int mtk_afe_runtime_resume(struct device *dev)
1144 {
1145         struct mtk_afe *afe = dev_get_drvdata(dev);
1146         int ret;
1147
1148         ret = clk_prepare_enable(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1149         if (ret)
1150                 return ret;
1151
1152         ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1153         if (ret)
1154                 goto err_infra;
1155
1156         ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1157         if (ret)
1158                 goto err_top_aud_bus;
1159
1160         ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK0]);
1161         if (ret)
1162                 goto err_top_aud;
1163
1164         ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK1]);
1165         if (ret)
1166                 goto err_bck0;
1167
1168         /* enable AFE clk */
1169         regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
1170
1171         /* set O3/O4 16bits */
1172         regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
1173                            AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
1174
1175         /* unmask all IRQs */
1176         regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
1177
1178         /* enable AFE */
1179         regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1180         return 0;
1181
1182 err_bck0:
1183         clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1184 err_top_aud:
1185         clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1186 err_top_aud_bus:
1187         clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1188 err_infra:
1189         clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1190         return ret;
1191 }
1192
1193 static int mtk_afe_init_audio_clk(struct mtk_afe *afe)
1194 {
1195         size_t i;
1196
1197         for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
1198                 afe->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1199                 if (IS_ERR(afe->clocks[i])) {
1200                         dev_err(afe->dev, "%s devm_clk_get %s fail\n",
1201                                 __func__, aud_clks[i]);
1202                         return PTR_ERR(afe->clocks[i]);
1203                 }
1204         }
1205         clk_set_rate(afe->clocks[MTK_CLK_BCK0], 22579200); /* 22M */
1206         clk_set_rate(afe->clocks[MTK_CLK_BCK1], 24576000); /* 24M */
1207         return 0;
1208 }
1209
1210 static int mtk_afe_pcm_dev_probe(struct platform_device *pdev)
1211 {
1212         int ret, i;
1213         unsigned int irq_id;
1214         struct mtk_afe *afe;
1215         struct resource *res;
1216
1217         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
1218         if (ret)
1219                 return ret;
1220
1221         afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1222         if (!afe)
1223                 return -ENOMEM;
1224
1225         afe->dev = &pdev->dev;
1226
1227         irq_id = platform_get_irq(pdev, 0);
1228         if (!irq_id) {
1229                 dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name);
1230                 return -ENXIO;
1231         }
1232         ret = devm_request_irq(afe->dev, irq_id, mtk_afe_irq_handler,
1233                                0, "Afe_ISR_Handle", (void *)afe);
1234         if (ret) {
1235                 dev_err(afe->dev, "could not request_irq\n");
1236                 return ret;
1237         }
1238
1239         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1240         afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
1241         if (IS_ERR(afe->base_addr))
1242                 return PTR_ERR(afe->base_addr);
1243
1244         afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1245                 &mtk_afe_regmap_config);
1246         if (IS_ERR(afe->regmap))
1247                 return PTR_ERR(afe->regmap);
1248
1249         /* initial audio related clock */
1250         ret = mtk_afe_init_audio_clk(afe);
1251         if (ret) {
1252                 dev_err(afe->dev, "mtk_afe_init_audio_clk fail\n");
1253                 return ret;
1254         }
1255
1256         for (i = 0; i < MTK_AFE_MEMIF_NUM; i++)
1257                 afe->memif[i].data = &memif_data[i];
1258
1259         platform_set_drvdata(pdev, afe);
1260
1261         pm_runtime_enable(&pdev->dev);
1262         if (!pm_runtime_enabled(&pdev->dev)) {
1263                 ret = mtk_afe_runtime_resume(&pdev->dev);
1264                 if (ret)
1265                         goto err_pm_disable;
1266         }
1267
1268         ret = snd_soc_register_platform(&pdev->dev, &mtk_afe_pcm_platform);
1269         if (ret)
1270                 goto err_pm_disable;
1271
1272         ret = snd_soc_register_component(&pdev->dev,
1273                                          &mtk_afe_pcm_dai_component,
1274                                          mtk_afe_pcm_dais,
1275                                          ARRAY_SIZE(mtk_afe_pcm_dais));
1276         if (ret)
1277                 goto err_platform;
1278
1279         ret = snd_soc_register_component(&pdev->dev,
1280                                          &mtk_afe_hdmi_dai_component,
1281                                          mtk_afe_hdmi_dais,
1282                                          ARRAY_SIZE(mtk_afe_hdmi_dais));
1283         if (ret)
1284                 goto err_comp;
1285
1286         dev_info(&pdev->dev, "MTK AFE driver initialized.\n");
1287         return 0;
1288
1289 err_comp:
1290         snd_soc_unregister_component(&pdev->dev);
1291 err_platform:
1292         snd_soc_unregister_platform(&pdev->dev);
1293 err_pm_disable:
1294         pm_runtime_disable(&pdev->dev);
1295         return ret;
1296 }
1297
1298 static int mtk_afe_pcm_dev_remove(struct platform_device *pdev)
1299 {
1300         pm_runtime_disable(&pdev->dev);
1301         if (!pm_runtime_status_suspended(&pdev->dev))
1302                 mtk_afe_runtime_suspend(&pdev->dev);
1303         snd_soc_unregister_component(&pdev->dev);
1304         snd_soc_unregister_platform(&pdev->dev);
1305         return 0;
1306 }
1307
1308 static const struct of_device_id mtk_afe_pcm_dt_match[] = {
1309         { .compatible = "mediatek,mt8173-afe-pcm", },
1310         { }
1311 };
1312 MODULE_DEVICE_TABLE(of, mtk_afe_pcm_dt_match);
1313
1314 static const struct dev_pm_ops mtk_afe_pm_ops = {
1315         SET_RUNTIME_PM_OPS(mtk_afe_runtime_suspend, mtk_afe_runtime_resume,
1316                            NULL)
1317 };
1318
1319 static struct platform_driver mtk_afe_pcm_driver = {
1320         .driver = {
1321                    .name = "mtk-afe-pcm",
1322                    .of_match_table = mtk_afe_pcm_dt_match,
1323                    .pm = &mtk_afe_pm_ops,
1324         },
1325         .probe = mtk_afe_pcm_dev_probe,
1326         .remove = mtk_afe_pcm_dev_remove,
1327 };
1328
1329 module_platform_driver(mtk_afe_pcm_driver);
1330
1331 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1332 MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1333 MODULE_LICENSE("GPL v2");