1 /* sound/soc/samsung/hdmi_audio.h
3 * ALSA SoC Audio Layer - Samsung S/PDIF Controller driver
5 * Copyright (c) 2012 Samsung Electronics Co. Ltd
6 * http://www.samsung.com/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __SND_SOC_SAMSUNG_HDMI_AUDIO_H
14 #define __SND_SOC_SAMSUNG_HDMI_AUDIO_H
16 #define BYTE0_CLR (~((u32)0xFF))
22 /* HDMI Version 1.3 & Common */
23 #define HDMI_CORE_BASE(x) ((x) + 0x00010000)
24 #define HDMI_I2S_BASE(x) ((x) + 0x00040000)
27 #define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040)
28 #define HDMI_CON_0 HDMI_CORE_BASE(0x0000)
29 #define HDMI_CON_1 HDMI_CORE_BASE(0x0004)
31 /* Audio related registers */
32 #define HDMI_ASP_CON HDMI_CORE_BASE(0x0300)
33 #define HDMI_ASP_SP_FLAT HDMI_CORE_BASE(0x0304)
34 #define HDMI_ASP_CHCFG0 HDMI_CORE_BASE(0x0310)
35 #define HDMI_ASP_CHCFG1 HDMI_CORE_BASE(0x0314)
36 #define HDMI_ASP_CHCFG2 HDMI_CORE_BASE(0x0318)
37 #define HDMI_ASP_CHCFG3 HDMI_CORE_BASE(0x031C)
39 #define HDMI_ACR_CON HDMI_CORE_BASE(0x0400)
40 #define HDMI_ACR_MCTS0 HDMI_CORE_BASE(0x0410)
41 #define HDMI_ACR_MCTS1 HDMI_CORE_BASE(0x0414)
42 #define HDMI_ACR_MCTS2 HDMI_CORE_BASE(0x0418)
43 #define HDMI_ACR_CTS0 HDMI_CORE_BASE(0x0420)
44 #define HDMI_ACR_CTS1 HDMI_CORE_BASE(0x0424)
45 #define HDMI_ACR_CTS2 HDMI_CORE_BASE(0x0428)
46 #define HDMI_ACR_N0 HDMI_CORE_BASE(0x0430)
47 #define HDMI_ACR_N1 HDMI_CORE_BASE(0x0434)
48 #define HDMI_ACR_N2 HDMI_CORE_BASE(0x0438)
50 /* Packet related registers */
51 #define HDMI_ACP_CON HDMI_CORE_BASE(0x0500)
52 #define HDMI_ACP_TYPE HDMI_CORE_BASE(0x0514)
53 #define HDMI_ACP_DATA(n) HDMI_CORE_BASE(0x0520 + 4 * (n))
55 #define HDMI_ISRC_CON HDMI_CORE_BASE(0x0600)
56 #define HDMI_ISRC1_HEADER1 HDMI_CORE_BASE(0x0614)
57 #define HDMI_ISRC1_DATA(n) HDMI_CORE_BASE(0x0620 + 4 * (n))
58 #define HDMI_ISRC2_DATA(n) HDMI_CORE_BASE(0x06A0 + 4 * (n))
60 #define HDMI_AVI_CON HDMI_CORE_BASE(0x0700)
61 #define HDMI_AVI_HEADER0 HDMI_CORE_BASE(0x0710)
62 #define HDMI_AVI_HEADER1 HDMI_CORE_BASE(0x0714)
63 #define HDMI_AVI_HEADER2 HDMI_CORE_BASE(0x0718)
64 #define HDMI_AVI_CHECK_SUM HDMI_CORE_BASE(0x071C)
65 #define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0720 + 4 * (n-1))
67 #define HDMI_AUI_CON HDMI_CORE_BASE(0x0800)
68 #define HDMI_AUI_HEADER0 HDMI_CORE_BASE(0x0810)
69 #define HDMI_AUI_HEADER1 HDMI_CORE_BASE(0x0814)
70 #define HDMI_AUI_HEADER2 HDMI_CORE_BASE(0x0818)
71 #define HDMI_AUI_CHECK_SUM HDMI_CORE_BASE(0x081C)
72 #define HDMI_AUI_BYTE(n) HDMI_CORE_BASE(0x0820 + 4 * (n-1))
74 #define HDMI_MPG_CON HDMI_CORE_BASE(0x0900)
75 #define HDMI_MPG_CHECK_SUM HDMI_CORE_BASE(0x091C)
76 #define HDMI_MPG_DATA(n) HDMI_CORE_BASE(0x0920 + 4 * (n-1))
78 #define HDMI_SPD_CON HDMI_CORE_BASE(0x0A00)
79 #define HDMI_SPD_HEADER0 HDMI_CORE_BASE(0x0A10)
80 #define HDMI_SPD_HEADER1 HDMI_CORE_BASE(0x0A14)
81 #define HDMI_SPD_HEADER2 HDMI_CORE_BASE(0x0A18)
82 #define HDMI_SPD_DATA(n) HDMI_CORE_BASE(0x0A20 + 4 * (n))
84 #define HDMI_GAMUT_CON HDMI_CORE_BASE(0x0B00)
85 #define HDMI_GAMUT_HEADER0 HDMI_CORE_BASE(0x0B10)
86 #define HDMI_GAMUT_HEADER1 HDMI_CORE_BASE(0x0B14)
87 #define HDMI_GAMUT_HEADER2 HDMI_CORE_BASE(0x0B18)
88 #define HDMI_GAMUT_METADATA(n) HDMI_CORE_BASE(0x0B20 + 4 * (n))
90 #define HDMI_VSI_CON HDMI_CORE_BASE(0x0C00)
91 #define HDMI_VSI_HEADER0 HDMI_CORE_BASE(0x0C10)
92 #define HDMI_VSI_HEADER1 HDMI_CORE_BASE(0x0C14)
93 #define HDMI_VSI_HEADER2 HDMI_CORE_BASE(0x0C18)
94 #define HDMI_VSI_DATA(n) HDMI_CORE_BASE(0x0C20 + 4 * (n))
96 #define HDMI_DC_CONTROL HDMI_CORE_BASE(0x0D00)
97 #define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x0D04)
99 #define HDMI_AN_SEED_SEL HDMI_CORE_BASE(0x0E48)
100 #define HDMI_AN_SEED_0 HDMI_CORE_BASE(0x0E58)
101 #define HDMI_AN_SEED_1 HDMI_CORE_BASE(0x0E5C)
102 #define HDMI_AN_SEED_2 HDMI_CORE_BASE(0x0E60)
103 #define HDMI_AN_SEED_3 HDMI_CORE_BASE(0x0E64)
107 #define HDMI_MODE_HDMI_EN (1 << 1)
108 #define HDMI_MODE_DVI_EN (1 << 0)
109 #define HDMI_DVI_MODE_EN (1)
112 #define HDMI_BLUE_SCR_EN (1 << 5)
113 #define HDMI_ASP_EN (1 << 2)
114 #define HDMI_ASP_DIS (0 << 2)
115 #define HDMI_ASP_MASK (1 << 2)
116 #define HDMI_EN (1 << 0)
119 /* HDMI I2S register */
120 #define HDMI_I2S_CLK_CON HDMI_I2S_BASE(0x000)
121 #define HDMI_I2S_CON_1 HDMI_I2S_BASE(0x004)
122 #define HDMI_I2S_CON_2 HDMI_I2S_BASE(0x008)
123 #define HDMI_I2S_PIN_SEL_0 HDMI_I2S_BASE(0x00c)
124 #define HDMI_I2S_PIN_SEL_1 HDMI_I2S_BASE(0x010)
125 #define HDMI_I2S_PIN_SEL_2 HDMI_I2S_BASE(0x014)
126 #define HDMI_I2S_PIN_SEL_3 HDMI_I2S_BASE(0x018)
127 #define HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c)
128 #define HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020)
129 #define HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024)
130 #define HDMI_I2S_CH_ST_0 HDMI_I2S_BASE(0x028)
131 #define HDMI_I2S_CH_ST_1 HDMI_I2S_BASE(0x02c)
132 #define HDMI_I2S_CH_ST_2 HDMI_I2S_BASE(0x030)
133 #define HDMI_I2S_CH_ST_3 HDMI_I2S_BASE(0x034)
134 #define HDMI_I2S_CH_ST_4 HDMI_I2S_BASE(0x038)
135 #define HDMI_I2S_CH_ST_SH_0 HDMI_I2S_BASE(0x03c)
136 #define HDMI_I2S_CH_ST_SH_1 HDMI_I2S_BASE(0x040)
137 #define HDMI_I2S_CH_ST_SH_2 HDMI_I2S_BASE(0x044)
138 #define HDMI_I2S_CH_ST_SH_3 HDMI_I2S_BASE(0x048)
139 #define HDMI_I2S_CH_ST_SH_4 HDMI_I2S_BASE(0x04c)
140 #define HDMI_I2S_MUX_CH HDMI_I2S_BASE(0x054)
141 #define HDMI_I2S_MUX_CUV HDMI_I2S_BASE(0x058)
143 /* I2S bit definition */
146 #define HDMI_I2S_CLK_DIS (0)
147 #define HDMI_I2S_CLK_EN (1)
150 #define HDMI_I2S_SCLK_FALLING_EDGE (0 << 1)
151 #define HDMI_I2S_SCLK_RISING_EDGE (1 << 1)
152 #define HDMI_I2S_L_CH_LOW_POL (0)
153 #define HDMI_I2S_L_CH_HIGH_POL (1)
156 #define HDMI_I2S_MSB_FIRST_MODE (0 << 6)
157 #define HDMI_I2S_LSB_FIRST_MODE (1 << 6)
158 #define HDMI_I2S_BIT_CH_32FS (0 << 4)
159 #define HDMI_I2S_BIT_CH_48FS (1 << 4)
160 #define HDMI_I2S_BIT_CH_RESERVED (2 << 4)
161 #define HDMI_I2S_SDATA_16BIT (1 << 2)
162 #define HDMI_I2S_SDATA_20BIT (2 << 2)
163 #define HDMI_I2S_SDATA_24BIT (3 << 2)
164 #define HDMI_I2S_BASIC_FORMAT (0)
165 #define HDMI_I2S_L_JUST_FORMAT (2)
166 #define HDMI_I2S_R_JUST_FORMAT (3)
167 #define HDMI_I2S_CON_2_CLR (BYTE0_CLR)
168 #define HDMI_I2S_SET_BIT_CH(x) (((x) & 0x7) << 4)
169 #define HDMI_I2S_SET_SDATA_BIT(x) (((x) & 0x7) << 2)
172 #define HDMI_I2S_SEL_SCLK(x) (((x) & 0x7) << 4)
173 #define HDMI_I2S_SEL_LRCK(x) ((x) & 0x7)
176 #define HDMI_I2S_SEL_SDATA1(x) (((x) & 0x7) << 4)
177 #define HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7)
180 #define HDMI_I2S_SEL_SDATA3(x) (((x) & 0x7) << 4)
181 #define HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7)
184 #define HDMI_I2S_SEL_DSD(x) ((x) & 0x7)
187 #define HDMI_I2S_DSD_CLK_RI_EDGE (1 << 1)
188 #define HDMI_I2S_DSD_CLK_FA_EDGE (0 << 1)
189 #define HDMI_I2S_DSD_ENABLE (1)
190 #define HDMI_I2S_DSD_DISABLE (0)
193 #define HDMI_I2S_NOISE_FILTER_ZERO (0 << 5)
194 #define HDMI_I2S_NOISE_FILTER_2_STAGE (1 << 5)
195 #define HDMI_I2S_NOISE_FILTER_3_STAGE (2 << 5)
196 #define HDMI_I2S_NOISE_FILTER_4_STAGE (3 << 5)
197 #define HDMI_I2S_NOISE_FILTER_5_STAGE (4 << 5)
198 #define HDMI_I2S_IN_DISABLE (1 << 4)
199 #define HDMI_I2S_IN_ENABLE (0 << 4)
200 #define HDMI_I2S_AUD_SPDIF (0 << 2)
201 #define HDMI_I2S_AUD_I2S (1 << 2)
202 #define HDMI_I2S_AUD_DSD (2 << 2)
203 #define HDMI_I2S_CUV_SPDIF_ENABLE (0 << 1)
204 #define HDMI_I2S_CUV_I2S_ENABLE (1 << 1)
205 #define HDMI_I2S_MUX_DISABLE (0)
206 #define HDMI_I2S_MUX_ENABLE (1)
207 #define HDMI_I2S_MUX_CON_CLR (BYTE0_CLR)
210 #define HDMI_I2S_CH_STATUS_RELOAD (1)
211 #define HDMI_I2S_CH_ST_CON_CLR (~(1))
213 /* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */
214 #define HDMI_I2S_CH_STATUS_MODE_0 (0 << 6)
215 #define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH (0 << 3)
216 #define HDMI_I2S_2AUD_CH_WITH_PREEMPH (1 << 3)
217 #define HDMI_I2S_DEFAULT_EMPHASIS (0 << 3)
218 #define HDMI_I2S_COPYRIGHT (0 << 2)
219 #define HDMI_I2S_NO_COPYRIGHT (1 << 2)
220 #define HDMI_I2S_LINEAR_PCM (0 << 1)
221 #define HDMI_I2S_NO_LINEAR_PCM (1 << 1)
222 #define HDMI_I2S_CONSUMER_FORMAT (0)
223 #define HDMI_I2S_PROF_FORMAT (1)
224 #define HDMI_I2S_CH_ST_0_CLR (BYTE0_CLR)
226 /* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */
227 #define HDMI_I2S_CD_PLAYER (0x00)
228 #define HDMI_I2S_DAT_PLAYER (0x03)
229 #define HDMI_I2S_DCC_PLAYER (0x43)
230 #define HDMI_I2S_MINI_DISC_PLAYER (0x49)
232 /* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */
233 #define HDMI_I2S_CHANNEL_NUM_MASK (0xF << 4)
234 #define HDMI_I2S_SOURCE_NUM_MASK (0xF)
235 #define HDMI_I2S_SET_CHANNEL_NUM(x) (((x) & (0xF)) << 4)
236 #define HDMI_I2S_SET_SOURCE_NUM(x) ((x) & (0xF))
238 /* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */
239 #define HDMI_I2S_CLK_ACCUR_LEVEL_1 (1 << 4)
240 #define HDMI_I2S_CLK_ACCUR_LEVEL_2 (0 << 4)
241 #define HDMI_I2S_CLK_ACCUR_LEVEL_3 (2 << 4)
242 #define HDMI_I2S_SMP_FREQ_44_1 (0x0)
243 #define HDMI_I2S_SMP_FREQ_48 (0x2)
244 #define HDMI_I2S_SMP_FREQ_32 (0x3)
245 #define HDMI_I2S_SMP_FREQ_96 (0xA)
246 #define HDMI_I2S_SET_SMP_FREQ(x) ((x) & (0xF))
248 /* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */
249 #define HDMI_I2S_ORG_SMP_FREQ_44_1 (0xF << 4)
250 #define HDMI_I2S_ORG_SMP_FREQ_88_2 (0x7 << 4)
251 #define HDMI_I2S_ORG_SMP_FREQ_22_05 (0xB << 4)
252 #define HDMI_I2S_ORG_SMP_FREQ_176_4 (0x3 << 4)
253 #define HDMI_I2S_WORD_LEN_NOT_DEFINE (0x0 << 1)
254 #define HDMI_I2S_WORD_LEN_MAX24_20BITS (0x1 << 1)
255 #define HDMI_I2S_WORD_LEN_MAX24_22BITS (0x2 << 1)
256 #define HDMI_I2S_WORD_LEN_MAX24_23BITS (0x4 << 1)
257 #define HDMI_I2S_WORD_LEN_MAX24_24BITS (0x5 << 1)
258 #define HDMI_I2S_WORD_LEN_MAX24_21BITS (0x6 << 1)
259 #define HDMI_I2S_WORD_LEN_MAX20_16BITS (0x1 << 1)
260 #define HDMI_I2S_WORD_LEN_MAX20_18BITS (0x2 << 1)
261 #define HDMI_I2S_WORD_LEN_MAX20_19BITS (0x4 << 1)
262 #define HDMI_I2S_WORD_LEN_MAX20_20BITS (0x5 << 1)
263 #define HDMI_I2S_WORD_LEN_MAX20_17BITS (0x6 << 1)
264 #define HDMI_I2S_WORD_LEN_MAX_24BITS (1)
265 #define HDMI_I2S_WORD_LEN_MAX_20BITS (0)
268 #define HDMI_I2S_CH3_R_EN (1 << 7)
269 #define HDMI_I2S_CH3_L_EN (1 << 6)
270 #define HDMI_I2S_CH3_EN (3 << 6)
271 #define HDMI_I2S_CH2_R_EN (1 << 5)
272 #define HDMI_I2S_CH2_L_EN (1 << 4)
273 #define HDMI_I2S_CH2_EN (3 << 4)
274 #define HDMI_I2S_CH1_R_EN (1 << 3)
275 #define HDMI_I2S_CH1_L_EN (1 << 2)
276 #define HDMI_I2S_CH1_EN (3 << 2)
277 #define HDMI_I2S_CH0_R_EN (1 << 1)
278 #define HDMI_I2S_CH0_L_EN (1)
279 #define HDMI_I2S_CH0_EN (3)
280 #define HDMI_I2S_CH_ALL_EN (0xFF)
281 #define HDMI_I2S_MUX_CH_CLR (~(u32)HDMI_I2S_CH_ALL_EN)
284 #define HDMI_I2S_CUV_R_EN (1 << 1)
285 #define HDMI_I2S_CUV_L_EN (1)
286 #define HDMI_I2S_CUV_RL_EN (0x03)
289 #define HDMI_I2S_CUV_R_DATA_MASK (0x7 << 4)
290 #define HDMI_I2S_CUV_L_DATA_MASK (0x7)
292 /* AVI header Info */
293 #define HDMI_AVI_VERSION 0x02
294 #define HDMI_AVI_LENGTH 0x0d
295 #define AVI_ACTIVE_FORMAT_VALID (1 << 4)
296 /* AVI Aspect Ratio */
297 #define AVI_PIC_ASPECT_RATIO_4_3 (1 << 4)
298 #define AVI_PIC_ASPECT_RATIO_16_9 (2 << 4)
299 #define AVI_SAME_AS_PIC_ASPECT_RATIO 8
301 #define HDMI_AVI_CON_DO_NOT_TRANSMIT (0 << 1)
302 #define HDMI_AVI_CON_EVERY_VSYNC (1 << 1)
304 #define HDMI_AUI_VERSION 0x01
305 #define HDMI_AUI_LENGTH 0x0a
307 #define HDMI_AUI_CON_NO_TRAN (0 << 0)
308 #define HDMI_AUI_CON_TRANS_ONCE (1 << 0)
309 #define HDMI_AUI_CON_TRANS_EVERY_VSYNC (2 << 0)
311 #define HDMI_VSI_CON_DO_NOT_TRANSMIT (0 << 0)
312 #define HDMI_VSI_CON_EVERY_VSYNC (1 << 1)
314 #define DEFAULT_RATE (44100)
315 #define DEFAULT_BPS (16)
317 enum HDMI_PACKET_TYPE {
318 /** refer to Table 5-8 Packet Type in HDMI specification v1.4a */
319 /** InfoFrame packet type */
320 HDMI_PACKET_TYPE_INFOFRAME = 0X80,
321 /** Vendor-Specific InfoFrame */
322 HDMI_PACKET_TYPE_VSI = HDMI_PACKET_TYPE_INFOFRAME + 1,
323 /** Auxiliary Video information InfoFrame */
324 HDMI_PACKET_TYPE_AVI = HDMI_PACKET_TYPE_INFOFRAME + 2,
325 /** Audio information InfoFrame */
326 HDMI_PACKET_TYPE_AUI = HDMI_PACKET_TYPE_INFOFRAME + 4
329 struct hdmi_infoframe {
330 enum HDMI_PACKET_TYPE type;
335 struct audio_params {
344 struct hdmi_audio_context {
345 struct platform_device *pdev;
347 struct audio_params params;
348 struct audio_codec_plugin plugin;
351 #endif /* __SND_SOC_SAMSUNG_SPDIF_H */