virt/kvm/arm/vgic/vgic-its.c

   1 /*
   2  * GICv3 ITS emulation
   3  *
   4  * Copyright (C) 2015,2016 ARM Ltd.
   5  * Author: Andre Przywara <andre.przywara@arm.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/cpu.h>
  21 #include <linux/kvm.h>
  22 #include <linux/kvm_host.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/list.h>
  25 #include <linux/uaccess.h>
  26
  27 #include <linux/irqchip/arm-gic-v3.h>
  28
  29 #include <asm/kvm_emulate.h>
  30 #include <asm/kvm_arm.h>
  31 #include <asm/kvm_mmu.h>
  32
  33 #include "vgic.h"
  34 #include "vgic-mmio.h"
  35
  36 struct its_device {
  37         struct list_head dev_list;
  38
  39         /* the head for the list of ITTEs */
  40         struct list_head itt_head;
  41         u32 device_id;
  42 };
  43
  44 #define COLLECTION_NOT_MAPPED ((u32)~0)
  45
  46 struct its_collection {
  47         struct list_head coll_list;
  48
  49         u32 collection_id;
  50         u32 target_addr;
  51 };
  52
  53 #define its_is_collection_mapped(coll) ((coll) && \
  54                                 ((coll)->target_addr != COLLECTION_NOT_MAPPED))
  55
  56 struct its_itte {
  57         struct list_head itte_list;
  58
  59         struct vgic_irq *irq;
  60         struct its_collection *collection;
  61         u32 lpi;
  62         u32 event_id;
  63 };
  64
  65 /*
  66  * We only implement 48 bits of PA at the moment, although the ITS
  67  * supports more. Let's be restrictive here.
  68  */
  69 #define CBASER_ADDRESS(x)       ((x) & GENMASK_ULL(47, 12))
  70 #define PENDBASER_ADDRESS(x)    ((x) & GENMASK_ULL(47, 16))
  71
  72 /*
  73  * Create a snapshot of the current LPI list, so that we can enumerate all
  74  * LPIs without holding any lock.
  75  * Returns the array length and puts the kmalloc'ed array into intid_ptr.
  76  */
  77 static int vgic_copy_lpi_list(struct kvm *kvm, u32 **intid_ptr)
  78 {
  79         struct vgic_dist *dist = &kvm->arch.vgic;
  80         struct vgic_irq *irq;
  81         u32 *intids;
  82         int irq_count = dist->lpi_list_count, i = 0;
  83
  84         /*
  85          * We use the current value of the list length, which may change
  86          * after the kmalloc. We don't care, because the guest shouldn't
  87          * change anything while the command handling is still running,
  88          * and in the worst case we would miss a new IRQ, which one wouldn't
  89          * expect to be covered by this command anyway.
  90          */
  91         intids = kmalloc_array(irq_count, sizeof(intids[0]), GFP_KERNEL);
  92         if (!intids)
  93                 return -ENOMEM;
  94
  95         spin_lock(&dist->lpi_list_lock);
  96         list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
  97                 /* We don't need to "get" the IRQ, as we hold the list lock. */
  98                 intids[i] = irq->intid;
  99                 if (++i == irq_count)
 100                         break;
 101         }
 102         spin_unlock(&dist->lpi_list_lock);
 103
 104         *intid_ptr = intids;
 105         return irq_count;
 106 }
 107
 108 /*
 109  * Scan the whole LPI pending table and sync the pending bit in there
 110  * with our own data structures. This relies on the LPI being
 111  * mapped before.
 112  */
 113 static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
 114 {
 115         gpa_t pendbase = PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 116         struct vgic_irq *irq;
 117         int last_byte_offset = -1;
 118         int ret = 0;
 119         u32 *intids;
 120         int nr_irqs, i;
 121
 122         nr_irqs = vgic_copy_lpi_list(vcpu->kvm, &intids);
 123         if (nr_irqs < 0)
 124                 return nr_irqs;
 125
 126         for (i = 0; i < nr_irqs; i++) {
 127                 int byte_offset, bit_nr;
 128                 u8 pendmask;
 129
 130                 byte_offset = intids[i] / BITS_PER_BYTE;
 131                 bit_nr = intids[i] % BITS_PER_BYTE;
 132
 133                 /*
 134                  * For contiguously allocated LPIs chances are we just read
 135                  * this very same byte in the last iteration. Reuse that.
 136                  */
 137                 if (byte_offset != last_byte_offset) {
 138                         ret = kvm_read_guest(vcpu->kvm, pendbase + byte_offset,
 139                                              &pendmask, 1);
 140                         if (ret) {
 141                                 kfree(intids);
 142                                 return ret;
 143                         }
 144                         last_byte_offset = byte_offset;
 145                 }
 146
 147                 irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);
 148                 spin_lock(&irq->irq_lock);
 149                 irq->pending = pendmask & (1U << bit_nr);
 150                 vgic_queue_irq_unlock(vcpu->kvm, irq);
 151                 vgic_put_irq(vcpu->kvm, irq);
 152         }
 153
 154         kfree(intids);
 155
 156         return ret;
 157 }
 158
 159 static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
 160                                              struct vgic_its *its,
 161                                              gpa_t addr, unsigned int len)
 162 {
 163         u32 reg = 0;
 164
 165         mutex_lock(&its->cmd_lock);
 166         if (its->creadr == its->cwriter)
 167                 reg |= GITS_CTLR_QUIESCENT;
 168         if (its->enabled)
 169                 reg |= GITS_CTLR_ENABLE;
 170         mutex_unlock(&its->cmd_lock);
 171
 172         return reg;
 173 }
 174
 175 static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
 176                                      gpa_t addr, unsigned int len,
 177                                      unsigned long val)
 178 {
 179         its->enabled = !!(val & GITS_CTLR_ENABLE);
 180 }
 181
 182 static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
 183                                               struct vgic_its *its,
 184                                               gpa_t addr, unsigned int len)
 185 {
 186         u64 reg = GITS_TYPER_PLPIS;
 187
 188         /*
 189          * We use linear CPU numbers for redistributor addressing,
 190          * so GITS_TYPER.PTA is 0.
 191          * Also we force all PROPBASER registers to be the same, so
 192          * CommonLPIAff is 0 as well.
 193          * To avoid memory waste in the guest, we keep the number of IDBits and
 194          * DevBits low - as least for the time being.
 195          */
 196         reg |= 0x0f << GITS_TYPER_DEVBITS_SHIFT;
 197         reg |= 0x0f << GITS_TYPER_IDBITS_SHIFT;
 198
 199         return extract_bytes(reg, addr & 7, len);
 200 }
 201
 202 static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
 203                                              struct vgic_its *its,
 204                                              gpa_t addr, unsigned int len)
 205 {
 206         return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
 207 }
 208
 209 static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm,
 210                                                struct vgic_its *its,
 211                                                gpa_t addr, unsigned int len)
 212 {
 213         switch (addr & 0xffff) {
 214         case GITS_PIDR0:
 215                 return 0x92;    /* part number, bits[7:0] */
 216         case GITS_PIDR1:
 217                 return 0xb4;    /* part number, bits[11:8] */
 218         case GITS_PIDR2:
 219                 return GIC_PIDR2_ARCH_GICv3 | 0x0b;
 220         case GITS_PIDR4:
 221                 return 0x40;    /* This is a 64K software visible page */
 222         /* The following are the ID registers for (any) GIC. */
 223         case GITS_CIDR0:
 224                 return 0x0d;
 225         case GITS_CIDR1:
 226                 return 0xf0;
 227         case GITS_CIDR2:
 228                 return 0x05;
 229         case GITS_CIDR3:
 230                 return 0xb1;
 231         }
 232
 233         return 0;
 234 }
 235
 236 /* Requires the its_lock to be held. */
 237 static void its_free_itte(struct kvm *kvm, struct its_itte *itte)
 238 {
 239         list_del(&itte->itte_list);
 240
 241         /* This put matches the get in vgic_add_lpi. */
 242         vgic_put_irq(kvm, itte->irq);
 243
 244         kfree(itte);
 245 }
 246
 247 static int vgic_its_handle_command(struct kvm *kvm, struct vgic_its *its,
 248                                    u64 *its_cmd)
 249 {
 250         return -ENODEV;
 251 }
 252
 253 static u64 vgic_sanitise_its_baser(u64 reg)
 254 {
 255         reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK,
 256                                   GITS_BASER_SHAREABILITY_SHIFT,
 257                                   vgic_sanitise_shareability);
 258         reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK,
 259                                   GITS_BASER_INNER_CACHEABILITY_SHIFT,
 260                                   vgic_sanitise_inner_cacheability);
 261         reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK,
 262                                   GITS_BASER_OUTER_CACHEABILITY_SHIFT,
 263                                   vgic_sanitise_outer_cacheability);
 264
 265         /* Bits 15:12 contain bits 51:48 of the PA, which we don't support. */
 266         reg &= ~GENMASK_ULL(15, 12);
 267
 268         /* We support only one (ITS) page size: 64K */
 269         reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K;
 270
 271         return reg;
 272 }
 273
 274 static u64 vgic_sanitise_its_cbaser(u64 reg)
 275 {
 276         reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK,
 277                                   GITS_CBASER_SHAREABILITY_SHIFT,
 278                                   vgic_sanitise_shareability);
 279         reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK,
 280                                   GITS_CBASER_INNER_CACHEABILITY_SHIFT,
 281                                   vgic_sanitise_inner_cacheability);
 282         reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK,
 283                                   GITS_CBASER_OUTER_CACHEABILITY_SHIFT,
 284                                   vgic_sanitise_outer_cacheability);
 285
 286         /*
 287          * Sanitise the physical address to be 64k aligned.
 288          * Also limit the physical addresses to 48 bits.
 289          */
 290         reg &= ~(GENMASK_ULL(51, 48) | GENMASK_ULL(15, 12));
 291
 292         return reg;
 293 }
 294
 295 static unsigned long vgic_mmio_read_its_cbaser(struct kvm *kvm,
 296                                                struct vgic_its *its,
 297                                                gpa_t addr, unsigned int len)
 298 {
 299         return extract_bytes(its->cbaser, addr & 7, len);
 300 }
 301
 302 static void vgic_mmio_write_its_cbaser(struct kvm *kvm, struct vgic_its *its,
 303                                        gpa_t addr, unsigned int len,
 304                                        unsigned long val)
 305 {
 306         /* When GITS_CTLR.Enable is 1, this register is RO. */
 307         if (its->enabled)
 308                 return;
 309
 310         mutex_lock(&its->cmd_lock);
 311         its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val);
 312         its->cbaser = vgic_sanitise_its_cbaser(its->cbaser);
 313         its->creadr = 0;
 314         /*
 315          * CWRITER is architecturally UNKNOWN on reset, but we need to reset
 316          * it to CREADR to make sure we start with an empty command buffer.
 317          */
 318         its->cwriter = its->creadr;
 319         mutex_unlock(&its->cmd_lock);
 320 }
 321
 322 #define ITS_CMD_BUFFER_SIZE(baser)      ((((baser) & 0xff) + 1) << 12)
 323 #define ITS_CMD_SIZE                    32
 324 #define ITS_CMD_OFFSET(reg)             ((reg) & GENMASK(19, 5))
 325
 326 /*
 327  * By writing to CWRITER the guest announces new commands to be processed.
 328  * To avoid any races in the first place, we take the its_cmd lock, which
 329  * protects our ring buffer variables, so that there is only one user
 330  * per ITS handling commands at a given time.
 331  */
 332 static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
 333                                         gpa_t addr, unsigned int len,
 334                                         unsigned long val)
 335 {
 336         gpa_t cbaser;
 337         u64 cmd_buf[4];
 338         u32 reg;
 339
 340         if (!its)
 341                 return;
 342
 343         mutex_lock(&its->cmd_lock);
 344
 345         reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
 346         reg = ITS_CMD_OFFSET(reg);
 347         if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
 348                 mutex_unlock(&its->cmd_lock);
 349                 return;
 350         }
 351
 352         its->cwriter = reg;
 353         cbaser = CBASER_ADDRESS(its->cbaser);
 354
 355         while (its->cwriter != its->creadr) {
 356                 int ret = kvm_read_guest(kvm, cbaser + its->creadr,
 357                                          cmd_buf, ITS_CMD_SIZE);
 358                 /*
 359                  * If kvm_read_guest() fails, this could be due to the guest
 360                  * programming a bogus value in CBASER or something else going
 361                  * wrong from which we cannot easily recover.
 362                  * According to section 6.3.2 in the GICv3 spec we can just
 363                  * ignore that command then.
 364                  */
 365                 if (!ret)
 366                         vgic_its_handle_command(kvm, its, cmd_buf);
 367
 368                 its->creadr += ITS_CMD_SIZE;
 369                 if (its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser))
 370                         its->creadr = 0;
 371         }
 372
 373         mutex_unlock(&its->cmd_lock);
 374 }
 375
 376 static unsigned long vgic_mmio_read_its_cwriter(struct kvm *kvm,
 377                                                 struct vgic_its *its,
 378                                                 gpa_t addr, unsigned int len)
 379 {
 380         return extract_bytes(its->cwriter, addr & 0x7, len);
 381 }
 382
 383 static unsigned long vgic_mmio_read_its_creadr(struct kvm *kvm,
 384                                                struct vgic_its *its,
 385                                                gpa_t addr, unsigned int len)
 386 {
 387         return extract_bytes(its->creadr, addr & 0x7, len);
 388 }
 389
 390 #define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7)
 391 static unsigned long vgic_mmio_read_its_baser(struct kvm *kvm,
 392                                               struct vgic_its *its,
 393                                               gpa_t addr, unsigned int len)
 394 {
 395         u64 reg;
 396
 397         switch (BASER_INDEX(addr)) {
 398         case 0:
 399                 reg = its->baser_device_table;
 400                 break;
 401         case 1:
 402                 reg = its->baser_coll_table;
 403                 break;
 404         default:
 405                 reg = 0;
 406                 break;
 407         }
 408
 409         return extract_bytes(reg, addr & 7, len);
 410 }
 411
 412 #define GITS_BASER_RO_MASK      (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56))
 413 static void vgic_mmio_write_its_baser(struct kvm *kvm,
 414                                       struct vgic_its *its,
 415                                       gpa_t addr, unsigned int len,
 416                                       unsigned long val)
 417 {
 418         u64 entry_size, device_type;
 419         u64 reg, *regptr, clearbits = 0;
 420
 421         /* When GITS_CTLR.Enable is 1, we ignore write accesses. */
 422         if (its->enabled)
 423                 return;
 424
 425         switch (BASER_INDEX(addr)) {
 426         case 0:
 427                 regptr = &its->baser_device_table;
 428                 entry_size = 8;
 429                 device_type = GITS_BASER_TYPE_DEVICE;
 430                 break;
 431         case 1:
 432                 regptr = &its->baser_coll_table;
 433                 entry_size = 8;
 434                 device_type = GITS_BASER_TYPE_COLLECTION;
 435                 clearbits = GITS_BASER_INDIRECT;
 436                 break;
 437         default:
 438                 return;
 439         }
 440
 441         reg = update_64bit_reg(*regptr, addr & 7, len, val);
 442         reg &= ~GITS_BASER_RO_MASK;
 443         reg &= ~clearbits;
 444
 445         reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT;
 446         reg |= device_type << GITS_BASER_TYPE_SHIFT;
 447         reg = vgic_sanitise_its_baser(reg);
 448
 449         *regptr = reg;
 450 }
 451
 452 #define REGISTER_ITS_DESC(off, rd, wr, length, acc)             \
 453 {                                                               \
 454         .reg_offset = off,                                      \
 455         .len = length,                                          \
 456         .access_flags = acc,                                    \
 457         .its_read = rd,                                         \
 458         .its_write = wr,                                        \
 459 }
 460
 461 static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
 462                               gpa_t addr, unsigned int len, unsigned long val)
 463 {
 464         /* Ignore */
 465 }
 466
 467 static struct vgic_register_region its_registers[] = {
 468         REGISTER_ITS_DESC(GITS_CTLR,
 469                 vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
 470                 VGIC_ACCESS_32bit),
 471         REGISTER_ITS_DESC(GITS_IIDR,
 472                 vgic_mmio_read_its_iidr, its_mmio_write_wi, 4,
 473                 VGIC_ACCESS_32bit),
 474         REGISTER_ITS_DESC(GITS_TYPER,
 475                 vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
 476                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 477         REGISTER_ITS_DESC(GITS_CBASER,
 478                 vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8,
 479                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 480         REGISTER_ITS_DESC(GITS_CWRITER,
 481                 vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
 482                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 483         REGISTER_ITS_DESC(GITS_CREADR,
 484                 vgic_mmio_read_its_creadr, its_mmio_write_wi, 8,
 485                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 486         REGISTER_ITS_DESC(GITS_BASER,
 487                 vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
 488                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 489         REGISTER_ITS_DESC(GITS_IDREGS_BASE,
 490                 vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30,
 491                 VGIC_ACCESS_32bit),
 492 };
 493
 494 /* This is called on setting the LPI enable bit in the redistributor. */
 495 void vgic_enable_lpis(struct kvm_vcpu *vcpu)
 496 {
 497         if (!(vcpu->arch.vgic_cpu.pendbaser & GICR_PENDBASER_PTZ))
 498                 its_sync_lpi_pending_table(vcpu);
 499 }
 500
 501 static int vgic_its_init_its(struct kvm *kvm, struct vgic_its *its)
 502 {
 503         struct vgic_io_device *iodev = &its->iodev;
 504         int ret;
 505
 506         if (its->initialized)
 507                 return 0;
 508
 509         if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base))
 510                 return -ENXIO;
 511
 512         iodev->regions = its_registers;
 513         iodev->nr_regions = ARRAY_SIZE(its_registers);
 514         kvm_iodevice_init(&iodev->dev, &kvm_io_gic_ops);
 515
 516         iodev->base_addr = its->vgic_its_base;
 517         iodev->iodev_type = IODEV_ITS;
 518         iodev->its = its;
 519         mutex_lock(&kvm->slots_lock);
 520         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, iodev->base_addr,
 521                                       KVM_VGIC_V3_ITS_SIZE, &iodev->dev);
 522         mutex_unlock(&kvm->slots_lock);
 523
 524         if (!ret)
 525                 its->initialized = true;
 526
 527         return ret;
 528 }
 529
 530 #define INITIAL_BASER_VALUE                                               \
 531         (GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb)                | \
 532          GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner)         | \
 533          GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)             | \
 534          ((8ULL - 1) << GITS_BASER_ENTRY_SIZE_SHIFT)                    | \
 535          GITS_BASER_PAGE_SIZE_64K)
 536
 537 #define INITIAL_PROPBASER_VALUE                                           \
 538         (GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb)            | \
 539          GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, SameAsInner)     | \
 540          GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable))
 541
 542 static int vgic_its_create(struct kvm_device *dev, u32 type)
 543 {
 544         struct vgic_its *its;
 545
 546         if (type != KVM_DEV_TYPE_ARM_VGIC_ITS)
 547                 return -ENODEV;
 548
 549         its = kzalloc(sizeof(struct vgic_its), GFP_KERNEL);
 550         if (!its)
 551                 return -ENOMEM;
 552
 553         mutex_init(&its->its_lock);
 554         mutex_init(&its->cmd_lock);
 555
 556         its->vgic_its_base = VGIC_ADDR_UNDEF;
 557
 558         INIT_LIST_HEAD(&its->device_list);
 559         INIT_LIST_HEAD(&its->collection_list);
 560
 561         dev->kvm->arch.vgic.has_its = true;
 562         its->initialized = false;
 563         its->enabled = false;
 564
 565         its->baser_device_table = INITIAL_BASER_VALUE                   |
 566                 ((u64)GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT);
 567         its->baser_coll_table = INITIAL_BASER_VALUE |
 568                 ((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT);
 569         dev->kvm->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE;
 570
 571         dev->private = its;
 572
 573         return 0;
 574 }
 575
 576 static void vgic_its_destroy(struct kvm_device *kvm_dev)
 577 {
 578         struct kvm *kvm = kvm_dev->kvm;
 579         struct vgic_its *its = kvm_dev->private;
 580         struct its_device *dev;
 581         struct its_itte *itte;
 582         struct list_head *dev_cur, *dev_temp;
 583         struct list_head *cur, *temp;
 584
 585         /*
 586          * We may end up here without the lists ever having been initialized.
 587          * Check this and bail out early to avoid dereferencing a NULL pointer.
 588          */
 589         if (!its->device_list.next)
 590                 return;
 591
 592         mutex_lock(&its->its_lock);
 593         list_for_each_safe(dev_cur, dev_temp, &its->device_list) {
 594                 dev = container_of(dev_cur, struct its_device, dev_list);
 595                 list_for_each_safe(cur, temp, &dev->itt_head) {
 596                         itte = (container_of(cur, struct its_itte, itte_list));
 597                         its_free_itte(kvm, itte);
 598                 }
 599                 list_del(dev_cur);
 600                 kfree(dev);
 601         }
 602
 603         list_for_each_safe(cur, temp, &its->collection_list) {
 604                 list_del(cur);
 605                 kfree(container_of(cur, struct its_collection, coll_list));
 606         }
 607         mutex_unlock(&its->its_lock);
 608
 609         kfree(its);
 610 }
 611
 612 static int vgic_its_has_attr(struct kvm_device *dev,
 613                              struct kvm_device_attr *attr)
 614 {
 615         switch (attr->group) {
 616         case KVM_DEV_ARM_VGIC_GRP_ADDR:
 617                 switch (attr->attr) {
 618                 case KVM_VGIC_ITS_ADDR_TYPE:
 619                         return 0;
 620                 }
 621                 break;
 622         case KVM_DEV_ARM_VGIC_GRP_CTRL:
 623                 switch (attr->attr) {
 624                 case KVM_DEV_ARM_VGIC_CTRL_INIT:
 625                         return 0;
 626                 }
 627                 break;
 628         }
 629         return -ENXIO;
 630 }
 631
 632 static int vgic_its_set_attr(struct kvm_device *dev,
 633                              struct kvm_device_attr *attr)
 634 {
 635         struct vgic_its *its = dev->private;
 636         int ret;
 637
 638         switch (attr->group) {
 639         case KVM_DEV_ARM_VGIC_GRP_ADDR: {
 640                 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
 641                 unsigned long type = (unsigned long)attr->attr;
 642                 u64 addr;
 643
 644                 if (type != KVM_VGIC_ITS_ADDR_TYPE)
 645                         return -ENODEV;
 646
 647                 if (its->initialized)
 648                         return -EBUSY;
 649
 650                 if (copy_from_user(&addr, uaddr, sizeof(addr)))
 651                         return -EFAULT;
 652
 653                 ret = vgic_check_ioaddr(dev->kvm, &its->vgic_its_base,
 654                                         addr, SZ_64K);
 655                 if (ret)
 656                         return ret;
 657
 658                 its->vgic_its_base = addr;
 659
 660                 return 0;
 661         }
 662         case KVM_DEV_ARM_VGIC_GRP_CTRL:
 663                 switch (attr->attr) {
 664                 case KVM_DEV_ARM_VGIC_CTRL_INIT:
 665                         return vgic_its_init_its(dev->kvm, its);
 666                 }
 667                 break;
 668         }
 669         return -ENXIO;
 670 }
 671
 672 static int vgic_its_get_attr(struct kvm_device *dev,
 673                              struct kvm_device_attr *attr)
 674 {
 675         switch (attr->group) {
 676         case KVM_DEV_ARM_VGIC_GRP_ADDR: {
 677                 struct vgic_its *its = dev->private;
 678                 u64 addr = its->vgic_its_base;
 679                 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
 680                 unsigned long type = (unsigned long)attr->attr;
 681
 682                 if (type != KVM_VGIC_ITS_ADDR_TYPE)
 683                         return -ENODEV;
 684
 685                 if (copy_to_user(uaddr, &addr, sizeof(addr)))
 686                         return -EFAULT;
 687                 break;
 688         default:
 689                 return -ENXIO;
 690         }
 691         }
 692
 693         return 0;
 694 }
 695
 696 static struct kvm_device_ops kvm_arm_vgic_its_ops = {
 697         .name = "kvm-arm-vgic-its",
 698         .create = vgic_its_create,
 699         .destroy = vgic_its_destroy,
 700         .set_attr = vgic_its_set_attr,
 701         .get_attr = vgic_its_get_attr,
 702         .has_attr = vgic_its_has_attr,
 703 };
 704
 705 int kvm_vgic_register_its_device(void)
 706 {
 707         return kvm_register_device_ops(&kvm_arm_vgic_its_ops,
 708                                        KVM_DEV_TYPE_ARM_VGIC_ITS);
 709 }