virt/kvm/arm/vgic/vgic-mmio.h

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __KVM_ARM_VGIC_MMIO_H__
  17 #define __KVM_ARM_VGIC_MMIO_H__
  18
  19 struct vgic_register_region {
  20         unsigned int reg_offset;
  21         unsigned int len;
  22         unsigned int bits_per_irq;
  23         unsigned int access_flags;
  24         unsigned long (*read)(struct kvm_vcpu *vcpu, gpa_t addr,
  25                               unsigned int len);
  26         void (*write)(struct kvm_vcpu *vcpu, gpa_t addr, unsigned int len,
  27                       unsigned long val);
  28 };
  29
  30 extern struct kvm_io_device_ops kvm_io_gic_ops;
  31
  32 #define VGIC_ACCESS_8bit        1
  33 #define VGIC_ACCESS_32bit       2
  34 #define VGIC_ACCESS_64bit       4
  35
  36 /*
  37  * Generate a mask that covers the number of bytes required to address
  38  * up to 1024 interrupts, each represented by <bits> bits. This assumes
  39  * that <bits> is a power of two.
  40  */
  41 #define VGIC_ADDR_IRQ_MASK(bits) (((bits) * 1024 / 8) - 1)
  42
  43 /*
  44  * (addr & mask) gives us the byte offset for the INT ID, so we want to
  45  * divide this with 'bytes per irq' to get the INT ID, which is given
  46  * by '(bits) / 8'.  But we do this with fixed-point-arithmetic and
  47  * take advantage of the fact that division by a fraction equals
  48  * multiplication with the inverted fraction, and scale up both the
  49  * numerator and denominator with 8 to support at most 64 bits per IRQ:
  50  */
  51 #define VGIC_ADDR_TO_INTID(addr, bits)  (((addr) & VGIC_ADDR_IRQ_MASK(bits)) * \
  52                                         64 / (bits) / 8)
  53
  54 /*
  55  * Some VGIC registers store per-IRQ information, with a different number
  56  * of bits per IRQ. For those registers this macro is used.
  57  * The _WITH_LENGTH version instantiates registers with a fixed length
  58  * and is mutually exclusive with the _PER_IRQ version.
  59  */
  60 #define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, bpi, acc)          \
  61         {                                                               \
  62                 .reg_offset = off,                                      \
  63                 .bits_per_irq = bpi,                                    \
  64                 .len = bpi * 1024 / 8,                                  \
  65                 .access_flags = acc,                                    \
  66                 .read = rd,                                             \
  67                 .write = wr,                                            \
  68         }
  69
  70 #define REGISTER_DESC_WITH_LENGTH(off, rd, wr, length, acc)             \
  71         {                                                               \
  72                 .reg_offset = off,                                      \
  73                 .bits_per_irq = 0,                                      \
  74                 .len = length,                                          \
  75                 .access_flags = acc,                                    \
  76                 .read = rd,                                             \
  77                 .write = wr,                                            \
  78         }
  79
  80 int kvm_vgic_register_mmio_region(struct kvm *kvm, struct kvm_vcpu *vcpu,
  81                                   struct vgic_register_region *reg_desc,
  82                                   struct vgic_io_device *region,
  83                                   int nr_irqs, bool offset_private);
  84
  85 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len);
  86
  87 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
  88                                 unsigned long data);
  89
  90 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
  91                                  gpa_t addr, unsigned int len);
  92
  93 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
  94                                  gpa_t addr, unsigned int len);
  95
  96 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
  97                         unsigned int len, unsigned long val);
  98
  99 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
 100                                     gpa_t addr, unsigned int len);
 101
 102 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
 103                              gpa_t addr, unsigned int len,
 104                              unsigned long val);
 105
 106 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
 107                              gpa_t addr, unsigned int len,
 108                              unsigned long val);
 109
 110 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
 111                                      gpa_t addr, unsigned int len);
 112
 113 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
 114                               gpa_t addr, unsigned int len,
 115                               unsigned long val);
 116
 117 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
 118                               gpa_t addr, unsigned int len,
 119                               unsigned long val);
 120
 121 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
 122                                     gpa_t addr, unsigned int len);
 123
 124 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
 125                              gpa_t addr, unsigned int len,
 126                              unsigned long val);
 127
 128 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
 129                              gpa_t addr, unsigned int len,
 130                              unsigned long val);
 131
 132 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
 133                                       gpa_t addr, unsigned int len);
 134
 135 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
 136                               gpa_t addr, unsigned int len,
 137                               unsigned long val);
 138
 139 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
 140                                     gpa_t addr, unsigned int len);
 141
 142 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
 143                             gpa_t addr, unsigned int len,
 144                             unsigned long val);
 145
 146 unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
 147
 148 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
 149
 150 #endif