virt/kvm/arm/vgic/vgic-v2.c

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/irqchip/arm-gic.h>
  18 #include <linux/kvm.h>
  19 #include <linux/kvm_host.h>
  20 #include <kvm/arm_vgic.h>
  21 #include <asm/kvm_mmu.h>
  22
  23 #include "vgic.h"
  24
  25 /*
  26  * Call this function to convert a u64 value to an unsigned long * bitmask
  27  * in a way that works on both 32-bit and 64-bit LE and BE platforms.
  28  *
  29  * Warning: Calling this function may modify *val.
  30  */
  31 static unsigned long *u64_to_bitmask(u64 *val)
  32 {
  33 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
  34         *val = (*val >> 32) | (*val << 32);
  35 #endif
  36         return (unsigned long *)val;
  37 }
  38
  39 void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu)
  40 {
  41         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  42
  43         if (cpuif->vgic_misr & GICH_MISR_EOI) {
  44                 u64 eisr = cpuif->vgic_eisr;
  45                 unsigned long *eisr_bmap = u64_to_bitmask(&eisr);
  46                 int lr;
  47
  48                 for_each_set_bit(lr, eisr_bmap, kvm_vgic_global_state.nr_lr) {
  49                         u32 intid = cpuif->vgic_lr[lr] & GICH_LR_VIRTUALID;
  50
  51                         WARN_ON(cpuif->vgic_lr[lr] & GICH_LR_STATE);
  52
  53                         kvm_notify_acked_irq(vcpu->kvm, 0,
  54                                              intid - VGIC_NR_PRIVATE_IRQS);
  55                 }
  56         }
  57
  58         /* check and disable underflow maintenance IRQ */
  59         cpuif->vgic_hcr &= ~GICH_HCR_UIE;
  60
  61         /*
  62          * In the next iterations of the vcpu loop, if we sync the
  63          * vgic state after flushing it, but before entering the guest
  64          * (this happens for pending signals and vmid rollovers), then
  65          * make sure we don't pick up any old maintenance interrupts
  66          * here.
  67          */
  68         cpuif->vgic_eisr = 0;
  69 }
  70
  71 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
  72 {
  73         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  74
  75         cpuif->vgic_hcr |= GICH_HCR_UIE;
  76 }
  77
  78 /*
  79  * transfer the content of the LRs back into the corresponding ap_list:
  80  * - active bit is transferred as is
  81  * - pending bit is
  82  *   - transferred as is in case of edge sensitive IRQs
  83  *   - set to the line-level (resample time) for level sensitive IRQs
  84  */
  85 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
  86 {
  87         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  88         int lr;
  89
  90         for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
  91                 u32 val = cpuif->vgic_lr[lr];
  92                 u32 intid = val & GICH_LR_VIRTUALID;
  93                 struct vgic_irq *irq;
  94
  95                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  96
  97                 spin_lock(&irq->irq_lock);
  98
  99                 /* Always preserve the active bit */
 100                 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
 101
 102                 /* Edge is the only case where we preserve the pending bit */
 103                 if (irq->config == VGIC_CONFIG_EDGE &&
 104                     (val & GICH_LR_PENDING_BIT)) {
 105                         irq->pending = true;
 106
 107                         if (vgic_irq_is_sgi(intid)) {
 108                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
 109
 110                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
 111                                 irq->source |= (1 << cpuid);
 112                         }
 113                 }
 114
 115                 /*
 116                  * Clear soft pending state when level irqs have been acked.
 117                  * Always regenerate the pending state.
 118                  */
 119                 if (irq->config == VGIC_CONFIG_LEVEL) {
 120                         if (!(val & GICH_LR_PENDING_BIT))
 121                                 irq->soft_pending = false;
 122
 123                         irq->pending = irq->line_level || irq->soft_pending;
 124                 }
 125
 126                 spin_unlock(&irq->irq_lock);
 127                 vgic_put_irq(vcpu->kvm, irq);
 128         }
 129 }
 130
 131 /*
 132  * Populates the particular LR with the state of a given IRQ:
 133  * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
 134  * - for a level sensitive IRQ the pending state value is unchanged;
 135  *   it is dictated directly by the input level
 136  *
 137  * If @irq describes an SGI with multiple sources, we choose the
 138  * lowest-numbered source VCPU and clear that bit in the source bitmap.
 139  *
 140  * The irq_lock must be held by the caller.
 141  */
 142 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 143 {
 144         u32 val = irq->intid;
 145
 146         if (irq->pending) {
 147                 val |= GICH_LR_PENDING_BIT;
 148
 149                 if (irq->config == VGIC_CONFIG_EDGE)
 150                         irq->pending = false;
 151
 152                 if (vgic_irq_is_sgi(irq->intid)) {
 153                         u32 src = ffs(irq->source);
 154
 155                         BUG_ON(!src);
 156                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 157                         irq->source &= ~(1 << (src - 1));
 158                         if (irq->source)
 159                                 irq->pending = true;
 160                 }
 161         }
 162
 163         if (irq->active)
 164                 val |= GICH_LR_ACTIVE_BIT;
 165
 166         if (irq->hw) {
 167                 val |= GICH_LR_HW;
 168                 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
 169         } else {
 170                 if (irq->config == VGIC_CONFIG_LEVEL)
 171                         val |= GICH_LR_EOI;
 172         }
 173
 174         /* The GICv2 LR only holds five bits of priority. */
 175         val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
 176
 177         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
 178 }
 179
 180 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
 181 {
 182         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
 183 }
 184
 185 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 186 {
 187         u32 vmcr;
 188
 189         vmcr  = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
 190         vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
 191                 GICH_VMCR_ALIAS_BINPOINT_MASK;
 192         vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
 193                 GICH_VMCR_BINPOINT_MASK;
 194         vmcr |= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) &
 195                 GICH_VMCR_PRIMASK_MASK;
 196
 197         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;
 198 }
 199
 200 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 201 {
 202         u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr;
 203
 204         vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >>
 205                         GICH_VMCR_CTRL_SHIFT;
 206         vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
 207                         GICH_VMCR_ALIAS_BINPOINT_SHIFT;
 208         vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
 209                         GICH_VMCR_BINPOINT_SHIFT;
 210         vmcrp->pmr  = (vmcr & GICH_VMCR_PRIMASK_MASK) >>
 211                         GICH_VMCR_PRIMASK_SHIFT;
 212 }
 213
 214 void vgic_v2_enable(struct kvm_vcpu *vcpu)
 215 {
 216         /*
 217          * By forcing VMCR to zero, the GIC will restore the binary
 218          * points to their reset values. Anything else resets to zero
 219          * anyway.
 220          */
 221         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
 222         vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
 223
 224         /* Get the show on the road... */
 225         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
 226 }
 227
 228 /* check for overlapping regions and for regions crossing the end of memory */
 229 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
 230 {
 231         if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
 232                 return false;
 233         if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
 234                 return false;
 235
 236         if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
 237                 return true;
 238         if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
 239                 return true;
 240
 241         return false;
 242 }
 243
 244 int vgic_v2_map_resources(struct kvm *kvm)
 245 {
 246         struct vgic_dist *dist = &kvm->arch.vgic;
 247         int ret = 0;
 248
 249         if (vgic_ready(kvm))
 250                 goto out;
 251
 252         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 253             IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
 254                 kvm_err("Need to set vgic cpu and dist addresses first\n");
 255                 ret = -ENXIO;
 256                 goto out;
 257         }
 258
 259         if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
 260                 kvm_err("VGIC CPU and dist frames overlap\n");
 261                 ret = -EINVAL;
 262                 goto out;
 263         }
 264
 265         /*
 266          * Initialize the vgic if this hasn't already been done on demand by
 267          * accessing the vgic state from userspace.
 268          */
 269         ret = vgic_init(kvm);
 270         if (ret) {
 271                 kvm_err("Unable to initialize VGIC dynamic data structures\n");
 272                 goto out;
 273         }
 274
 275         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
 276         if (ret) {
 277                 kvm_err("Unable to register VGIC MMIO regions\n");
 278                 goto out;
 279         }
 280
 281         ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
 282                                     kvm_vgic_global_state.vcpu_base,
 283                                     KVM_VGIC_V2_CPU_SIZE, true);
 284         if (ret) {
 285                 kvm_err("Unable to remap VGIC CPU to VCPU\n");
 286                 goto out;
 287         }
 288
 289         dist->ready = true;
 290
 291 out:
 292         if (ret)
 293                 kvm_vgic_destroy(kvm);
 294         return ret;
 295 }
 296
 297 /**
 298  * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 299  * @node:       pointer to the DT node
 300  *
 301  * Returns 0 if a GICv2 has been found, returns an error code otherwise
 302  */
 303 int vgic_v2_probe(const struct gic_kvm_info *info)
 304 {
 305         int ret;
 306         u32 vtr;
 307
 308         if (!info->vctrl.start) {
 309                 kvm_err("GICH not present in the firmware table\n");
 310                 return -ENXIO;
 311         }
 312
 313         if (!PAGE_ALIGNED(info->vcpu.start)) {
 314                 kvm_err("GICV physical address 0x%llx not page aligned\n",
 315                         (unsigned long long)info->vcpu.start);
 316                 return -ENXIO;
 317         }
 318
 319         if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
 320                 kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n",
 321                         (unsigned long long)resource_size(&info->vcpu),
 322                         PAGE_SIZE);
 323                 return -ENXIO;
 324         }
 325
 326         kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
 327                                                    resource_size(&info->vctrl));
 328         if (!kvm_vgic_global_state.vctrl_base) {
 329                 kvm_err("Cannot ioremap GICH\n");
 330                 return -ENOMEM;
 331         }
 332
 333         vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
 334         kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
 335
 336         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 337         if (ret) {
 338                 kvm_err("Cannot register GICv2 KVM device\n");
 339                 iounmap(kvm_vgic_global_state.vctrl_base);
 340                 return ret;
 341         }
 342
 343         ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
 344                                      kvm_vgic_global_state.vctrl_base +
 345                                          resource_size(&info->vctrl),
 346                                      info->vctrl.start);
 347         if (ret) {
 348                 kvm_err("Cannot map VCTRL into hyp\n");
 349                 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
 350                 iounmap(kvm_vgic_global_state.vctrl_base);
 351                 return ret;
 352         }
 353
 354         kvm_vgic_global_state.can_emulate_gicv2 = true;
 355         kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 356         kvm_vgic_global_state.type = VGIC_V2;
 357         kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
 358
 359         kvm_info("vgic-v2@%llx\n", info->vctrl.start);
 360
 361         return 0;
 362 }