virt/kvm/arm/vgic-v3.c

   1 /*
   2  * Copyright (C) 2013 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/cpu.h>
  19 #include <linux/kvm.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23
  24 #include <linux/irqchip/arm-gic-v3.h>
  25 #include <linux/irqchip/arm-gic-common.h>
  26
  27 #include <asm/kvm_emulate.h>
  28 #include <asm/kvm_arm.h>
  29 #include <asm/kvm_asm.h>
  30 #include <asm/kvm_mmu.h>
  31
  32 static u32 ich_vtr_el2;
  33
  34 static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
  35 {
  36         struct vgic_lr lr_desc;
  37         u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr];
  38
  39         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
  40                 lr_desc.irq = val & ICH_LR_VIRTUAL_ID_MASK;
  41         else
  42                 lr_desc.irq = val & GICH_LR_VIRTUALID;
  43
  44         lr_desc.source = 0;
  45         if (lr_desc.irq <= 15 &&
  46             vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2)
  47                 lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
  48
  49         lr_desc.state = 0;
  50
  51         if (val & ICH_LR_PENDING_BIT)
  52                 lr_desc.state |= LR_STATE_PENDING;
  53         if (val & ICH_LR_ACTIVE_BIT)
  54                 lr_desc.state |= LR_STATE_ACTIVE;
  55         if (val & ICH_LR_EOI)
  56                 lr_desc.state |= LR_EOI_INT;
  57         if (val & ICH_LR_HW) {
  58                 lr_desc.state |= LR_HW;
  59                 lr_desc.hwirq = (val >> ICH_LR_PHYS_ID_SHIFT) & GENMASK(9, 0);
  60         }
  61
  62         return lr_desc;
  63 }
  64
  65 static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
  66                            struct vgic_lr lr_desc)
  67 {
  68         u64 lr_val;
  69
  70         lr_val = lr_desc.irq;
  71
  72         /*
  73          * Currently all guest IRQs are Group1, as Group0 would result
  74          * in a FIQ in the guest, which it wouldn't expect.
  75          * Eventually we want to make this configurable, so we may revisit
  76          * this in the future.
  77          */
  78         switch (vcpu->kvm->arch.vgic.vgic_model) {
  79         case KVM_DEV_TYPE_ARM_VGIC_V3:
  80                 lr_val |= ICH_LR_GROUP;
  81                 break;
  82         case  KVM_DEV_TYPE_ARM_VGIC_V2:
  83                 if (lr_desc.irq < VGIC_NR_SGIS)
  84                         lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
  85                 break;
  86         default:
  87                 BUG();
  88         }
  89
  90         if (lr_desc.state & LR_STATE_PENDING)
  91                 lr_val |= ICH_LR_PENDING_BIT;
  92         if (lr_desc.state & LR_STATE_ACTIVE)
  93                 lr_val |= ICH_LR_ACTIVE_BIT;
  94         if (lr_desc.state & LR_EOI_INT)
  95                 lr_val |= ICH_LR_EOI;
  96         if (lr_desc.state & LR_HW) {
  97                 lr_val |= ICH_LR_HW;
  98                 lr_val |= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;
  99         }
 100
 101         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = lr_val;
 102
 103         if (!(lr_desc.state & LR_STATE_MASK))
 104                 vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr |= (1U << lr);
 105         else
 106                 vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr &= ~(1U << lr);
 107 }
 108
 109 static u64 vgic_v3_get_elrsr(const struct kvm_vcpu *vcpu)
 110 {
 111         return vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr;
 112 }
 113
 114 static u64 vgic_v3_get_eisr(const struct kvm_vcpu *vcpu)
 115 {
 116         return vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr;
 117 }
 118
 119 static void vgic_v3_clear_eisr(struct kvm_vcpu *vcpu)
 120 {
 121         vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr = 0;
 122 }
 123
 124 static u32 vgic_v3_get_interrupt_status(const struct kvm_vcpu *vcpu)
 125 {
 126         u32 misr = vcpu->arch.vgic_cpu.vgic_v3.vgic_misr;
 127         u32 ret = 0;
 128
 129         if (misr & ICH_MISR_EOI)
 130                 ret |= INT_STATUS_EOI;
 131         if (misr & ICH_MISR_U)
 132                 ret |= INT_STATUS_UNDERFLOW;
 133
 134         return ret;
 135 }
 136
 137 static void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 138 {
 139         u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
 140
 141         vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
 142         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 143         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 144         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 145 }
 146
 147 static void vgic_v3_enable_underflow(struct kvm_vcpu *vcpu)
 148 {
 149         vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr |= ICH_HCR_UIE;
 150 }
 151
 152 static void vgic_v3_disable_underflow(struct kvm_vcpu *vcpu)
 153 {
 154         vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr &= ~ICH_HCR_UIE;
 155 }
 156
 157 static void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 158 {
 159         u32 vmcr;
 160
 161         vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
 162         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 163         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 164         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
 165
 166         vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
 167 }
 168
 169 static void vgic_v3_enable(struct kvm_vcpu *vcpu)
 170 {
 171         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 172
 173         /*
 174          * By forcing VMCR to zero, the GIC will restore the binary
 175          * points to their reset values. Anything else resets to zero
 176          * anyway.
 177          */
 178         vgic_v3->vgic_vmcr = 0;
 179         vgic_v3->vgic_elrsr = ~0;
 180
 181         /*
 182          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
 183          * way, so we force SRE to 1 to demonstrate this to the guest.
 184          * This goes with the spec allowing the value to be RAO/WI.
 185          */
 186         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
 187                 vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
 188         else
 189                 vgic_v3->vgic_sre = 0;
 190
 191         /* Get the show on the road... */
 192         vgic_v3->vgic_hcr = ICH_HCR_EN;
 193 }
 194
 195 static const struct vgic_ops vgic_v3_ops = {
 196         .get_lr                 = vgic_v3_get_lr,
 197         .set_lr                 = vgic_v3_set_lr,
 198         .get_elrsr              = vgic_v3_get_elrsr,
 199         .get_eisr               = vgic_v3_get_eisr,
 200         .clear_eisr             = vgic_v3_clear_eisr,
 201         .get_interrupt_status   = vgic_v3_get_interrupt_status,
 202         .enable_underflow       = vgic_v3_enable_underflow,
 203         .disable_underflow      = vgic_v3_disable_underflow,
 204         .get_vmcr               = vgic_v3_get_vmcr,
 205         .set_vmcr               = vgic_v3_set_vmcr,
 206         .enable                 = vgic_v3_enable,
 207 };
 208
 209 static struct vgic_params vgic_v3_params;
 210
 211 static void vgic_cpu_init_lrs(void *params)
 212 {
 213         kvm_call_hyp(__vgic_v3_init_lrs);
 214 }
 215
 216 /**
 217  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller
 218  * @gic_kvm_info:       pointer to the GIC description
 219  * @ops:                address of a pointer to the GICv3 operations
 220  * @params:             address of a pointer to HW-specific parameters
 221  *
 222  * Returns 0 if a GICv3 has been found, with the low level operations
 223  * in *ops and the HW parameters in *params. Returns an error code
 224  * otherwise.
 225  */
 226 int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info,
 227                   const struct vgic_ops **ops,
 228                   const struct vgic_params **params)
 229 {
 230         int ret = 0;
 231         struct vgic_params *vgic = &vgic_v3_params;
 232         const struct resource *vcpu_res = &gic_kvm_info->vcpu;
 233
 234         vgic->maint_irq = gic_kvm_info->maint_irq;
 235
 236         ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
 237
 238         /*
 239          * The ListRegs field is 5 bits, but there is a architectural
 240          * maximum of 16 list registers. Just ignore bit 4...
 241          */
 242         vgic->nr_lr = (ich_vtr_el2 & 0xf) + 1;
 243         vgic->can_emulate_gicv2 = false;
 244
 245         if (!vcpu_res->start) {
 246                 kvm_info("GICv3: no GICV resource entry\n");
 247                 vgic->vcpu_base = 0;
 248         } else if (!PAGE_ALIGNED(vcpu_res->start)) {
 249                 pr_warn("GICV physical address 0x%llx not page aligned\n",
 250                         (unsigned long long)vcpu_res->start);
 251                 vgic->vcpu_base = 0;
 252         } else if (!PAGE_ALIGNED(resource_size(vcpu_res))) {
 253                 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
 254                         (unsigned long long)resource_size(vcpu_res),
 255                         PAGE_SIZE);
 256         } else {
 257                 vgic->vcpu_base = vcpu_res->start;
 258                 vgic->can_emulate_gicv2 = true;
 259                 kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
 260                                         KVM_DEV_TYPE_ARM_VGIC_V2);
 261         }
 262         if (vgic->vcpu_base == 0)
 263                 kvm_info("disabling GICv2 emulation\n");
 264         kvm_register_device_ops(&kvm_arm_vgic_v3_ops, KVM_DEV_TYPE_ARM_VGIC_V3);
 265
 266         vgic->vctrl_base = NULL;
 267         vgic->type = VGIC_V3;
 268         vgic->max_gic_vcpus = VGIC_V3_MAX_CPUS;
 269
 270         kvm_info("GICV base=0x%llx, IRQ=%d\n",
 271                  vgic->vcpu_base, vgic->maint_irq);
 272
 273         on_each_cpu(vgic_cpu_init_lrs, vgic, 1);
 274
 275         *ops = &vgic_v3_ops;
 276         *params = vgic;
 277
 278         return ret;
 279 }