virt/kvm/arm/vgic.c

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17  */
  18
  19 #include <linux/cpu.h>
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_host.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/uaccess.h>
  28
  29 #include <linux/irqchip/arm-gic.h>
  30
  31 #include <asm/kvm_emulate.h>
  32 #include <asm/kvm_arm.h>
  33 #include <asm/kvm_mmu.h>
  34
  35 /*
  36  * How the whole thing works (courtesy of Christoffer Dall):
  37  *
  38  * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
  39  *   something is pending
  40  * - VGIC pending interrupts are stored on the vgic.irq_state vgic
  41  *   bitmap (this bitmap is updated by both user land ioctls and guest
  42  *   mmio ops, and other in-kernel peripherals such as the
  43  *   arch. timers) and indicate the 'wire' state.
  44  * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
  45  *   recalculated
  46  * - To calculate the oracle, we need info for each cpu from
  47  *   compute_pending_for_cpu, which considers:
  48  *   - PPI: dist->irq_state & dist->irq_enable
  49  *   - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
  50  *   - irq_spi_target is a 'formatted' version of the GICD_ICFGR
  51  *     registers, stored on each vcpu. We only keep one bit of
  52  *     information per interrupt, making sure that only one vcpu can
  53  *     accept the interrupt.
  54  * - The same is true when injecting an interrupt, except that we only
  55  *   consider a single interrupt at a time. The irq_spi_cpu array
  56  *   contains the target CPU for each SPI.
  57  *
  58  * The handling of level interrupts adds some extra complexity. We
  59  * need to track when the interrupt has been EOIed, so we can sample
  60  * the 'line' again. This is achieved as such:
  61  *
  62  * - When a level interrupt is moved onto a vcpu, the corresponding
  63  *   bit in irq_active is set. As long as this bit is set, the line
  64  *   will be ignored for further interrupts. The interrupt is injected
  65  *   into the vcpu with the GICH_LR_EOI bit set (generate a
  66  *   maintenance interrupt on EOI).
  67  * - When the interrupt is EOIed, the maintenance interrupt fires,
  68  *   and clears the corresponding bit in irq_active. This allow the
  69  *   interrupt line to be sampled again.
  70  */
  71
  72 #define VGIC_ADDR_UNDEF         (-1)
  73 #define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)
  74
  75 #define PRODUCT_ID_KVM          0x4b    /* ASCII code K */
  76 #define IMPLEMENTER_ARM         0x43b
  77 #define GICC_ARCH_VERSION_V2    0x2
  78
  79 /* Physical address of vgic virtual cpu interface */
  80 static phys_addr_t vgic_vcpu_base;
  81
  82 /* Virtual control interface base address */
  83 static void __iomem *vgic_vctrl_base;
  84
  85 static struct device_node *vgic_node;
  86
  87 #define ACCESS_READ_VALUE       (1 << 0)
  88 #define ACCESS_READ_RAZ         (0 << 0)
  89 #define ACCESS_READ_MASK(x)     ((x) & (1 << 0))
  90 #define ACCESS_WRITE_IGNORED    (0 << 1)
  91 #define ACCESS_WRITE_SETBIT     (1 << 1)
  92 #define ACCESS_WRITE_CLEARBIT   (2 << 1)
  93 #define ACCESS_WRITE_VALUE      (3 << 1)
  94 #define ACCESS_WRITE_MASK(x)    ((x) & (3 << 1))
  95
  96 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
  97 static void vgic_update_state(struct kvm *kvm);
  98 static void vgic_kick_vcpus(struct kvm *kvm);
  99 static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
 100 static u32 vgic_nr_lr;
 101
 102 static unsigned int vgic_maint_irq;
 103
 104 static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
 105                                 int cpuid, u32 offset)
 106 {
 107         offset >>= 2;
 108         if (!offset)
 109                 return x->percpu[cpuid].reg;
 110         else
 111                 return x->shared.reg + offset - 1;
 112 }
 113
 114 static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
 115                                    int cpuid, int irq)
 116 {
 117         if (irq < VGIC_NR_PRIVATE_IRQS)
 118                 return test_bit(irq, x->percpu[cpuid].reg_ul);
 119
 120         return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul);
 121 }
 122
 123 static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
 124                                     int irq, int val)
 125 {
 126         unsigned long *reg;
 127
 128         if (irq < VGIC_NR_PRIVATE_IRQS) {
 129                 reg = x->percpu[cpuid].reg_ul;
 130         } else {
 131                 reg =  x->shared.reg_ul;
 132                 irq -= VGIC_NR_PRIVATE_IRQS;
 133         }
 134
 135         if (val)
 136                 set_bit(irq, reg);
 137         else
 138                 clear_bit(irq, reg);
 139 }
 140
 141 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
 142 {
 143         if (unlikely(cpuid >= VGIC_MAX_CPUS))
 144                 return NULL;
 145         return x->percpu[cpuid].reg_ul;
 146 }
 147
 148 static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
 149 {
 150         return x->shared.reg_ul;
 151 }
 152
 153 static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
 154 {
 155         offset >>= 2;
 156         BUG_ON(offset > (VGIC_NR_IRQS / 4));
 157         if (offset < 8)
 158                 return x->percpu[cpuid] + offset;
 159         else
 160                 return x->shared + offset - 8;
 161 }
 162
 163 #define VGIC_CFG_LEVEL  0
 164 #define VGIC_CFG_EDGE   1
 165
 166 static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
 167 {
 168         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 169         int irq_val;
 170
 171         irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
 172         return irq_val == VGIC_CFG_EDGE;
 173 }
 174
 175 static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
 176 {
 177         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 178
 179         return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
 180 }
 181
 182 static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
 183 {
 184         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 185
 186         return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
 187 }
 188
 189 static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
 190 {
 191         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 192
 193         vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
 194 }
 195
 196 static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
 197 {
 198         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 199
 200         vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
 201 }
 202
 203 static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
 204 {
 205         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 206
 207         return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq);
 208 }
 209
 210 static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq)
 211 {
 212         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 213
 214         vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 1);
 215 }
 216
 217 static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq)
 218 {
 219         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 220
 221         vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 0);
 222 }
 223
 224 static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
 225 {
 226         if (irq < VGIC_NR_PRIVATE_IRQS)
 227                 set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
 228         else
 229                 set_bit(irq - VGIC_NR_PRIVATE_IRQS,
 230                         vcpu->arch.vgic_cpu.pending_shared);
 231 }
 232
 233 static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
 234 {
 235         if (irq < VGIC_NR_PRIVATE_IRQS)
 236                 clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
 237         else
 238                 clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
 239                           vcpu->arch.vgic_cpu.pending_shared);
 240 }
 241
 242 static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
 243 {
 244         return *((u32 *)mmio->data) & mask;
 245 }
 246
 247 static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
 248 {
 249         *((u32 *)mmio->data) = value & mask;
 250 }
 251
 252 /**
 253  * vgic_reg_access - access vgic register
 254  * @mmio:   pointer to the data describing the mmio access
 255  * @reg:    pointer to the virtual backing of vgic distributor data
 256  * @offset: least significant 2 bits used for word offset
 257  * @mode:   ACCESS_ mode (see defines above)
 258  *
 259  * Helper to make vgic register access easier using one of the access
 260  * modes defined for vgic register access
 261  * (read,raz,write-ignored,setbit,clearbit,write)
 262  */
 263 static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
 264                             phys_addr_t offset, int mode)
 265 {
 266         int word_offset = (offset & 3) * 8;
 267         u32 mask = (1UL << (mmio->len * 8)) - 1;
 268         u32 regval;
 269
 270         /*
 271          * Any alignment fault should have been delivered to the guest
 272          * directly (ARM ARM B3.12.7 "Prioritization of aborts").
 273          */
 274
 275         if (reg) {
 276                 regval = *reg;
 277         } else {
 278                 BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
 279                 regval = 0;
 280         }
 281
 282         if (mmio->is_write) {
 283                 u32 data = mmio_data_read(mmio, mask) << word_offset;
 284                 switch (ACCESS_WRITE_MASK(mode)) {
 285                 case ACCESS_WRITE_IGNORED:
 286                         return;
 287
 288                 case ACCESS_WRITE_SETBIT:
 289                         regval |= data;
 290                         break;
 291
 292                 case ACCESS_WRITE_CLEARBIT:
 293                         regval &= ~data;
 294                         break;
 295
 296                 case ACCESS_WRITE_VALUE:
 297                         regval = (regval & ~(mask << word_offset)) | data;
 298                         break;
 299                 }
 300                 *reg = regval;
 301         } else {
 302                 switch (ACCESS_READ_MASK(mode)) {
 303                 case ACCESS_READ_RAZ:
 304                         regval = 0;
 305                         /* fall through */
 306
 307                 case ACCESS_READ_VALUE:
 308                         mmio_data_write(mmio, mask, regval >> word_offset);
 309                 }
 310         }
 311 }
 312
 313 static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
 314                              struct kvm_exit_mmio *mmio, phys_addr_t offset)
 315 {
 316         u32 reg;
 317         u32 word_offset = offset & 3;
 318
 319         switch (offset & ~3) {
 320         case 0:                 /* GICD_CTLR */
 321                 reg = vcpu->kvm->arch.vgic.enabled;
 322                 vgic_reg_access(mmio, &reg, word_offset,
 323                                 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
 324                 if (mmio->is_write) {
 325                         vcpu->kvm->arch.vgic.enabled = reg & 1;
 326                         vgic_update_state(vcpu->kvm);
 327                         return true;
 328                 }
 329                 break;
 330
 331         case 4:                 /* GICD_TYPER */
 332                 reg  = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
 333                 reg |= (VGIC_NR_IRQS >> 5) - 1;
 334                 vgic_reg_access(mmio, &reg, word_offset,
 335                                 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
 336                 break;
 337
 338         case 8:                 /* GICD_IIDR */
 339                 reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
 340                 vgic_reg_access(mmio, &reg, word_offset,
 341                                 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
 342                 break;
 343         }
 344
 345         return false;
 346 }
 347
 348 static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
 349                                struct kvm_exit_mmio *mmio, phys_addr_t offset)
 350 {
 351         vgic_reg_access(mmio, NULL, offset,
 352                         ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
 353         return false;
 354 }
 355
 356 static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
 357                                        struct kvm_exit_mmio *mmio,
 358                                        phys_addr_t offset)
 359 {
 360         u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
 361                                        vcpu->vcpu_id, offset);
 362         vgic_reg_access(mmio, reg, offset,
 363                         ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
 364         if (mmio->is_write) {
 365                 vgic_update_state(vcpu->kvm);
 366                 return true;
 367         }
 368
 369         return false;
 370 }
 371
 372 static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
 373                                          struct kvm_exit_mmio *mmio,
 374                                          phys_addr_t offset)
 375 {
 376         u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
 377                                        vcpu->vcpu_id, offset);
 378         vgic_reg_access(mmio, reg, offset,
 379                         ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
 380         if (mmio->is_write) {
 381                 if (offset < 4) /* Force SGI enabled */
 382                         *reg |= 0xffff;
 383                 vgic_retire_disabled_irqs(vcpu);
 384                 vgic_update_state(vcpu->kvm);
 385                 return true;
 386         }
 387
 388         return false;
 389 }
 390
 391 static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
 392                                         struct kvm_exit_mmio *mmio,
 393                                         phys_addr_t offset)
 394 {
 395         u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
 396                                        vcpu->vcpu_id, offset);
 397         vgic_reg_access(mmio, reg, offset,
 398                         ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
 399         if (mmio->is_write) {
 400                 vgic_update_state(vcpu->kvm);
 401                 return true;
 402         }
 403
 404         return false;
 405 }
 406
 407 static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
 408                                           struct kvm_exit_mmio *mmio,
 409                                           phys_addr_t offset)
 410 {
 411         u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
 412                                        vcpu->vcpu_id, offset);
 413         vgic_reg_access(mmio, reg, offset,
 414                         ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
 415         if (mmio->is_write) {
 416                 vgic_update_state(vcpu->kvm);
 417                 return true;
 418         }
 419
 420         return false;
 421 }
 422
 423 static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
 424                                      struct kvm_exit_mmio *mmio,
 425                                      phys_addr_t offset)
 426 {
 427         u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
 428                                         vcpu->vcpu_id, offset);
 429         vgic_reg_access(mmio, reg, offset,
 430                         ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
 431         return false;
 432 }
 433
 434 #define GICD_ITARGETSR_SIZE     32
 435 #define GICD_CPUTARGETS_BITS    8
 436 #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
 437 static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
 438 {
 439         struct vgic_dist *dist = &kvm->arch.vgic;
 440         int i;
 441         u32 val = 0;
 442
 443         irq -= VGIC_NR_PRIVATE_IRQS;
 444
 445         for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
 446                 val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8);
 447
 448         return val;
 449 }
 450
 451 static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
 452 {
 453         struct vgic_dist *dist = &kvm->arch.vgic;
 454         struct kvm_vcpu *vcpu;
 455         int i, c;
 456         unsigned long *bmap;
 457         u32 target;
 458
 459         irq -= VGIC_NR_PRIVATE_IRQS;
 460
 461         /*
 462          * Pick the LSB in each byte. This ensures we target exactly
 463          * one vcpu per IRQ. If the byte is null, assume we target
 464          * CPU0.
 465          */
 466         for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
 467                 int shift = i * GICD_CPUTARGETS_BITS;
 468                 target = ffs((val >> shift) & 0xffU);
 469                 target = target ? (target - 1) : 0;
 470                 dist->irq_spi_cpu[irq + i] = target;
 471                 kvm_for_each_vcpu(c, vcpu, kvm) {
 472                         bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
 473                         if (c == target)
 474                                 set_bit(irq + i, bmap);
 475                         else
 476                                 clear_bit(irq + i, bmap);
 477                 }
 478         }
 479 }
 480
 481 static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
 482                                    struct kvm_exit_mmio *mmio,
 483                                    phys_addr_t offset)
 484 {
 485         u32 reg;
 486
 487         /* We treat the banked interrupts targets as read-only */
 488         if (offset < 32) {
 489                 u32 roreg = 1 << vcpu->vcpu_id;
 490                 roreg |= roreg << 8;
 491                 roreg |= roreg << 16;
 492
 493                 vgic_reg_access(mmio, &roreg, offset,
 494                                 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
 495                 return false;
 496         }
 497
 498         reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
 499         vgic_reg_access(mmio, &reg, offset,
 500                         ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
 501         if (mmio->is_write) {
 502                 vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
 503                 vgic_update_state(vcpu->kvm);
 504                 return true;
 505         }
 506
 507         return false;
 508 }
 509
 510 static u32 vgic_cfg_expand(u16 val)
 511 {
 512         u32 res = 0;
 513         int i;
 514
 515         /*
 516          * Turn a 16bit value like abcd...mnop into a 32bit word
 517          * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
 518          */
 519         for (i = 0; i < 16; i++)
 520                 res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
 521
 522         return res;
 523 }
 524
 525 static u16 vgic_cfg_compress(u32 val)
 526 {
 527         u16 res = 0;
 528         int i;
 529
 530         /*
 531          * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
 532          * abcd...mnop which is what we really care about.
 533          */
 534         for (i = 0; i < 16; i++)
 535                 res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
 536
 537         return res;
 538 }
 539
 540 /*
 541  * The distributor uses 2 bits per IRQ for the CFG register, but the
 542  * LSB is always 0. As such, we only keep the upper bit, and use the
 543  * two above functions to compress/expand the bits
 544  */
 545 static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
 546                                 struct kvm_exit_mmio *mmio, phys_addr_t offset)
 547 {
 548         u32 val;
 549         u32 *reg;
 550
 551         offset >>= 1;
 552         reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
 553                                   vcpu->vcpu_id, offset);
 554
 555         if (offset & 2)
 556                 val = *reg >> 16;
 557         else
 558                 val = *reg & 0xffff;
 559
 560         val = vgic_cfg_expand(val);
 561         vgic_reg_access(mmio, &val, offset,
 562                         ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
 563         if (mmio->is_write) {
 564                 if (offset < 4) {
 565                         *reg = ~0U; /* Force PPIs/SGIs to 1 */
 566                         return false;
 567                 }
 568
 569                 val = vgic_cfg_compress(val);
 570                 if (offset & 2) {
 571                         *reg &= 0xffff;
 572                         *reg |= val << 16;
 573                 } else {
 574                         *reg &= 0xffff << 16;
 575                         *reg |= val;
 576                 }
 577         }
 578
 579         return false;
 580 }
 581
 582 static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
 583                                 struct kvm_exit_mmio *mmio, phys_addr_t offset)
 584 {
 585         u32 reg;
 586         vgic_reg_access(mmio, &reg, offset,
 587                         ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
 588         if (mmio->is_write) {
 589                 vgic_dispatch_sgi(vcpu, reg);
 590                 vgic_update_state(vcpu->kvm);
 591                 return true;
 592         }
 593
 594         return false;
 595 }
 596
 597 #define LR_CPUID(lr)    \
 598         (((lr) & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT)
 599 #define LR_IRQID(lr)    \
 600         ((lr) & GICH_LR_VIRTUALID)
 601
 602 static void vgic_retire_lr(int lr_nr, int irq, struct vgic_cpu *vgic_cpu)
 603 {
 604         clear_bit(lr_nr, vgic_cpu->lr_used);
 605         vgic_cpu->vgic_lr[lr_nr] &= ~GICH_LR_STATE;
 606         vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
 607 }
 608
 609 /**
 610  * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor
 611  * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
 612  *
 613  * Move any pending IRQs that have already been assigned to LRs back to the
 614  * emulated distributor state so that the complete emulated state can be read
 615  * from the main emulation structures without investigating the LRs.
 616  *
 617  * Note that IRQs in the active state in the LRs get their pending state moved
 618  * to the distributor but the active state stays in the LRs, because we don't
 619  * track the active state on the distributor side.
 620  */
 621 static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
 622 {
 623         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 624         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 625         int vcpu_id = vcpu->vcpu_id;
 626         int i, irq, source_cpu;
 627         u32 *lr;
 628
 629         for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
 630                 lr = &vgic_cpu->vgic_lr[i];
 631                 irq = LR_IRQID(*lr);
 632                 source_cpu = LR_CPUID(*lr);
 633
 634                 /*
 635                  * There are three options for the state bits:
 636                  *
 637                  * 01: pending
 638                  * 10: active
 639                  * 11: pending and active
 640                  *
 641                  * If the LR holds only an active interrupt (not pending) then
 642                  * just leave it alone.
 643                  */
 644                 if ((*lr & GICH_LR_STATE) == GICH_LR_ACTIVE_BIT)
 645                         continue;
 646
 647                 /*
 648                  * Reestablish the pending state on the distributor and the
 649                  * CPU interface.  It may have already been pending, but that
 650                  * is fine, then we are only setting a few bits that were
 651                  * already set.
 652                  */
 653                 vgic_dist_irq_set(vcpu, irq);
 654                 if (irq < VGIC_NR_SGIS)
 655                         dist->irq_sgi_sources[vcpu_id][irq] |= 1 << source_cpu;
 656                 *lr &= ~GICH_LR_PENDING_BIT;
 657
 658                 /*
 659                  * If there's no state left on the LR (it could still be
 660                  * active), then the LR does not hold any useful info and can
 661                  * be marked as free for other use.
 662                  */
 663                 if (!(*lr & GICH_LR_STATE))
 664                         vgic_retire_lr(i, irq, vgic_cpu);
 665
 666                 /* Finally update the VGIC state. */
 667                 vgic_update_state(vcpu->kvm);
 668         }
 669 }
 670
 671 /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */
 672 static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
 673                                         struct kvm_exit_mmio *mmio,
 674                                         phys_addr_t offset)
 675 {
 676         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 677         int sgi;
 678         int min_sgi = (offset & ~0x3) * 4;
 679         int max_sgi = min_sgi + 3;
 680         int vcpu_id = vcpu->vcpu_id;
 681         u32 reg = 0;
 682
 683         /* Copy source SGIs from distributor side */
 684         for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
 685                 int shift = 8 * (sgi - min_sgi);
 686                 reg |= (u32)dist->irq_sgi_sources[vcpu_id][sgi] << shift;
 687         }
 688
 689         mmio_data_write(mmio, ~0, reg);
 690         return false;
 691 }
 692
 693 static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
 694                                          struct kvm_exit_mmio *mmio,
 695                                          phys_addr_t offset, bool set)
 696 {
 697         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 698         int sgi;
 699         int min_sgi = (offset & ~0x3) * 4;
 700         int max_sgi = min_sgi + 3;
 701         int vcpu_id = vcpu->vcpu_id;
 702         u32 reg;
 703         bool updated = false;
 704
 705         reg = mmio_data_read(mmio, ~0);
 706
 707         /* Clear pending SGIs on the distributor */
 708         for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
 709                 u8 mask = reg >> (8 * (sgi - min_sgi));
 710                 if (set) {
 711                         if ((dist->irq_sgi_sources[vcpu_id][sgi] & mask) != mask)
 712                                 updated = true;
 713                         dist->irq_sgi_sources[vcpu_id][sgi] |= mask;
 714                 } else {
 715                         if (dist->irq_sgi_sources[vcpu_id][sgi] & mask)
 716                                 updated = true;
 717                         dist->irq_sgi_sources[vcpu_id][sgi] &= ~mask;
 718                 }
 719         }
 720
 721         if (updated)
 722                 vgic_update_state(vcpu->kvm);
 723
 724         return updated;
 725 }
 726
 727 static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu,
 728                                 struct kvm_exit_mmio *mmio,
 729                                 phys_addr_t offset)
 730 {
 731         if (!mmio->is_write)
 732                 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
 733         else
 734                 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true);
 735 }
 736
 737 static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu,
 738                                   struct kvm_exit_mmio *mmio,
 739                                   phys_addr_t offset)
 740 {
 741         if (!mmio->is_write)
 742                 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
 743         else
 744                 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false);
 745 }
 746
 747 /*
 748  * I would have liked to use the kvm_bus_io_*() API instead, but it
 749  * cannot cope with banked registers (only the VM pointer is passed
 750  * around, and we need the vcpu). One of these days, someone please
 751  * fix it!
 752  */
 753 struct mmio_range {
 754         phys_addr_t base;
 755         unsigned long len;
 756         bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
 757                             phys_addr_t offset);
 758 };
 759
 760 static const struct mmio_range vgic_dist_ranges[] = {
 761         {
 762                 .base           = GIC_DIST_CTRL,
 763                 .len            = 12,
 764                 .handle_mmio    = handle_mmio_misc,
 765         },
 766         {
 767                 .base           = GIC_DIST_IGROUP,
 768                 .len            = VGIC_NR_IRQS / 8,
 769                 .handle_mmio    = handle_mmio_raz_wi,
 770         },
 771         {
 772                 .base           = GIC_DIST_ENABLE_SET,
 773                 .len            = VGIC_NR_IRQS / 8,
 774                 .handle_mmio    = handle_mmio_set_enable_reg,
 775         },
 776         {
 777                 .base           = GIC_DIST_ENABLE_CLEAR,
 778                 .len            = VGIC_NR_IRQS / 8,
 779                 .handle_mmio    = handle_mmio_clear_enable_reg,
 780         },
 781         {
 782                 .base           = GIC_DIST_PENDING_SET,
 783                 .len            = VGIC_NR_IRQS / 8,
 784                 .handle_mmio    = handle_mmio_set_pending_reg,
 785         },
 786         {
 787                 .base           = GIC_DIST_PENDING_CLEAR,
 788                 .len            = VGIC_NR_IRQS / 8,
 789                 .handle_mmio    = handle_mmio_clear_pending_reg,
 790         },
 791         {
 792                 .base           = GIC_DIST_ACTIVE_SET,
 793                 .len            = VGIC_NR_IRQS / 8,
 794                 .handle_mmio    = handle_mmio_raz_wi,
 795         },
 796         {
 797                 .base           = GIC_DIST_ACTIVE_CLEAR,
 798                 .len            = VGIC_NR_IRQS / 8,
 799                 .handle_mmio    = handle_mmio_raz_wi,
 800         },
 801         {
 802                 .base           = GIC_DIST_PRI,
 803                 .len            = VGIC_NR_IRQS,
 804                 .handle_mmio    = handle_mmio_priority_reg,
 805         },
 806         {
 807                 .base           = GIC_DIST_TARGET,
 808                 .len            = VGIC_NR_IRQS,
 809                 .handle_mmio    = handle_mmio_target_reg,
 810         },
 811         {
 812                 .base           = GIC_DIST_CONFIG,
 813                 .len            = VGIC_NR_IRQS / 4,
 814                 .handle_mmio    = handle_mmio_cfg_reg,
 815         },
 816         {
 817                 .base           = GIC_DIST_SOFTINT,
 818                 .len            = 4,
 819                 .handle_mmio    = handle_mmio_sgi_reg,
 820         },
 821         {
 822                 .base           = GIC_DIST_SGI_PENDING_CLEAR,
 823                 .len            = VGIC_NR_SGIS,
 824                 .handle_mmio    = handle_mmio_sgi_clear,
 825         },
 826         {
 827                 .base           = GIC_DIST_SGI_PENDING_SET,
 828                 .len            = VGIC_NR_SGIS,
 829                 .handle_mmio    = handle_mmio_sgi_set,
 830         },
 831         {}
 832 };
 833
 834 static const
 835 struct mmio_range *find_matching_range(const struct mmio_range *ranges,
 836                                        struct kvm_exit_mmio *mmio,
 837                                        phys_addr_t offset)
 838 {
 839         const struct mmio_range *r = ranges;
 840
 841         while (r->len) {
 842                 if (offset >= r->base &&
 843                     (offset + mmio->len) <= (r->base + r->len))
 844                         return r;
 845                 r++;
 846         }
 847
 848         return NULL;
 849 }
 850
 851 /**
 852  * vgic_handle_mmio - handle an in-kernel MMIO access
 853  * @vcpu:       pointer to the vcpu performing the access
 854  * @run:        pointer to the kvm_run structure
 855  * @mmio:       pointer to the data describing the access
 856  *
 857  * returns true if the MMIO access has been performed in kernel space,
 858  * and false if it needs to be emulated in user space.
 859  */
 860 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
 861                       struct kvm_exit_mmio *mmio)
 862 {
 863         const struct mmio_range *range;
 864         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 865         unsigned long base = dist->vgic_dist_base;
 866         bool updated_state;
 867         unsigned long offset;
 868
 869         if (!irqchip_in_kernel(vcpu->kvm) ||
 870             mmio->phys_addr < base ||
 871             (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
 872                 return false;
 873
 874         /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
 875         if (mmio->len > 4) {
 876                 kvm_inject_dabt(vcpu, mmio->phys_addr);
 877                 return true;
 878         }
 879
 880         offset = mmio->phys_addr - base;
 881         range = find_matching_range(vgic_dist_ranges, mmio, offset);
 882         if (unlikely(!range || !range->handle_mmio)) {
 883                 pr_warn("Unhandled access %d %08llx %d\n",
 884                         mmio->is_write, mmio->phys_addr, mmio->len);
 885                 return false;
 886         }
 887
 888         spin_lock(&vcpu->kvm->arch.vgic.lock);
 889         offset = mmio->phys_addr - range->base - base;
 890         updated_state = range->handle_mmio(vcpu, mmio, offset);
 891         spin_unlock(&vcpu->kvm->arch.vgic.lock);
 892         kvm_prepare_mmio(run, mmio);
 893         kvm_handle_mmio_return(vcpu, run);
 894
 895         if (updated_state)
 896                 vgic_kick_vcpus(vcpu->kvm);
 897
 898         return true;
 899 }
 900
 901 static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
 902 {
 903         struct kvm *kvm = vcpu->kvm;
 904         struct vgic_dist *dist = &kvm->arch.vgic;
 905         int nrcpus = atomic_read(&kvm->online_vcpus);
 906         u8 target_cpus;
 907         int sgi, mode, c, vcpu_id;
 908
 909         vcpu_id = vcpu->vcpu_id;
 910
 911         sgi = reg & 0xf;
 912         target_cpus = (reg >> 16) & 0xff;
 913         mode = (reg >> 24) & 3;
 914
 915         switch (mode) {
 916         case 0:
 917                 if (!target_cpus)
 918                         return;
 919                 break;
 920
 921         case 1:
 922                 target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
 923                 break;
 924
 925         case 2:
 926                 target_cpus = 1 << vcpu_id;
 927                 break;
 928         }
 929
 930         kvm_for_each_vcpu(c, vcpu, kvm) {
 931                 if (target_cpus & 1) {
 932                         /* Flag the SGI as pending */
 933                         vgic_dist_irq_set(vcpu, sgi);
 934                         dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id;
 935                         kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
 936                 }
 937
 938                 target_cpus >>= 1;
 939         }
 940 }
 941
 942 static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
 943 {
 944         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 945         unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
 946         unsigned long pending_private, pending_shared;
 947         int vcpu_id;
 948
 949         vcpu_id = vcpu->vcpu_id;
 950         pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
 951         pend_shared = vcpu->arch.vgic_cpu.pending_shared;
 952
 953         pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id);
 954         enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
 955         bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
 956
 957         pending = vgic_bitmap_get_shared_map(&dist->irq_state);
 958         enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
 959         bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS);
 960         bitmap_and(pend_shared, pend_shared,
 961                    vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
 962                    VGIC_NR_SHARED_IRQS);
 963
 964         pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
 965         pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS);
 966         return (pending_private < VGIC_NR_PRIVATE_IRQS ||
 967                 pending_shared < VGIC_NR_SHARED_IRQS);
 968 }
 969
 970 /*
 971  * Update the interrupt state and determine which CPUs have pending
 972  * interrupts. Must be called with distributor lock held.
 973  */
 974 static void vgic_update_state(struct kvm *kvm)
 975 {
 976         struct vgic_dist *dist = &kvm->arch.vgic;
 977         struct kvm_vcpu *vcpu;
 978         int c;
 979
 980         if (!dist->enabled) {
 981                 set_bit(0, &dist->irq_pending_on_cpu);
 982                 return;
 983         }
 984
 985         kvm_for_each_vcpu(c, vcpu, kvm) {
 986                 if (compute_pending_for_cpu(vcpu)) {
 987                         pr_debug("CPU%d has pending interrupts\n", c);
 988                         set_bit(c, &dist->irq_pending_on_cpu);
 989                 }
 990         }
 991 }
 992
 993 #define MK_LR_PEND(src, irq)    \
 994         (GICH_LR_PENDING_BIT | ((src) << GICH_LR_PHYSID_CPUID_SHIFT) | (irq))
 995
 996 /*
 997  * An interrupt may have been disabled after being made pending on the
 998  * CPU interface (the classic case is a timer running while we're
 999  * rebooting the guest - the interrupt would kick as soon as the CPU
1000  * interface gets enabled, with deadly consequences).
1001  *
1002  * The solution is to examine already active LRs, and check the
1003  * interrupt is still enabled. If not, just retire it.
1004  */
1005 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
1006 {
1007         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1008         int lr;
1009
1010         for_each_set_bit(lr, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
1011                 int irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
1012
1013                 if (!vgic_irq_is_enabled(vcpu, irq)) {
1014                         vgic_retire_lr(lr, irq, vgic_cpu);
1015                         if (vgic_irq_is_active(vcpu, irq))
1016                                 vgic_irq_clear_active(vcpu, irq);
1017                 }
1018         }
1019 }
1020
1021 /*
1022  * Queue an interrupt to a CPU virtual interface. Return true on success,
1023  * or false if it wasn't possible to queue it.
1024  */
1025 static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
1026 {
1027         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1028         int lr;
1029
1030         /* Sanitize the input... */
1031         BUG_ON(sgi_source_id & ~7);
1032         BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
1033         BUG_ON(irq >= VGIC_NR_IRQS);
1034
1035         kvm_debug("Queue IRQ%d\n", irq);
1036
1037         lr = vgic_cpu->vgic_irq_lr_map[irq];
1038
1039         /* Do we have an active interrupt for the same CPUID? */
1040         if (lr != LR_EMPTY &&
1041             (LR_CPUID(vgic_cpu->vgic_lr[lr]) == sgi_source_id)) {
1042                 kvm_debug("LR%d piggyback for IRQ%d %x\n",
1043                           lr, irq, vgic_cpu->vgic_lr[lr]);
1044                 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
1045                 vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
1046                 return true;
1047         }
1048
1049         /* Try to use another LR for this interrupt */
1050         lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
1051                                vgic_cpu->nr_lr);
1052         if (lr >= vgic_cpu->nr_lr)
1053                 return false;
1054
1055         kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
1056         vgic_cpu->vgic_lr[lr] = MK_LR_PEND(sgi_source_id, irq);
1057         vgic_cpu->vgic_irq_lr_map[irq] = lr;
1058         set_bit(lr, vgic_cpu->lr_used);
1059
1060         if (!vgic_irq_is_edge(vcpu, irq))
1061                 vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
1062
1063         return true;
1064 }
1065
1066 static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
1067 {
1068         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1069         unsigned long sources;
1070         int vcpu_id = vcpu->vcpu_id;
1071         int c;
1072
1073         sources = dist->irq_sgi_sources[vcpu_id][irq];
1074
1075         for_each_set_bit(c, &sources, VGIC_MAX_CPUS) {
1076                 if (vgic_queue_irq(vcpu, c, irq))
1077                         clear_bit(c, &sources);
1078         }
1079
1080         dist->irq_sgi_sources[vcpu_id][irq] = sources;
1081
1082         /*
1083          * If the sources bitmap has been cleared it means that we
1084          * could queue all the SGIs onto link registers (see the
1085          * clear_bit above), and therefore we are done with them in
1086          * our emulated gic and can get rid of them.
1087          */
1088         if (!sources) {
1089                 vgic_dist_irq_clear(vcpu, irq);
1090                 vgic_cpu_irq_clear(vcpu, irq);
1091                 return true;
1092         }
1093
1094         return false;
1095 }
1096
1097 static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
1098 {
1099         if (vgic_irq_is_active(vcpu, irq))
1100                 return true; /* level interrupt, already queued */
1101
1102         if (vgic_queue_irq(vcpu, 0, irq)) {
1103                 if (vgic_irq_is_edge(vcpu, irq)) {
1104                         vgic_dist_irq_clear(vcpu, irq);
1105                         vgic_cpu_irq_clear(vcpu, irq);
1106                 } else {
1107                         vgic_irq_set_active(vcpu, irq);
1108                 }
1109
1110                 return true;
1111         }
1112
1113         return false;
1114 }
1115
1116 /*
1117  * Fill the list registers with pending interrupts before running the
1118  * guest.
1119  */
1120 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1121 {
1122         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1123         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1124         int i, vcpu_id;
1125         int overflow = 0;
1126
1127         vcpu_id = vcpu->vcpu_id;
1128
1129         /*
1130          * We may not have any pending interrupt, or the interrupts
1131          * may have been serviced from another vcpu. In all cases,
1132          * move along.
1133          */
1134         if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
1135                 pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
1136                 goto epilog;
1137         }
1138
1139         /* SGIs */
1140         for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
1141                 if (!vgic_queue_sgi(vcpu, i))
1142                         overflow = 1;
1143         }
1144
1145         /* PPIs */
1146         for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
1147                 if (!vgic_queue_hwirq(vcpu, i))
1148                         overflow = 1;
1149         }
1150
1151         /* SPIs */
1152         for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) {
1153                 if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
1154                         overflow = 1;
1155         }
1156
1157 epilog:
1158         if (overflow) {
1159                 vgic_cpu->vgic_hcr |= GICH_HCR_UIE;
1160         } else {
1161                 vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
1162                 /*
1163                  * We're about to run this VCPU, and we've consumed
1164                  * everything the distributor had in store for
1165                  * us. Claim we don't have anything pending. We'll
1166                  * adjust that if needed while exiting.
1167                  */
1168                 clear_bit(vcpu_id, &dist->irq_pending_on_cpu);
1169         }
1170 }
1171
1172 static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1173 {
1174         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1175         bool level_pending = false;
1176
1177         kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
1178
1179         if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
1180                 /*
1181                  * Some level interrupts have been EOIed. Clear their
1182                  * active bit.
1183                  */
1184                 int lr, irq;
1185
1186                 for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_eisr,
1187                                  vgic_cpu->nr_lr) {
1188                         irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
1189
1190                         vgic_irq_clear_active(vcpu, irq);
1191                         vgic_cpu->vgic_lr[lr] &= ~GICH_LR_EOI;
1192
1193                         /* Any additional pending interrupt? */
1194                         if (vgic_dist_irq_is_pending(vcpu, irq)) {
1195                                 vgic_cpu_irq_set(vcpu, irq);
1196                                 level_pending = true;
1197                         } else {
1198                                 vgic_cpu_irq_clear(vcpu, irq);
1199                         }
1200
1201                         /*
1202                          * Despite being EOIed, the LR may not have
1203                          * been marked as empty.
1204                          */
1205                         set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
1206                         vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT;
1207                 }
1208         }
1209
1210         if (vgic_cpu->vgic_misr & GICH_MISR_U)
1211                 vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
1212
1213         return level_pending;
1214 }
1215
1216 /*
1217  * Sync back the VGIC state after a guest run. The distributor lock is
1218  * needed so we don't get preempted in the middle of the state processing.
1219  */
1220 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1221 {
1222         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1223         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1224         int lr, pending;
1225         bool level_pending;
1226
1227         level_pending = vgic_process_maintenance(vcpu);
1228
1229         /* Clear mappings for empty LRs */
1230         for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr,
1231                          vgic_cpu->nr_lr) {
1232                 int irq;
1233
1234                 if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
1235                         continue;
1236
1237                 irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
1238
1239                 BUG_ON(irq >= VGIC_NR_IRQS);
1240                 vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
1241         }
1242
1243         /* Check if we still have something up our sleeve... */
1244         pending = find_first_zero_bit((unsigned long *)vgic_cpu->vgic_elrsr,
1245                                       vgic_cpu->nr_lr);
1246         if (level_pending || pending < vgic_cpu->nr_lr)
1247                 set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
1248 }
1249
1250 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1251 {
1252         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1253
1254         if (!irqchip_in_kernel(vcpu->kvm))
1255                 return;
1256
1257         spin_lock(&dist->lock);
1258         __kvm_vgic_flush_hwstate(vcpu);
1259         spin_unlock(&dist->lock);
1260 }
1261
1262 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1263 {
1264         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1265
1266         if (!irqchip_in_kernel(vcpu->kvm))
1267                 return;
1268
1269         spin_lock(&dist->lock);
1270         __kvm_vgic_sync_hwstate(vcpu);
1271         spin_unlock(&dist->lock);
1272 }
1273
1274 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
1275 {
1276         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1277
1278         if (!irqchip_in_kernel(vcpu->kvm))
1279                 return 0;
1280
1281         return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
1282 }
1283
1284 static void vgic_kick_vcpus(struct kvm *kvm)
1285 {
1286         struct kvm_vcpu *vcpu;
1287         int c;
1288
1289         /*
1290          * We've injected an interrupt, time to find out who deserves
1291          * a good kick...
1292          */
1293         kvm_for_each_vcpu(c, vcpu, kvm) {
1294                 if (kvm_vgic_vcpu_pending_irq(vcpu))
1295                         kvm_vcpu_kick(vcpu);
1296         }
1297 }
1298
1299 static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
1300 {
1301         int is_edge = vgic_irq_is_edge(vcpu, irq);
1302         int state = vgic_dist_irq_is_pending(vcpu, irq);
1303
1304         /*
1305          * Only inject an interrupt if:
1306          * - edge triggered and we have a rising edge
1307          * - level triggered and we change level
1308          */
1309         if (is_edge)
1310                 return level > state;
1311         else
1312                 return level != state;
1313 }
1314
1315 static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
1316                                   unsigned int irq_num, bool level)
1317 {
1318         struct vgic_dist *dist = &kvm->arch.vgic;
1319         struct kvm_vcpu *vcpu;
1320         int is_edge, is_level;
1321         int enabled;
1322         bool ret = true;
1323
1324         spin_lock(&dist->lock);
1325
1326         vcpu = kvm_get_vcpu(kvm, cpuid);
1327         is_edge = vgic_irq_is_edge(vcpu, irq_num);
1328         is_level = !is_edge;
1329
1330         if (!vgic_validate_injection(vcpu, irq_num, level)) {
1331                 ret = false;
1332                 goto out;
1333         }
1334
1335         if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
1336                 cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
1337                 vcpu = kvm_get_vcpu(kvm, cpuid);
1338         }
1339
1340         kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
1341
1342         if (level)
1343                 vgic_dist_irq_set(vcpu, irq_num);
1344         else
1345                 vgic_dist_irq_clear(vcpu, irq_num);
1346
1347         enabled = vgic_irq_is_enabled(vcpu, irq_num);
1348
1349         if (!enabled) {
1350                 ret = false;
1351                 goto out;
1352         }
1353
1354         if (is_level && vgic_irq_is_active(vcpu, irq_num)) {
1355                 /*
1356                  * Level interrupt in progress, will be picked up
1357                  * when EOId.
1358                  */
1359                 ret = false;
1360                 goto out;
1361         }
1362
1363         if (level) {
1364                 vgic_cpu_irq_set(vcpu, irq_num);
1365                 set_bit(cpuid, &dist->irq_pending_on_cpu);
1366         }
1367
1368 out:
1369         spin_unlock(&dist->lock);
1370
1371         return ret;
1372 }
1373
1374 /**
1375  * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1376  * @kvm:     The VM structure pointer
1377  * @cpuid:   The CPU for PPIs
1378  * @irq_num: The IRQ number that is assigned to the device
1379  * @level:   Edge-triggered:  true:  to trigger the interrupt
1380  *                            false: to ignore the call
1381  *           Level-sensitive  true:  activates an interrupt
1382  *                            false: deactivates an interrupt
1383  *
1384  * The GIC is not concerned with devices being active-LOW or active-HIGH for
1385  * level-sensitive interrupts.  You can think of the level parameter as 1
1386  * being HIGH and 0 being LOW and all devices being active-HIGH.
1387  */
1388 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
1389                         bool level)
1390 {
1391         if (vgic_update_irq_state(kvm, cpuid, irq_num, level))
1392                 vgic_kick_vcpus(kvm);
1393
1394         return 0;
1395 }
1396
1397 static irqreturn_t vgic_maintenance_handler(int irq, void *data)
1398 {
1399         /*
1400          * We cannot rely on the vgic maintenance interrupt to be
1401          * delivered synchronously. This means we can only use it to
1402          * exit the VM, and we perform the handling of EOIed
1403          * interrupts on the exit path (see vgic_process_maintenance).
1404          */
1405         return IRQ_HANDLED;
1406 }
1407
1408 /**
1409  * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state
1410  * @vcpu: pointer to the vcpu struct
1411  *
1412  * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to
1413  * this vcpu and enable the VGIC for this VCPU
1414  */
1415 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
1416 {
1417         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1418         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1419         int i;
1420
1421         if (vcpu->vcpu_id >= VGIC_MAX_CPUS)
1422                 return -EBUSY;
1423
1424         for (i = 0; i < VGIC_NR_IRQS; i++) {
1425                 if (i < VGIC_NR_PPIS)
1426                         vgic_bitmap_set_irq_val(&dist->irq_enabled,
1427                                                 vcpu->vcpu_id, i, 1);
1428                 if (i < VGIC_NR_PRIVATE_IRQS)
1429                         vgic_bitmap_set_irq_val(&dist->irq_cfg,
1430                                                 vcpu->vcpu_id, i, VGIC_CFG_EDGE);
1431
1432                 vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY;
1433         }
1434
1435         /*
1436          * By forcing VMCR to zero, the GIC will restore the binary
1437          * points to their reset values. Anything else resets to zero
1438          * anyway.
1439          */
1440         vgic_cpu->vgic_vmcr = 0;
1441
1442         vgic_cpu->nr_lr = vgic_nr_lr;
1443         vgic_cpu->vgic_hcr = GICH_HCR_EN; /* Get the show on the road... */
1444
1445         return 0;
1446 }
1447
1448 static void vgic_init_maintenance_interrupt(void *info)
1449 {
1450         enable_percpu_irq(vgic_maint_irq, 0);
1451 }
1452
1453 static int vgic_cpu_notify(struct notifier_block *self,
1454                            unsigned long action, void *cpu)
1455 {
1456         switch (action) {
1457         case CPU_STARTING:
1458         case CPU_STARTING_FROZEN:
1459                 vgic_init_maintenance_interrupt(NULL);
1460                 break;
1461         case CPU_DYING:
1462         case CPU_DYING_FROZEN:
1463                 disable_percpu_irq(vgic_maint_irq);
1464                 break;
1465         }
1466
1467         return NOTIFY_OK;
1468 }
1469
1470 static struct notifier_block vgic_cpu_nb = {
1471         .notifier_call = vgic_cpu_notify,
1472 };
1473
1474 int kvm_vgic_hyp_init(void)
1475 {
1476         int ret;
1477         struct resource vctrl_res;
1478         struct resource vcpu_res;
1479
1480         vgic_node = of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic");
1481         if (!vgic_node) {
1482                 kvm_err("error: no compatible vgic node in DT\n");
1483                 return -ENODEV;
1484         }
1485
1486         vgic_maint_irq = irq_of_parse_and_map(vgic_node, 0);
1487         if (!vgic_maint_irq) {
1488                 kvm_err("error getting vgic maintenance irq from DT\n");
1489                 ret = -ENXIO;
1490                 goto out;
1491         }
1492
1493         ret = request_percpu_irq(vgic_maint_irq, vgic_maintenance_handler,
1494                                  "vgic", kvm_get_running_vcpus());
1495         if (ret) {
1496                 kvm_err("Cannot register interrupt %d\n", vgic_maint_irq);
1497                 goto out;
1498         }
1499
1500         ret = __register_cpu_notifier(&vgic_cpu_nb);
1501         if (ret) {
1502                 kvm_err("Cannot register vgic CPU notifier\n");
1503                 goto out_free_irq;
1504         }
1505
1506         ret = of_address_to_resource(vgic_node, 2, &vctrl_res);
1507         if (ret) {
1508                 kvm_err("Cannot obtain VCTRL resource\n");
1509                 goto out_free_irq;
1510         }
1511
1512         vgic_vctrl_base = of_iomap(vgic_node, 2);
1513         if (!vgic_vctrl_base) {
1514                 kvm_err("Cannot ioremap VCTRL\n");
1515                 ret = -ENOMEM;
1516                 goto out_free_irq;
1517         }
1518
1519         vgic_nr_lr = readl_relaxed(vgic_vctrl_base + GICH_VTR);
1520         vgic_nr_lr = (vgic_nr_lr & 0x3f) + 1;
1521
1522         ret = create_hyp_io_mappings(vgic_vctrl_base,
1523                                      vgic_vctrl_base + resource_size(&vctrl_res),
1524                                      vctrl_res.start);
1525         if (ret) {
1526                 kvm_err("Cannot map VCTRL into hyp\n");
1527                 goto out_unmap;
1528         }
1529
1530         kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
1531                  vctrl_res.start, vgic_maint_irq);
1532         on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
1533
1534         if (of_address_to_resource(vgic_node, 3, &vcpu_res)) {
1535                 kvm_err("Cannot obtain VCPU resource\n");
1536                 ret = -ENXIO;
1537                 goto out_unmap;
1538         }
1539         vgic_vcpu_base = vcpu_res.start;
1540
1541         goto out;
1542
1543 out_unmap:
1544         iounmap(vgic_vctrl_base);
1545 out_free_irq:
1546         free_percpu_irq(vgic_maint_irq, kvm_get_running_vcpus());
1547 out:
1548         of_node_put(vgic_node);
1549         return ret;
1550 }
1551
1552 /**
1553  * kvm_vgic_init - Initialize global VGIC state before running any VCPUs
1554  * @kvm: pointer to the kvm struct
1555  *
1556  * Map the virtual CPU interface into the VM before running any VCPUs.  We
1557  * can't do this at creation time, because user space must first set the
1558  * virtual CPU interface address in the guest physical address space.  Also
1559  * initialize the ITARGETSRn regs to 0 on the emulated distributor.
1560  */
1561 int kvm_vgic_init(struct kvm *kvm)
1562 {
1563         int ret = 0, i;
1564
1565         if (!irqchip_in_kernel(kvm))
1566                 return 0;
1567
1568         mutex_lock(&kvm->lock);
1569
1570         if (vgic_initialized(kvm))
1571                 goto out;
1572
1573         if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
1574             IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
1575                 kvm_err("Need to set vgic cpu and dist addresses first\n");
1576                 ret = -ENXIO;
1577                 goto out;
1578         }
1579
1580         ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
1581                                     vgic_vcpu_base, KVM_VGIC_V2_CPU_SIZE);
1582         if (ret) {
1583                 kvm_err("Unable to remap VGIC CPU to VCPU\n");
1584                 goto out;
1585         }
1586
1587         for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4)
1588                 vgic_set_target_reg(kvm, 0, i);
1589
1590         kvm->arch.vgic.ready = true;
1591 out:
1592         mutex_unlock(&kvm->lock);
1593         return ret;
1594 }
1595
1596 int kvm_vgic_create(struct kvm *kvm)
1597 {
1598         int i, vcpu_lock_idx = -1, ret = 0;
1599         struct kvm_vcpu *vcpu;
1600
1601         mutex_lock(&kvm->lock);
1602
1603         if (kvm->arch.vgic.vctrl_base) {
1604                 ret = -EEXIST;
1605                 goto out;
1606         }
1607
1608         /*
1609          * Any time a vcpu is run, vcpu_load is called which tries to grab the
1610          * vcpu->mutex.  By grabbing the vcpu->mutex of all VCPUs we ensure
1611          * that no other VCPUs are run while we create the vgic.
1612          */
1613         kvm_for_each_vcpu(i, vcpu, kvm) {
1614                 if (!mutex_trylock(&vcpu->mutex))
1615                         goto out_unlock;
1616                 vcpu_lock_idx = i;
1617         }
1618
1619         kvm_for_each_vcpu(i, vcpu, kvm) {
1620                 if (vcpu->arch.has_run_once) {
1621                         ret = -EBUSY;
1622                         goto out_unlock;
1623                 }
1624         }
1625
1626         spin_lock_init(&kvm->arch.vgic.lock);
1627         kvm->arch.vgic.vctrl_base = vgic_vctrl_base;
1628         kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
1629         kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
1630
1631 out_unlock:
1632         for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
1633                 vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
1634                 mutex_unlock(&vcpu->mutex);
1635         }
1636
1637 out:
1638         mutex_unlock(&kvm->lock);
1639         return ret;
1640 }
1641
1642 static bool vgic_ioaddr_overlap(struct kvm *kvm)
1643 {
1644         phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
1645         phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
1646
1647         if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
1648                 return 0;
1649         if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
1650             (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
1651                 return -EBUSY;
1652         return 0;
1653 }
1654
1655 static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
1656                               phys_addr_t addr, phys_addr_t size)
1657 {
1658         int ret;
1659
1660         if (addr & ~KVM_PHYS_MASK)
1661                 return -E2BIG;
1662
1663         if (addr & (SZ_4K - 1))
1664                 return -EINVAL;
1665
1666         if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
1667                 return -EEXIST;
1668         if (addr + size < addr)
1669                 return -EINVAL;
1670
1671         ret = vgic_ioaddr_overlap(kvm);
1672         if (ret)
1673                 return ret;
1674         *ioaddr = addr;
1675         return ret;
1676 }
1677
1678 /**
1679  * kvm_vgic_addr - set or get vgic VM base addresses
1680  * @kvm:   pointer to the vm struct
1681  * @type:  the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX
1682  * @addr:  pointer to address value
1683  * @write: if true set the address in the VM address space, if false read the
1684  *          address
1685  *
1686  * Set or get the vgic base addresses for the distributor and the virtual CPU
1687  * interface in the VM physical address space.  These addresses are properties
1688  * of the emulated core/SoC and therefore user space initially knows this
1689  * information.
1690  */
1691 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
1692 {
1693         int r = 0;
1694         struct vgic_dist *vgic = &kvm->arch.vgic;
1695
1696         mutex_lock(&kvm->lock);
1697         switch (type) {
1698         case KVM_VGIC_V2_ADDR_TYPE_DIST:
1699                 if (write) {
1700                         r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
1701                                                *addr, KVM_VGIC_V2_DIST_SIZE);
1702                 } else {
1703                         *addr = vgic->vgic_dist_base;
1704                 }
1705                 break;
1706         case KVM_VGIC_V2_ADDR_TYPE_CPU:
1707                 if (write) {
1708                         r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
1709                                                *addr, KVM_VGIC_V2_CPU_SIZE);
1710                 } else {
1711                         *addr = vgic->vgic_cpu_base;
1712                 }
1713                 break;
1714         default:
1715                 r = -ENODEV;
1716         }
1717
1718         mutex_unlock(&kvm->lock);
1719         return r;
1720 }
1721
1722 static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu,
1723                                  struct kvm_exit_mmio *mmio, phys_addr_t offset)
1724 {
1725         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1726         u32 reg, mask = 0, shift = 0;
1727         bool updated = false;
1728
1729         switch (offset & ~0x3) {
1730         case GIC_CPU_CTRL:
1731                 mask = GICH_VMCR_CTRL_MASK;
1732                 shift = GICH_VMCR_CTRL_SHIFT;
1733                 break;
1734         case GIC_CPU_PRIMASK:
1735                 mask = GICH_VMCR_PRIMASK_MASK;
1736                 shift = GICH_VMCR_PRIMASK_SHIFT;
1737                 break;
1738         case GIC_CPU_BINPOINT:
1739                 mask = GICH_VMCR_BINPOINT_MASK;
1740                 shift = GICH_VMCR_BINPOINT_SHIFT;
1741                 break;
1742         case GIC_CPU_ALIAS_BINPOINT:
1743                 mask = GICH_VMCR_ALIAS_BINPOINT_MASK;
1744                 shift = GICH_VMCR_ALIAS_BINPOINT_SHIFT;
1745                 break;
1746         }
1747
1748         if (!mmio->is_write) {
1749                 reg = (vgic_cpu->vgic_vmcr & mask) >> shift;
1750                 mmio_data_write(mmio, ~0, reg);
1751         } else {
1752                 reg = mmio_data_read(mmio, ~0);
1753                 reg = (reg << shift) & mask;
1754                 if (reg != (vgic_cpu->vgic_vmcr & mask))
1755                         updated = true;
1756                 vgic_cpu->vgic_vmcr &= ~mask;
1757                 vgic_cpu->vgic_vmcr |= reg;
1758         }
1759         return updated;
1760 }
1761
1762 static bool handle_mmio_abpr(struct kvm_vcpu *vcpu,
1763                              struct kvm_exit_mmio *mmio, phys_addr_t offset)
1764 {
1765         return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT);
1766 }
1767
1768 static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu,
1769                                   struct kvm_exit_mmio *mmio,
1770                                   phys_addr_t offset)
1771 {
1772         u32 reg;
1773
1774         if (mmio->is_write)
1775                 return false;
1776
1777         /* GICC_IIDR */
1778         reg = (PRODUCT_ID_KVM << 20) |
1779               (GICC_ARCH_VERSION_V2 << 16) |
1780               (IMPLEMENTER_ARM << 0);
1781         mmio_data_write(mmio, ~0, reg);
1782         return false;
1783 }
1784
1785 /*
1786  * CPU Interface Register accesses - these are not accessed by the VM, but by
1787  * user space for saving and restoring VGIC state.
1788  */
1789 static const struct mmio_range vgic_cpu_ranges[] = {
1790         {
1791                 .base           = GIC_CPU_CTRL,
1792                 .len            = 12,
1793                 .handle_mmio    = handle_cpu_mmio_misc,
1794         },
1795         {
1796                 .base           = GIC_CPU_ALIAS_BINPOINT,
1797                 .len            = 4,
1798                 .handle_mmio    = handle_mmio_abpr,
1799         },
1800         {
1801                 .base           = GIC_CPU_ACTIVEPRIO,
1802                 .len            = 16,
1803                 .handle_mmio    = handle_mmio_raz_wi,
1804         },
1805         {
1806                 .base           = GIC_CPU_IDENT,
1807                 .len            = 4,
1808                 .handle_mmio    = handle_cpu_mmio_ident,
1809         },
1810 };
1811
1812 static int vgic_attr_regs_access(struct kvm_device *dev,
1813                                  struct kvm_device_attr *attr,
1814                                  u32 *reg, bool is_write)
1815 {
1816         const struct mmio_range *r = NULL, *ranges;
1817         phys_addr_t offset;
1818         int ret, cpuid, c;
1819         struct kvm_vcpu *vcpu, *tmp_vcpu;
1820         struct vgic_dist *vgic;
1821         struct kvm_exit_mmio mmio;
1822
1823         offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
1824         cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
1825                 KVM_DEV_ARM_VGIC_CPUID_SHIFT;
1826
1827         mutex_lock(&dev->kvm->lock);
1828
1829         if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) {
1830                 ret = -EINVAL;
1831                 goto out;
1832         }
1833
1834         vcpu = kvm_get_vcpu(dev->kvm, cpuid);
1835         vgic = &dev->kvm->arch.vgic;
1836
1837         mmio.len = 4;
1838         mmio.is_write = is_write;
1839         if (is_write)
1840                 mmio_data_write(&mmio, ~0, *reg);
1841         switch (attr->group) {
1842         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
1843                 mmio.phys_addr = vgic->vgic_dist_base + offset;
1844                 ranges = vgic_dist_ranges;
1845                 break;
1846         case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
1847                 mmio.phys_addr = vgic->vgic_cpu_base + offset;
1848                 ranges = vgic_cpu_ranges;
1849                 break;
1850         default:
1851                 BUG();
1852         }
1853         r = find_matching_range(ranges, &mmio, offset);
1854
1855         if (unlikely(!r || !r->handle_mmio)) {
1856                 ret = -ENXIO;
1857                 goto out;
1858         }
1859
1860
1861         spin_lock(&vgic->lock);
1862
1863         /*
1864          * Ensure that no other VCPU is running by checking the vcpu->cpu
1865          * field.  If no other VPCUs are running we can safely access the VGIC
1866          * state, because even if another VPU is run after this point, that
1867          * VCPU will not touch the vgic state, because it will block on
1868          * getting the vgic->lock in kvm_vgic_sync_hwstate().
1869          */
1870         kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) {
1871                 if (unlikely(tmp_vcpu->cpu != -1)) {
1872                         ret = -EBUSY;
1873                         goto out_vgic_unlock;
1874                 }
1875         }
1876
1877         /*
1878          * Move all pending IRQs from the LRs on all VCPUs so the pending
1879          * state can be properly represented in the register state accessible
1880          * through this API.
1881          */
1882         kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm)
1883                 vgic_unqueue_irqs(tmp_vcpu);
1884
1885         offset -= r->base;
1886         r->handle_mmio(vcpu, &mmio, offset);
1887
1888         if (!is_write)
1889                 *reg = mmio_data_read(&mmio, ~0);
1890
1891         ret = 0;
1892 out_vgic_unlock:
1893         spin_unlock(&vgic->lock);
1894 out:
1895         mutex_unlock(&dev->kvm->lock);
1896         return ret;
1897 }
1898
1899 static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
1900 {
1901         int r;
1902
1903         switch (attr->group) {
1904         case KVM_DEV_ARM_VGIC_GRP_ADDR: {
1905                 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
1906                 u64 addr;
1907                 unsigned long type = (unsigned long)attr->attr;
1908
1909                 if (copy_from_user(&addr, uaddr, sizeof(addr)))
1910                         return -EFAULT;
1911
1912                 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
1913                 return (r == -ENODEV) ? -ENXIO : r;
1914         }
1915
1916         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
1917         case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
1918                 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
1919                 u32 reg;
1920
1921                 if (get_user(reg, uaddr))
1922                         return -EFAULT;
1923
1924                 return vgic_attr_regs_access(dev, attr, &reg, true);
1925         }
1926
1927         }
1928
1929         return -ENXIO;
1930 }
1931
1932 static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
1933 {
1934         int r = -ENXIO;
1935
1936         switch (attr->group) {
1937         case KVM_DEV_ARM_VGIC_GRP_ADDR: {
1938                 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
1939                 u64 addr;
1940                 unsigned long type = (unsigned long)attr->attr;
1941
1942                 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
1943                 if (r)
1944                         return (r == -ENODEV) ? -ENXIO : r;
1945
1946                 if (copy_to_user(uaddr, &addr, sizeof(addr)))
1947                         return -EFAULT;
1948                 break;
1949         }
1950
1951         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
1952         case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
1953                 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
1954                 u32 reg = 0;
1955
1956                 r = vgic_attr_regs_access(dev, attr, &reg, false);
1957                 if (r)
1958                         return r;
1959                 r = put_user(reg, uaddr);
1960                 break;
1961         }
1962
1963         }
1964
1965         return r;
1966 }
1967
1968 static int vgic_has_attr_regs(const struct mmio_range *ranges,
1969                               phys_addr_t offset)
1970 {
1971         struct kvm_exit_mmio dev_attr_mmio;
1972
1973         dev_attr_mmio.len = 4;
1974         if (find_matching_range(ranges, &dev_attr_mmio, offset))
1975                 return 0;
1976         else
1977                 return -ENXIO;
1978 }
1979
1980 static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
1981 {
1982         phys_addr_t offset;
1983
1984         switch (attr->group) {
1985         case KVM_DEV_ARM_VGIC_GRP_ADDR:
1986                 switch (attr->attr) {
1987                 case KVM_VGIC_V2_ADDR_TYPE_DIST:
1988                 case KVM_VGIC_V2_ADDR_TYPE_CPU:
1989                         return 0;
1990                 }
1991                 break;
1992         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
1993                 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
1994                 return vgic_has_attr_regs(vgic_dist_ranges, offset);
1995         case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
1996                 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
1997                 return vgic_has_attr_regs(vgic_cpu_ranges, offset);
1998         }
1999         return -ENXIO;
2000 }
2001
2002 static void vgic_destroy(struct kvm_device *dev)
2003 {
2004         kfree(dev);
2005 }
2006
2007 static int vgic_create(struct kvm_device *dev, u32 type)
2008 {
2009         return kvm_vgic_create(dev->kvm);
2010 }
2011
2012 struct kvm_device_ops kvm_arm_vgic_v2_ops = {
2013         .name = "kvm-arm-vgic",
2014         .create = vgic_create,
2015         .destroy = vgic_destroy,
2016         .set_attr = vgic_set_attr,
2017         .get_attr = vgic_get_attr,
2018         .has_attr = vgic_has_attr,
2019 };