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Merge git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf
[cascardo/linux.git]
/
drivers
/
pci
/
host
/
pcie-hisi.c
diff --git
a/drivers/pci/host/pcie-hisi.c
b/drivers/pci/host/pcie-hisi.c
index
7ee9dfc
..
56154c2
100644
(file)
--- a/
drivers/pci/host/pcie-hisi.c
+++ b/
drivers/pci/host/pcie-hisi.c
@@
-22,51
+22,38
@@
#include "pcie-designware.h"
#include "pcie-designware.h"
-#define PCIE_
LTSSM_LINKUP_STATE 0x11
-#define PCIE_
LTSSM_STATE_MASK 0x3F
-#define PCIE_S
UBCTRL_SYS_STATE4_REG 0x6818
-#define PCIE_
SYS_STATE4 0x31c
-#define PCIE_
HIP06_CTRL_OFF 0x1000
+#define PCIE_
SUBCTRL_SYS_STATE4_REG 0x6818
+#define PCIE_
HIP06_CTRL_OFF 0x1000
+#define PCIE_S
YS_STATE4 (PCIE_HIP06_CTRL_OFF + 0x31c)
+#define PCIE_
LTSSM_LINKUP_STATE 0x11
+#define PCIE_
LTSSM_STATE_MASK 0x3F
#define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp)
struct hisi_pcie;
struct pcie_soc_ops {
#define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp)
struct hisi_pcie;
struct pcie_soc_ops {
- int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
+ int (*hisi_pcie_link_up)(struct hisi_pcie *
hisi_
pcie);
};
struct hisi_pcie {
};
struct hisi_pcie {
+ struct pcie_port pp; /* pp.dbi_base is DT rc_dbi */
struct regmap *subctrl;
struct regmap *subctrl;
- void __iomem *reg_base;
u32 port_id;
u32 port_id;
- struct pcie_port pp;
struct pcie_soc_ops *soc_ops;
};
struct pcie_soc_ops *soc_ops;
};
-static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
- u32 val, u32 reg)
-{
- writel(val, pcie->reg_base + reg);
-}
-
-static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg)
-{
- return readl(pcie->reg_base + reg);
-}
-
/* HipXX PCIe host only supports 32-bit config access */
static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
u32 *val)
{
u32 reg;
u32 reg_val;
/* HipXX PCIe host only supports 32-bit config access */
static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
u32 *val)
{
u32 reg;
u32 reg_val;
- struct hisi_pcie *pcie = to_hisi_pcie(pp);
void *walker = ®_val;
walker += (where & 0x3);
reg = where & ~0x3;
void *walker = ®_val;
walker += (where & 0x3);
reg = where & ~0x3;
- reg_val =
hisi_pcie_apb_readl(pcie
, reg);
+ reg_val =
dw_pcie_readl_rc(pp
, reg);
if (size == 1)
*val = *(u8 __force *) walker;
if (size == 1)
*val = *(u8 __force *) walker;
@@
-86,21
+73,20
@@
static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
{
u32 reg_val;
u32 reg;
{
u32 reg_val;
u32 reg;
- struct hisi_pcie *pcie = to_hisi_pcie(pp);
void *walker = ®_val;
walker += (where & 0x3);
reg = where & ~0x3;
if (size == 4)
void *walker = ®_val;
walker += (where & 0x3);
reg = where & ~0x3;
if (size == 4)
-
hisi_pcie_apb_writel(pcie, val, reg
);
+
dw_pcie_writel_rc(pp, reg, val
);
else if (size == 2) {
else if (size == 2) {
- reg_val =
hisi_pcie_apb_readl(pcie
, reg);
+ reg_val =
dw_pcie_readl_rc(pp
, reg);
*(u16 __force *) walker = val;
*(u16 __force *) walker = val;
-
hisi_pcie_apb_writel(pcie, reg_val, reg
);
+
dw_pcie_writel_rc(pp, reg, reg_val
);
} else if (size == 1) {
} else if (size == 1) {
- reg_val =
hisi_pcie_apb_readl(pcie
, reg);
+ reg_val =
dw_pcie_readl_rc(pp
, reg);
*(u8 __force *) walker = val;
*(u8 __force *) walker = val;
-
hisi_pcie_apb_writel(pcie, reg_val, reg
);
+
dw_pcie_writel_rc(pp, reg, reg_val
);
} else
return PCIBIOS_BAD_REGISTER_NUMBER;
} else
return PCIBIOS_BAD_REGISTER_NUMBER;
@@
-119,10
+105,10
@@
static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
{
static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
{
+ struct pcie_port *pp = &hisi_pcie->pp;
u32 val;
u32 val;
- val = hisi_pcie_apb_readl(hisi_pcie, PCIE_HIP06_CTRL_OFF +
- PCIE_SYS_STATE4);
+ val = dw_pcie_readl_rc(pp, PCIE_SYS_STATE4);
return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
}
return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
}
@@
-140,19
+126,20
@@
static struct pcie_host_ops hisi_pcie_host_ops = {
.link_up = hisi_pcie_link_up,
};
.link_up = hisi_pcie_link_up,
};
-static int hisi_add_pcie_port(struct
pcie_port *pp
,
-
struct platform_device *pdev)
+static int hisi_add_pcie_port(struct
hisi_pcie *hisi_pcie
,
+ struct platform_device *pdev)
{
{
+ struct pcie_port *pp = &hisi_pcie->pp;
+ struct device *dev = pp->dev;
int ret;
u32 port_id;
int ret;
u32 port_id;
- struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
- if (of_property_read_u32(
pdev->dev.
of_node, "port-id", &port_id)) {
- dev_err(
&pdev->
dev, "failed to read port-id\n");
+ if (of_property_read_u32(
dev->
of_node, "port-id", &port_id)) {
+ dev_err(dev, "failed to read port-id\n");
return -EINVAL;
}
if (port_id > 3) {
return -EINVAL;
}
if (port_id > 3) {
- dev_err(
&pdev->
dev, "Invalid port-id: %d\n", port_id);
+ dev_err(dev, "Invalid port-id: %d\n", port_id);
return -EINVAL;
}
hisi_pcie->port_id = port_id;
return -EINVAL;
}
hisi_pcie->port_id = port_id;
@@
-161,7
+148,7
@@
static int hisi_add_pcie_port(struct pcie_port *pp,
ret = dw_pcie_host_init(pp);
if (ret) {
ret = dw_pcie_host_init(pp);
if (ret) {
- dev_err(
&pdev->
dev, "failed to initialize host\n");
+ dev_err(dev, "failed to initialize host\n");
return ret;
}
return ret;
}
@@
-170,6
+157,7
@@
static int hisi_add_pcie_port(struct pcie_port *pp,
static int hisi_pcie_probe(struct platform_device *pdev)
{
static int hisi_pcie_probe(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
struct hisi_pcie *hisi_pcie;
struct pcie_port *pp;
const struct of_device_id *match;
struct hisi_pcie *hisi_pcie;
struct pcie_port *pp;
const struct of_device_id *match;
@@
-177,40
+165,36
@@
static int hisi_pcie_probe(struct platform_device *pdev)
struct device_driver *driver;
int ret;
struct device_driver *driver;
int ret;
- hisi_pcie = devm_kzalloc(
&pdev->
dev, sizeof(*hisi_pcie), GFP_KERNEL);
+ hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL);
if (!hisi_pcie)
return -ENOMEM;
pp = &hisi_pcie->pp;
if (!hisi_pcie)
return -ENOMEM;
pp = &hisi_pcie->pp;
- pp->dev =
&pdev->
dev;
- driver =
(pdev->dev).
driver;
+ pp->dev = dev;
+ driver =
dev->
driver;
- match = of_match_device(driver->of_match_table,
&pdev->
dev);
+ match = of_match_device(driver->of_match_table, dev);
hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data;
hisi_pcie->subctrl =
syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
if (IS_ERR(hisi_pcie->subctrl)) {
hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data;
hisi_pcie->subctrl =
syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
if (IS_ERR(hisi_pcie->subctrl)) {
- dev_err(
pp->
dev, "cannot get subctrl base\n");
+ dev_err(dev, "cannot get subctrl base\n");
return PTR_ERR(hisi_pcie->subctrl);
}
reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
return PTR_ERR(hisi_pcie->subctrl);
}
reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
-
hisi_pcie->reg_base = devm_ioremap_resource(&pdev->
dev, reg);
- if (IS_ERR(
hisi_pcie->reg
_base)) {
- dev_err(
pp->
dev, "cannot get rc_dbi base\n");
- return PTR_ERR(
hisi_pcie->reg
_base);
+
pp->dbi_base = devm_ioremap_resource(
dev, reg);
+ if (IS_ERR(
pp->dbi
_base)) {
+ dev_err(dev, "cannot get rc_dbi base\n");
+ return PTR_ERR(
pp->dbi
_base);
}
}
- hisi_pcie->pp.dbi_base = hisi_pcie->reg_base;
-
- ret = hisi_add_pcie_port(pp, pdev);
+ ret = hisi_add_pcie_port(hisi_pcie, pdev);
if (ret)
return ret;
if (ret)
return ret;
- platform_set_drvdata(pdev, hisi_pcie);
-
- dev_warn(pp->dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
+ dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
return 0;
}
return 0;
}