mtd: nand: omap2: Implement NAND ready using gpiolib

[cascardo/linux.git] / Documentation / devicetree / bindings / mtd / gpmc-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index fb733c4..3ee7e20 100644 (file)
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -13,7 +13,11 @@ Documentation/devicetree/bindings/mtd/nand.txt
 
 Required properties:
 
- - reg:                The CS line the peripheral is connected to
+ - compatible: "ti,omap2-nand"
+ - reg:                range id (CS number), base offset and length of the
+               NAND I/O space
+ - interrupt-parent: must point to gpmc node
+ - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
 
 Optional properties:
 
@@ -44,6 +48,7 @@ Optional properties:
                locating ECC errors for BCHx algorithms. SoC devices which have
                ELM hardware engines should specify this device node in .dtsi
                Using ELM for ECC error correction frees some CPU cycles.
+ - rb-gpios:   GPIO specifier for the ready/busy# pin.
 
 For inline partition table parsing (optional):
 
@@ -55,20 +60,26 @@ Example for an AM33xx board:
        gpmc: gpmc@50000000 {
                compatible = "ti,am3352-gpmc";
                ti,hwmods = "gpmc";
-               reg = <0x50000000 0x1000000>;
+               reg = <0x50000000 0x36c>;
                interrupts = <100>;
                gpmc,num-cs = <8>;
                gpmc,num-waitpins = <2>;
                #address-cells = <2>;
                #size-cells = <1>;
-               ranges = <0 0 0x08000000 0x2000>;       /* CS0: NAND */
+               ranges = <0 0 0x08000000 0x1000000>;    /* CS0 space, 16MB */
                elm_id = <&elm>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
 
                nand@0,0 {
-                       reg = <0 0 0>; /* CS0, offset 0 */
+                       compatible = "ti,omap2-nand";
+                       reg = <0 0 4>;          /* CS0, offset 0, NAND I/O window 4 */
+                       interrupt-parent = <&gpmc>;
+                       interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;
                        nand-bus-width = <16>;
                        ti,nand-ecc-opt = "bch8";
                        ti,nand-xfer-type = "polled";
+                       rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 
                        gpmc,sync-clk-ps = <0>;
                        gpmc,cs-on-ns = <0>;