mboxes = <&mailbox &mbox_wkupm3>;
};
+ edma_xbar: dma-router@f90 {
+ compatible = "ti,am335x-edma-crossbar";
+ reg = <0xf90 0x40>;
+ #dma-cells = <3>;
+ dma-requests = <32>;
+ dma-masters = <&edma>;
+ };
+
scm_clockdomains: clockdomains {
};
};
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>;
- ti,edma-memcpy-channels = /bits/ 16 <20 21>;
+ ti,edma-memcpy-channels = <20 21>;
};
edma_tptc0: tptc@49800000 {
interrupt-names = "edma3_tcerrint";
};
- edma_xbar: dma-router@44e10f90 {
- compatible = "ti,am335x-edma-crossbar";
- reg = <0x44e10f90 0x40>;
-
- #dma-cells = <3>;
- dma-requests = <32>;
-
- dma-masters = <&edma>;
- };
-
gpio0: gpio@44e07000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
ti,no-idle-on-init;
reg = <0x50000000 0x2000>;
interrupts = <100>;
+ dmas = <&edma 52>;
+ dma-names = "rxtx";
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;