ARM: mvebu: Fix the main PLL frequency on Armada 375, 38x and 39x SoCs
[cascardo/linux.git] / arch / arm / boot / dts / armada-38x.dtsi
index 1dff30a..218a2ac 100644 (file)
        aliases {
                gpio0 = &gpio0;
                gpio1 = &gpio1;
-               ethernet0 = &eth0;
-               ethernet1 = &eth1;
-               ethernet2 = &eth2;
+               serial0 = &uart0;
+               serial1 = &uart1;
+       };
+
+       pmu {
+               compatible = "arm,cortex-a9-pmu";
+               interrupts-extended = <&mpic 3>;
        };
 
        soc {
                                status = "disabled";
                        };
 
-                       serial@12100 {
+                       uart1: serial@12100 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x12100 0x100>;
                                reg-shift = <2>;
                                reg = <0x20000 0x100>, <0x20180 0x20>;
                        };
 
-                       mpic: interrupt-controller@20000 {
+                       mpic: interrupt-controller@20a00 {
                                compatible = "marvell,mpic";
                                reg = <0x20a00 0x2d0>, <0x21070 0x58>;
                                #interrupt-cells = <1>;
                                status = "disabled";
                        };
 
-                       usb@50000 {
+                       usb@58000 {
                                compatible = "marvell,orion-ehci";
                                reg = <0x58000 0x500>;
                                interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 
                        sdhci@d8000 {
                                compatible = "marvell,armada-380-sdhci";
-                               reg = <0xd8000 0x1000>, <0xdc000 0x100>;
-                               interrupts = <0 25 0x4>;
+                               reg-names = "sdhci", "mbus", "conf-sdio3";
+                               reg = <0xd8000 0x1000>,
+                                       <0xdc000 0x100>,
+                                       <0x18454 0x4>;
+                               interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gateclk 17>;
                                mrvl,clk-delay-cycles = <0x1F>;
                                status = "disabled";
                mainpll: mainpll {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
-                       clock-frequency = <2000000000>;
+                       clock-frequency = <1000000000>;
                };
 
                /* 25 MHz reference crystal */