clock-div = <1>;
};
- aes1_ick: aes1_ick {
+ aes1_ick: aes1_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
reg = <0x0a14>;
};
- rng_ick: rng_ick {
+ rng_ick: rng_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
ti,bit-shift = <2>;
};
- sha11_ick: sha11_ick {
+ sha11_ick: sha11_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
ti,bit-shift = <1>;
};
- des1_ick: des1_ick {
+ des1_ick: des1_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
ti,bit-shift = <0>;
};
- cam_mclk: cam_mclk {
+ cam_mclk: cam_mclk@f00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m5x2_ck>;
ti,set-rate-parent;
};
- cam_ick: cam_ick {
+ cam_ick: cam_ick@f10 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ick>;
ti,bit-shift = <0>;
};
- csi2_96m_fck: csi2_96m_fck {
+ csi2_96m_fck: csi2_96m_fck@f00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&core_96m_fck>;
clock-div = <1>;
};
- pka_ick: pka_ick {
+ pka_ick: pka_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l3_ick>;
ti,bit-shift = <4>;
};
- icr_ick: icr_ick {
+ icr_ick: icr_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
ti,bit-shift = <29>;
};
- des2_ick: des2_ick {
+ des2_ick: des2_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
ti,bit-shift = <26>;
};
- mspro_ick: mspro_ick {
+ mspro_ick: mspro_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
ti,bit-shift = <23>;
};
- mailboxes_ick: mailboxes_ick {
+ mailboxes_ick: mailboxes_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
clock-div = <1>;
};
- sr1_fck: sr1_fck {
+ sr1_fck: sr1_fck@c00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
ti,bit-shift = <6>;
};
- sr2_fck: sr2_fck {
+ sr2_fck: sr2_fck@c00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
clock-div = <1>;
};
- dpll2_fck: dpll2_fck {
+ dpll2_fck: dpll2_fck@40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&core_ck>;
ti,index-starts-at-one;
};
- dpll2_ck: dpll2_ck {
+ dpll2_ck: dpll2_ck@4 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&dpll2_fck>;
ti,low-power-bypass;
};
- dpll2_m2_ck: dpll2_m2_ck {
+ dpll2_m2_ck: dpll2_m2_ck@44 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll2_ck>;
ti,index-starts-at-one;
};
- iva2_ck: iva2_ck {
+ iva2_ck: iva2_ck@0 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&dpll2_m2_ck>;
ti,bit-shift = <0>;
};
- modem_fck: modem_fck {
+ modem_fck: modem_fck@a00 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
ti,bit-shift = <31>;
};
- sad2d_ick: sad2d_ick {
+ sad2d_ick: sad2d_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l3_ick>;
ti,bit-shift = <3>;
};
- mad2d_ick: mad2d_ick {
+ mad2d_ick: mad2d_ick@a18 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l3_ick>;
ti,bit-shift = <3>;
};
- mspro_fck: mspro_fck {
+ mspro_fck: mspro_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;