Merge branch 'drm-rockchip-next-fixes-2016-03-28' of https://github.com/markyzq/kerne...

[cascardo/linux.git] / arch / arm / boot / dts / stm32f429.dtsi

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35b2ab1..35df462 100644 (file)
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -171,6 +171,11 @@
                        status = "disabled";
                };
 
+               syscfg: system-config@40013800 {
+                       compatible = "syscon";
+                       reg = <0x40013800 0x400>;
+               };
+
                pin-controller {
                        #address-cells = <1>;
                        #size-cells = <1>;
@@ -182,7 +187,7 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                reg = <0x0 0x400>;
-                               clocks = <&rcc 0 256>;
+                               clocks = <&rcc 0 0>;
                                st,bank-name = "GPIOA";
                        };
 
@@ -190,7 +195,7 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                reg = <0x400 0x400>;
-                               clocks = <&rcc 0 257>;
+                               clocks = <&rcc 0 1>;
                                st,bank-name = "GPIOB";
                        };
 
@@ -198,7 +203,7 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                reg = <0x800 0x400>;
-                               clocks = <&rcc 0 258>;
+                               clocks = <&rcc 0 2>;
                                st,bank-name = "GPIOC";
                        };
 
@@ -206,7 +211,7 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                reg = <0xc00 0x400>;
-                               clocks = <&rcc 0 259>;
+                               clocks = <&rcc 0 3>;
                                st,bank-name = "GPIOD";
                        };
 
@@ -214,7 +219,7 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                reg = <0x1000 0x400>;
-                               clocks = <&rcc 0 260>;
+                               clocks = <&rcc 0 4>;
                                st,bank-name = "GPIOE";
                        };
 
@@ -222,7 +227,7 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                reg = <0x1400 0x400>;
-                               clocks = <&rcc 0 261>;
+                               clocks = <&rcc 0 5>;
                                st,bank-name = "GPIOF";
                        };
 
@@ -230,7 +235,7 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                reg = <0x1800 0x400>;
-                               clocks = <&rcc 0 262>;
+                               clocks = <&rcc 0 6>;
                                st,bank-name = "GPIOG";
                        };
 
@@ -238,7 +243,7 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                reg = <0x1c00 0x400>;
-                               clocks = <&rcc 0 263>;
+                               clocks = <&rcc 0 7>;
                                st,bank-name = "GPIOH";
                        };
 
@@ -246,7 +251,7 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                reg = <0x2000 0x400>;
-                               clocks = <&rcc 0 264>;
+                               clocks = <&rcc 0 8>;
                                st,bank-name = "GPIOI";
                        };
 
@@ -254,7 +259,7 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                reg = <0x2400 0x400>;
-                               clocks = <&rcc 0 265>;
+                               clocks = <&rcc 0 9>;
                                st,bank-name = "GPIOJ";
                        };
 
@@ -262,7 +267,7 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                reg = <0x2800 0x400>;
-                               clocks = <&rcc 0 266>;
+                               clocks = <&rcc 0 10>;
                                st,bank-name = "GPIOK";
                        };
 
@@ -278,6 +283,46 @@
                                        bias-disable;
                                };
                        };
+
+                       usbotg_hs_pins_a: usbotg_hs@0 {
+                               pins {
+                                       pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
+                                                <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
+                                                <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
+                                                <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
+                                                <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
+                                                <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
+                                                <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
+                                                <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
+                                                <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
+                                                <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
+                                                <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
+                                                <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <2>;
+                               };
+                       };
+
+                       ethernet0_mii: mii@0 {
+                               pins {
+                                       pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+                                                <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+                                                <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
+                                                <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
+                                                <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
+                                                <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+                                                <STM32F429_PA2_FUNC_ETH_MDIO>,
+                                                <STM32F429_PC1_FUNC_ETH_MDC>,
+                                                <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+                                                <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+                                                <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+                                                <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
+                                                <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
+                                                <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
+                                       slew-rate = <2>;
+                               };
+                       };
                };
 
                rcc: rcc@40023810 {
@@ -318,6 +363,31 @@
                        st,mem2mem;
                };
 
+               ethernet0: dwmac@40028000 {
+                       compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
+                       reg = <0x40028000 0x8000>;
+                       reg-names = "stmmaceth";
+                       interrupts = <61>, <62>;
+                       interrupt-names = "macirq", "eth_wake_irq";
+                       clock-names = "stmmaceth", "tx-clk", "rx-clk";
+                       clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
+                       st,syscon = <&syscfg 0x4>;
+                       snps,pbl = <8>;
+                       snps,mixed-burst;
+                       dma-ranges;
+                       status = "disabled";
+               };
+
+               usbotg_hs: usb@40040000 {
+                       compatible = "snps,dwc2";
+                       dma-ranges;
+                       reg = <0x40040000 0x40000>;
+                       interrupts = <77>;
+                       clocks = <&rcc 0 29>;
+                       clock-names = "otg";
+                       status = "disabled";
+               };
+
                rng: rng@50060800 {
                        compatible = "st,stm32-rng";
                        reg = <0x50060800 0x400>;