ARM: imx: use endian-safe readl/readw/writel/writew

[cascardo/linux.git] / arch / arm / mach-imx / avic.c

diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index 1a89323..7fa176e 100644 (file)
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -66,12 +66,12 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
                return -EINVAL;
 
        if (irq < AVIC_NUM_IRQS / 2) {
-               irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
-               __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
+               irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
+               imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
        } else {
                irq -= AVIC_NUM_IRQS / 2;
-               irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
-               __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
+               irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
+               imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
        }
 
        return 0;
@@ -94,8 +94,8 @@ static void avic_irq_suspend(struct irq_data *d)
        struct irq_chip_type *ct = gc->chip_types;
        int idx = d->hwirq >> 5;
 
-       avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
-       __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
+       avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
+       imx_writel(gc->wake_active, avic_base + ct->regs.mask);
 }
 
 static void avic_irq_resume(struct irq_data *d)
@@ -104,7 +104,7 @@ static void avic_irq_resume(struct irq_data *d)
        struct irq_chip_type *ct = gc->chip_types;
        int idx = d->hwirq >> 5;
 
-       __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
+       imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
 }
 
 #else
@@ -140,7 +140,7 @@ static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
        u32 nivector;
 
        do {
-               nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
+               nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;
                if (nivector == 0xffff)
                        break;
 
@@ -164,16 +164,16 @@ void __init mxc_init_irq(void __iomem *irqbase)
        /* put the AVIC into the reset value with
         * all interrupts disabled
         */
-       __raw_writel(0, avic_base + AVIC_INTCNTL);
-       __raw_writel(0x1f, avic_base + AVIC_NIMASK);
+       imx_writel(0, avic_base + AVIC_INTCNTL);
+       imx_writel(0x1f, avic_base + AVIC_NIMASK);
 
        /* disable all interrupts */
-       __raw_writel(0, avic_base + AVIC_INTENABLEH);
-       __raw_writel(0, avic_base + AVIC_INTENABLEL);
+       imx_writel(0, avic_base + AVIC_INTENABLEH);
+       imx_writel(0, avic_base + AVIC_INTENABLEL);
 
        /* all IRQ no FIQ */
-       __raw_writel(0, avic_base + AVIC_INTTYPEH);
-       __raw_writel(0, avic_base + AVIC_INTTYPEL);
+       imx_writel(0, avic_base + AVIC_INTTYPEH);
+       imx_writel(0, avic_base + AVIC_INTTYPEL);
 
        irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
        WARN_ON(irq_base < 0);
@@ -188,7 +188,7 @@ void __init mxc_init_irq(void __iomem *irqbase)
 
        /* Set default priority value (0) for all IRQ's */
        for (i = 0; i < 8; i++)
-               __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
+               imx_writel(0, avic_base + AVIC_NIPRIORITY(i));
 
        set_handle_irq(avic_handle_irq);