Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm

[cascardo/linux.git] / arch / arm / mach-omap2 / id.c

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index ff0bc9e..0f4c18e 100644 (file)
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -18,6 +18,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+
+#ifdef CONFIG_SOC_BUS
+#include <linux/sys_soc.h>
+#endif
 
 #include <asm/cputype.h>
 
@@ -31,8 +36,11 @@
 #define OMAP4_SILICON_TYPE_STANDARD            0x01
 #define OMAP4_SILICON_TYPE_PERFORMANCE         0x02
 
+#define OMAP_SOC_MAX_NAME_LENGTH               16
+
 static unsigned int omap_revision;
-static const char *cpu_rev;
+static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
+static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
 u32 omap_features;
 
 unsigned int omap_rev(void)
@@ -169,9 +177,12 @@ void __init omap2xxx_check_revision(void)
                j = i;
        }
 
-       pr_info("OMAP%04x", omap_rev() >> 16);
+       sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+       sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
+
+       pr_info("%s", soc_name);
        if ((omap_rev() >> 8) & 0x0f)
-               pr_info("ES%x", (omap_rev() >> 12) & 0xf);
+               pr_info("%s", soc_rev);
        pr_info("\n");
 }
 
@@ -211,8 +222,10 @@ static void __init omap3_cpuinfo(void)
                cpu_name = "OMAP3503";
        }
 
+       sprintf(soc_name, "%s", cpu_name);
+
        /* Print verbose information */
-       pr_info("%s ES%s (", cpu_name, cpu_rev);
+       pr_info("%s %s (", soc_name, soc_rev);
 
        OMAP3_SHOW_FEATURE(l2cache);
        OMAP3_SHOW_FEATURE(iva);
@@ -291,6 +304,7 @@ void __init ti81xx_check_features(void)
 
 void __init omap3xxx_check_revision(void)
 {
+       const char *cpu_rev;
        u32 cpuid, idcode;
        u16 hawkeye;
        u8 rev;
@@ -300,7 +314,7 @@ void __init omap3xxx_check_revision(void)
         * If the processor type is Cortex-A8 and the revision is 0x0
         * it means its Cortex r0p0 which is 3430 ES1.0.
         */
-       cpuid = read_cpuid(CPUID_ID);
+       cpuid = read_cpuid_id();
        if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
                omap_revision = OMAP3430_REV_ES1_0;
                cpu_rev = "1.0";
@@ -438,6 +452,7 @@ void __init omap3xxx_check_revision(void)
                cpu_rev = "1.2";
                pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
        }
+       sprintf(soc_rev, "ES%s", cpu_rev);
 }
 
 void __init omap4xxx_check_revision(void)
@@ -460,7 +475,7 @@ void __init omap4xxx_check_revision(void)
         * Use ARM register to detect the correct ES version
         */
        if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
-               idcode = read_cpuid(CPUID_ID);
+               idcode = read_cpuid_id();
                rev = (idcode & 0xf) - 1;
        }
 
@@ -512,8 +527,10 @@ void __init omap4xxx_check_revision(void)
                omap_revision = OMAP4430_REV_ES2_3;
        }
 
-       pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
-               ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
+       sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+       sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
+                                               (omap_rev() >> 8) & 0xf);
+       pr_info("%s %s\n", soc_name, soc_rev);
 }
 
 void __init omap5xxx_check_revision(void)
@@ -553,8 +570,10 @@ void __init omap5xxx_check_revision(void)
                omap_revision = OMAP5430_REV_ES2_0;
        }
 
-       pr_info("OMAP%04x ES%d.0\n",
-                       omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
+       sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+       sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
+
+       pr_info("%s %s\n", soc_name, soc_rev);
 }
 
 /*
@@ -575,3 +594,63 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
        else
                tap_prod_id = 0x0208;
 }
+
+#ifdef CONFIG_SOC_BUS
+
+static const char const *omap_types[] = {
+       [OMAP2_DEVICE_TYPE_TEST]        = "TST",
+       [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
+       [OMAP2_DEVICE_TYPE_SEC]         = "HS",
+       [OMAP2_DEVICE_TYPE_GP]          = "GP",
+       [OMAP2_DEVICE_TYPE_BAD]         = "BAD",
+};
+
+static const char * __init omap_get_family(void)
+{
+       if (cpu_is_omap24xx())
+               return kasprintf(GFP_KERNEL, "OMAP2");
+       else if (cpu_is_omap34xx())
+               return kasprintf(GFP_KERNEL, "OMAP3");
+       else if (cpu_is_omap44xx())
+               return kasprintf(GFP_KERNEL, "OMAP4");
+       else if (soc_is_omap54xx())
+               return kasprintf(GFP_KERNEL, "OMAP5");
+       else
+               return kasprintf(GFP_KERNEL, "Unknown");
+}
+
+static ssize_t omap_get_type(struct device *dev,
+                                       struct device_attribute *attr,
+                                       char *buf)
+{
+       return sprintf(buf, "%s\n", omap_types[omap_type()]);
+}
+
+static struct device_attribute omap_soc_attr =
+       __ATTR(type,  S_IRUGO, omap_get_type,  NULL);
+
+void __init omap_soc_device_init(void)
+{
+       struct device *parent;
+       struct soc_device *soc_dev;
+       struct soc_device_attribute *soc_dev_attr;
+
+       soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+       if (!soc_dev_attr)
+               return;
+
+       soc_dev_attr->machine  = soc_name;
+       soc_dev_attr->family   = omap_get_family();
+       soc_dev_attr->revision = soc_rev;
+
+       soc_dev = soc_device_register(soc_dev_attr);
+       if (IS_ERR_OR_NULL(soc_dev)) {
+               kfree(soc_dev_attr);
+               return;
+       }
+
+       parent = soc_device_to_device(soc_dev);
+       if (!IS_ERR_OR_NULL(parent))
+               device_create_file(parent, &omap_soc_attr);
+}
+#endif /* CONFIG_SOC_BUS */