ARM: shmobile: r7s72100: Switch to new style MTU2 device

[cascardo/linux.git] / arch / arm / mach-shmobile / clock-r7s72100.c

diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index e6ab0cd..644f1c2 100644 (file)
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -22,12 +22,15 @@
 #include <mach/common.h>
 #include <mach/r7s72100.h>
 
-/* registers */
+/* Frequency Control Registers */
 #define FRQCR          0xfcfe0010
 #define FRQCR2         0xfcfe0014
+/* Standby Control Registers */
 #define STBCR3         0xfcfe0420
 #define STBCR4         0xfcfe0424
+#define STBCR7         0xfcfe0430
 #define STBCR9         0xfcfe0438
+#define STBCR10                0xfcfe043c
 
 #define PLL_RATE 30
 
@@ -67,7 +70,7 @@ static struct clk pll_clk = {
 
 static unsigned long bus_recalc(struct clk *clk)
 {
-       return clk->parent->rate * 2 / 3;
+       return clk->parent->rate / 3;
 }
 
 static struct sh_clk_ops bus_clk_ops = {
@@ -145,15 +148,25 @@ struct clk div4_clks[DIV4_NR] = {
                                        | CLK_ENABLE_ON_INIT),
 };
 
-enum { MSTP97, MSTP96, MSTP95, MSTP94,
+enum {
+       MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
+       MSTP97, MSTP96, MSTP95, MSTP94,
+       MSTP74,
        MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
-       MSTP33, MSTP_NR };
+       MSTP33, MSTP_NR
+};
 
 static struct clk mstp_clks[MSTP_NR] = {
+       [MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
+       [MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
+       [MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
+       [MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
+       [MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
        [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
        [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
        [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
        [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
+       [MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
        [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
        [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
        [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
@@ -176,7 +189,21 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 
        /* MSTP clocks */
-       CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
+       CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
+       CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
+       CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
+       CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
+       CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
+       CLKDEV_DEV_ID("e800c800.spi", &mstp_clks[MSTP107]),
+       CLKDEV_DEV_ID("e800d000.spi", &mstp_clks[MSTP106]),
+       CLKDEV_DEV_ID("e800d800.spi", &mstp_clks[MSTP105]),
+       CLKDEV_DEV_ID("e800e000.spi", &mstp_clks[MSTP104]),
+       CLKDEV_DEV_ID("e800e800.spi", &mstp_clks[MSTP103]),
+       CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]),
+       CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]),
+       CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]),
+       CLKDEV_DEV_ID("fcfeec00.i2c", &mstp_clks[MSTP94]),
+       CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
 
        /* ICK */
        CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
@@ -187,6 +214,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
        CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
        CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
+       CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP33]),
 };
 
 void __init r7s72100_clock_init(void)