ARM: 6077/1: ux500: add SOC Kconfig variables

[cascardo/linux.git] / arch / arm / mach-ux500 / include / mach / hardware.h

diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 04ea836..d86b354 100644 (file)
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -23,6 +23,8 @@
 
 /* typesafe io address */
 #define __io_address(n)                __io(IO_ADDRESS(n))
+/* used by some plat-nomadik code */
+#define io_p2v(n)              __io_address(n)
 
 /*
  * Base address definitions for U8500 Onchip IPs. All the
@@ -56,16 +58,19 @@
 #define U8500_TWD_SIZE         0x100
 
 /* per7 base addressess */
-#define U8500_CR_BASE          (U8500_PER7_BASE + 0x8000)
-#define U8500_MTU0_BASE                (U8500_PER7_BASE + 0xa000)
-#define U8500_MTU1_BASE                (U8500_PER7_BASE + 0xb000)
-#define U8500_TZPC0_BASE       (U8500_PER7_BASE + 0xc000)
-#define U8500_CLKRST7_BASE     (U8500_PER7_BASE + 0xf000)
+#define U8500_CR_BASE_ED       (U8500_PER7_BASE + 0x8000)
+#define U8500_MTU0_BASE_ED     (U8500_PER7_BASE + 0xa000)
+#define U8500_MTU1_BASE_ED     (U8500_PER7_BASE + 0xb000)
+#define U8500_TZPC0_BASE_ED    (U8500_PER7_BASE + 0xc000)
+#define U8500_CLKRST7_BASE_ED  (U8500_PER7_BASE + 0xf000)
 
 /* per6 base addressess */
 #define U8500_RNG_BASE         (U8500_PER6_BASE + 0x0000)
 #define U8500_PKA_BASE         (U8500_PER6_BASE + 0x1000)
 #define U8500_PKAM_BASE                (U8500_PER6_BASE + 0x2000)
+#define U8500_MTU0_BASE_V1     (U8500_PER6_BASE + 0x6000)
+#define U8500_MTU1_BASE_V1     (U8500_PER6_BASE + 0x7000)
+#define U8500_CR_BASE_V1       (U8500_PER6_BASE + 0x8000)
 #define U8500_CRYPTO0_BASE     (U8500_PER6_BASE + 0xa000)
 #define U8500_CRYPTO1_BASE     (U8500_PER6_BASE + 0xb000)
 #define U8500_CLKRST6_BASE     (U8500_PER6_BASE + 0xf000)
@@ -125,7 +130,42 @@
 #define U8500_GPIO1_BASE       (U8500_PER1_BASE + 0xe000)
 #define U8500_CLKRST1_BASE     (U8500_PER1_BASE + 0xf000)
 
+#define U8500_GPIOBANK0_BASE   U8500_GPIO1_BASE
+#define U8500_GPIOBANK1_BASE   (U8500_GPIO1_BASE + 0x80)
+#define U8500_GPIOBANK2_BASE   U8500_GPIO3_BASE
+#define U8500_GPIOBANK3_BASE   (U8500_GPIO3_BASE + 0x80)
+#define U8500_GPIOBANK4_BASE   (U8500_GPIO3_BASE + 0x100)
+#define U8500_GPIOBANK5_BASE   (U8500_GPIO3_BASE + 0x180)
+#define U8500_GPIOBANK6_BASE   U8500_GPIO2_BASE
+#define U8500_GPIOBANK7_BASE   (U8500_GPIO2_BASE + 0x80)
+#define U8500_GPIOBANK8_BASE   U8500_GPIO5_BASE
+
 /* ST-Ericsson modified pl022 id */
 #define SSP_PER_ID             0x01080022
 
+#ifndef __ASSEMBLY__
+
+#include <asm/cputype.h>
+
+static inline bool cpu_is_u8500(void)
+{
+#ifdef CONFIG_UX500_SOC_DB8500
+       return 1;
+#else
+       return 0;
+#endif
+}
+
+static inline bool cpu_is_u8500ed(void)
+{
+       return cpu_is_u8500() && (read_cpuid_id() & 15) == 0;
+}
+
+static inline bool cpu_is_u8500v1(void)
+{
+       return cpu_is_u8500() && (read_cpuid_id() & 15) == 1;
+}
+
+#endif
+
 #endif                         /* __MACH_HARDWARE_H */