BACKPORT: arm: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)

[cascardo/linux.git] / arch / arm / mm / context.c

diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 4babb4a..c82bcb7 100644 (file)
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -100,6 +100,7 @@ static void flush_context(void)
 {
        cpu_set_reserved_ttbr0();
        local_flush_tlb_all();
+       dummy_flush_tlb_a15_erratum();
        if (icache_is_vivt_asid_tagged()) {
                __flush_icache_all();
                dsb();