Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[cascardo/linux.git] / arch / arm64 / boot / dts / mediatek / mt8173.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index fd71a87..424a493 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/clock/mt8173-clk.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8173-power.h>
 #include <dt-bindings/reset/mt8173-resets.h>
 #include "mt8173-pinfunc.h"
@@ -510,6 +511,47 @@
                        status = "disabled";
                };
 
+               usb30: usb@11270000 {
+                       compatible = "mediatek,mt8173-xhci";
+                       reg = <0 0x11270000 0 0x1000>,
+                             <0 0x11280700 0 0x0100>;
+                       interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+                       power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+                       clocks = <&topckgen CLK_TOP_USB30_SEL>,
+                                <&pericfg CLK_PERI_USB0>,
+                                <&pericfg CLK_PERI_USB1>;
+                       clock-names = "sys_ck",
+                                     "wakeup_deb_p0",
+                                     "wakeup_deb_p1";
+                       phys = <&phy_port0 PHY_TYPE_USB3>,
+                              <&phy_port1 PHY_TYPE_USB2>;
+                       mediatek,syscon-wakeup = <&pericfg>;
+                       status = "okay";
+               };
+
+               u3phy: usb-phy@11290000 {
+                       compatible = "mediatek,mt8173-u3phy";
+                       reg = <0 0x11290000 0 0x800>;
+                       clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+                       clock-names = "u3phya_ref";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       status = "okay";
+
+                       phy_port0: port@11290800 {
+                               reg = <0 0x11290800 0 0x800>;
+                               #phy-cells = <1>;
+                               status = "okay";
+                       };
+
+                       phy_port1: port@11291000 {
+                               reg = <0 0x11291000 0 0x800>;
+                               #phy-cells = <1>;
+                               status = "okay";
+                       };
+               };
+
                mmsys: clock-controller@14000000 {
                        compatible = "mediatek,mt8173-mmsys", "syscon";
                        reg = <0 0x14000000 0 0x1000>;