Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[cascardo/linux.git] / arch / arm64 / boot / dts / mediatek / mt8173.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 424a493..ec135ea 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -96,7 +96,7 @@
        };
 
        psci {
-               compatible = "arm,psci";
+               compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
                method = "smc";
                cpu_suspend   = <0x84000001>;
                cpu_off       = <0x84000002>;
@@ -248,6 +248,15 @@
                        reg = <0 0x10007000 0 0x100>;
                };
 
+               timer: timer@10008000 {
+                       compatible = "mediatek,mt8173-timer",
+                                    "mediatek,mt6577-timer";
+                       reg = <0 0x10008000 0 0x1000>;
+                       interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&infracfg CLK_INFRA_CLK_13M>,
+                                <&topckgen CLK_TOP_RTC_SEL>;
+               };
+
                pwrap: pwrap@1000d000 {
                        compatible = "mediatek,mt8173-pwrap";
                        reg = <0 0x1000d000 0 0x1000>;
@@ -558,6 +567,28 @@
                        #clock-cells = <1>;
                };
 
+               pwm0: pwm@1401e000 {
+                       compatible = "mediatek,mt8173-disp-pwm",
+                                    "mediatek,mt6595-disp-pwm";
+                       reg = <0 0x1401e000 0 0x1000>;
+                       #pwm-cells = <2>;
+                       clocks = <&mmsys CLK_MM_DISP_PWM026M>,
+                                <&mmsys CLK_MM_DISP_PWM0MM>;
+                       clock-names = "main", "mm";
+                       status = "disabled";
+               };
+
+               pwm1: pwm@1401f000 {
+                       compatible = "mediatek,mt8173-disp-pwm",
+                                    "mediatek,mt6595-disp-pwm";
+                       reg = <0 0x1401f000 0 0x1000>;
+                       #pwm-cells = <2>;
+                       clocks = <&mmsys CLK_MM_DISP_PWM126M>,
+                                <&mmsys CLK_MM_DISP_PWM1MM>;
+                       clock-names = "main", "mm";
+                       status = "disabled";
+               };
+
                imgsys: clock-controller@15000000 {
                        compatible = "mediatek,mt8173-imgsys", "syscon";
                        reg = <0 0x15000000 0 0x1000>;